LINT build test. Aggregated source code adjustments to bring most of the
[dragonfly.git] / sys / i386 / i386 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
7b95be2a 26 * $DragonFly: src/sys/i386/i386/Attic/mp_machdep.c,v 1.13 2003/07/21 07:57:43 dillon Exp $
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27 */
28
29#include "opt_cpu.h"
30#include "opt_htt.h"
31#include "opt_user_ldt.h"
32
33#ifdef SMP
34#include <machine/smptests.h>
35#else
36#error
37#endif
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/kernel.h>
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42#include <sys/sysctl.h>
43#include <sys/malloc.h>
44#include <sys/memrange.h>
45#ifdef BETTER_CLOCK
46#include <sys/dkstat.h>
47#endif
48#include <sys/cons.h> /* cngetc() */
49
50#include <vm/vm.h>
51#include <vm/vm_param.h>
52#include <vm/pmap.h>
53#include <vm/vm_kern.h>
54#include <vm/vm_extern.h>
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55#include <sys/lock.h>
56#include <vm/vm_map.h>
57#include <sys/user.h>
58#ifdef GPROF
59#include <sys/gmon.h>
60#endif
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61
62#include <machine/smp.h>
63#include <machine/apic.h>
64#include <machine/atomic.h>
65#include <machine/cpufunc.h>
66#include <machine/mpapic.h>
67#include <machine/psl.h>
68#include <machine/segments.h>
69#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
70#include <machine/tss.h>
71#include <machine/specialreg.h>
72#include <machine/globaldata.h>
73
74#if defined(APIC_IO)
75#include <machine/md_var.h> /* setidt() */
76#include <i386/isa/icu.h> /* IPIs */
77#include <i386/isa/intr_machdep.h> /* IPIs */
78#endif /* APIC_IO */
79
80#if defined(TEST_DEFAULT_CONFIG)
81#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
82#else
83#define MPFPS_MPFB1 mpfps->mpfb1
84#endif /* TEST_DEFAULT_CONFIG */
85
86#define WARMBOOT_TARGET 0
87#define WARMBOOT_OFF (KERNBASE + 0x0467)
88#define WARMBOOT_SEG (KERNBASE + 0x0469)
89
90#ifdef PC98
91#define BIOS_BASE (0xe8000)
92#define BIOS_SIZE (0x18000)
93#else
94#define BIOS_BASE (0xf0000)
95#define BIOS_SIZE (0x10000)
96#endif
97#define BIOS_COUNT (BIOS_SIZE/4)
98
99#define CMOS_REG (0x70)
100#define CMOS_DATA (0x71)
101#define BIOS_RESET (0x0f)
102#define BIOS_WARM (0x0a)
103
104#define PROCENTRY_FLAG_EN 0x01
105#define PROCENTRY_FLAG_BP 0x02
106#define IOAPICENTRY_FLAG_EN 0x01
107
108
109/* MP Floating Pointer Structure */
110typedef struct MPFPS {
111 char signature[4];
112 void *pap;
113 u_char length;
114 u_char spec_rev;
115 u_char checksum;
116 u_char mpfb1;
117 u_char mpfb2;
118 u_char mpfb3;
119 u_char mpfb4;
120 u_char mpfb5;
121} *mpfps_t;
122
123/* MP Configuration Table Header */
124typedef struct MPCTH {
125 char signature[4];
126 u_short base_table_length;
127 u_char spec_rev;
128 u_char checksum;
129 u_char oem_id[8];
130 u_char product_id[12];
131 void *oem_table_pointer;
132 u_short oem_table_size;
133 u_short entry_count;
134 void *apic_address;
135 u_short extended_table_length;
136 u_char extended_table_checksum;
137 u_char reserved;
138} *mpcth_t;
139
140
141typedef struct PROCENTRY {
142 u_char type;
143 u_char apic_id;
144 u_char apic_version;
145 u_char cpu_flags;
146 u_long cpu_signature;
147 u_long feature_flags;
148 u_long reserved1;
149 u_long reserved2;
150} *proc_entry_ptr;
151
152typedef struct BUSENTRY {
153 u_char type;
154 u_char bus_id;
155 char bus_type[6];
156} *bus_entry_ptr;
157
158typedef struct IOAPICENTRY {
159 u_char type;
160 u_char apic_id;
161 u_char apic_version;
162 u_char apic_flags;
163 void *apic_address;
164} *io_apic_entry_ptr;
165
166typedef struct INTENTRY {
167 u_char type;
168 u_char int_type;
169 u_short int_flags;
170 u_char src_bus_id;
171 u_char src_bus_irq;
172 u_char dst_apic_id;
173 u_char dst_apic_int;
174} *int_entry_ptr;
175
176/* descriptions of MP basetable entries */
177typedef struct BASETABLE_ENTRY {
178 u_char type;
179 u_char length;
180 char name[16];
181} basetable_entry;
182
183/*
184 * this code MUST be enabled here and in mpboot.s.
185 * it follows the very early stages of AP boot by placing values in CMOS ram.
186 * it NORMALLY will never be needed and thus the primitive method for enabling.
187 *
984263bc 188 */
8a8d5d85 189#define CHECK_POINTS
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190
191#if defined(CHECK_POINTS) && !defined(PC98)
192#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
193#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
194
195#define CHECK_INIT(D); \
196 CHECK_WRITE(0x34, (D)); \
197 CHECK_WRITE(0x35, (D)); \
198 CHECK_WRITE(0x36, (D)); \
199 CHECK_WRITE(0x37, (D)); \
200 CHECK_WRITE(0x38, (D)); \
201 CHECK_WRITE(0x39, (D));
202
203#define CHECK_PRINT(S); \
204 printf("%s: %d, %d, %d, %d, %d, %d\n", \
205 (S), \
206 CHECK_READ(0x34), \
207 CHECK_READ(0x35), \
208 CHECK_READ(0x36), \
209 CHECK_READ(0x37), \
210 CHECK_READ(0x38), \
211 CHECK_READ(0x39));
212
213#else /* CHECK_POINTS */
214
215#define CHECK_INIT(D)
216#define CHECK_PRINT(S)
217
218#endif /* CHECK_POINTS */
219
220/*
221 * Values to send to the POST hardware.
222 */
223#define MP_BOOTADDRESS_POST 0x10
224#define MP_PROBE_POST 0x11
225#define MPTABLE_PASS1_POST 0x12
226
227#define MP_START_POST 0x13
228#define MP_ENABLE_POST 0x14
229#define MPTABLE_PASS2_POST 0x15
230
231#define START_ALL_APS_POST 0x16
232#define INSTALL_AP_TRAMP_POST 0x17
233#define START_AP_POST 0x18
234
235#define MP_ANNOUNCE_POST 0x19
236
237#ifdef HTT
238static int need_hyperthreading_fixup;
239static u_int logical_cpus;
240#endif
241
242/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
243int current_postcode;
244
245/** XXX FIXME: what system files declare these??? */
246extern struct region_descriptor r_gdt, r_idt;
247
248int bsp_apic_ready = 0; /* flags useability of BSP apic */
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249int mp_naps; /* # of Applications processors */
250int mp_nbusses; /* # of busses */
251int mp_napics; /* # of IO APICs */
252int boot_cpu_id; /* designated BSP */
253vm_offset_t cpu_apic_address;
254vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
255extern int nkpt;
256
257u_int32_t cpu_apic_versions[MAXCPU];
258u_int32_t *io_apic_versions;
259
8a8d5d85 260struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
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261
262#ifdef APIC_INTR_REORDER
263struct {
264 volatile int *location;
265 int bit;
266} apic_isrbit_location[32];
267#endif
268
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269
270/*
271 * APIC ID logical/physical mapping structures.
272 * We oversize these to simplify boot-time config.
273 */
274int cpu_num_to_apic_id[NAPICID];
275int io_num_to_apic_id[NAPICID];
276int apic_id_to_logical[NAPICID];
277
278
279/* Bitmap of all available CPUs */
280u_int all_cpus;
281
282/* AP uses this during bootstrap. Do not staticize. */
283char *bootSTK;
284static int bootAP;
285
286/* Hotwire a 0->4MB V==P mapping */
287extern pt_entry_t *KPTphys;
288
289/* SMP page table page */
290extern pt_entry_t *SMPpt;
291
292struct pcb stoppcbs[MAXCPU];
293
294int smp_started; /* has the system started? */
295
296/*
297 * Local data and functions.
298 */
299
300static int mp_capable;
301static u_int boot_address;
302static u_int base_memory;
303
304static int picmode; /* 0: virtual wire mode, 1: PIC mode */
305static mpfps_t mpfps;
306static int search_for_sig(u_int32_t target, int count);
307static void mp_enable(u_int boot_addr);
308
309#ifdef HTT
310static void mptable_hyperthread_fixup(u_int id_mask);
311#endif
312static void mptable_pass1(void);
313static int mptable_pass2(void);
314static void default_mp_table(int type);
315static void fix_mp_table(void);
316static void setup_apic_irq_mapping(void);
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317static int start_all_aps(u_int boot_addr);
318static void install_ap_tramp(u_int boot_addr);
319static int start_ap(int logicalCpu, u_int boot_addr);
320static int apic_int_is_bus_type(int intr, int bus_type);
321
322/*
323 * Calculate usable address in base memory for AP trampoline code.
324 */
325u_int
326mp_bootaddress(u_int basemem)
327{
328 POSTCODE(MP_BOOTADDRESS_POST);
329
330 base_memory = basemem * 1024; /* convert to bytes */
331
332 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
333 if ((base_memory - boot_address) < bootMP_size)
334 boot_address -= 4096; /* not enough, lower by 4k */
335
336 return boot_address;
337}
338
339
340/*
341 * Look for an Intel MP spec table (ie, SMP capable hardware).
342 */
343int
344mp_probe(void)
345{
346 int x;
347 u_long segment;
348 u_int32_t target;
349
350 POSTCODE(MP_PROBE_POST);
351
352 /* see if EBDA exists */
353 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
354 /* search first 1K of EBDA */
355 target = (u_int32_t) (segment << 4);
356 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
357 goto found;
358 } else {
359 /* last 1K of base memory, effective 'top of base' passed in */
360 target = (u_int32_t) (base_memory - 0x400);
361 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
362 goto found;
363 }
364
365 /* search the BIOS */
366 target = (u_int32_t) BIOS_BASE;
367 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
368 goto found;
369
370 /* nothing found */
371 mpfps = (mpfps_t)0;
372 mp_capable = 0;
373 return 0;
374
375found:
376 /* calculate needed resources */
377 mpfps = (mpfps_t)x;
378 mptable_pass1();
379
380 /* flag fact that we are running multiple processors */
381 mp_capable = 1;
382 return 1;
383}
384
385
386/*
387 * Startup the SMP processors.
388 */
389void
390mp_start(void)
391{
392 POSTCODE(MP_START_POST);
393
394 /* look for MP capable motherboard */
395 if (mp_capable)
396 mp_enable(boot_address);
397 else
398 panic("MP hardware not found!");
399}
400
401
402/*
403 * Print various information about the SMP system hardware and setup.
404 */
405void
406mp_announce(void)
407{
408 int x;
409
410 POSTCODE(MP_ANNOUNCE_POST);
411
412 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
413 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
414 printf(", version: 0x%08x", cpu_apic_versions[0]);
415 printf(", at 0x%08x\n", cpu_apic_address);
416 for (x = 1; x <= mp_naps; ++x) {
417 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
418 printf(", version: 0x%08x", cpu_apic_versions[x]);
419 printf(", at 0x%08x\n", cpu_apic_address);
420 }
421
422#if defined(APIC_IO)
423 for (x = 0; x < mp_napics; ++x) {
424 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
425 printf(", version: 0x%08x", io_apic_versions[x]);
426 printf(", at 0x%08x\n", io_apic_address[x]);
427 }
428#else
429 printf(" Warning: APIC I/O disabled\n");
430#endif /* APIC_IO */
431}
432
433/*
434 * AP cpu's call this to sync up protected mode.
435 */
436void
437init_secondary(void)
438{
439 int gsel_tss;
440 int x, myid = bootAP;
441 u_int cr0;
8a8d5d85 442 struct mdglobaldata *md;
984263bc 443
8ad65e08 444 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[myid];
984263bc 445 gdt_segs[GPROC0_SEL].ssd_base =
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446 (int) &CPU_prvspace[myid].mdglobaldata.gd_common_tss;
447 CPU_prvspace[myid].mdglobaldata.mi.gd_prvspace = &CPU_prvspace[myid];
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448
449 for (x = 0; x < NGDT; x++) {
450 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
451 }
452
453 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
454 r_gdt.rd_base = (int) &gdt[myid * NGDT];
455 lgdt(&r_gdt); /* does magic intra-segment return */
456
457 lidt(&r_idt);
458
459 lldt(_default_ldt);
460#ifdef USER_LDT
7b95be2a 461 mdcpu->gd_currentldt = _default_ldt;
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462#endif
463
464 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
465 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
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466
467 md = mdcpu;
468
469 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
470 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
471 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
472 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
473 md->gd_common_tssd = *md->gd_tss_gdt;
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474 ltr(gsel_tss);
475
476 /*
477 * Set to a known state:
478 * Set by mpboot.s: CR0_PG, CR0_PE
479 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
480 */
481 cr0 = rcr0();
482 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
483 load_cr0(cr0);
484
485 pmap_set_opt();
486}
487
488
489#if defined(APIC_IO)
490/*
491 * Final configuration of the BSP's local APIC:
492 * - disable 'pic mode'.
493 * - disable 'virtual wire mode'.
494 * - enable NMI.
495 */
496void
497bsp_apic_configure(void)
498{
499 u_char byte;
500 u_int32_t temp;
501
502 /* leave 'pic mode' if necessary */
503 if (picmode) {
504 outb(0x22, 0x70); /* select IMCR */
505 byte = inb(0x23); /* current contents */
506 byte |= 0x01; /* mask external INTR */
507 outb(0x23, byte); /* disconnect 8259s/NMI */
508 }
509
510 /* mask lint0 (the 8259 'virtual wire' connection) */
511 temp = lapic.lvt_lint0;
512 temp |= APIC_LVT_M; /* set the mask */
513 lapic.lvt_lint0 = temp;
514
515 /* setup lint1 to handle NMI */
516 temp = lapic.lvt_lint1;
517 temp &= ~APIC_LVT_M; /* clear the mask */
518 lapic.lvt_lint1 = temp;
519
520 if (bootverbose)
521 apic_dump("bsp_apic_configure()");
522}
523#endif /* APIC_IO */
524
525
526/*******************************************************************
527 * local functions and data
528 */
529
530/*
531 * start the SMP system
532 */
533static void
534mp_enable(u_int boot_addr)
535{
536 int x;
537#if defined(APIC_IO)
538 int apic;
539 u_int ux;
540#endif /* APIC_IO */
541
542 POSTCODE(MP_ENABLE_POST);
543
544 /* turn on 4MB of V == P addressing so we can get to MP table */
545 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
546 invltlb();
547
548 /* examine the MP table for needed info, uses physical addresses */
549 x = mptable_pass2();
550
551 *(int *)PTD = 0;
552 invltlb();
553
554 /* can't process default configs till the CPU APIC is pmapped */
555 if (x)
556 default_mp_table(x);
557
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558 /* post scan cleanup */
559 fix_mp_table();
560 setup_apic_irq_mapping();
561
562#if defined(APIC_IO)
563
564 /* fill the LOGICAL io_apic_versions table */
565 for (apic = 0; apic < mp_napics; ++apic) {
566 ux = io_apic_read(apic, IOAPIC_VER);
567 io_apic_versions[apic] = ux;
568 io_apic_set_id(apic, IO_TO_ID(apic));
569 }
570
571 /* program each IO APIC in the system */
572 for (apic = 0; apic < mp_napics; ++apic)
573 if (io_apic_setup(apic) < 0)
574 panic("IO APIC setup failure");
575
576 /* install a 'Spurious INTerrupt' vector */
577 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
578 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
579
580 /* install an inter-CPU IPI for TLB invalidation */
581 setidt(XINVLTLB_OFFSET, Xinvltlb,
582 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
583
8a8d5d85 584#if 0
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585#ifdef BETTER_CLOCK
586 /* install an inter-CPU IPI for reading processor state */
587 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
8a8d5d85 589#endif
984263bc 590#endif
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591
592 /* install an inter-CPU IPI for IPIQ messaging */
593 setidt(XIPIQ_OFFSET, Xipiq,
594 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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595
596 /* install an inter-CPU IPI for all-CPU rendezvous */
597 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
598 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599
cb973d15 600#if 0
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601 /* install an inter-CPU IPI for forcing an additional software trap */
602 setidt(XCPUAST_OFFSET, Xcpuast,
603 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
604
605 /* install an inter-CPU IPI for interrupt forwarding */
606 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
607 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
cb973d15 608#endif
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609
610 /* install an inter-CPU IPI for CPU stop/restart */
611 setidt(XCPUSTOP_OFFSET, Xcpustop,
612 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
613
614#if defined(TEST_TEST1)
615 /* install a "fake hardware INTerrupt" vector */
616 setidt(XTEST1_OFFSET, Xtest1,
617 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
618#endif /** TEST_TEST1 */
619
620#endif /* APIC_IO */
621
622 /* start each Application Processor */
623 start_all_aps(boot_addr);
624}
625
626
627/*
628 * look for the MP spec signature
629 */
630
631/* string defined by the Intel MP Spec as identifying the MP table */
632#define MP_SIG 0x5f504d5f /* _MP_ */
633#define NEXT(X) ((X) += 4)
634static int
635search_for_sig(u_int32_t target, int count)
636{
637 int x;
638 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
639
640 for (x = 0; x < count; NEXT(x))
641 if (addr[x] == MP_SIG)
642 /* make array index a byte index */
643 return (target + (x * sizeof(u_int32_t)));
644
645 return -1;
646}
647
648
649static basetable_entry basetable_entry_types[] =
650{
651 {0, 20, "Processor"},
652 {1, 8, "Bus"},
653 {2, 8, "I/O APIC"},
654 {3, 8, "I/O INT"},
655 {4, 8, "Local INT"}
656};
657
658typedef struct BUSDATA {
659 u_char bus_id;
660 enum busTypes bus_type;
661} bus_datum;
662
663typedef struct INTDATA {
664 u_char int_type;
665 u_short int_flags;
666 u_char src_bus_id;
667 u_char src_bus_irq;
668 u_char dst_apic_id;
669 u_char dst_apic_int;
670 u_char int_vector;
671} io_int, local_int;
672
673typedef struct BUSTYPENAME {
674 u_char type;
675 char name[7];
676} bus_type_name;
677
678static bus_type_name bus_type_table[] =
679{
680 {CBUS, "CBUS"},
681 {CBUSII, "CBUSII"},
682 {EISA, "EISA"},
683 {MCA, "MCA"},
684 {UNKNOWN_BUSTYPE, "---"},
685 {ISA, "ISA"},
686 {MCA, "MCA"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {PCI, "PCI"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {XPRESS, "XPRESS"},
698 {UNKNOWN_BUSTYPE, "---"}
699};
700/* from MP spec v1.4, table 5-1 */
701static int default_data[7][5] =
702{
703/* nbus, id0, type0, id1, type1 */
704 {1, 0, ISA, 255, 255},
705 {1, 0, EISA, 255, 255},
706 {1, 0, EISA, 255, 255},
707 {1, 0, MCA, 255, 255},
708 {2, 0, ISA, 1, PCI},
709 {2, 0, EISA, 1, PCI},
710 {2, 0, MCA, 1, PCI}
711};
712
713
714/* the bus data */
715static bus_datum *bus_data;
716
717/* the IO INT data, one entry per possible APIC INTerrupt */
718static io_int *io_apic_ints;
719
720static int nintrs;
721
722static int processor_entry __P((proc_entry_ptr entry, int cpu));
723static int bus_entry __P((bus_entry_ptr entry, int bus));
724static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
725static int int_entry __P((int_entry_ptr entry, int intr));
726static int lookup_bus_type __P((char *name));
727
728
729/*
730 * 1st pass on motherboard's Intel MP specification table.
731 *
732 * initializes:
8a8d5d85 733 * ncpus = 1
984263bc
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734 *
735 * determines:
736 * cpu_apic_address (common to all CPUs)
737 * io_apic_address[N]
738 * mp_naps
739 * mp_nbusses
740 * mp_napics
741 * nintrs
742 */
743static void
744mptable_pass1(void)
745{
746 int x;
747 mpcth_t cth;
748 int totalSize;
749 void* position;
750 int count;
751 int type;
752#ifdef HTT
753 u_int id_mask;
754#endif
755
756 POSTCODE(MPTABLE_PASS1_POST);
757
758 /* clear various tables */
759 for (x = 0; x < NAPICID; ++x) {
760 io_apic_address[x] = ~0; /* IO APIC address table */
761 }
762
763 /* init everything to empty */
764 mp_naps = 0;
765 mp_nbusses = 0;
766 mp_napics = 0;
767 nintrs = 0;
768#ifdef HTT
769 id_mask = 0;
770#endif
771
772 /* check for use of 'default' configuration */
773 if (MPFPS_MPFB1 != 0) {
774 /* use default addresses */
775 cpu_apic_address = DEFAULT_APIC_BASE;
776 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
777
778 /* fill in with defaults */
779 mp_naps = 2; /* includes BSP */
780 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
781#if defined(APIC_IO)
782 mp_napics = 1;
783 nintrs = 16;
784#endif /* APIC_IO */
785 }
786 else {
787 if ((cth = mpfps->pap) == 0)
788 panic("MP Configuration Table Header MISSING!");
789
790 cpu_apic_address = (vm_offset_t) cth->apic_address;
791
792 /* walk the table, recording info of interest */
793 totalSize = cth->base_table_length - sizeof(struct MPCTH);
794 position = (u_char *) cth + sizeof(struct MPCTH);
795 count = cth->entry_count;
796
797 while (count--) {
798 switch (type = *(u_char *) position) {
799 case 0: /* processor_entry */
800 if (((proc_entry_ptr)position)->cpu_flags
801 & PROCENTRY_FLAG_EN) {
802 ++mp_naps;
803#ifdef HTT
804 id_mask |= 1 <<
805 ((proc_entry_ptr)position)->apic_id;
806#endif
807 }
808 break;
809 case 1: /* bus_entry */
810 ++mp_nbusses;
811 break;
812 case 2: /* io_apic_entry */
813 if (((io_apic_entry_ptr)position)->apic_flags
814 & IOAPICENTRY_FLAG_EN)
815 io_apic_address[mp_napics++] =
816 (vm_offset_t)((io_apic_entry_ptr)
817 position)->apic_address;
818 break;
819 case 3: /* int_entry */
820 ++nintrs;
821 break;
822 case 4: /* int_entry */
823 break;
824 default:
825 panic("mpfps Base Table HOSED!");
826 /* NOTREACHED */
827 }
828
829 totalSize -= basetable_entry_types[type].length;
830 (u_char*)position += basetable_entry_types[type].length;
831 }
832 }
833
834 /* qualify the numbers */
835 if (mp_naps > MAXCPU) {
836 printf("Warning: only using %d of %d available CPUs!\n",
837 MAXCPU, mp_naps);
838 mp_naps = MAXCPU;
839 }
840
841#ifdef HTT
842 /* See if we need to fixup HT logical CPUs. */
843 mptable_hyperthread_fixup(id_mask);
844#endif
845
846 /*
847 * Count the BSP.
848 * This is also used as a counter while starting the APs.
849 */
8a8d5d85 850 ncpus = 1;
984263bc
MD
851
852 --mp_naps; /* subtract the BSP */
853}
854
855
856/*
857 * 2nd pass on motherboard's Intel MP specification table.
858 *
859 * sets:
860 * boot_cpu_id
861 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
862 * CPU_TO_ID(N), logical CPU to APIC ID table
863 * IO_TO_ID(N), logical IO to APIC ID table
864 * bus_data[N]
865 * io_apic_ints[N]
866 */
867static int
868mptable_pass2(void)
869{
870#ifdef HTT
871 struct PROCENTRY proc;
872#endif
873 int x;
874 mpcth_t cth;
875 int totalSize;
876 void* position;
877 int count;
878 int type;
879 int apic, bus, cpu, intr;
880 int i, j;
881 int pgeflag;
882
883 POSTCODE(MPTABLE_PASS2_POST);
884
885#ifdef HTT
886 /* Initialize fake proc entry for use with HT fixup. */
887 bzero(&proc, sizeof(proc));
888 proc.type = 0;
889 proc.cpu_flags = PROCENTRY_FLAG_EN;
890#endif
891
892 pgeflag = 0; /* XXX - Not used under SMP yet. */
893
894 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
895 M_DEVBUF, M_WAITOK);
896 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
897 M_DEVBUF, M_WAITOK);
898 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
899 M_DEVBUF, M_WAITOK);
900 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
901 M_DEVBUF, M_WAITOK);
902
903 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
904
905 for (i = 0; i < mp_napics; i++) {
906 for (j = 0; j < mp_napics; j++) {
907 /* same page frame as a previous IO apic? */
908 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
909 (io_apic_address[i] & PG_FRAME)) {
8ad65e08 910 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
984263bc
MD
911 + (NPTEPG-2-j) * PAGE_SIZE
912 + (io_apic_address[i] & PAGE_MASK));
913 break;
914 }
915 /* use this slot if available */
916 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
917 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
918 pgeflag | (io_apic_address[i] & PG_FRAME));
8ad65e08 919 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
984263bc
MD
920 + (NPTEPG-2-j) * PAGE_SIZE
921 + (io_apic_address[i] & PAGE_MASK));
922 break;
923 }
924 }
925 }
926
927 /* clear various tables */
928 for (x = 0; x < NAPICID; ++x) {
929 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
930 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
931 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
932 }
933
934 /* clear bus data table */
935 for (x = 0; x < mp_nbusses; ++x)
936 bus_data[x].bus_id = 0xff;
937
938 /* clear IO APIC INT table */
939 for (x = 0; x < (nintrs + 1); ++x) {
940 io_apic_ints[x].int_type = 0xff;
941 io_apic_ints[x].int_vector = 0xff;
942 }
943
944 /* setup the cpu/apic mapping arrays */
945 boot_cpu_id = -1;
946
947 /* record whether PIC or virtual-wire mode */
948 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
949
950 /* check for use of 'default' configuration */
951 if (MPFPS_MPFB1 != 0)
952 return MPFPS_MPFB1; /* return default configuration type */
953
954 if ((cth = mpfps->pap) == 0)
955 panic("MP Configuration Table Header MISSING!");
956
957 /* walk the table, recording info of interest */
958 totalSize = cth->base_table_length - sizeof(struct MPCTH);
959 position = (u_char *) cth + sizeof(struct MPCTH);
960 count = cth->entry_count;
961 apic = bus = intr = 0;
962 cpu = 1; /* pre-count the BSP */
963
964 while (count--) {
965 switch (type = *(u_char *) position) {
966 case 0:
967 if (processor_entry(position, cpu))
968 ++cpu;
969
970#ifdef HTT
971 if (need_hyperthreading_fixup) {
972 /*
973 * Create fake mptable processor entries
974 * and feed them to processor_entry() to
975 * enumerate the logical CPUs.
976 */
977 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
978 for (i = 1; i < logical_cpus; i++) {
979 proc.apic_id++;
980 (void)processor_entry(&proc, cpu);
981 cpu++;
982 }
983 }
984#endif
985 break;
986 case 1:
987 if (bus_entry(position, bus))
988 ++bus;
989 break;
990 case 2:
991 if (io_apic_entry(position, apic))
992 ++apic;
993 break;
994 case 3:
995 if (int_entry(position, intr))
996 ++intr;
997 break;
998 case 4:
999 /* int_entry(position); */
1000 break;
1001 default:
1002 panic("mpfps Base Table HOSED!");
1003 /* NOTREACHED */
1004 }
1005
1006 totalSize -= basetable_entry_types[type].length;
1007 (u_char *) position += basetable_entry_types[type].length;
1008 }
1009
1010 if (boot_cpu_id == -1)
1011 panic("NO BSP found!");
1012
1013 /* report fact that its NOT a default configuration */
1014 return 0;
1015}
1016
1017#ifdef HTT
1018/*
1019 * Check if we should perform a hyperthreading "fix-up" to
1020 * enumerate any logical CPU's that aren't already listed
1021 * in the table.
1022 *
1023 * XXX: We assume that all of the physical CPUs in the
1024 * system have the same number of logical CPUs.
1025 *
1026 * XXX: We assume that APIC ID's are allocated such that
1027 * the APIC ID's for a physical processor are aligned
1028 * with the number of logical CPU's in the processor.
1029 */
1030static void
1031mptable_hyperthread_fixup(u_int id_mask)
1032{
1033 u_int i, id;
1034
1035 /* Nothing to do if there is no HTT support. */
1036 if ((cpu_feature & CPUID_HTT) == 0)
1037 return;
1038 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1039 if (logical_cpus <= 1)
1040 return;
1041
1042 /*
1043 * For each APIC ID of a CPU that is set in the mask,
1044 * scan the other candidate APIC ID's for this
1045 * physical processor. If any of those ID's are
1046 * already in the table, then kill the fixup.
1047 */
1048 for (id = 0; id <= MAXCPU; id++) {
1049 if ((id_mask & 1 << id) == 0)
1050 continue;
1051 /* First, make sure we are on a logical_cpus boundary. */
1052 if (id % logical_cpus != 0)
1053 return;
1054 for (i = id + 1; i < id + logical_cpus; i++)
1055 if ((id_mask & 1 << i) != 0)
1056 return;
1057 }
1058
1059 /*
1060 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1061 * mp_naps right now.
1062 */
1063 need_hyperthreading_fixup = 1;
1064 mp_naps *= logical_cpus;
1065}
1066#endif
1067
1068void
1069assign_apic_irq(int apic, int intpin, int irq)
1070{
1071 int x;
1072
1073 if (int_to_apicintpin[irq].ioapic != -1)
1074 panic("assign_apic_irq: inconsistent table");
1075
1076 int_to_apicintpin[irq].ioapic = apic;
1077 int_to_apicintpin[irq].int_pin = intpin;
1078 int_to_apicintpin[irq].apic_address = ioapic[apic];
1079 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1080
1081 for (x = 0; x < nintrs; x++) {
1082 if ((io_apic_ints[x].int_type == 0 ||
1083 io_apic_ints[x].int_type == 3) &&
1084 io_apic_ints[x].int_vector == 0xff &&
1085 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1086 io_apic_ints[x].dst_apic_int == intpin)
1087 io_apic_ints[x].int_vector = irq;
1088 }
1089}
1090
1091void
1092revoke_apic_irq(int irq)
1093{
1094 int x;
1095 int oldapic;
1096 int oldintpin;
1097
1098 if (int_to_apicintpin[irq].ioapic == -1)
1099 panic("revoke_apic_irq: inconsistent table");
1100
1101 oldapic = int_to_apicintpin[irq].ioapic;
1102 oldintpin = int_to_apicintpin[irq].int_pin;
1103
1104 int_to_apicintpin[irq].ioapic = -1;
1105 int_to_apicintpin[irq].int_pin = 0;
1106 int_to_apicintpin[irq].apic_address = NULL;
1107 int_to_apicintpin[irq].redirindex = 0;
1108
1109 for (x = 0; x < nintrs; x++) {
1110 if ((io_apic_ints[x].int_type == 0 ||
1111 io_apic_ints[x].int_type == 3) &&
1112 io_apic_ints[x].int_vector != 0xff &&
1113 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1114 io_apic_ints[x].dst_apic_int == oldintpin)
1115 io_apic_ints[x].int_vector = 0xff;
1116 }
1117}
1118
1119
1120static void
1121allocate_apic_irq(int intr)
1122{
1123 int apic;
1124 int intpin;
1125 int irq;
1126
1127 if (io_apic_ints[intr].int_vector != 0xff)
1128 return; /* Interrupt handler already assigned */
1129
1130 if (io_apic_ints[intr].int_type != 0 &&
1131 (io_apic_ints[intr].int_type != 3 ||
1132 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1133 io_apic_ints[intr].dst_apic_int == 0)))
1134 return; /* Not INT or ExtInt on != (0, 0) */
1135
1136 irq = 0;
1137 while (irq < APIC_INTMAPSIZE &&
1138 int_to_apicintpin[irq].ioapic != -1)
1139 irq++;
1140
1141 if (irq >= APIC_INTMAPSIZE)
1142 return; /* No free interrupt handlers */
1143
1144 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1145 intpin = io_apic_ints[intr].dst_apic_int;
1146
1147 assign_apic_irq(apic, intpin, irq);
1148 io_apic_setup_intpin(apic, intpin);
1149}
1150
1151
1152static void
1153swap_apic_id(int apic, int oldid, int newid)
1154{
1155 int x;
1156 int oapic;
1157
1158
1159 if (oldid == newid)
1160 return; /* Nothing to do */
1161
1162 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1163 apic, oldid, newid);
1164
1165 /* Swap physical APIC IDs in interrupt entries */
1166 for (x = 0; x < nintrs; x++) {
1167 if (io_apic_ints[x].dst_apic_id == oldid)
1168 io_apic_ints[x].dst_apic_id = newid;
1169 else if (io_apic_ints[x].dst_apic_id == newid)
1170 io_apic_ints[x].dst_apic_id = oldid;
1171 }
1172
1173 /* Swap physical APIC IDs in IO_TO_ID mappings */
1174 for (oapic = 0; oapic < mp_napics; oapic++)
1175 if (IO_TO_ID(oapic) == newid)
1176 break;
1177
1178 if (oapic < mp_napics) {
1179 printf("Changing APIC ID for IO APIC #%d from "
1180 "%d to %d in MP table\n",
1181 oapic, newid, oldid);
1182 IO_TO_ID(oapic) = oldid;
1183 }
1184 IO_TO_ID(apic) = newid;
1185}
1186
1187
1188static void
1189fix_id_to_io_mapping(void)
1190{
1191 int x;
1192
1193 for (x = 0; x < NAPICID; x++)
1194 ID_TO_IO(x) = -1;
1195
1196 for (x = 0; x <= mp_naps; x++)
1197 if (CPU_TO_ID(x) < NAPICID)
1198 ID_TO_IO(CPU_TO_ID(x)) = x;
1199
1200 for (x = 0; x < mp_napics; x++)
1201 if (IO_TO_ID(x) < NAPICID)
1202 ID_TO_IO(IO_TO_ID(x)) = x;
1203}
1204
1205
1206static int
1207first_free_apic_id(void)
1208{
1209 int freeid, x;
1210
1211 for (freeid = 0; freeid < NAPICID; freeid++) {
1212 for (x = 0; x <= mp_naps; x++)
1213 if (CPU_TO_ID(x) == freeid)
1214 break;
1215 if (x <= mp_naps)
1216 continue;
1217 for (x = 0; x < mp_napics; x++)
1218 if (IO_TO_ID(x) == freeid)
1219 break;
1220 if (x < mp_napics)
1221 continue;
1222 return freeid;
1223 }
1224 return freeid;
1225}
1226
1227
1228static int
1229io_apic_id_acceptable(int apic, int id)
1230{
1231 int cpu; /* Logical CPU number */
1232 int oapic; /* Logical IO APIC number for other IO APIC */
1233
1234 if (id >= NAPICID)
1235 return 0; /* Out of range */
1236
1237 for (cpu = 0; cpu <= mp_naps; cpu++)
1238 if (CPU_TO_ID(cpu) == id)
1239 return 0; /* Conflict with CPU */
1240
1241 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1242 if (IO_TO_ID(oapic) == id)
1243 return 0; /* Conflict with other APIC */
1244
1245 return 1; /* ID is acceptable for IO APIC */
1246}
1247
1248
1249/*
1250 * parse an Intel MP specification table
1251 */
1252static void
1253fix_mp_table(void)
1254{
1255 int x;
1256 int id;
1257 int bus_0 = 0; /* Stop GCC warning */
1258 int bus_pci = 0; /* Stop GCC warning */
1259 int num_pci_bus;
1260 int apic; /* IO APIC unit number */
1261 int freeid; /* Free physical APIC ID */
1262 int physid; /* Current physical IO APIC ID */
1263
1264 /*
1265 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1266 * did it wrong. The MP spec says that when more than 1 PCI bus
1267 * exists the BIOS must begin with bus entries for the PCI bus and use
1268 * actual PCI bus numbering. This implies that when only 1 PCI bus
1269 * exists the BIOS can choose to ignore this ordering, and indeed many
1270 * MP motherboards do ignore it. This causes a problem when the PCI
1271 * sub-system makes requests of the MP sub-system based on PCI bus
1272 * numbers. So here we look for the situation and renumber the
1273 * busses and associated INTs in an effort to "make it right".
1274 */
1275
1276 /* find bus 0, PCI bus, count the number of PCI busses */
1277 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1278 if (bus_data[x].bus_id == 0) {
1279 bus_0 = x;
1280 }
1281 if (bus_data[x].bus_type == PCI) {
1282 ++num_pci_bus;
1283 bus_pci = x;
1284 }
1285 }
1286 /*
1287 * bus_0 == slot of bus with ID of 0
1288 * bus_pci == slot of last PCI bus encountered
1289 */
1290
1291 /* check the 1 PCI bus case for sanity */
1292 /* if it is number 0 all is well */
1293 if (num_pci_bus == 1 &&
1294 bus_data[bus_pci].bus_id != 0) {
1295
1296 /* mis-numbered, swap with whichever bus uses slot 0 */
1297
1298 /* swap the bus entry types */
1299 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1300 bus_data[bus_0].bus_type = PCI;
1301
1302 /* swap each relavant INTerrupt entry */
1303 id = bus_data[bus_pci].bus_id;
1304 for (x = 0; x < nintrs; ++x) {
1305 if (io_apic_ints[x].src_bus_id == id) {
1306 io_apic_ints[x].src_bus_id = 0;
1307 }
1308 else if (io_apic_ints[x].src_bus_id == 0) {
1309 io_apic_ints[x].src_bus_id = id;
1310 }
1311 }
1312 }
1313
1314 /* Assign IO APIC IDs.
1315 *
1316 * First try the existing ID. If a conflict is detected, try
1317 * the ID in the MP table. If a conflict is still detected, find
1318 * a free id.
1319 *
1320 * We cannot use the ID_TO_IO table before all conflicts has been
1321 * resolved and the table has been corrected.
1322 */
1323 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1324
1325 /* First try to use the value set by the BIOS */
1326 physid = io_apic_get_id(apic);
1327 if (io_apic_id_acceptable(apic, physid)) {
1328 if (IO_TO_ID(apic) != physid)
1329 swap_apic_id(apic, IO_TO_ID(apic), physid);
1330 continue;
1331 }
1332
1333 /* Then check if the value in the MP table is acceptable */
1334 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1335 continue;
1336
1337 /* Last resort, find a free APIC ID and use it */
1338 freeid = first_free_apic_id();
1339 if (freeid >= NAPICID)
1340 panic("No free physical APIC IDs found");
1341
1342 if (io_apic_id_acceptable(apic, freeid)) {
1343 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1344 continue;
1345 }
1346 panic("Free physical APIC ID not usable");
1347 }
1348 fix_id_to_io_mapping();
1349
1350 /* detect and fix broken Compaq MP table */
1351 if (apic_int_type(0, 0) == -1) {
1352 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1353 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1354 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1355 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1356 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1357 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1358 nintrs++;
1359 }
1360}
1361
1362
1363/* Assign low level interrupt handlers */
1364static void
1365setup_apic_irq_mapping(void)
1366{
1367 int x;
1368 int int_vector;
1369
1370 /* Clear array */
1371 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1372 int_to_apicintpin[x].ioapic = -1;
1373 int_to_apicintpin[x].int_pin = 0;
1374 int_to_apicintpin[x].apic_address = NULL;
1375 int_to_apicintpin[x].redirindex = 0;
1376 }
1377
1378 /* First assign ISA/EISA interrupts */
1379 for (x = 0; x < nintrs; x++) {
1380 int_vector = io_apic_ints[x].src_bus_irq;
1381 if (int_vector < APIC_INTMAPSIZE &&
1382 io_apic_ints[x].int_vector == 0xff &&
1383 int_to_apicintpin[int_vector].ioapic == -1 &&
1384 (apic_int_is_bus_type(x, ISA) ||
1385 apic_int_is_bus_type(x, EISA)) &&
1386 io_apic_ints[x].int_type == 0) {
1387 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1388 io_apic_ints[x].dst_apic_int,
1389 int_vector);
1390 }
1391 }
1392
1393 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1394 for (x = 0; x < nintrs; x++) {
1395 if (io_apic_ints[x].dst_apic_int == 0 &&
1396 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1397 io_apic_ints[x].int_vector == 0xff &&
1398 int_to_apicintpin[0].ioapic == -1 &&
1399 io_apic_ints[x].int_type == 3) {
1400 assign_apic_irq(0, 0, 0);
1401 break;
1402 }
1403 }
1404 /* PCI interrupt assignment is deferred */
1405}
1406
1407
1408static int
1409processor_entry(proc_entry_ptr entry, int cpu)
1410{
1411 /* check for usability */
1412 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1413 return 0;
1414
1415 if(entry->apic_id >= NAPICID)
1416 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1417 /* check for BSP flag */
1418 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1419 boot_cpu_id = entry->apic_id;
1420 CPU_TO_ID(0) = entry->apic_id;
1421 ID_TO_CPU(entry->apic_id) = 0;
1422 return 0; /* its already been counted */
1423 }
1424
1425 /* add another AP to list, if less than max number of CPUs */
1426 else if (cpu < MAXCPU) {
1427 CPU_TO_ID(cpu) = entry->apic_id;
1428 ID_TO_CPU(entry->apic_id) = cpu;
1429 return 1;
1430 }
1431
1432 return 0;
1433}
1434
1435
1436static int
1437bus_entry(bus_entry_ptr entry, int bus)
1438{
1439 int x;
1440 char c, name[8];
1441
1442 /* encode the name into an index */
1443 for (x = 0; x < 6; ++x) {
1444 if ((c = entry->bus_type[x]) == ' ')
1445 break;
1446 name[x] = c;
1447 }
1448 name[x] = '\0';
1449
1450 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1451 panic("unknown bus type: '%s'", name);
1452
1453 bus_data[bus].bus_id = entry->bus_id;
1454 bus_data[bus].bus_type = x;
1455
1456 return 1;
1457}
1458
1459
1460static int
1461io_apic_entry(io_apic_entry_ptr entry, int apic)
1462{
1463 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1464 return 0;
1465
1466 IO_TO_ID(apic) = entry->apic_id;
1467 if (entry->apic_id < NAPICID)
1468 ID_TO_IO(entry->apic_id) = apic;
1469
1470 return 1;
1471}
1472
1473
1474static int
1475lookup_bus_type(char *name)
1476{
1477 int x;
1478
1479 for (x = 0; x < MAX_BUSTYPE; ++x)
1480 if (strcmp(bus_type_table[x].name, name) == 0)
1481 return bus_type_table[x].type;
1482
1483 return UNKNOWN_BUSTYPE;
1484}
1485
1486
1487static int
1488int_entry(int_entry_ptr entry, int intr)
1489{
1490 int apic;
1491
1492 io_apic_ints[intr].int_type = entry->int_type;
1493 io_apic_ints[intr].int_flags = entry->int_flags;
1494 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1495 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1496 if (entry->dst_apic_id == 255) {
1497 /* This signal goes to all IO APICS. Select an IO APIC
1498 with sufficient number of interrupt pins */
1499 for (apic = 0; apic < mp_napics; apic++)
1500 if (((io_apic_read(apic, IOAPIC_VER) &
1501 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1502 entry->dst_apic_int)
1503 break;
1504 if (apic < mp_napics)
1505 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1506 else
1507 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1508 } else
1509 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1510 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1511
1512 return 1;
1513}
1514
1515
1516static int
1517apic_int_is_bus_type(int intr, int bus_type)
1518{
1519 int bus;
1520
1521 for (bus = 0; bus < mp_nbusses; ++bus)
1522 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1523 && ((int) bus_data[bus].bus_type == bus_type))
1524 return 1;
1525
1526 return 0;
1527}
1528
1529
1530/*
1531 * Given a traditional ISA INT mask, return an APIC mask.
1532 */
1533u_int
1534isa_apic_mask(u_int isa_mask)
1535{
1536 int isa_irq;
1537 int apic_pin;
1538
1539#if defined(SKIP_IRQ15_REDIRECT)
1540 if (isa_mask == (1 << 15)) {
1541 printf("skipping ISA IRQ15 redirect\n");
1542 return isa_mask;
1543 }
1544#endif /* SKIP_IRQ15_REDIRECT */
1545
1546 isa_irq = ffs(isa_mask); /* find its bit position */
1547 if (isa_irq == 0) /* doesn't exist */
1548 return 0;
1549 --isa_irq; /* make it zero based */
1550
1551 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1552 if (apic_pin == -1)
1553 return 0;
1554
1555 return (1 << apic_pin); /* convert pin# to a mask */
1556}
1557
1558
1559/*
1560 * Determine which APIC pin an ISA/EISA INT is attached to.
1561 */
1562#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1563#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1564#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1565#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1566
1567#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1568int
1569isa_apic_irq(int isa_irq)
1570{
1571 int intr;
1572
1573 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1574 if (INTTYPE(intr) == 0) { /* standard INT */
1575 if (SRCBUSIRQ(intr) == isa_irq) {
1576 if (apic_int_is_bus_type(intr, ISA) ||
1577 apic_int_is_bus_type(intr, EISA)) {
1578 if (INTIRQ(intr) == 0xff)
1579 return -1; /* unassigned */
1580 return INTIRQ(intr); /* found */
1581 }
1582 }
1583 }
1584 }
1585 return -1; /* NOT found */
1586}
1587
1588
1589/*
1590 * Determine which APIC pin a PCI INT is attached to.
1591 */
1592#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1593#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1594#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1595int
1596pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1597{
1598 int intr;
1599
1600 --pciInt; /* zero based */
1601
1602 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1603 if ((INTTYPE(intr) == 0) /* standard INT */
1604 && (SRCBUSID(intr) == pciBus)
1605 && (SRCBUSDEVICE(intr) == pciDevice)
1606 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1607 if (apic_int_is_bus_type(intr, PCI)) {
1608 if (INTIRQ(intr) == 0xff)
1609 allocate_apic_irq(intr);
1610 if (INTIRQ(intr) == 0xff)
1611 return -1; /* unassigned */
1612 return INTIRQ(intr); /* exact match */
1613 }
1614
1615 return -1; /* NOT found */
1616}
1617
1618int
1619next_apic_irq(int irq)
1620{
1621 int intr, ointr;
1622 int bus, bustype;
1623
1624 bus = 0;
1625 bustype = 0;
1626 for (intr = 0; intr < nintrs; intr++) {
1627 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1628 continue;
1629 bus = SRCBUSID(intr);
1630 bustype = apic_bus_type(bus);
1631 if (bustype != ISA &&
1632 bustype != EISA &&
1633 bustype != PCI)
1634 continue;
1635 break;
1636 }
1637 if (intr >= nintrs) {
1638 return -1;
1639 }
1640 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1641 if (INTTYPE(ointr) != 0)
1642 continue;
1643 if (bus != SRCBUSID(ointr))
1644 continue;
1645 if (bustype == PCI) {
1646 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1647 continue;
1648 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1649 continue;
1650 }
1651 if (bustype == ISA || bustype == EISA) {
1652 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1653 continue;
1654 }
1655 if (INTPIN(intr) == INTPIN(ointr))
1656 continue;
1657 break;
1658 }
1659 if (ointr >= nintrs) {
1660 return -1;
1661 }
1662 return INTIRQ(ointr);
1663}
1664#undef SRCBUSLINE
1665#undef SRCBUSDEVICE
1666#undef SRCBUSID
1667#undef SRCBUSIRQ
1668
1669#undef INTPIN
1670#undef INTIRQ
1671#undef INTAPIC
1672#undef INTTYPE
1673
1674
1675/*
1676 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1677 *
1678 * XXX FIXME:
1679 * Exactly what this means is unclear at this point. It is a solution
1680 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1681 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1682 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1683 * option.
1684 */
1685int
1686undirect_isa_irq(int rirq)
1687{
1688#if defined(READY)
1689 if (bootverbose)
1690 printf("Freeing redirected ISA irq %d.\n", rirq);
1691 /** FIXME: tickle the MB redirector chip */
1692 return ???;
1693#else
1694 if (bootverbose)
1695 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1696 return 0;
1697#endif /* READY */
1698}
1699
1700
1701/*
1702 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1703 */
1704int
1705undirect_pci_irq(int rirq)
1706{
1707#if defined(READY)
1708 if (bootverbose)
1709 printf("Freeing redirected PCI irq %d.\n", rirq);
1710
1711 /** FIXME: tickle the MB redirector chip */
1712 return ???;
1713#else
1714 if (bootverbose)
1715 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1716 rirq);
1717 return 0;
1718#endif /* READY */
1719}
1720
1721
1722/*
1723 * given a bus ID, return:
1724 * the bus type if found
1725 * -1 if NOT found
1726 */
1727int
1728apic_bus_type(int id)
1729{
1730 int x;
1731
1732 for (x = 0; x < mp_nbusses; ++x)
1733 if (bus_data[x].bus_id == id)
1734 return bus_data[x].bus_type;
1735
1736 return -1;
1737}
1738
1739
1740/*
1741 * given a LOGICAL APIC# and pin#, return:
1742 * the associated src bus ID if found
1743 * -1 if NOT found
1744 */
1745int
1746apic_src_bus_id(int apic, int pin)
1747{
1748 int x;
1749
1750 /* search each of the possible INTerrupt sources */
1751 for (x = 0; x < nintrs; ++x)
1752 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1753 (pin == io_apic_ints[x].dst_apic_int))
1754 return (io_apic_ints[x].src_bus_id);
1755
1756 return -1; /* NOT found */
1757}
1758
1759
1760/*
1761 * given a LOGICAL APIC# and pin#, return:
1762 * the associated src bus IRQ if found
1763 * -1 if NOT found
1764 */
1765int
1766apic_src_bus_irq(int apic, int pin)
1767{
1768 int x;
1769
1770 for (x = 0; x < nintrs; x++)
1771 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1772 (pin == io_apic_ints[x].dst_apic_int))
1773 return (io_apic_ints[x].src_bus_irq);
1774
1775 return -1; /* NOT found */
1776}
1777
1778
1779/*
1780 * given a LOGICAL APIC# and pin#, return:
1781 * the associated INTerrupt type if found
1782 * -1 if NOT found
1783 */
1784int
1785apic_int_type(int apic, int pin)
1786{
1787 int x;
1788
1789 /* search each of the possible INTerrupt sources */
1790 for (x = 0; x < nintrs; ++x)
1791 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1792 (pin == io_apic_ints[x].dst_apic_int))
1793 return (io_apic_ints[x].int_type);
1794
1795 return -1; /* NOT found */
1796}
1797
1798int
1799apic_irq(int apic, int pin)
1800{
1801 int x;
1802 int res;
1803
1804 for (x = 0; x < nintrs; ++x)
1805 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1806 (pin == io_apic_ints[x].dst_apic_int)) {
1807 res = io_apic_ints[x].int_vector;
1808 if (res == 0xff)
1809 return -1;
1810 if (apic != int_to_apicintpin[res].ioapic)
1811 panic("apic_irq: inconsistent table");
1812 if (pin != int_to_apicintpin[res].int_pin)
1813 panic("apic_irq inconsistent table (2)");
1814 return res;
1815 }
1816 return -1;
1817}
1818
1819
1820/*
1821 * given a LOGICAL APIC# and pin#, return:
1822 * the associated trigger mode if found
1823 * -1 if NOT found
1824 */
1825int
1826apic_trigger(int apic, int pin)
1827{
1828 int x;
1829
1830 /* search each of the possible INTerrupt sources */
1831 for (x = 0; x < nintrs; ++x)
1832 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1833 (pin == io_apic_ints[x].dst_apic_int))
1834 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1835
1836 return -1; /* NOT found */
1837}
1838
1839
1840/*
1841 * given a LOGICAL APIC# and pin#, return:
1842 * the associated 'active' level if found
1843 * -1 if NOT found
1844 */
1845int
1846apic_polarity(int apic, int pin)
1847{
1848 int x;
1849
1850 /* search each of the possible INTerrupt sources */
1851 for (x = 0; x < nintrs; ++x)
1852 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1853 (pin == io_apic_ints[x].dst_apic_int))
1854 return (io_apic_ints[x].int_flags & 0x03);
1855
1856 return -1; /* NOT found */
1857}
1858
1859
1860/*
1861 * set data according to MP defaults
1862 * FIXME: probably not complete yet...
1863 */
1864static void
1865default_mp_table(int type)
1866{
1867 int ap_cpu_id;
1868#if defined(APIC_IO)
1869 int io_apic_id;
1870 int pin;
1871#endif /* APIC_IO */
1872
1873#if 0
1874 printf(" MP default config type: %d\n", type);
1875 switch (type) {
1876 case 1:
1877 printf(" bus: ISA, APIC: 82489DX\n");
1878 break;
1879 case 2:
1880 printf(" bus: EISA, APIC: 82489DX\n");
1881 break;
1882 case 3:
1883 printf(" bus: EISA, APIC: 82489DX\n");
1884 break;
1885 case 4:
1886 printf(" bus: MCA, APIC: 82489DX\n");
1887 break;
1888 case 5:
1889 printf(" bus: ISA+PCI, APIC: Integrated\n");
1890 break;
1891 case 6:
1892 printf(" bus: EISA+PCI, APIC: Integrated\n");
1893 break;
1894 case 7:
1895 printf(" bus: MCA+PCI, APIC: Integrated\n");
1896 break;
1897 default:
1898 printf(" future type\n");
1899 break;
1900 /* NOTREACHED */
1901 }
1902#endif /* 0 */
1903
1904 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1905 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1906
1907 /* BSP */
1908 CPU_TO_ID(0) = boot_cpu_id;
1909 ID_TO_CPU(boot_cpu_id) = 0;
1910
1911 /* one and only AP */
1912 CPU_TO_ID(1) = ap_cpu_id;
1913 ID_TO_CPU(ap_cpu_id) = 1;
1914
1915#if defined(APIC_IO)
1916 /* one and only IO APIC */
1917 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1918
1919 /*
1920 * sanity check, refer to MP spec section 3.6.6, last paragraph
1921 * necessary as some hardware isn't properly setting up the IO APIC
1922 */
1923#if defined(REALLY_ANAL_IOAPICID_VALUE)
1924 if (io_apic_id != 2) {
1925#else
1926 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1927#endif /* REALLY_ANAL_IOAPICID_VALUE */
1928 io_apic_set_id(0, 2);
1929 io_apic_id = 2;
1930 }
1931 IO_TO_ID(0) = io_apic_id;
1932 ID_TO_IO(io_apic_id) = 0;
1933#endif /* APIC_IO */
1934
1935 /* fill out bus entries */
1936 switch (type) {
1937 case 1:
1938 case 2:
1939 case 3:
1940 case 4:
1941 case 5:
1942 case 6:
1943 case 7:
1944 bus_data[0].bus_id = default_data[type - 1][1];
1945 bus_data[0].bus_type = default_data[type - 1][2];
1946 bus_data[1].bus_id = default_data[type - 1][3];
1947 bus_data[1].bus_type = default_data[type - 1][4];
1948 break;
1949
1950 /* case 4: case 7: MCA NOT supported */
1951 default: /* illegal/reserved */
1952 panic("BAD default MP config: %d", type);
1953 /* NOTREACHED */
1954 }
1955
1956#if defined(APIC_IO)
1957 /* general cases from MP v1.4, table 5-2 */
1958 for (pin = 0; pin < 16; ++pin) {
1959 io_apic_ints[pin].int_type = 0;
1960 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1961 io_apic_ints[pin].src_bus_id = 0;
1962 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1963 io_apic_ints[pin].dst_apic_id = io_apic_id;
1964 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1965 }
1966
1967 /* special cases from MP v1.4, table 5-2 */
1968 if (type == 2) {
1969 io_apic_ints[2].int_type = 0xff; /* N/C */
1970 io_apic_ints[13].int_type = 0xff; /* N/C */
1971#if !defined(APIC_MIXED_MODE)
1972 /** FIXME: ??? */
1973 panic("sorry, can't support type 2 default yet");
1974#endif /* APIC_MIXED_MODE */
1975 }
1976 else
1977 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1978
1979 if (type == 7)
1980 io_apic_ints[0].int_type = 0xff; /* N/C */
1981 else
1982 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1983#endif /* APIC_IO */
1984}
1985
984263bc
MD
1986/*
1987 * start each AP in our list
1988 */
1989static int
1990start_all_aps(u_int boot_addr)
1991{
1992 int x, i, pg;
1993 u_char mpbiosreason;
1994 u_long mpbioswarmvec;
8a8d5d85 1995 struct mdglobaldata *gd;
984263bc
MD
1996 char *stack;
1997 uintptr_t kptbase;
1998
1999 POSTCODE(START_ALL_APS_POST);
2000
2001 /* initialize BSP's local APIC */
2002 apic_initialize();
2003 bsp_apic_ready = 1;
2004
2005 /* install the AP 1st level boot code */
2006 install_ap_tramp(boot_addr);
2007
2008
2009 /* save the current value of the warm-start vector */
2010 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2011#ifndef PC98
2012 outb(CMOS_REG, BIOS_RESET);
2013 mpbiosreason = inb(CMOS_DATA);
2014#endif
2015
2016 /* record BSP in CPU map */
2017 all_cpus = 1;
2018
2019 /* set up temporary P==V mapping for AP boot */
2020 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2021 kptbase = (uintptr_t)(void *)KPTphys;
2022 for (x = 0; x < NKPT; x++)
2023 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2024 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2025 invltlb();
2026
2027 /* start each AP */
2028 for (x = 1; x <= mp_naps; ++x) {
2029
2030 /* This is a bit verbose, it will go away soon. */
2031
2032 /* first page of AP's private space */
2033 pg = x * i386_btop(sizeof(struct privatespace));
2034
2035 /* allocate a new private data page */
8a8d5d85 2036 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
984263bc
MD
2037
2038 /* wire it into the private page table page */
2039 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
2040
2041 /* allocate and set up an idle stack data page */
2042 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2043 for (i = 0; i < UPAGES; i++) {
984263bc
MD
2044 SMPpt[pg + 5 + i] = (pt_entry_t)
2045 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
8a8d5d85 2046 }
984263bc 2047
85100692
MD
2048 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2049 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2050 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2051 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
984263bc 2052
8a8d5d85
MD
2053 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2054 bzero(gd, sizeof(*gd));
2055 gd->mi.gd_prvspace = &CPU_prvspace[x];
2056
984263bc 2057 /* prime data page for it to use */
8a8d5d85 2058 mi_gdinit(&gd->mi, x);
8ad65e08 2059 cpu_gdinit(gd, x);
f1d1c3fa 2060 gd->gd_cpu_lockid = x << 24;
85100692
MD
2061 gd->gd_CMAP1 = &SMPpt[pg + 1];
2062 gd->gd_CMAP2 = &SMPpt[pg + 2];
2063 gd->gd_CMAP3 = &SMPpt[pg + 3];
2064 gd->gd_PMAP1 = &SMPpt[pg + 4];
2065 gd->gd_CADDR1 = CPU_prvspace[x].CPAGE1;
2066 gd->gd_CADDR2 = CPU_prvspace[x].CPAGE2;
2067 gd->gd_CADDR3 = CPU_prvspace[x].CPAGE3;
2068 gd->gd_PADDR1 = (unsigned *)CPU_prvspace[x].PPAGE1;
96728c05
MD
2069 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2070 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc
MD
2071
2072 /* setup a vector to our boot code */
2073 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2074 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2075#ifndef PC98
2076 outb(CMOS_REG, BIOS_RESET);
2077 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2078#endif
2079
8a8d5d85
MD
2080 /*
2081 * Setup the AP boot stack
2082 */
2083 bootSTK = &CPU_prvspace[x].idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
2084 bootAP = x;
2085
2086 /* attempt to start the Application Processor */
2087 CHECK_INIT(99); /* setup checkpoints */
2088 if (!start_ap(x, boot_addr)) {
2089 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2090 CHECK_PRINT("trace"); /* show checkpoints */
2091 /* better panic as the AP may be running loose */
2092 printf("panic y/n? [y] ");
2093 if (cngetc() != 'n')
2094 panic("bye-bye");
2095 }
2096 CHECK_PRINT("trace"); /* show checkpoints */
2097
2098 /* record its version info */
2099 cpu_apic_versions[x] = cpu_apic_versions[0];
2100
2101 all_cpus |= (1 << x); /* record AP in CPU map */
2102 }
2103
2104 /* build our map of 'other' CPUs */
8a8d5d85 2105 mycpu->gd_other_cpus = all_cpus & ~(1 << mycpu->gd_cpuid);
96728c05
MD
2106 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2107 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD
2108
2109 /* fill in our (BSP) APIC version */
2110 cpu_apic_versions[0] = lapic.version;
2111
2112 /* restore the warmstart vector */
2113 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2114#ifndef PC98
2115 outb(CMOS_REG, BIOS_RESET);
2116 outb(CMOS_DATA, mpbiosreason);
2117#endif
2118
2119 /*
8a8d5d85
MD
2120 * NOTE! The idlestack for the BSP was setup by locore. Finish
2121 * up, clean out the P==V mapping we did earlier.
984263bc 2122 */
984263bc
MD
2123 for (x = 0; x < NKPT; x++)
2124 PTD[x] = 0;
2125 pmap_set_opt();
2126
2127 /* number of APs actually started */
8a8d5d85 2128 return ncpus - 1;
984263bc
MD
2129}
2130
2131
2132/*
2133 * load the 1st level AP boot code into base memory.
2134 */
2135
2136/* targets for relocation */
2137extern void bigJump(void);
2138extern void bootCodeSeg(void);
2139extern void bootDataSeg(void);
2140extern void MPentry(void);
2141extern u_int MP_GDT;
2142extern u_int mp_gdtbase;
2143
2144static void
2145install_ap_tramp(u_int boot_addr)
2146{
2147 int x;
2148 int size = *(int *) ((u_long) & bootMP_size);
2149 u_char *src = (u_char *) ((u_long) bootMP);
2150 u_char *dst = (u_char *) boot_addr + KERNBASE;
2151 u_int boot_base = (u_int) bootMP;
2152 u_int8_t *dst8;
2153 u_int16_t *dst16;
2154 u_int32_t *dst32;
2155
2156 POSTCODE(INSTALL_AP_TRAMP_POST);
2157
2158 for (x = 0; x < size; ++x)
2159 *dst++ = *src++;
2160
2161 /*
2162 * modify addresses in code we just moved to basemem. unfortunately we
2163 * need fairly detailed info about mpboot.s for this to work. changes
2164 * to mpboot.s might require changes here.
2165 */
2166
2167 /* boot code is located in KERNEL space */
2168 dst = (u_char *) boot_addr + KERNBASE;
2169
2170 /* modify the lgdt arg */
2171 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2172 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2173
2174 /* modify the ljmp target for MPentry() */
2175 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2176 *dst32 = ((u_int) MPentry - KERNBASE);
2177
2178 /* modify the target for boot code segment */
2179 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2180 dst8 = (u_int8_t *) (dst16 + 1);
2181 *dst16 = (u_int) boot_addr & 0xffff;
2182 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2183
2184 /* modify the target for boot data segment */
2185 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2186 dst8 = (u_int8_t *) (dst16 + 1);
2187 *dst16 = (u_int) boot_addr & 0xffff;
2188 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2189}
2190
2191
2192/*
2193 * this function starts the AP (application processor) identified
2194 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2195 * to accomplish this. This is necessary because of the nuances
2196 * of the different hardware we might encounter. It ain't pretty,
2197 * but it seems to work.
2198 */
2199static int
2200start_ap(int logical_cpu, u_int boot_addr)
2201{
2202 int physical_cpu;
2203 int vector;
2204 int cpus;
2205 u_long icr_lo, icr_hi;
2206
2207 POSTCODE(START_AP_POST);
2208
2209 /* get the PHYSICAL APIC ID# */
2210 physical_cpu = CPU_TO_ID(logical_cpu);
2211
2212 /* calculate the vector */
2213 vector = (boot_addr >> 12) & 0xff;
2214
2215 /* used as a watchpoint to signal AP startup */
8a8d5d85
MD
2216 cpus = ncpus;
2217
2218 /* Make sure the target cpu sees everything */
2219 wbinvd();
984263bc
MD
2220
2221 /*
2222 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2223 * and running the target CPU. OR this INIT IPI might be latched (P5
2224 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2225 * ignored.
2226 */
2227
2228 /* setup the address for the target AP */
2229 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2230 icr_hi |= (physical_cpu << 24);
2231 lapic.icr_hi = icr_hi;
2232
2233 /* do an INIT IPI: assert RESET */
2234 icr_lo = lapic.icr_lo & 0xfff00000;
2235 lapic.icr_lo = icr_lo | 0x0000c500;
2236
2237 /* wait for pending status end */
2238 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2239 /* spin */ ;
2240
2241 /* do an INIT IPI: deassert RESET */
2242 lapic.icr_lo = icr_lo | 0x00008500;
2243
2244 /* wait for pending status end */
2245 u_sleep(10000); /* wait ~10mS */
2246 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2247 /* spin */ ;
2248
2249 /*
2250 * next we do a STARTUP IPI: the previous INIT IPI might still be
2251 * latched, (P5 bug) this 1st STARTUP would then terminate
2252 * immediately, and the previously started INIT IPI would continue. OR
2253 * the previous INIT IPI has already run. and this STARTUP IPI will
2254 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2255 * will run.
2256 */
2257
2258 /* do a STARTUP IPI */
2259 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2260 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2261 /* spin */ ;
2262 u_sleep(200); /* wait ~200uS */
2263
2264 /*
2265 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2266 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2267 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2268 * recognized after hardware RESET or INIT IPI.
2269 */
2270
2271 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2272 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2273 /* spin */ ;
2274 u_sleep(200); /* wait ~200uS */
2275
8a8d5d85 2276 /* wait for it to start, see ap_init() */
984263bc 2277 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85
MD
2278 while (read_apic_timer()) {
2279 if (ncpus > cpus)
984263bc 2280 return 1; /* return SUCCESS */
8a8d5d85 2281 }
984263bc
MD
2282 return 0; /* return FAILURE */
2283}
2284
2285
2286/*
2287 * Flush the TLB on all other CPU's
2288 *
2289 * XXX: Needs to handshake and wait for completion before proceding.
2290 */
2291void
2292smp_invltlb(void)
2293{
2294#if defined(APIC_IO)
2295 if (smp_started && invltlb_ok)
2296 all_but_self_ipi(XINVLTLB_OFFSET);
2297#endif /* APIC_IO */
2298}
2299
984263bc
MD
2300/*
2301 * When called the executing CPU will send an IPI to all other CPUs
2302 * requesting that they halt execution.
2303 *
2304 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2305 *
2306 * - Signals all CPUs in map to stop.
2307 * - Waits for each to stop.
2308 *
2309 * Returns:
2310 * -1: error
2311 * 0: NA
2312 * 1: ok
2313 *
2314 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2315 * from executing at same time.
2316 */
2317int
2318stop_cpus(u_int map)
2319{
2320 if (!smp_started)
2321 return 0;
2322
2323 /* send the Xcpustop IPI to all CPUs in map */
2324 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2325
2326 while ((stopped_cpus & map) != map)
2327 /* spin */ ;
2328
2329 return 1;
2330}
2331
2332
2333/*
2334 * Called by a CPU to restart stopped CPUs.
2335 *
2336 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2337 *
2338 * - Signals all CPUs in map to restart.
2339 * - Waits for each to restart.
2340 *
2341 * Returns:
2342 * -1: error
2343 * 0: NA
2344 * 1: ok
2345 */
2346int
2347restart_cpus(u_int map)
2348{
2349 if (!smp_started)
2350 return 0;
2351
2352 started_cpus = map; /* signal other cpus to restart */
2353
2354 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2355 /* spin */ ;
2356
2357 return 1;
2358}
2359
2360int smp_active = 0; /* are the APs allowed to run? */
2361SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2362
2363/* XXX maybe should be hw.ncpu */
2364static int smp_cpus = 1; /* how many cpu's running */
2365SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2366
2367int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2368SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2369
2370/* Warning: Do not staticize. Used from swtch.s */
2371int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2372SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2373 &do_page_zero_idle, 0, "");
2374
2375/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2376int forward_irq_enabled = 1;
2377SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2378 &forward_irq_enabled, 0, "");
2379
2380/* Enable forwarding of a signal to a process running on a different CPU */
2381static int forward_signal_enabled = 1;
2382SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2383 &forward_signal_enabled, 0, "");
2384
2385/* Enable forwarding of roundrobin to all other cpus */
2386static int forward_roundrobin_enabled = 1;
2387SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2388 &forward_roundrobin_enabled, 0, "");
2389
2390/*
8a8d5d85
MD
2391 * This is called once the mpboot code has gotten us properly relocated
2392 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2393 * and when it returns the scheduler will call the real cpu_idle() main
2394 * loop for the idlethread. Interrupts are disabled on entry and should
2395 * remain disabled at return.
984263bc 2396 */
984263bc
MD
2397
2398void
8a8d5d85 2399ap_init(void)
984263bc
MD
2400{
2401 u_int apic_id;
2402
8a8d5d85
MD
2403 /*
2404 * Signal the BSP that we have started up successfully by incrementing
2405 * ncpus. Note that we do not hold the BGL yet. The BSP is waiting
2406 * for our signal.
2407 */
2408 ++ncpus;
2409
2410 /*
96728c05
MD
2411 * Get the MP lock so we can finish initializing. Note: we are
2412 * in a critical section.
8a8d5d85
MD
2413 */
2414 while (cpu_try_mplock() == 0)
2415 ;
96728c05 2416 ++curthread->td_mpcount;
8a8d5d85 2417
984263bc
MD
2418 /* BSP may have changed PTD while we're waiting for the lock */
2419 cpu_invltlb();
2420
984263bc
MD
2421#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2422 lidt(&r_idt);
2423#endif
2424
2425 /* Build our map of 'other' CPUs. */
8a8d5d85 2426 mycpu->gd_other_cpus = all_cpus & ~(1 << mycpu->gd_cpuid);
984263bc 2427
8a8d5d85 2428 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc
MD
2429
2430 /* set up CPU registers and state */
2431 cpu_setregs();
2432
2433 /* set up FPU state on the AP */
2434 npxinit(__INITIAL_NPXCW__);
2435
2436 /* set up SSE registers */
2437 enable_sse();
2438
2439 /* A quick check from sanity claus */
2440 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85
MD
2441 if (mycpu->gd_cpuid != apic_id) {
2442 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
984263bc
MD
2443 printf("SMP: apic_id = %d\n", apic_id);
2444 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2445 panic("cpuid mismatch! boom!!");
2446 }
2447
2448 /* Init local apic for irq's */
2449 apic_initialize();
2450
2451 /* Set memory range attributes for this CPU to match the BSP */
2452 mem_range_AP_init();
2453
2454 /*
8a8d5d85
MD
2455 * Since we have the BGL if smp_cpus matches ncpus then we are
2456 * the last AP to get to this point and we can enable IPI's,
2457 * tlb shootdowns, freezes, and so forth.
984263bc 2458 */
8a8d5d85
MD
2459 ++smp_cpus;
2460 if (smp_cpus == ncpus) {
984263bc
MD
2461 invltlb_ok = 1;
2462 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2463 smp_active = 1; /* historic */
2464 }
8a8d5d85 2465
a2a5ad0d
MD
2466 /*
2467 * Startup helper thread(s) one per cpu.
2468 */
2469 sched_thread_init();
2470
8a8d5d85
MD
2471 /*
2472 * The idle loop doesn't expect the BGL to be held and while
2473 * lwkt_switch() normally cleans things up this is a special case
2474 * because we returning almost directly into the idle loop.
2475 */
96728c05
MD
2476 KKASSERT(curthread->td_mpcount == 1);
2477 rel_mplock();
984263bc
MD
2478}
2479
2480#ifdef BETTER_CLOCK
2481
2482#define CHECKSTATE_USER 0
2483#define CHECKSTATE_SYS 1
2484#define CHECKSTATE_INTR 2
2485
2486/* Do not staticize. Used from apic_vector.s */
8a8d5d85 2487struct thread *checkstate_curtd[MAXCPU];
984263bc
MD
2488int checkstate_cpustate[MAXCPU];
2489u_long checkstate_pc[MAXCPU];
2490
2491#define PC_TO_INDEX(pc, prof) \
2492 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2493 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2494
8a8d5d85 2495#if 0
984263bc
MD
2496static void
2497addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2498{
2499 int i;
2500 struct uprof *prof;
2501 u_long pc;
2502
2503 pc = checkstate_pc[id];
2504 prof = &p->p_stats->p_prof;
2505 if (pc >= prof->pr_off &&
2506 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2507 if ((p->p_flag & P_OWEUPC) == 0) {
2508 prof->pr_addr = pc;
2509 prof->pr_ticks = 1;
2510 p->p_flag |= P_OWEUPC;
2511 }
2512 *astmap |= (1 << id);
2513 }
2514}
8a8d5d85 2515#endif
984263bc
MD
2516
2517static void
2518forwarded_statclock(int id, int pscnt, int *astmap)
2519{
8a8d5d85 2520#if 0
984263bc
MD
2521 struct pstats *pstats;
2522 long rss;
2523 struct rusage *ru;
2524 struct vmspace *vm;
2525 int cpustate;
8a8d5d85 2526 struct thread *td;
984263bc
MD
2527#ifdef GPROF
2528 register struct gmonparam *g;
2529 int i;
2530#endif
2531
8a8d5d85 2532 t = checkstate_curtd[id];
984263bc
MD
2533 cpustate = checkstate_cpustate[id];
2534
2535 switch (cpustate) {
2536 case CHECKSTATE_USER:
8a8d5d85
MD
2537 if (td->td_proc && td->td_proc->p_flag & P_PROFIL)
2538 addupc_intr_forwarded(td->td_proc, id, astmap);
984263bc
MD
2539 if (pscnt > 1)
2540 return;
2541 p->p_uticks++;
2542 if (p->p_nice > NZERO)
2543 cp_time[CP_NICE]++;
2544 else
2545 cp_time[CP_USER]++;
2546 break;
2547 case CHECKSTATE_SYS:
2548#ifdef GPROF
2549 /*
2550 * Kernel statistics are just like addupc_intr, only easier.
2551 */
2552 g = &_gmonparam;
2553 if (g->state == GMON_PROF_ON) {
2554 i = checkstate_pc[id] - g->lowpc;
2555 if (i < g->textsize) {
2556 i /= HISTFRACTION * sizeof(*g->kcount);
2557 g->kcount[i]++;
2558 }
2559 }
2560#endif
2561 if (pscnt > 1)
2562 return;
2563
2564 if (!p)
2565 cp_time[CP_IDLE]++;
2566 else {
2567 p->p_sticks++;
2568 cp_time[CP_SYS]++;
2569 }
2570 break;
2571 case CHECKSTATE_INTR:
2572 default:
2573#ifdef GPROF
2574 /*
2575 * Kernel statistics are just like addupc_intr, only easier.
2576 */
2577 g = &_gmonparam;
2578 if (g->state == GMON_PROF_ON) {
2579 i = checkstate_pc[id] - g->lowpc;
2580 if (i < g->textsize) {
2581 i /= HISTFRACTION * sizeof(*g->kcount);
2582 g->kcount[i]++;
2583 }
2584 }
2585#endif
2586 if (pscnt > 1)
2587 return;
2588 if (p)
2589 p->p_iticks++;
2590 cp_time[CP_INTR]++;
2591 }
2592 if (p != NULL) {
2593 schedclock(p);
2594
2595 /* Update resource usage integrals and maximums. */
2596 if ((pstats = p->p_stats) != NULL &&
2597 (ru = &pstats->p_ru) != NULL &&
2598 (vm = p->p_vmspace) != NULL) {
2599 ru->ru_ixrss += pgtok(vm->vm_tsize);
2600 ru->ru_idrss += pgtok(vm->vm_dsize);
2601 ru->ru_isrss += pgtok(vm->vm_ssize);
2602 rss = pgtok(vmspace_resident_count(vm));
2603 if (ru->ru_maxrss < rss)
2604 ru->ru_maxrss = rss;
2605 }
2606 }
8a8d5d85 2607#endif
984263bc
MD
2608}
2609
2610void
2611forward_statclock(int pscnt)
2612{
2613 int map;
2614 int id;
2615 int i;
2616
2617 /* Kludge. We don't yet have separate locks for the interrupts
2618 * and the kernel. This means that we cannot let the other processors
2619 * handle complex interrupts while inhibiting them from entering
2620 * the kernel in a non-interrupt context.
2621 *
2622 * What we can do, without changing the locking mechanisms yet,
2623 * is letting the other processors handle a very simple interrupt
2624 * (wich determines the processor states), and do the main
2625 * work ourself.
2626 */
2627
2628 if (!smp_started || !invltlb_ok || cold || panicstr)
2629 return;
2630
8a8d5d85 2631 printf("forward_statclock\n");
984263bc
MD
2632 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2633
8a8d5d85 2634 map = mycpu->gd_other_cpus & ~stopped_cpus ;
984263bc
MD
2635 checkstate_probed_cpus = 0;
2636 if (map != 0)
2637 selected_apic_ipi(map,
2638 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2639
2640 i = 0;
2641 while (checkstate_probed_cpus != map) {
2642 /* spin */
2643 i++;
2644 if (i == 100000) {
2645#ifdef BETTER_CLOCK_DIAGNOSTIC
2646 printf("forward_statclock: checkstate %x\n",
2647 checkstate_probed_cpus);
2648#endif
2649 break;
2650 }
2651 }
2652
2653 /*
2654 * Step 2: walk through other processors processes, update ticks and
2655 * profiling info.
2656 */
2657
2658 map = 0;
8a8d5d85
MD
2659 for (id = 0; id < ncpus; id++) {
2660 if (id == mycpu->gd_cpuid)
984263bc
MD
2661 continue;
2662 if (((1 << id) & checkstate_probed_cpus) == 0)
2663 continue;
2664 forwarded_statclock(id, pscnt, &map);
2665 }
cb973d15
MD
2666 if (map != 0)
2667 resched_cpus(map);
984263bc
MD
2668}
2669
2670void
2671forward_hardclock(int pscnt)
2672{
2673 int map;
2674 int id;
8a8d5d85 2675#if 0
984263bc
MD
2676 struct proc *p;
2677 struct pstats *pstats;
8a8d5d85 2678#endif
984263bc
MD
2679 int i;
2680
2681 /* Kludge. We don't yet have separate locks for the interrupts
2682 * and the kernel. This means that we cannot let the other processors
2683 * handle complex interrupts while inhibiting them from entering
2684 * the kernel in a non-interrupt context.
2685 *
2686 * What we can do, without changing the locking mechanisms yet,
2687 * is letting the other processors handle a very simple interrupt
2688 * (wich determines the processor states), and do the main
2689 * work ourself.
2690 */
2691
2692 if (!smp_started || !invltlb_ok || cold || panicstr)
2693 return;
2694
2695 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2696
8a8d5d85 2697 map = mycpu->gd_other_cpus & ~stopped_cpus ;
984263bc
MD
2698 checkstate_probed_cpus = 0;
2699 if (map != 0)
2700 selected_apic_ipi(map,
2701 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2702
2703 i = 0;
2704 while (checkstate_probed_cpus != map) {
2705 /* spin */
2706 i++;
2707 if (i == 100000) {
2708#ifdef BETTER_CLOCK_DIAGNOSTIC
2709 printf("forward_hardclock: checkstate %x\n",
2710 checkstate_probed_cpus);
2711#endif
2712 break;
2713 }
2714 }
2715
2716 /*
2717 * Step 2: walk through other processors processes, update virtual
2718 * timer and profiling timer. If stathz == 0, also update ticks and
2719 * profiling info.
2720 */
2721
2722 map = 0;
8a8d5d85
MD
2723 for (id = 0; id < ncpus; id++) {
2724 if (id == mycpu->gd_cpuid)
984263bc
MD
2725 continue;
2726 if (((1 << id) & checkstate_probed_cpus) == 0)
2727 continue;
8a8d5d85
MD
2728 printf("forward_hardclock\n");
2729#if 0
984263bc
MD
2730 p = checkstate_curproc[id];
2731 if (p) {
2732 pstats = p->p_stats;
2733 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2734 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2735 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2736 psignal(p, SIGVTALRM);
2737 map |= (1 << id);
2738 }
2739 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2740 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2741 psignal(p, SIGPROF);
2742 map |= (1 << id);
2743 }
2744 }
2745 if (stathz == 0) {
2746 forwarded_statclock( id, pscnt, &map);
2747 }
8a8d5d85 2748#endif
984263bc 2749 }
cb973d15
MD
2750 if (map != 0)
2751 resched_cpus(map);
984263bc
MD
2752}
2753
2754#endif /* BETTER_CLOCK */
2755
984263bc
MD
2756#ifdef APIC_INTR_REORDER
2757/*
8a8d5d85 2758 * Maintain mapping from softintr vector to isr bit in local apic.
984263bc
MD
2759 */
2760void
2761set_lapic_isrloc(int intr, int vector)
2762{
2763 if (intr < 0 || intr > 32)
8a8d5d85 2764 panic("set_apic_isrloc: bad intr argument: %d",intr);
984263bc 2765 if (vector < ICU_OFFSET || vector > 255)
8a8d5d85 2766 panic("set_apic_isrloc: bad vector argument: %d",vector);
984263bc
MD
2767 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2768 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2769}
2770#endif
2771
2772/*
2773 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2774 * (if specified), rendezvous, execute the action function (if specified),
2775 * rendezvous again, execute the teardown function (if specified), and then
2776 * resume.
2777 *
2778 * Note that the supplied external functions _must_ be reentrant and aware
2779 * that they are running in parallel and in an unknown lock context.
2780 */
2781static void (*smp_rv_setup_func)(void *arg);
2782static void (*smp_rv_action_func)(void *arg);
2783static void (*smp_rv_teardown_func)(void *arg);
2784static void *smp_rv_func_arg;
2785static volatile int smp_rv_waiters[2];
2786
2787void
2788smp_rendezvous_action(void)
2789{
2790 /* setup function */
2791 if (smp_rv_setup_func != NULL)
2792 smp_rv_setup_func(smp_rv_func_arg);
2793 /* spin on entry rendezvous */
2794 atomic_add_int(&smp_rv_waiters[0], 1);
8a8d5d85 2795 while (smp_rv_waiters[0] < ncpus)
984263bc
MD
2796 ;
2797 /* action function */
2798 if (smp_rv_action_func != NULL)
2799 smp_rv_action_func(smp_rv_func_arg);
2800 /* spin on exit rendezvous */
2801 atomic_add_int(&smp_rv_waiters[1], 1);
8a8d5d85 2802 while (smp_rv_waiters[1] < ncpus)
984263bc
MD
2803 ;
2804 /* teardown function */
2805 if (smp_rv_teardown_func != NULL)
2806 smp_rv_teardown_func(smp_rv_func_arg);
2807}
2808
2809void
2810smp_rendezvous(void (* setup_func)(void *),
2811 void (* action_func)(void *),
2812 void (* teardown_func)(void *),
2813 void *arg)
2814{
8a8d5d85
MD
2815 /* obtain rendezvous lock. This disables interrupts */
2816 spin_lock(&smp_rv_spinlock); /* XXX sleep here? NOWAIT flag? */
984263bc
MD
2817
2818 /* set static function pointers */
2819 smp_rv_setup_func = setup_func;
2820 smp_rv_action_func = action_func;
2821 smp_rv_teardown_func = teardown_func;
2822 smp_rv_func_arg = arg;
2823 smp_rv_waiters[0] = 0;
2824 smp_rv_waiters[1] = 0;
2825
984263bc
MD
2826 /* signal other processors, which will enter the IPI with interrupts off */
2827 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2828
2829 /* call executor function */
2830 smp_rendezvous_action();
2831
984263bc 2832 /* release lock */
8a8d5d85 2833 spin_unlock(&smp_rv_spinlock);
984263bc 2834}
96728c05
MD
2835
2836void
2837cpu_send_ipiq(int dcpu)
2838{
2839 selected_apic_ipi(1 << dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2840}