intr: Further delay MachIntrABI.finalize()
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
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41 */
42
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43//#include "use_npx.h"
44#include "use_isa.h"
45#include "opt_atalk.h"
46#include "opt_compat.h"
47#include "opt_cpu.h"
48#include "opt_ddb.h"
49#include "opt_directio.h"
50#include "opt_inet.h"
51#include "opt_ipx.h"
52#include "opt_msgbuf.h"
53#include "opt_swap.h"
eac0bf8f 54#include "opt_apic.h"
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55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/sysproto.h>
59#include <sys/signalvar.h>
60#include <sys/kernel.h>
61#include <sys/linker.h>
62#include <sys/malloc.h>
63#include <sys/proc.h>
895c1f85 64#include <sys/priv.h>
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65#include <sys/buf.h>
66#include <sys/reboot.h>
67#include <sys/mbuf.h>
68#include <sys/msgbuf.h>
69#include <sys/sysent.h>
70#include <sys/sysctl.h>
71#include <sys/vmmeter.h>
72#include <sys/bus.h>
73#include <sys/upcall.h>
74#include <sys/usched.h>
75#include <sys/reg.h>
76
77#include <vm/vm.h>
78#include <vm/vm_param.h>
79#include <sys/lock.h>
80#include <vm/vm_kern.h>
81#include <vm/vm_object.h>
82#include <vm/vm_page.h>
83#include <vm/vm_map.h>
84#include <vm/vm_pager.h>
85#include <vm/vm_extern.h>
86
87#include <sys/thread2.h>
684a93c4 88#include <sys/mplock2.h>
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89
90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
96#include <machine/cpu.h>
97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#if JG
100#include <machine/bootinfo.h>
101#endif
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102#include <machine/md_var.h>
103#include <machine/metadata.h>
104#include <machine/pc/bios.h>
105#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
106#include <machine/globaldata.h> /* CPU_prvspace */
107#include <machine/smp.h>
108#ifdef PERFMON
109#include <machine/perfmon.h>
110#endif
111#include <machine/cputypes.h>
57a9c56b 112#include <machine/intr_machdep.h>
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113
114#ifdef OLD_BUS_ARCH
46d4e165 115#include <bus/isa/isa_device.h>
c8fe38ae 116#endif
57a9c56b 117#include <machine_base/isa/isa_intr.h>
e24dd6e0 118#include <machine_base/isa/elcr_var.h>
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119#include <bus/isa/rtc.h>
120#include <sys/random.h>
121#include <sys/ptrace.h>
122#include <machine/sigframe.h>
123
faaf4131 124#include <sys/machintr.h>
9284cddf 125#include <machine_base/icu/icu_abi.h>
faaf4131 126
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127#define PHYSMAP_ENTRIES 10
128
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129extern u_int64_t hammer_time(u_int64_t, u_int64_t);
130
131extern void printcpuinfo(void); /* XXX header file */
132extern void identify_cpu(void);
133#if JG
134extern void finishidentcpu(void);
135#endif
136extern void panicifcpuunsupported(void);
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137
138static void cpu_startup(void *);
139#ifndef CPU_DISABLE_SSE
140static void set_fpregs_xmm(struct save87 *, struct savexmm *);
141static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
142#endif /* CPU_DISABLE_SSE */
143#ifdef DIRECTIO
144extern void ffs_rawread_setup(void);
145#endif /* DIRECTIO */
146static void init_locks(void);
147
148SYSINIT(cpu, SI_BOOT2_SMP, SI_ORDER_FIRST, cpu_startup, NULL)
149
150#ifdef DDB
151extern vm_offset_t ksym_start, ksym_end;
152#endif
153
da23a592 154struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
48ffc236 155
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156int _udatasel, _ucodesel, _ucode32sel;
157u_long atdevbase;
158#ifdef SMP
159int64_t tsc_offsets[MAXCPU];
160#else
161int64_t tsc_offsets[1];
162#endif
163
164#if defined(SWTCH_OPTIM_STATS)
165extern int swtch_optim_stats;
166SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
167 CTLFLAG_RD, &swtch_optim_stats, 0, "");
168SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
169 CTLFLAG_RD, &tlb_flush_count, 0, "");
170#endif
171
172int physmem = 0;
173
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174u_long ebda_addr = 0;
175
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176static int
177sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
178{
179 int error = sysctl_handle_int(oidp, 0, ctob(physmem), req);
180 return (error);
181}
182
183SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_INT|CTLFLAG_RD,
184 0, 0, sysctl_hw_physmem, "IU", "");
185
186static int
187sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
188{
189 int error = sysctl_handle_int(oidp, 0,
190 ctob(physmem - vmstats.v_wire_count), req);
191 return (error);
192}
193
194SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
195 0, 0, sysctl_hw_usermem, "IU", "");
196
197static int
198sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
199{
c8fe38ae 200 int error = sysctl_handle_int(oidp, 0,
b2b3ffcd 201 x86_64_btop(avail_end - avail_start), req);
c8fe38ae 202 return (error);
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203}
204
205SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
206 0, 0, sysctl_hw_availpages, "I", "");
207
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208vm_paddr_t Maxmem;
209vm_paddr_t Realmem;
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210
211/*
212 * The number of PHYSMAP entries must be one less than the number of
213 * PHYSSEG entries because the PHYSMAP entry that spans the largest
214 * physical address that is accessible by ISA DMA is split into two
215 * PHYSSEG entries.
216 */
217#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
218
219vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
220vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
221
222/* must be 2 less so 0 0 can signal end of chunks */
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223#define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
224#define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
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225
226static vm_offset_t buffer_sva, buffer_eva;
227vm_offset_t clean_sva, clean_eva;
228static vm_offset_t pager_sva, pager_eva;
229static struct trapframe proc0_tf;
230
231static void
232cpu_startup(void *dummy)
233{
234 caddr_t v;
235 vm_size_t size = 0;
236 vm_offset_t firstaddr;
237
238 if (boothowto & RB_VERBOSE)
239 bootverbose++;
240
241 /*
242 * Good {morning,afternoon,evening,night}.
243 */
244 kprintf("%s", version);
245 startrtclock();
246 printcpuinfo();
247 panicifcpuunsupported();
248#ifdef PERFMON
249 perfmon_init();
250#endif
15dc6550 251 kprintf("real memory = %ju (%ju MB)\n",
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252 (intmax_t)Realmem,
253 (intmax_t)Realmem / 1024 / 1024);
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254 /*
255 * Display any holes after the first chunk of extended memory.
256 */
257 if (bootverbose) {
258 int indx;
259
260 kprintf("Physical memory chunk(s):\n");
261 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
262 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
263
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264 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
265 (intmax_t)phys_avail[indx],
266 (intmax_t)phys_avail[indx + 1] - 1,
267 (intmax_t)size1,
268 (intmax_t)(size1 / PAGE_SIZE));
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269 }
270 }
271
272 /*
273 * Allocate space for system data structures.
274 * The first available kernel virtual address is in "v".
275 * As pages of kernel virtual memory are allocated, "v" is incremented.
276 * As pages of memory are allocated and cleared,
277 * "firstaddr" is incremented.
278 * An index into the kernel page table corresponding to the
279 * virtual memory address maintained in "v" is kept in "mapaddr".
280 */
281
282 /*
283 * Make two passes. The first pass calculates how much memory is
284 * needed and allocates it. The second pass assigns virtual
285 * addresses to the various data structures.
286 */
287 firstaddr = 0;
288again:
289 v = (caddr_t)firstaddr;
290
291#define valloc(name, type, num) \
292 (name) = (type *)v; v = (caddr_t)((name)+(num))
293#define valloclim(name, type, num, lim) \
294 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
295
296 /*
297 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
298 * For the first 64MB of ram nominally allocate sufficient buffers to
299 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
300 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
301 * the buffer cache we limit the eventual kva reservation to
302 * maxbcache bytes.
303 *
304 * factor represents the 1/4 x ram conversion.
305 */
306 if (nbuf == 0) {
307 int factor = 4 * BKVASIZE / 1024;
308 int kbytes = physmem * (PAGE_SIZE / 1024);
309
310 nbuf = 50;
311 if (kbytes > 4096)
312 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
313 if (kbytes > 65536)
314 nbuf += (kbytes - 65536) * 2 / (factor * 5);
315 if (maxbcache && nbuf > maxbcache / BKVASIZE)
316 nbuf = maxbcache / BKVASIZE;
317 }
318
319 /*
320 * Do not allow the buffer_map to be more then 1/2 the size of the
321 * kernel_map.
322 */
323 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
324 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
325 kprintf("Warning: nbufs capped at %d\n", nbuf);
326 }
327
328 nswbuf = max(min(nbuf/4, 256), 16);
329#ifdef NSWBUF_MIN
330 if (nswbuf < NSWBUF_MIN)
331 nswbuf = NSWBUF_MIN;
332#endif
333#ifdef DIRECTIO
334 ffs_rawread_setup();
335#endif
336
337 valloc(swbuf, struct buf, nswbuf);
338 valloc(buf, struct buf, nbuf);
339
340 /*
341 * End of first pass, size has been calculated so allocate memory
342 */
343 if (firstaddr == 0) {
344 size = (vm_size_t)(v - firstaddr);
345 firstaddr = kmem_alloc(&kernel_map, round_page(size));
346 if (firstaddr == 0)
347 panic("startup: no room for tables");
348 goto again;
349 }
350
351 /*
352 * End of second pass, addresses have been assigned
353 */
354 if ((vm_size_t)(v - firstaddr) != size)
355 panic("startup: table size inconsistency");
356
357 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
358 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
359 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
360 (nbuf*BKVASIZE));
361 buffer_map.system_map = 1;
362 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
363 (nswbuf*MAXPHYS) + pager_map_size);
364 pager_map.system_map = 1;
365
366#if defined(USERCONFIG)
367 userconfig();
368 cninit(); /* the preferred console may have changed */
369#endif
370
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371 kprintf("avail memory = %ju (%ju MB)\n",
372 (uintmax_t)ptoa(vmstats.v_free_count),
373 (uintmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
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374
375 /*
376 * Set up buffers, so they can be used to read disk labels.
377 */
378 bufinit();
379 vm_pager_bufferinit();
380
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381 /* Log ELCR information */
382 elcr_dump();
383
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384#ifdef SMP
385 /*
386 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
387 */
388 mp_start(); /* fire up the APs and APICs */
389 mp_announce();
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390#else
391 MachIntrABI.finalize();
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392#endif /* SMP */
393 cpu_setregs();
394}
395
396/*
397 * Send an interrupt to process.
398 *
399 * Stack is set up to allow sigcode stored
400 * at top to call routine, followed by kcall
401 * to sigreturn routine below. After sigreturn
402 * resets the signal mask, the stack, and the
403 * frame pointer, it returns to the user
404 * specified pc, psl.
405 */
406void
407sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
408{
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409 struct lwp *lp = curthread->td_lwp;
410 struct proc *p = lp->lwp_proc;
411 struct trapframe *regs;
412 struct sigacts *psp = p->p_sigacts;
413 struct sigframe sf, *sfp;
414 int oonstack;
a6a09809 415 char *sp;
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416
417 regs = lp->lwp_md.md_regs;
418 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
419
a6a09809 420 /* Save user context */
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421 bzero(&sf, sizeof(struct sigframe));
422 sf.sf_uc.uc_sigmask = *mask;
423 sf.sf_uc.uc_stack = lp->lwp_sigstk;
424 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
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425 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
426 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
c8fe38ae 427
a6a09809 428 /* Make the size of the saved context visible to userland */
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429 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
430
a6a09809 431 /* Save mailbox pending state for syscall interlock semantics */
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432 if (p->p_flag & P_MAILBOX)
433 sf.sf_uc.uc_mcontext.mc_xflags |= PGEX_MAILBOX;
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434
435 /* Allocate and validate space for the signal handler context. */
436 if ((lp->lwp_flag & LWP_ALTSTACK) != 0 && !oonstack &&
437 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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438 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
439 sizeof(struct sigframe));
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440 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
441 } else {
89954408
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442 /* We take red zone into account */
443 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
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444 }
445
a6a09809 446 /* Align to 16 bytes */
4117f2fd 447 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
a6a09809 448
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449 /* Translate the signal is appropriate */
450 if (p->p_sysent->sv_sigtbl) {
451 if (sig <= p->p_sysent->sv_sigsize)
452 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
453 }
454
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455 /*
456 * Build the argument list for the signal handler.
457 *
458 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
459 */
460 regs->tf_rdi = sig; /* argument 1 */
461 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
462
c8fe38ae 463 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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464 /*
465 * Signal handler installed with SA_SIGINFO.
466 *
467 * action(signo, siginfo, ucontext)
468 */
469 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
630d9ab4 470 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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471 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
472
473 /* fill siginfo structure */
474 sf.sf_si.si_signo = sig;
475 sf.sf_si.si_code = code;
630d9ab4 476 sf.sf_si.si_addr = (void *)regs->tf_addr;
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477 } else {
478 /*
479 * Old FreeBSD-style arguments.
480 *
481 * handler (signo, code, [uc], addr)
482 */
483 regs->tf_rsi = (register_t)code; /* argument 2 */
630d9ab4 484 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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485 sf.sf_ahu.sf_handler = catcher;
486 }
487
488 /*
489 * If we're a vm86 process, we want to save the segment registers.
490 * We also change eflags to be our emulated eflags, not the actual
491 * eflags.
492 */
493#if JG
494 if (regs->tf_eflags & PSL_VM) {
495 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
496 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
497
498 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
499 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
500 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
501 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
502
503 if (vm86->vm86_has_vme == 0)
504 sf.sf_uc.uc_mcontext.mc_eflags =
505 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
506 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
507
508 /*
509 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
510 * syscalls made by the signal handler. This just avoids
511 * wasting time for our lazy fixup of such faults. PSL_NT
512 * does nothing in vm86 mode, but vm86 programs can set it
513 * almost legitimately in probes for old cpu types.
514 */
515 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
516 }
517#endif
518
519 /*
520 * Save the FPU state and reinit the FP unit
521 */
c8fe38ae 522 npxpush(&sf.sf_uc.uc_mcontext);
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523
524 /*
525 * Copy the sigframe out to the user's stack.
526 */
527 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
528 /*
529 * Something is wrong with the stack pointer.
530 * ...Kill the process.
531 */
532 sigexit(lp, SIGILL);
533 }
534
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535 regs->tf_rsp = (register_t)sfp;
536 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
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537
538 /*
539 * i386 abi specifies that the direction flag must be cleared
540 * on function entry
541 */
5b9f6cc4 542 regs->tf_rflags &= ~(PSL_T|PSL_D);
c8fe38ae 543
c8fe38ae 544 /*
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545 * 64 bit mode has a code and stack selector but
546 * no data or extra selector. %fs and %gs are not
547 * stored in-context.
c8fe38ae 548 */
a6a09809 549 regs->tf_cs = _ucodesel;
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550 regs->tf_ss = _udatasel;
551}
552
553/*
554 * Sanitize the trapframe for a virtual kernel passing control to a custom
555 * VM context. Remove any items that would otherwise create a privilage
556 * issue.
557 *
558 * XXX at the moment we allow userland to set the resume flag. Is this a
559 * bad idea?
560 */
561int
562cpu_sanitize_frame(struct trapframe *frame)
563{
c8fe38ae 564 frame->tf_cs = _ucodesel;
c8fe38ae 565 frame->tf_ss = _udatasel;
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566 /* XXX VM (8086) mode not supported? */
567 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
568 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
569
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570 return(0);
571}
572
573/*
574 * Sanitize the tls so loading the descriptor does not blow up
b2b3ffcd 575 * on us. For x86_64 we don't have to do anything.
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576 */
577int
578cpu_sanitize_tls(struct savetls *tls)
579{
580 return(0);
581}
582
583/*
584 * sigreturn(ucontext_t *sigcntxp)
585 *
586 * System call to cleanup state after a signal
587 * has been taken. Reset signal mask and
588 * stack state from context left by sendsig (above).
589 * Return to previous pc and psl as specified by
590 * context left by sendsig. Check carefully to
591 * make sure that the user has not modified the
592 * state to gain improper privileges.
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593 *
594 * MPSAFE
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595 */
596#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
597#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
598
599int
600sys_sigreturn(struct sigreturn_args *uap)
601{
602 struct lwp *lp = curthread->td_lwp;
603 struct proc *p = lp->lwp_proc;
604 struct trapframe *regs;
605 ucontext_t uc;
606 ucontext_t *ucp;
5b9f6cc4 607 register_t rflags;
c8fe38ae 608 int cs;
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609 int error;
610
611 /*
612 * We have to copy the information into kernel space so userland
613 * can't modify it while we are sniffing it.
614 */
615 regs = lp->lwp_md.md_regs;
616 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
617 if (error)
618 return (error);
619 ucp = &uc;
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620 rflags = ucp->uc_mcontext.mc_rflags;
621
622 /* VM (8086) mode not supported */
623 rflags &= ~PSL_VM_UNSUPP;
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624
625#if JG
626 if (eflags & PSL_VM) {
627 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
628 struct vm86_kernel *vm86;
629
630 /*
631 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
632 * set up the vm86 area, and we can't enter vm86 mode.
633 */
634 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
635 return (EINVAL);
636 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
637 if (vm86->vm86_inited == 0)
638 return (EINVAL);
639
640 /* go back to user mode if both flags are set */
641 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
642 trapsignal(lp, SIGBUS, 0);
643
644 if (vm86->vm86_has_vme) {
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645 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
646 (eflags & VME_USERCHANGE) | PSL_VM;
c8fe38ae 647 } else {
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648 vm86->vm86_eflags = eflags; /* save VIF, VIP */
649 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
650 (eflags & VM_USERCHANGE) | PSL_VM;
c8fe38ae 651 }
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652 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
653 tf->tf_eflags = eflags;
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654 tf->tf_vm86_ds = tf->tf_ds;
655 tf->tf_vm86_es = tf->tf_es;
656 tf->tf_vm86_fs = tf->tf_fs;
657 tf->tf_vm86_gs = tf->tf_gs;
658 tf->tf_ds = _udatasel;
659 tf->tf_es = _udatasel;
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660 tf->tf_fs = _udatasel;
661 tf->tf_gs = _udatasel;
5b9f6cc4 662 } else
c8fe38ae 663#endif
5b9f6cc4 664 {
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665 /*
666 * Don't allow users to change privileged or reserved flags.
667 */
668 /*
669 * XXX do allow users to change the privileged flag PSL_RF.
670 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
671 * should sometimes set it there too. tf_eflags is kept in
672 * the signal context during signal handling and there is no
673 * other place to remember it, so the PSL_RF bit may be
674 * corrupted by the signal handler without us knowing.
675 * Corruption of the PSL_RF bit at worst causes one more or
676 * one less debugger trap, so allowing it is fairly harmless.
677 */
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678 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
679 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
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680 return(EINVAL);
681 }
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682
683 /*
684 * Don't allow users to load a valid privileged %cs. Let the
685 * hardware check for invalid selectors, excess privilege in
686 * other selectors, invalid %eip's and invalid %esp's.
687 */
688 cs = ucp->uc_mcontext.mc_cs;
689 if (!CS_SECURE(cs)) {
690 kprintf("sigreturn: cs = 0x%x\n", cs);
691 trapsignal(lp, SIGBUS, T_PROTFLT);
692 return(EINVAL);
693 }
5b9f6cc4 694 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
c8fe38ae 695 }
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696
697 /*
698 * Restore the FPU state from the frame
699 */
3919ced0 700 crit_enter();
c8fe38ae 701 npxpop(&ucp->uc_mcontext);
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702
703 /*
704 * Merge saved signal mailbox pending flag to maintain interlock
705 * semantics against system calls.
706 */
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707 if (ucp->uc_mcontext.mc_xflags & PGEX_MAILBOX)
708 p->p_flag |= P_MAILBOX;
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709
710 if (ucp->uc_mcontext.mc_onstack & 1)
711 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
712 else
713 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
714
715 lp->lwp_sigmask = ucp->uc_sigmask;
716 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 717 crit_exit();
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718 return(EJUSTRETURN);
719}
720
721/*
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722 * Stack frame on entry to function. %rax will contain the function vector,
723 * %rcx will contain the function data. flags, rcx, and rax will have
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724 * already been pushed on the stack.
725 */
726struct upc_frame {
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727 register_t rax;
728 register_t rcx;
729 register_t rdx;
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730 register_t flags;
731 register_t oldip;
732};
733
734void
735sendupcall(struct vmupcall *vu, int morepending)
736{
737 struct lwp *lp = curthread->td_lwp;
738 struct trapframe *regs;
739 struct upcall upcall;
740 struct upc_frame upc_frame;
741 int crit_count = 0;
742
743 /*
744 * If we are a virtual kernel running an emulated user process
745 * context, switch back to the virtual kernel context before
746 * trying to post the signal.
747 */
748 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
749 lp->lwp_md.md_regs->tf_trapno = 0;
750 vkernel_trap(lp, lp->lwp_md.md_regs);
751 }
752
753 /*
754 * Get the upcall data structure
755 */
756 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
757 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
758 ) {
759 vu->vu_pending = 0;
760 kprintf("bad upcall address\n");
761 return;
762 }
763
764 /*
765 * If the data structure is already marked pending or has a critical
766 * section count, mark the data structure as pending and return
767 * without doing an upcall. vu_pending is left set.
768 */
769 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
770 if (upcall.upc_pending < vu->vu_pending) {
771 upcall.upc_pending = vu->vu_pending;
772 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
773 sizeof(upcall.upc_pending));
774 }
775 return;
776 }
777
778 /*
779 * We can run this upcall now, clear vu_pending.
780 *
781 * Bump our critical section count and set or clear the
782 * user pending flag depending on whether more upcalls are
783 * pending. The user will be responsible for calling
784 * upc_dispatch(-1) to process remaining upcalls.
785 */
786 vu->vu_pending = 0;
787 upcall.upc_pending = morepending;
f9235b6d 788 ++crit_count;
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789 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
790 sizeof(upcall.upc_pending));
791 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
792 sizeof(int));
793
794 /*
795 * Construct a stack frame and issue the upcall
796 */
797 regs = lp->lwp_md.md_regs;
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798 upc_frame.rax = regs->tf_rax;
799 upc_frame.rcx = regs->tf_rcx;
800 upc_frame.rdx = regs->tf_rdx;
801 upc_frame.flags = regs->tf_rflags;
802 upc_frame.oldip = regs->tf_rip;
803 if (copyout(&upc_frame, (void *)(regs->tf_rsp - sizeof(upc_frame)),
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804 sizeof(upc_frame)) != 0) {
805 kprintf("bad stack on upcall\n");
806 } else {
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807 regs->tf_rax = (register_t)vu->vu_func;
808 regs->tf_rcx = (register_t)vu->vu_data;
809 regs->tf_rdx = (register_t)lp->lwp_upcall;
810 regs->tf_rip = (register_t)vu->vu_ctx;
811 regs->tf_rsp -= sizeof(upc_frame);
c8fe38ae 812 }
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813}
814
815/*
816 * fetchupcall occurs in the context of a system call, which means that
817 * we have to return EJUSTRETURN in order to prevent eax and edx from
818 * being overwritten by the syscall return value.
819 *
820 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
821 * and the function pointer in %eax.
822 */
823int
824fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
825{
826 struct upc_frame upc_frame;
827 struct lwp *lp = curthread->td_lwp;
828 struct trapframe *regs;
829 int error;
830 struct upcall upcall;
831 int crit_count;
832
833 regs = lp->lwp_md.md_regs;
834
835 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
836 if (error == 0) {
837 if (vu) {
838 /*
839 * This jumps us to the next ready context.
840 */
841 vu->vu_pending = 0;
842 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
843 crit_count = 0;
844 if (error == 0)
845 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 846 ++crit_count;
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847 if (error == 0)
848 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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849 regs->tf_rax = (register_t)vu->vu_func;
850 regs->tf_rcx = (register_t)vu->vu_data;
851 regs->tf_rdx = (register_t)lp->lwp_upcall;
852 regs->tf_rip = (register_t)vu->vu_ctx;
853 regs->tf_rsp = (register_t)rsp;
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854 } else {
855 /*
856 * This returns us to the originally interrupted code.
857 */
858 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
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859 regs->tf_rax = upc_frame.rax;
860 regs->tf_rcx = upc_frame.rcx;
861 regs->tf_rdx = upc_frame.rdx;
862 regs->tf_rflags = (regs->tf_rflags & ~PSL_USERCHANGE) |
c8fe38ae 863 (upc_frame.flags & PSL_USERCHANGE);
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864 regs->tf_rip = upc_frame.oldip;
865 regs->tf_rsp = (register_t)((char *)rsp + sizeof(upc_frame));
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866 }
867 }
868 if (error == 0)
869 error = EJUSTRETURN;
870 return(error);
871}
872
873/*
874 * Machine dependent boot() routine
875 *
876 * I haven't seen anything to put here yet
877 * Possibly some stuff might be grafted back here from boot()
878 */
879void
880cpu_boot(int howto)
881{
882}
883
884/*
885 * Shutdown the CPU as much as possible
886 */
887void
888cpu_halt(void)
889{
890 for (;;)
891 __asm__ __volatile("hlt");
892}
893
894/*
895 * cpu_idle() represents the idle LWKT. You cannot return from this function
896 * (unless you want to blow things up!). Instead we look for runnable threads
897 * and loop or halt as appropriate. Giant is not held on entry to the thread.
898 *
899 * The main loop is entered with a critical section held, we must release
900 * the critical section before doing anything else. lwkt_switch() will
901 * check for pending interrupts due to entering and exiting its own
902 * critical section.
903 *
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904 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
905 * However, there are cases where the idlethread will be entered with
906 * the possibility that no IPI will occur and in such cases
907 * lwkt_switch() sets TDF_IDLE_NOHLT.
908 *
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909 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
910 * 1 to just use hlt and for debugging purposes.
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911 *
912 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
913 * must occur before it starts using ACPI halt.
c8fe38ae 914 */
46e562ce 915static int cpu_idle_hlt = 2;
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916static int cpu_idle_hltcnt;
917static int cpu_idle_spincnt;
be71787b 918static u_int cpu_idle_repeat = 4;
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919SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
920 &cpu_idle_hlt, 0, "Idle loop HLT enable");
921SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
922 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
923SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
924 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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925SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
926 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
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927
928static void
929cpu_idle_default_hook(void)
930{
931 /*
932 * We must guarentee that hlt is exactly the instruction
933 * following the sti.
934 */
935 __asm __volatile("sti; hlt");
936}
937
938/* Other subsystems (e.g., ACPI) can hook this later. */
939void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
940
941void
942cpu_idle(void)
943{
0f0466c0 944 globaldata_t gd = mycpu;
86232a57 945 struct thread *td __debugvar = gd->gd_curthread;
0f0466c0 946 int reqflags;
be71787b 947 int quick;
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948
949 crit_exit();
f9235b6d 950 KKASSERT(td->td_critcount == 0);
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951 for (;;) {
952 /*
953 * See if there are any LWKTs ready to go.
954 */
955 lwkt_switch();
956
957 /*
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958 * When halting inside a cli we must check for reqflags
959 * races, particularly [re]schedule requests. Running
960 * splz() does the job.
961 *
962 * cpu_idle_hlt:
963 * 0 Never halt, just spin
964 *
965 * 1 Always use HLT (or MONITOR/MWAIT if avail).
966 * This typically eats more power than the
967 * ACPI halt.
968 *
969 * 2 Use HLT/MONITOR/MWAIT up to a point and then
970 * use the ACPI halt (default). This is a hybrid
971 * approach. See machdep.cpu_idle_repeat.
972 *
973 * 3 Always use the ACPI halt. This typically
974 * eats the least amount of power but the cpu
975 * will be slow waking up. Slows down e.g.
976 * compiles and other pipe/event oriented stuff.
977 *
978 * NOTE: Interrupts are enabled and we are not in a critical
979 * section.
980 *
981 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
982 * don't bother capping gd_idle_repeat, it is ok if
983 * it overflows.
c8fe38ae 984 */
be71787b 985 ++gd->gd_idle_repeat;
0f0466c0 986 reqflags = gd->gd_reqflags;
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987 quick = (cpu_idle_hlt == 1) ||
988 (cpu_idle_hlt < 3 &&
989 gd->gd_idle_repeat < cpu_idle_repeat);
990
991 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
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992 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
993 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
be71787b 994 ++cpu_idle_hltcnt;
0f0466c0 995 } else if (cpu_idle_hlt) {
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996 __asm __volatile("cli");
997 splz();
0f0466c0 998 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
be71787b 999 if (quick)
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1000 cpu_idle_default_hook();
1001 else
1002 cpu_idle_hook();
1003 }
7d4d6fdb 1004 __asm __volatile("sti");
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1005 ++cpu_idle_hltcnt;
1006 } else {
c8fe38ae 1007 splz();
c5724852 1008 __asm __volatile("sti");
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1009 ++cpu_idle_spincnt;
1010 }
1011 }
1012}
1013
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1014#ifdef SMP
1015
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1016/*
1017 * This routine is called if a spinlock has been held through the
1018 * exponential backoff period and is seriously contested. On a real cpu
1019 * we let it spin.
1020 */
1021void
1022cpu_spinlock_contested(void)
1023{
1024 cpu_pause();
1025}
1026
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1027#endif
1028
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1029/*
1030 * Clear registers on exec
1031 */
1032void
1033exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1034{
1035 struct thread *td = curthread;
1036 struct lwp *lp = td->td_lwp;
1037 struct pcb *pcb = td->td_pcb;
1038 struct trapframe *regs = lp->lwp_md.md_regs;
1039
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1040 /* was i386_user_cleanup() in NetBSD */
1041 user_ldt_free(pcb);
1042
1043 bzero((char *)regs, sizeof(struct trapframe));
1044 regs->tf_rip = entry;
1045 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1046 regs->tf_rdi = stack; /* argv */
1047 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1048 regs->tf_ss = _udatasel;
1049 regs->tf_cs = _ucodesel;
1050 regs->tf_rbx = ps_strings;
1051
1052 /*
1053 * Reset the hardware debug registers if they were in use.
1054 * They won't have any meaning for the newly exec'd process.
1055 */
1056 if (pcb->pcb_flags & PCB_DBREGS) {
1057 pcb->pcb_dr0 = 0;
1058 pcb->pcb_dr1 = 0;
1059 pcb->pcb_dr2 = 0;
1060 pcb->pcb_dr3 = 0;
1061 pcb->pcb_dr6 = 0;
0855a2af 1062 pcb->pcb_dr7 = 0; /* JG set bit 10? */
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1063 if (pcb == td->td_pcb) {
1064 /*
1065 * Clear the debug registers on the running
1066 * CPU, otherwise they will end up affecting
1067 * the next process we switch to.
1068 */
1069 reset_dbregs();
1070 }
1071 pcb->pcb_flags &= ~PCB_DBREGS;
1072 }
1073
1074 /*
1075 * Initialize the math emulator (if any) for the current process.
1076 * Actually, just clear the bit that says that the emulator has
1077 * been initialized. Initialization is delayed until the process
1078 * traps to the emulator (if it is done at all) mainly because
1079 * emulators don't provide an entry point for initialization.
1080 */
c8fe38ae 1081 pcb->pcb_flags &= ~FP_SOFTFP;
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1082
1083 /*
5b9f6cc4
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1084 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1085 * gd_npxthread. Otherwise a preemptive interrupt thread
1086 * may panic in npxdna().
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1087 */
1088 crit_enter();
1089 load_cr0(rcr0() | CR0_MP);
1090
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1091 /*
1092 * NOTE: The MSR values must be correct so we can return to
1093 * userland. gd_user_fs/gs must be correct so the switch
1094 * code knows what the current MSR values are.
1095 */
1096 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
c8fe38ae 1097 pcb->pcb_gsbase = 0;
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1098 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1099 mdcpu->gd_user_gs = 0;
1100 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1101 wrmsr(MSR_KGSBASE, 0);
c8fe38ae 1102
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1103 /* Initialize the npx (if any) for the current process. */
1104 npxinit(__INITIAL_NPXCW__);
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1105 crit_exit();
1106
1107 pcb->pcb_ds = _udatasel;
1108 pcb->pcb_es = _udatasel;
1109 pcb->pcb_fs = _udatasel;
1110 pcb->pcb_gs = _udatasel;
1111}
1112
1113void
1114cpu_setregs(void)
1115{
1116 register_t cr0;
1117
1118 cr0 = rcr0();
1119 cr0 |= CR0_NE; /* Done by npxinit() */
1120 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1121 cr0 |= CR0_WP | CR0_AM;
1122 load_cr0(cr0);
1123 load_gs(_udatasel);
1124}
1125
1126static int
1127sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1128{
1129 int error;
1130 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1131 req);
1132 if (!error && req->newptr)
1133 resettodr();
1134 return (error);
1135}
1136
1137SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1138 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1139
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1140SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1141 CTLFLAG_RW, &disable_rtc_set, 0, "");
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1142
1143#if JG
1144SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1145 CTLFLAG_RD, &bootinfo, bootinfo, "");
1146#endif
1147
1148SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1149 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1150
1151extern u_long bootdev; /* not a cdev_t - encoding is different */
1152SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1153 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1154
1155/*
1156 * Initialize 386 and configure to run kernel
1157 */
1158
1159/*
1160 * Initialize segments & interrupt table
1161 */
1162
1163int _default_ldt;
1164struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1165static struct gate_descriptor idt0[NIDT];
1166struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1167#if JG
1168union descriptor ldt[NLDT]; /* local descriptor table */
1169#endif
1170
1171/* table descriptors - used to load tables by cpu */
1172struct region_descriptor r_gdt, r_idt;
1173
1174#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1175extern int has_f00f_bug;
1176#endif
1177
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1178/* JG proc0paddr is a virtual address */
1179void *proc0paddr;
1180/* JG alignment? */
1181char proc0paddr_buff[LWKT_THREAD_STACK];
1182
1183
1184/* software prototypes -- in more palatable form */
1185struct soft_segment_descriptor gdt_segs[] = {
1186/* GNULL_SEL 0 Null Descriptor */
1187{ 0x0, /* segment base address */
1188 0x0, /* length */
1189 0, /* segment type */
1190 0, /* segment descriptor priority level */
1191 0, /* segment descriptor present */
1192 0, /* long */
1193 0, /* default 32 vs 16 bit size */
1194 0 /* limit granularity (byte/page units)*/ },
1195/* GCODE_SEL 1 Code Descriptor for kernel */
1196{ 0x0, /* segment base address */
1197 0xfffff, /* length - all address space */
1198 SDT_MEMERA, /* segment type */
1199 SEL_KPL, /* segment descriptor priority level */
1200 1, /* segment descriptor present */
1201 1, /* long */
1202 0, /* default 32 vs 16 bit size */
1203 1 /* limit granularity (byte/page units)*/ },
1204/* GDATA_SEL 2 Data Descriptor for kernel */
1205{ 0x0, /* segment base address */
1206 0xfffff, /* length - all address space */
1207 SDT_MEMRWA, /* segment type */
1208 SEL_KPL, /* segment descriptor priority level */
1209 1, /* segment descriptor present */
1210 1, /* long */
1211 0, /* default 32 vs 16 bit size */
1212 1 /* limit granularity (byte/page units)*/ },
1213/* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1214{ 0x0, /* segment base address */
1215 0xfffff, /* length - all address space */
1216 SDT_MEMERA, /* segment type */
1217 SEL_UPL, /* segment descriptor priority level */
1218 1, /* segment descriptor present */
1219 0, /* long */
1220 1, /* default 32 vs 16 bit size */
1221 1 /* limit granularity (byte/page units)*/ },
1222/* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1223{ 0x0, /* segment base address */
1224 0xfffff, /* length - all address space */
1225 SDT_MEMRWA, /* segment type */
1226 SEL_UPL, /* segment descriptor priority level */
1227 1, /* segment descriptor present */
1228 0, /* long */
1229 1, /* default 32 vs 16 bit size */
1230 1 /* limit granularity (byte/page units)*/ },
1231/* GUCODE_SEL 5 64 bit Code Descriptor for user */
1232{ 0x0, /* segment base address */
1233 0xfffff, /* length - all address space */
1234 SDT_MEMERA, /* segment type */
1235 SEL_UPL, /* segment descriptor priority level */
1236 1, /* segment descriptor present */
1237 1, /* long */
1238 0, /* default 32 vs 16 bit size */
1239 1 /* limit granularity (byte/page units)*/ },
1240/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1241{
1242 0x0, /* segment base address */
b2b3ffcd 1243 sizeof(struct x86_64tss)-1,/* length - all address space */
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MD
1244 SDT_SYSTSS, /* segment type */
1245 SEL_KPL, /* segment descriptor priority level */
1246 1, /* segment descriptor present */
1247 0, /* long */
1248 0, /* unused - default 32 vs 16 bit size */
1249 0 /* limit granularity (byte/page units)*/ },
1250/* Actually, the TSS is a system descriptor which is double size */
1251{ 0x0, /* segment base address */
1252 0x0, /* length */
1253 0, /* segment type */
1254 0, /* segment descriptor priority level */
1255 0, /* segment descriptor present */
1256 0, /* long */
1257 0, /* default 32 vs 16 bit size */
1258 0 /* limit granularity (byte/page units)*/ },
1259/* GUGS32_SEL 8 32 bit GS Descriptor for user */
1260{ 0x0, /* segment base address */
1261 0xfffff, /* length - all address space */
1262 SDT_MEMRWA, /* segment type */
1263 SEL_UPL, /* segment descriptor priority level */
1264 1, /* segment descriptor present */
1265 0, /* long */
1266 1, /* default 32 vs 16 bit size */
1267 1 /* limit granularity (byte/page units)*/ },
1268};
1269
1270void
1271setidt(int idx, inthand_t *func, int typ, int dpl, int ist)
1272{
1273 struct gate_descriptor *ip;
1274
1275 ip = idt + idx;
1276 ip->gd_looffset = (uintptr_t)func;
1277 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1278 ip->gd_ist = ist;
1279 ip->gd_xx = 0;
1280 ip->gd_type = typ;
1281 ip->gd_dpl = dpl;
1282 ip->gd_p = 1;
1283 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1284}
1285
1286#define IDTVEC(name) __CONCAT(X,name)
1287
1288extern inthand_t
1289 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1290 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1291 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1292 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1293 IDTVEC(xmm), IDTVEC(dblfault),
1294 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1295
1296#ifdef DEBUG_INTERRUPTS
1297extern inthand_t *Xrsvdary[256];
1298#endif
1299
1300void
1301sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1302{
1303 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1304 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1305 ssd->ssd_type = sd->sd_type;
1306 ssd->ssd_dpl = sd->sd_dpl;
1307 ssd->ssd_p = sd->sd_p;
1308 ssd->ssd_def32 = sd->sd_def32;
1309 ssd->ssd_gran = sd->sd_gran;
1310}
1311
1312void
1313ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1314{
1315
1316 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1317 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1318 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1319 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1320 sd->sd_type = ssd->ssd_type;
1321 sd->sd_dpl = ssd->ssd_dpl;
1322 sd->sd_p = ssd->ssd_p;
1323 sd->sd_long = ssd->ssd_long;
1324 sd->sd_def32 = ssd->ssd_def32;
1325 sd->sd_gran = ssd->ssd_gran;
1326}
1327
1328void
1329ssdtosyssd(struct soft_segment_descriptor *ssd,
1330 struct system_segment_descriptor *sd)
1331{
1332
1333 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1334 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1335 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1336 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1337 sd->sd_type = ssd->ssd_type;
1338 sd->sd_dpl = ssd->ssd_dpl;
1339 sd->sd_p = ssd->ssd_p;
1340 sd->sd_gran = ssd->ssd_gran;
1341}
1342
c8fe38ae
MD
1343/*
1344 * Populate the (physmap) array with base/bound pairs describing the
1345 * available physical memory in the system, then test this memory and
1346 * build the phys_avail array describing the actually-available memory.
1347 *
1348 * If we cannot accurately determine the physical memory map, then use
1349 * value from the 0xE801 call, and failing that, the RTC.
1350 *
1351 * Total memory size may be set by the kernel environment variable
1352 * hw.physmem or the compile-time define MAXMEM.
1353 *
b4d9abe2
MD
1354 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1355 * of PAGE_SIZE. This also greatly reduces the memory test time
1356 * which would otherwise be excessive on machines with > 8G of ram.
1357 *
c8fe38ae
MD
1358 * XXX first should be vm_paddr_t.
1359 */
b4d9abe2
MD
1360
1361#define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1362#define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1363
c8fe38ae
MD
1364static void
1365getmemsize(caddr_t kmdp, u_int64_t first)
1366{
b4d9abe2
MD
1367 int off, physmap_idx, pa_indx, da_indx;
1368 int i, j;
1369 vm_paddr_t physmap[PHYSMAP_SIZE];
1370 vm_paddr_t pa;
1371 vm_paddr_t msgbuf_size;
c8fe38ae
MD
1372 u_long physmem_tunable;
1373 pt_entry_t *pte;
1374 struct bios_smap *smapbase, *smap, *smapend;
1375 u_int32_t smapsize;
1376 quad_t dcons_addr, dcons_size;
1377
1378 bzero(physmap, sizeof(physmap));
c8fe38ae
MD
1379 physmap_idx = 0;
1380
1381 /*
1382 * get memory map from INT 15:E820, kindly supplied by the loader.
1383 *
1384 * subr_module.c says:
1385 * "Consumer may safely assume that size value precedes data."
1386 * ie: an int32_t immediately precedes smap.
1387 */
1388 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1389 MODINFO_METADATA | MODINFOMD_SMAP);
1390 if (smapbase == NULL)
1391 panic("No BIOS smap info from loader!");
1392
1393 smapsize = *((u_int32_t *)smapbase - 1);
1394 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1395
1396 for (smap = smapbase; smap < smapend; smap++) {
1397 if (boothowto & RB_VERBOSE)
1398 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1399 smap->type, smap->base, smap->length);
1400
1401 if (smap->type != SMAP_TYPE_MEMORY)
1402 continue;
1403
1404 if (smap->length == 0)
1405 continue;
1406
1407 for (i = 0; i <= physmap_idx; i += 2) {
1408 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1409 if (boothowto & RB_VERBOSE) {
1410 kprintf("Overlapping or non-monotonic "
1411 "memory region, ignoring "
1412 "second region\n");
1413 }
c8fe38ae
MD
1414 continue;
1415 }
1416 }
1bda0d3d 1417 Realmem += smap->length;
c8fe38ae
MD
1418
1419 if (smap->base == physmap[physmap_idx + 1]) {
1420 physmap[physmap_idx + 1] += smap->length;
1421 continue;
1422 }
1423
1424 physmap_idx += 2;
1425 if (physmap_idx == PHYSMAP_SIZE) {
1bda0d3d
MD
1426 kprintf("Too many segments in the physical "
1427 "address map, giving up\n");
c8fe38ae
MD
1428 break;
1429 }
1430 physmap[physmap_idx] = smap->base;
1431 physmap[physmap_idx + 1] = smap->base + smap->length;
1432 }
1433
c8fe38ae
MD
1434#ifdef SMP
1435 /* make hole for AP bootstrap code */
1436 physmap[1] = mp_bootaddress(physmap[1] / 1024);
2331304b 1437
927c4c1f
MN
1438 /* Save EBDA address, if any */
1439 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1440 ebda_addr <<= 4;
c8fe38ae
MD
1441#endif
1442
1443 /*
1444 * Maxmem isn't the "maximum memory", it's one larger than the
1445 * highest page of the physical address space. It should be
1446 * called something like "Maxphyspage". We may adjust this
1447 * based on ``hw.physmem'' and the results of the memory test.
1448 */
1449 Maxmem = atop(physmap[physmap_idx + 1]);
1450
1451#ifdef MAXMEM
1452 Maxmem = MAXMEM / 4;
1453#endif
1454
1455 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1456 Maxmem = atop(physmem_tunable);
1457
1458 /*
1459 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1460 * in the system.
1461 */
1462 if (Maxmem > atop(physmap[physmap_idx + 1]))
1463 Maxmem = atop(physmap[physmap_idx + 1]);
1464
8e5ea5f7 1465 /*
b4d9abe2 1466 * Blowing out the DMAP will blow up the system.
8e5ea5f7
MD
1467 */
1468 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1469 kprintf("Limiting Maxmem due to DMAP size\n");
1470 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1471 }
1472
c8fe38ae 1473 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
b4d9abe2 1474 (boothowto & RB_VERBOSE)) {
c8fe38ae 1475 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
b4d9abe2 1476 }
c8fe38ae 1477
b4d9abe2
MD
1478 /*
1479 * Call pmap initialization to make new kernel address space
1480 *
1481 * Mask off page 0.
1482 */
48ffc236 1483 pmap_bootstrap(&first);
b4d9abe2
MD
1484 physmap[0] = PAGE_SIZE;
1485
1486 /*
1487 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1488 * exceeding Maxmem.
1489 */
1490 for (i = j = 0; i <= physmap_idx; i += 2) {
1491 if (physmap[i+1] > ptoa((vm_paddr_t)Maxmem))
1492 physmap[i+1] = ptoa((vm_paddr_t)Maxmem);
1493 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1494 ~PHYSMAP_ALIGN_MASK;
1495 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1496
1497 physmap[j] = physmap[i];
1498 physmap[j+1] = physmap[i+1];
1499
1500 if (physmap[i] < physmap[i+1])
1501 j += 2;
1502 }
1503 physmap_idx = j - 2;
1504
1505 /*
1506 * Align anything else used in the validation loop.
1507 */
1508 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
c8fe38ae
MD
1509
1510 /*
1511 * Size up each available chunk of physical memory.
1512 */
c8fe38ae
MD
1513 pa_indx = 0;
1514 da_indx = 1;
1515 phys_avail[pa_indx++] = physmap[0];
1516 phys_avail[pa_indx] = physmap[0];
1517 dump_avail[da_indx] = physmap[0];
1518 pte = CMAP1;
1519
1520 /*
1521 * Get dcons buffer address
1522 */
1523 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1524 kgetenv_quad("dcons.size", &dcons_size) == 0)
1525 dcons_addr = 0;
1526
1527 /*
b4d9abe2
MD
1528 * Validate the physical memory. The physical memory segments
1529 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1530 * of PAGE_SIZE.
c8fe38ae
MD
1531 */
1532 for (i = 0; i <= physmap_idx; i += 2) {
1533 vm_paddr_t end;
1534
b4d9abe2
MD
1535 end = physmap[i + 1];
1536
1537 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
c8fe38ae
MD
1538 int tmp, page_bad, full;
1539 int *ptr = (int *)CADDR1;
1540
1541 full = FALSE;
1542 /*
1543 * block out kernel memory as not available.
1544 */
1545 if (pa >= 0x100000 && pa < first)
1546 goto do_dump_avail;
1547
1548 /*
1549 * block out dcons buffer
1550 */
1551 if (dcons_addr > 0
1552 && pa >= trunc_page(dcons_addr)
b4d9abe2 1553 && pa < dcons_addr + dcons_size) {
c8fe38ae 1554 goto do_dump_avail;
b4d9abe2 1555 }
c8fe38ae
MD
1556
1557 page_bad = FALSE;
1558
1559 /*
1560 * map page into kernel: valid, read/write,non-cacheable
1561 */
1562 *pte = pa | PG_V | PG_RW | PG_N;
1563 cpu_invltlb();
1564
1565 tmp = *(int *)ptr;
1566 /*
1567 * Test for alternating 1's and 0's
1568 */
1569 *(volatile int *)ptr = 0xaaaaaaaa;
b4d9abe2 1570 cpu_mfence();
c8fe38ae
MD
1571 if (*(volatile int *)ptr != 0xaaaaaaaa)
1572 page_bad = TRUE;
1573 /*
1574 * Test for alternating 0's and 1's
1575 */
1576 *(volatile int *)ptr = 0x55555555;
b4d9abe2 1577 cpu_mfence();
c8fe38ae
MD
1578 if (*(volatile int *)ptr != 0x55555555)
1579 page_bad = TRUE;
1580 /*
1581 * Test for all 1's
1582 */
1583 *(volatile int *)ptr = 0xffffffff;
b4d9abe2 1584 cpu_mfence();
c8fe38ae
MD
1585 if (*(volatile int *)ptr != 0xffffffff)
1586 page_bad = TRUE;
1587 /*
1588 * Test for all 0's
1589 */
1590 *(volatile int *)ptr = 0x0;
b4d9abe2 1591 cpu_mfence();
c8fe38ae
MD
1592 if (*(volatile int *)ptr != 0x0)
1593 page_bad = TRUE;
1594 /*
1595 * Restore original value.
1596 */
1597 *(int *)ptr = tmp;
1598
1599 /*
1600 * Adjust array of valid/good pages.
1601 */
1602 if (page_bad == TRUE)
1603 continue;
1604 /*
1605 * If this good page is a continuation of the
1606 * previous set of good pages, then just increase
1607 * the end pointer. Otherwise start a new chunk.
1608 * Note that "end" points one higher than end,
1609 * making the range >= start and < end.
1610 * If we're also doing a speculative memory
1611 * test and we at or past the end, bump up Maxmem
1612 * so that we keep going. The first bad page
1613 * will terminate the loop.
1614 */
1615 if (phys_avail[pa_indx] == pa) {
b4d9abe2 1616 phys_avail[pa_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1617 } else {
1618 pa_indx++;
1619 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1620 kprintf(
1621 "Too many holes in the physical address space, giving up\n");
1622 pa_indx--;
1623 full = TRUE;
1624 goto do_dump_avail;
1625 }
b4d9abe2
MD
1626 phys_avail[pa_indx++] = pa;
1627 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1628 }
1629 physmem++;
1630do_dump_avail:
1631 if (dump_avail[da_indx] == pa) {
b4d9abe2 1632 dump_avail[da_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1633 } else {
1634 da_indx++;
1635 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1636 da_indx--;
1637 goto do_next;
1638 }
b4d9abe2
MD
1639 dump_avail[da_indx++] = pa;
1640 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1641 }
1642do_next:
1643 if (full)
1644 break;
1645 }
1646 }
1647 *pte = 0;
1648 cpu_invltlb();
1649
1650 /*
c8fe38ae
MD
1651 * The last chunk must contain at least one page plus the message
1652 * buffer to avoid complicating other code (message buffer address
1653 * calculation, etc.).
1654 */
b4d9abe2
MD
1655 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1656
1657 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1658 msgbuf_size >= phys_avail[pa_indx]) {
c8fe38ae
MD
1659 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1660 phys_avail[pa_indx--] = 0;
1661 phys_avail[pa_indx--] = 0;
1662 }
1663
1664 Maxmem = atop(phys_avail[pa_indx]);
1665
1666 /* Trim off space for the message buffer. */
b4d9abe2 1667 phys_avail[pa_indx] -= msgbuf_size;
c8fe38ae 1668
1185babf
JG
1669 avail_end = phys_avail[pa_indx];
1670
c8fe38ae 1671 /* Map the message buffer. */
b4d9abe2
MD
1672 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1673 pmap_kenter((vm_offset_t)msgbufp + off,
1674 phys_avail[pa_indx] + off);
1675 }
c8fe38ae
MD
1676}
1677
faaf4131 1678#ifdef SMP
eac0bf8f
MD
1679#ifdef APIC_IO
1680int apic_io_enable = 1; /* Enabled by default for kernels compiled w/APIC_IO */
1681#else
1682int apic_io_enable = 0; /* Disabled by default for kernels compiled without */
1683#endif
faaf4131 1684TUNABLE_INT("hw.apic_io_enable", &apic_io_enable);
faaf4131
MN
1685#endif
1686
faaf4131
MN
1687struct machintr_abi MachIntrABI;
1688
c8fe38ae
MD
1689/*
1690 * IDT VECTORS:
1691 * 0 Divide by zero
1692 * 1 Debug
1693 * 2 NMI
1694 * 3 BreakPoint
1695 * 4 OverFlow
1696 * 5 Bound-Range
1697 * 6 Invalid OpCode
1698 * 7 Device Not Available (x87)
1699 * 8 Double-Fault
1700 * 9 Coprocessor Segment overrun (unsupported, reserved)
1701 * 10 Invalid-TSS
1702 * 11 Segment not present
1703 * 12 Stack
1704 * 13 General Protection
1705 * 14 Page Fault
1706 * 15 Reserved
1707 * 16 x87 FP Exception pending
1708 * 17 Alignment Check
1709 * 18 Machine Check
1710 * 19 SIMD floating point
1711 * 20-31 reserved
1712 * 32-255 INTn/external sources
1713 */
1714u_int64_t
1715hammer_time(u_int64_t modulep, u_int64_t physfree)
1716{
1717 caddr_t kmdp;
5b9f6cc4
MD
1718 int gsel_tss, x;
1719#if JG
1720 int metadata_missing, off;
1721#endif
c8fe38ae
MD
1722 struct mdglobaldata *gd;
1723 u_int64_t msr;
c8fe38ae 1724
c8fe38ae
MD
1725 /*
1726 * Prevent lowering of the ipl if we call tsleep() early.
1727 */
1728 gd = &CPU_prvspace[0].mdglobaldata;
1729 bzero(gd, sizeof(*gd));
1730
1731 /*
1732 * Note: on both UP and SMP curthread must be set non-NULL
1733 * early in the boot sequence because the system assumes
1734 * that 'curthread' is never NULL.
1735 */
1736
1737 gd->mi.gd_curthread = &thread0;
1738 thread0.td_gd = &gd->mi;
1739
1740 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1741
1742#if JG
1743 metadata_missing = 0;
1744 if (bootinfo.bi_modulep) {
1745 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1746 preload_bootstrap_relocate(KERNBASE);
1747 } else {
1748 metadata_missing = 1;
1749 }
1750 if (bootinfo.bi_envp)
1751 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1752#endif
1753
1754 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1755 preload_bootstrap_relocate(PTOV_OFFSET);
1756 kmdp = preload_search_by_type("elf kernel");
1757 if (kmdp == NULL)
1758 kmdp = preload_search_by_type("elf64 kernel");
1759 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1760 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1761#ifdef DDB
1762 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1763 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1764#endif
1765
faaf4131 1766 /*
10db3cc6 1767 * Default MachIntrABI to ICU
faaf4131
MN
1768 */
1769 MachIntrABI = MachIntrABI_ICU;
1770#ifdef SMP
1771 TUNABLE_INT_FETCH("hw.apic_io_enable", &apic_io_enable);
faaf4131
MN
1772#endif
1773
c8fe38ae
MD
1774 /*
1775 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1776 * and ncpus_fit_mask remain 0.
1777 */
1778 ncpus = 1;
1779 ncpus2 = 1;
1780 ncpus_fit = 1;
1781 /* Init basic tunables, hz etc */
1782 init_param1();
1783
1784 /*
1785 * make gdt memory segments
1786 */
1787 gdt_segs[GPROC0_SEL].ssd_base =
1788 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1789
1790 gd->mi.gd_prvspace = &CPU_prvspace[0];
1791
1792 for (x = 0; x < NGDT; x++) {
1793 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1794 ssdtosd(&gdt_segs[x], &gdt[x]);
1795 }
1796 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1797 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
48ffc236 1798
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MD
1799 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1800 r_gdt.rd_base = (long) gdt;
1801 lgdt(&r_gdt);
1802
1803 wrmsr(MSR_FSBASE, 0); /* User value */
1804 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1805 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1806
1807 mi_gdinit(&gd->mi, 0);
1808 cpu_gdinit(gd, 0);
1809 proc0paddr = proc0paddr_buff;
1810 mi_proc0init(&gd->mi, proc0paddr);
1811 safepri = TDPRI_MAX;
1812
1813 /* spinlocks and the BGL */
1814 init_locks();
1815
1816 /* exceptions */
1817 for (x = 0; x < NIDT; x++)
1818 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1819 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1820 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1821 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1822 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1823 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1824 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1825 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1826 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1827 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1828 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1829 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1830 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1831 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1832 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1833 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1834 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1835 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1836 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1837 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1838
1839 r_idt.rd_limit = sizeof(idt0) - 1;
1840 r_idt.rd_base = (long) idt;
1841 lidt(&r_idt);
1842
1843 /*
1844 * Initialize the console before we print anything out.
1845 */
1846 cninit();
1847
1848#if JG
1849 if (metadata_missing)
1850 kprintf("WARNING: loader(8) metadata is missing!\n");
1851#endif
1852
1853#if NISA >0
e24dd6e0 1854 elcr_probe();
c8fe38ae
MD
1855 isa_defaultirq();
1856#endif
1857 rand_initialize();
1858
1859#ifdef DDB
1860 kdb_init();
1861 if (boothowto & RB_KDB)
1862 Debugger("Boot flags requested debugger");
1863#endif
1864
1865#if JG
1866 finishidentcpu(); /* Final stage of CPU initialization */
2883d2d8
MD
1867 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1868 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
c8fe38ae
MD
1869#endif
1870 identify_cpu(); /* Final stage of CPU initialization */
1871 initializecpu(); /* Initialize CPU registers */
1872
1873 /* make an initial tss so cpu can get interrupt stack on syscall! */
5b9f6cc4
MD
1874 gd->gd_common_tss.tss_rsp0 =
1875 (register_t)(thread0.td_kstack +
1876 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
c8fe38ae 1877 /* Ensure the stack is aligned to 16 bytes */
2883d2d8 1878 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
c8fe38ae 1879
093565f2
MD
1880 /* double fault stack */
1881 gd->gd_common_tss.tss_ist1 =
1882 (long)&gd->mi.gd_prvspace->idlestack[
1883 sizeof(gd->mi.gd_prvspace->idlestack)];
c8fe38ae
MD
1884
1885 /* Set the IO permission bitmap (empty due to tss seg limit) */
b2b3ffcd 1886 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
c8fe38ae
MD
1887
1888 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1889 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1890 gd->gd_common_tssd = *gd->gd_tss_gdt;
1891 ltr(gsel_tss);
1892
1893 /* Set up the fast syscall stuff */
1894 msr = rdmsr(MSR_EFER) | EFER_SCE;
1895 wrmsr(MSR_EFER, msr);
1896 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1897 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1898 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1899 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1900 wrmsr(MSR_STAR, msr);
1901 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
1902
1903 getmemsize(kmdp, physfree);
1904 init_param2(physmem);
1905
1906 /* now running on new page tables, configured,and u/iom is accessible */
1907
1908 /* Map the message buffer. */
1909#if JG
1910 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1911 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1912#endif
1913
1914 msgbufinit(msgbufp, MSGBUF_SIZE);
1915
1916
1917 /* transfer to user mode */
1918
1919 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1920 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1921 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1922
1923 load_ds(_udatasel);
1924 load_es(_udatasel);
1925 load_fs(_udatasel);
1926
1927 /* setup proc 0's pcb */
1928 thread0.td_pcb->pcb_flags = 0;
c8fe38ae 1929 thread0.td_pcb->pcb_cr3 = KPML4phys;
c8fe38ae 1930 thread0.td_pcb->pcb_ext = 0;
d1368d1a 1931 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
c8fe38ae
MD
1932
1933 /* Location of kernel stack for locore */
1934 return ((u_int64_t)thread0.td_pcb);
1935}
1936
1937/*
1938 * Initialize machine-dependant portions of the global data structure.
1939 * Note that the global data area and cpu0's idlestack in the private
1940 * data space were allocated in locore.
1941 *
1942 * Note: the idlethread's cpl is 0
1943 *
1944 * WARNING! Called from early boot, 'mycpu' may not work yet.
1945 */
1946void
1947cpu_gdinit(struct mdglobaldata *gd, int cpu)
1948{
1949 if (cpu)
1950 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
1951
1952 lwkt_init_thread(&gd->mi.gd_idlethread,
1953 gd->mi.gd_prvspace->idlestack,
1954 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 1955 0, &gd->mi);
c8fe38ae
MD
1956 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
1957 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
1958 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
1959 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
1960}
1961
1962int
1963is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
1964{
1965 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
1966 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
1967 return (TRUE);
1968 }
1969 return (FALSE);
1970}
1971
1972struct globaldata *
1973globaldata_find(int cpu)
1974{
1975 KKASSERT(cpu >= 0 && cpu < ncpus);
1976 return(&CPU_prvspace[cpu].mdglobaldata.mi);
1977}
1978
1979#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1980static void f00f_hack(void *unused);
1981SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
1982
1983static void
1984f00f_hack(void *unused)
1985{
1986 struct gate_descriptor *new_idt;
1987 vm_offset_t tmp;
1988
1989 if (!has_f00f_bug)
1990 return;
1991
1992 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
1993
1994 r_idt.rd_limit = sizeof(idt0) - 1;
1995
1996 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
1997 if (tmp == 0)
1998 panic("kmem_alloc returned 0");
1999 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2000 panic("kmem_alloc returned non-page-aligned memory");
2001 /* Put the first seven entries in the lower page */
2002 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2003 bcopy(idt, new_idt, sizeof(idt0));
2004 r_idt.rd_base = (int)new_idt;
2005 lidt(&r_idt);
2006 idt = new_idt;
2007 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
2008 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2009 panic("vm_map_protect failed");
2010 return;
2011}
2012#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2013
2014int
2015ptrace_set_pc(struct lwp *lp, unsigned long addr)
2016{
5b9f6cc4 2017 lp->lwp_md.md_regs->tf_rip = addr;
c8fe38ae
MD
2018 return (0);
2019}
2020
2021int
2022ptrace_single_step(struct lwp *lp)
2023{
5b9f6cc4 2024 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
c8fe38ae
MD
2025 return (0);
2026}
2027
2028int
2029fill_regs(struct lwp *lp, struct reg *regs)
2030{
c8fe38ae
MD
2031 struct trapframe *tp;
2032
2033 tp = lp->lwp_md.md_regs;
5b9f6cc4 2034 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
c8fe38ae
MD
2035 return (0);
2036}
2037
2038int
2039set_regs(struct lwp *lp, struct reg *regs)
2040{
c8fe38ae
MD
2041 struct trapframe *tp;
2042
2043 tp = lp->lwp_md.md_regs;
5b9f6cc4 2044 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
c8fe38ae
MD
2045 !CS_SECURE(regs->r_cs))
2046 return (EINVAL);
5b9f6cc4 2047 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
c8fe38ae
MD
2048 return (0);
2049}
2050
2051#ifndef CPU_DISABLE_SSE
2052static void
2053fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2054{
2055 struct env87 *penv_87 = &sv_87->sv_env;
2056 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2057 int i;
2058
2059 /* FPU control/status */
2060 penv_87->en_cw = penv_xmm->en_cw;
2061 penv_87->en_sw = penv_xmm->en_sw;
2062 penv_87->en_tw = penv_xmm->en_tw;
2063 penv_87->en_fip = penv_xmm->en_fip;
2064 penv_87->en_fcs = penv_xmm->en_fcs;
2065 penv_87->en_opcode = penv_xmm->en_opcode;
2066 penv_87->en_foo = penv_xmm->en_foo;
2067 penv_87->en_fos = penv_xmm->en_fos;
2068
2069 /* FPU registers */
2070 for (i = 0; i < 8; ++i)
2071 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2072
2073 sv_87->sv_ex_sw = sv_xmm->sv_ex_sw;
2074}
2075
2076static void
2077set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2078{
2079 struct env87 *penv_87 = &sv_87->sv_env;
2080 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2081 int i;
2082
2083 /* FPU control/status */
2084 penv_xmm->en_cw = penv_87->en_cw;
2085 penv_xmm->en_sw = penv_87->en_sw;
2086 penv_xmm->en_tw = penv_87->en_tw;
2087 penv_xmm->en_fip = penv_87->en_fip;
2088 penv_xmm->en_fcs = penv_87->en_fcs;
2089 penv_xmm->en_opcode = penv_87->en_opcode;
2090 penv_xmm->en_foo = penv_87->en_foo;
2091 penv_xmm->en_fos = penv_87->en_fos;
2092
2093 /* FPU registers */
2094 for (i = 0; i < 8; ++i)
2095 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2096
2097 sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
2098}
2099#endif /* CPU_DISABLE_SSE */
2100
2101int
2102fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2103{
2104#ifndef CPU_DISABLE_SSE
2105 if (cpu_fxsr) {
2106 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2107 (struct save87 *)fpregs);
2108 return (0);
2109 }
2110#endif /* CPU_DISABLE_SSE */
2111 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2112 return (0);
2113}
2114
2115int
2116set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2117{
2118#ifndef CPU_DISABLE_SSE
2119 if (cpu_fxsr) {
2120 set_fpregs_xmm((struct save87 *)fpregs,
2121 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2122 return (0);
2123 }
2124#endif /* CPU_DISABLE_SSE */
2125 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2126 return (0);
2127}
2128
2129int
2130fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2131{
2132 if (lp == NULL) {
0855a2af
JG
2133 dbregs->dr[0] = rdr0();
2134 dbregs->dr[1] = rdr1();
2135 dbregs->dr[2] = rdr2();
2136 dbregs->dr[3] = rdr3();
2137 dbregs->dr[4] = rdr4();
2138 dbregs->dr[5] = rdr5();
2139 dbregs->dr[6] = rdr6();
2140 dbregs->dr[7] = rdr7();
c8fe38ae
MD
2141 } else {
2142 struct pcb *pcb;
2143
2144 pcb = lp->lwp_thread->td_pcb;
0855a2af
JG
2145 dbregs->dr[0] = pcb->pcb_dr0;
2146 dbregs->dr[1] = pcb->pcb_dr1;
2147 dbregs->dr[2] = pcb->pcb_dr2;
2148 dbregs->dr[3] = pcb->pcb_dr3;
2149 dbregs->dr[4] = 0;
2150 dbregs->dr[5] = 0;
2151 dbregs->dr[6] = pcb->pcb_dr6;
2152 dbregs->dr[7] = pcb->pcb_dr7;
c8fe38ae
MD
2153 }
2154 return (0);
2155}
2156
2157int
2158set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2159{
2160 if (lp == NULL) {
0855a2af
JG
2161 load_dr0(dbregs->dr[0]);
2162 load_dr1(dbregs->dr[1]);
2163 load_dr2(dbregs->dr[2]);
2164 load_dr3(dbregs->dr[3]);
2165 load_dr4(dbregs->dr[4]);
2166 load_dr5(dbregs->dr[5]);
2167 load_dr6(dbregs->dr[6]);
2168 load_dr7(dbregs->dr[7]);
c8fe38ae
MD
2169 } else {
2170 struct pcb *pcb;
2171 struct ucred *ucred;
2172 int i;
0855a2af 2173 uint64_t mask1, mask2;
c8fe38ae
MD
2174
2175 /*
2176 * Don't let an illegal value for dr7 get set. Specifically,
2177 * check for undefined settings. Setting these bit patterns
2178 * result in undefined behaviour and can lead to an unexpected
2179 * TRCTRAP.
2180 */
0855a2af
JG
2181 /* JG this loop looks unreadable */
2182 /* Check 4 2-bit fields for invalid patterns.
2183 * These fields are R/Wi, for i = 0..3
2184 */
2185 /* Is 10 in LENi allowed when running in compatibility mode? */
2186 /* Pattern 10 in R/Wi might be used to indicate
2187 * breakpoint on I/O. Further analysis should be
2188 * carried to decide if it is safe and useful to
2189 * provide access to that capability
2190 */
2191 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2192 i++, mask1 <<= 4, mask2 <<= 4)
2193 if ((dbregs->dr[7] & mask1) == mask2)
c8fe38ae 2194 return (EINVAL);
c8fe38ae
MD
2195
2196 pcb = lp->lwp_thread->td_pcb;
2197 ucred = lp->lwp_proc->p_ucred;
2198
2199 /*
2200 * Don't let a process set a breakpoint that is not within the
2201 * process's address space. If a process could do this, it
2202 * could halt the system by setting a breakpoint in the kernel
2203 * (if ddb was enabled). Thus, we need to check to make sure
2204 * that no breakpoints are being enabled for addresses outside
2205 * process's address space, unless, perhaps, we were called by
2206 * uid 0.
2207 *
2208 * XXX - what about when the watched area of the user's
2209 * address space is written into from within the kernel
2210 * ... wouldn't that still cause a breakpoint to be generated
2211 * from within kernel mode?
2212 */
2213
895c1f85 2214 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
0855a2af 2215 if (dbregs->dr[7] & 0x3) {
c8fe38ae 2216 /* dr0 is enabled */
0855a2af 2217 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2218 return (EINVAL);
2219 }
2220
0855a2af 2221 if (dbregs->dr[7] & (0x3<<2)) {
c8fe38ae 2222 /* dr1 is enabled */
0855a2af 2223 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2224 return (EINVAL);
2225 }
2226
0855a2af 2227 if (dbregs->dr[7] & (0x3<<4)) {
c8fe38ae 2228 /* dr2 is enabled */
0855a2af 2229 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2230 return (EINVAL);
2231 }
2232
0855a2af 2233 if (dbregs->dr[7] & (0x3<<6)) {
c8fe38ae 2234 /* dr3 is enabled */
0855a2af 2235 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2236 return (EINVAL);
2237 }
c8fe38ae
MD
2238 }
2239
0855a2af
JG
2240 pcb->pcb_dr0 = dbregs->dr[0];
2241 pcb->pcb_dr1 = dbregs->dr[1];
2242 pcb->pcb_dr2 = dbregs->dr[2];
2243 pcb->pcb_dr3 = dbregs->dr[3];
2244 pcb->pcb_dr6 = dbregs->dr[6];
2245 pcb->pcb_dr7 = dbregs->dr[7];
c8fe38ae
MD
2246
2247 pcb->pcb_flags |= PCB_DBREGS;
2248 }
2249
2250 return (0);
2251}
2252
2253/*
2254 * Return > 0 if a hardware breakpoint has been hit, and the
2255 * breakpoint was in user space. Return 0, otherwise.
2256 */
2257int
2258user_dbreg_trap(void)
2259{
0855a2af
JG
2260 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2261 u_int64_t bp; /* breakpoint bits extracted from dr6 */
c8fe38ae
MD
2262 int nbp; /* number of breakpoints that triggered */
2263 caddr_t addr[4]; /* breakpoint addresses */
2264 int i;
2265
2266 dr7 = rdr7();
0855a2af 2267 if ((dr7 & 0xff) == 0) {
c8fe38ae
MD
2268 /*
2269 * all GE and LE bits in the dr7 register are zero,
2270 * thus the trap couldn't have been caused by the
2271 * hardware debug registers
2272 */
2273 return 0;
2274 }
2275
2276 nbp = 0;
2277 dr6 = rdr6();
0855a2af 2278 bp = dr6 & 0xf;
c8fe38ae 2279
0855a2af 2280 if (bp == 0) {
c8fe38ae
MD
2281 /*
2282 * None of the breakpoint bits are set meaning this
2283 * trap was not caused by any of the debug registers
2284 */
2285 return 0;
2286 }
2287
2288 /*
2289 * at least one of the breakpoints were hit, check to see
2290 * which ones and if any of them are user space addresses
2291 */
2292
2293 if (bp & 0x01) {
2294 addr[nbp++] = (caddr_t)rdr0();
2295 }
2296 if (bp & 0x02) {
2297 addr[nbp++] = (caddr_t)rdr1();
2298 }
2299 if (bp & 0x04) {
2300 addr[nbp++] = (caddr_t)rdr2();
2301 }
2302 if (bp & 0x08) {
2303 addr[nbp++] = (caddr_t)rdr3();
2304 }
2305
2306 for (i=0; i<nbp; i++) {
2307 if (addr[i] <
2308 (caddr_t)VM_MAX_USER_ADDRESS) {
2309 /*
2310 * addr[i] is in user space
2311 */
2312 return nbp;
2313 }
2314 }
2315
2316 /*
2317 * None of the breakpoints are in user space.
2318 */
2319 return 0;
2320}
2321
2322
2323#ifndef DDB
2324void
2325Debugger(const char *msg)
2326{
2327 kprintf("Debugger(\"%s\") called.\n", msg);
2328}
2329#endif /* no DDB */
2330
2331#ifdef DDB
2332
2333/*
2334 * Provide inb() and outb() as functions. They are normally only
2335 * available as macros calling inlined functions, thus cannot be
2336 * called inside DDB.
2337 *
2338 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2339 */
2340
2341#undef inb
2342#undef outb
2343
2344/* silence compiler warnings */
2345u_char inb(u_int);
2346void outb(u_int, u_char);
2347
2348u_char
2349inb(u_int port)
2350{
2351 u_char data;
2352 /*
2353 * We use %%dx and not %1 here because i/o is done at %dx and not at
2354 * %edx, while gcc generates inferior code (movw instead of movl)
2355 * if we tell it to load (u_short) port.
2356 */
2357 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2358 return (data);
2359}
2360
2361void
2362outb(u_int port, u_char data)
2363{
2364 u_char al;
2365 /*
2366 * Use an unnecessary assignment to help gcc's register allocator.
2367 * This make a large difference for gcc-1.40 and a tiny difference
2368 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2369 * best results. gcc-2.6.0 can't handle this.
2370 */
2371 al = data;
2372 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2373}
2374
2375#endif /* DDB */
2376
2377
2378
2379#include "opt_cpu.h"
2380
2381
2382/*
2383 * initialize all the SMP locks
2384 */
2385
2386/* critical region when masking or unmasking interupts */
2387struct spinlock_deprecated imen_spinlock;
2388
c8fe38ae
MD
2389/* critical region for old style disable_intr/enable_intr */
2390struct spinlock_deprecated mpintr_spinlock;
2391
2392/* critical region around INTR() routines */
2393struct spinlock_deprecated intr_spinlock;
2394
2395/* lock region used by kernel profiling */
2396struct spinlock_deprecated mcount_spinlock;
2397
2398/* locks com (tty) data/hardware accesses: a FASTINTR() */
2399struct spinlock_deprecated com_spinlock;
2400
c8fe38ae
MD
2401/* lock regions around the clock hardware */
2402struct spinlock_deprecated clock_spinlock;
2403
c8fe38ae
MD
2404static void
2405init_locks(void)
2406{
b5d16701 2407#ifdef SMP
c8fe38ae 2408 /*
b5d16701 2409 * Get the initial mplock with a count of 1 for the BSP.
c8fe38ae
MD
2410 * This uses a LOGICAL cpu ID, ie BSP == 0.
2411 */
c8fe38ae
MD
2412 cpu_get_initial_mplock();
2413#endif
2414 /* DEPRECATED */
2415 spin_lock_init(&mcount_spinlock);
c8fe38ae
MD
2416 spin_lock_init(&intr_spinlock);
2417 spin_lock_init(&mpintr_spinlock);
2418 spin_lock_init(&imen_spinlock);
c8fe38ae
MD
2419 spin_lock_init(&com_spinlock);
2420 spin_lock_init(&clock_spinlock);
c8fe38ae
MD
2421
2422 /* our token pool needs to work early */
2423 lwkt_token_pool_init();
2424}
2425