intr: Further delay MachIntrABI.finalize()
[dragonfly.git] / sys / platform / vkernel64 / platform / machintr.c
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1/*
2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/platform/vkernel/platform/machintr.c,v 1.17 2008/04/30 16:59:45 dillon Exp $
35 */
36
37#include <sys/types.h>
38#include <sys/systm.h>
39#include <sys/kernel.h>
40#include <sys/machintr.h>
41#include <sys/errno.h>
42#include <sys/mman.h>
43#include <sys/globaldata.h>
44#include <sys/interrupt.h>
45#include <stdio.h>
46#include <signal.h>
47#include <machine/globaldata.h>
48#include <machine/md_var.h>
49#include <sys/thread2.h>
50
51/*
52 * Interrupt Subsystem ABI
53 */
54
55static void dummy_intrdis(int);
56static void dummy_intren(int);
57static int dummy_vectorctl(int, int, int);
58static int dummy_setvar(int, const void *);
59static int dummy_getvar(int, void *);
60static void dummy_finalize(void);
61static void dummy_intrcleanup(void);
7bf5fa56 62static void dummy_stabilize(void);
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63
64struct machintr_abi MachIntrABI = {
65 MACHINTR_GENERIC,
66 .intrdis = dummy_intrdis,
67 .intren = dummy_intren,
68 .vectorctl = dummy_vectorctl,
69 .setvar = dummy_setvar,
70 .getvar = dummy_getvar,
71 .finalize = dummy_finalize,
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72 .cleanup = dummy_intrcleanup,
73 .stabilize = dummy_stabilize
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74};
75
76static void
77dummy_intrdis(int intr)
78{
79}
80
81static void
82dummy_intren(int intr)
83{
84}
85
86static int
87dummy_vectorctl(int op, int intr, int flags)
88{
89 return (0);
90 /* return (EOPNOTSUPP); */
91}
92
93static int
94dummy_setvar(int varid, const void *buf)
95{
96 return (ENOENT);
97}
98
99static int
100dummy_getvar(int varid, void *buf)
101{
102 return (ENOENT);
103}
104
105static void
106dummy_finalize(void)
107{
108}
109
110static void
111dummy_intrcleanup(void)
112{
113}
114
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115static void
116dummy_stabilize(void)
117{
118}
119
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120/*
121 * Process pending interrupts
122 */
123void
124splz(void)
125{
126 struct mdglobaldata *gd = mdcpu;
127 thread_t td = gd->mi.gd_curthread;
128 int irq;
129
130 while (gd->mi.gd_reqflags & (RQF_IPIQ|RQF_INTPEND)) {
131 crit_enter_quick(td);
132#ifdef SMP
133 if (gd->mi.gd_reqflags & RQF_IPIQ) {
2a418930 134 atomic_clear_int(&gd->mi.gd_reqflags, RQF_IPIQ);
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135 lwkt_process_ipiq();
136 }
137#endif
138 if (gd->mi.gd_reqflags & RQF_INTPEND) {
2a418930 139 atomic_clear_int(&gd->mi.gd_reqflags, RQF_INTPEND);
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140 while ((irq = ffs(gd->gd_spending)) != 0) {
141 --irq;
142 atomic_clear_int(&gd->gd_spending, 1 << irq);
143 irq += FIRST_SOFTINT;
144 sched_ithd(irq);
145 }
146 while ((irq = ffs(gd->gd_fpending)) != 0) {
147 --irq;
148 atomic_clear_int(&gd->gd_fpending, 1 << irq);
149 sched_ithd(irq);
150 }
151 }
152 crit_exit_noyield(td);
153 }
154}
155
156/*
157 * Allows an unprotected signal handler or mailbox to signal an interrupt
158 *
159 * For sched_ithd() to properly preempt via lwkt_schedule() we cannot
160 * enter a critical section here. We use td_nest_count instead.
161 */
162void
163signalintr(int intr)
164{
165 struct mdglobaldata *gd = mdcpu;
166 thread_t td = gd->mi.gd_curthread;
167
f9235b6d 168 if (td->td_critcount || td->td_nest_count) {
da673940 169 atomic_set_int_nonlocked(&gd->gd_fpending, 1 << intr);
2a418930 170 atomic_set_int(&gd->mi.gd_reqflags, RQF_INTPEND);
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171 } else {
172 ++td->td_nest_count;
173 atomic_clear_int(&gd->gd_fpending, 1 << intr);
174 sched_ithd(intr);
175 --td->td_nest_count;
176 }
177}
178
179void
180cpu_disable_intr(void)
181{
182 sigblock(sigmask(SIGALRM)|sigmask(SIGIO));
183}
184
185void
186cpu_enable_intr(void)
187{
188 sigsetmask(0);
189}
190
191void
192cpu_mask_all_signals(void)
193{
194 sigblock(sigmask(SIGALRM)|sigmask(SIGIO)|sigmask(SIGQUIT)|
195 sigmask(SIGUSR1)|sigmask(SIGTERM)|sigmask(SIGWINCH)|
196 sigmask(SIGUSR2));
197}
198
199void
200cpu_unmask_all_signals(void)
201{
202 sigsetmask(0);
203}
204
205void
206cpu_invlpg(void *addr)
207{
208 madvise(addr, PAGE_SIZE, MADV_INVAL);
209}
210
211void
212cpu_invltlb(void)
213{
214 madvise((void *)KvaStart, KvaEnd - KvaStart, MADV_INVAL);
215}