Correct the logical_cpus calculation in mptable_hyperthread_fixup()
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
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27 */
28
29#include "opt_cpu.h"
984263bc 30
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31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
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34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
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39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
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45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
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51
52#include <machine/smp.h>
a9295349 53#include <machine_base/apic/apicreg.h>
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54#include <machine/atomic.h>
55#include <machine/cpufunc.h>
a9295349 56#include <machine_base/apic/mpapic.h>
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57#include <machine/psl.h>
58#include <machine/segments.h>
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59#include <machine/tss.h>
60#include <machine/specialreg.h>
61#include <machine/globaldata.h>
62
984263bc 63#include <machine/md_var.h> /* setidt() */
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64#include <machine_base/icu/icu.h> /* IPIs */
65#include <machine_base/isa/intr_machdep.h> /* IPIs */
984263bc 66
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67#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
68
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69#define WARMBOOT_TARGET 0
70#define WARMBOOT_OFF (KERNBASE + 0x0467)
71#define WARMBOOT_SEG (KERNBASE + 0x0469)
72
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73#define BIOS_BASE (0xf0000)
74#define BIOS_SIZE (0x10000)
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75#define BIOS_COUNT (BIOS_SIZE/4)
76
77#define CMOS_REG (0x70)
78#define CMOS_DATA (0x71)
79#define BIOS_RESET (0x0f)
80#define BIOS_WARM (0x0a)
81
82#define PROCENTRY_FLAG_EN 0x01
83#define PROCENTRY_FLAG_BP 0x02
84#define IOAPICENTRY_FLAG_EN 0x01
85
86
87/* MP Floating Pointer Structure */
88typedef struct MPFPS {
89 char signature[4];
981bebd1 90 u_int32_t pap;
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91 u_char length;
92 u_char spec_rev;
93 u_char checksum;
94 u_char mpfb1;
95 u_char mpfb2;
96 u_char mpfb3;
97 u_char mpfb4;
98 u_char mpfb5;
99} *mpfps_t;
100
101/* MP Configuration Table Header */
102typedef struct MPCTH {
103 char signature[4];
104 u_short base_table_length;
105 u_char spec_rev;
106 u_char checksum;
107 u_char oem_id[8];
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
111 u_short entry_count;
112 void *apic_address;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
115 u_char reserved;
116} *mpcth_t;
117
118
119typedef struct PROCENTRY {
120 u_char type;
121 u_char apic_id;
122 u_char apic_version;
123 u_char cpu_flags;
124 u_long cpu_signature;
125 u_long feature_flags;
126 u_long reserved1;
127 u_long reserved2;
128} *proc_entry_ptr;
129
130typedef struct BUSENTRY {
131 u_char type;
132 u_char bus_id;
133 char bus_type[6];
134} *bus_entry_ptr;
135
136typedef struct IOAPICENTRY {
137 u_char type;
138 u_char apic_id;
139 u_char apic_version;
140 u_char apic_flags;
141 void *apic_address;
142} *io_apic_entry_ptr;
143
144typedef struct INTENTRY {
145 u_char type;
146 u_char int_type;
147 u_short int_flags;
148 u_char src_bus_id;
149 u_char src_bus_irq;
150 u_char dst_apic_id;
151 u_char dst_apic_int;
152} *int_entry_ptr;
153
154/* descriptions of MP basetable entries */
155typedef struct BASETABLE_ENTRY {
156 u_char type;
157 u_char length;
158 char name[16];
159} basetable_entry;
160
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161struct mptable_pos {
162 mpfps_t mp_fps;
163 mpcth_t mp_cth;
164 vm_size_t mp_cth_mapsz;
165};
166
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167/*
168 * this code MUST be enabled here and in mpboot.s.
169 * it follows the very early stages of AP boot by placing values in CMOS ram.
170 * it NORMALLY will never be needed and thus the primitive method for enabling.
171 *
984263bc 172 */
7d34994c 173#if defined(CHECK_POINTS)
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174#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
175#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
176
177#define CHECK_INIT(D); \
178 CHECK_WRITE(0x34, (D)); \
179 CHECK_WRITE(0x35, (D)); \
180 CHECK_WRITE(0x36, (D)); \
181 CHECK_WRITE(0x37, (D)); \
182 CHECK_WRITE(0x38, (D)); \
183 CHECK_WRITE(0x39, (D));
184
185#define CHECK_PRINT(S); \
26be20a0 186 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
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187 (S), \
188 CHECK_READ(0x34), \
189 CHECK_READ(0x35), \
190 CHECK_READ(0x36), \
191 CHECK_READ(0x37), \
192 CHECK_READ(0x38), \
193 CHECK_READ(0x39));
194
195#else /* CHECK_POINTS */
196
197#define CHECK_INIT(D)
198#define CHECK_PRINT(S)
199
200#endif /* CHECK_POINTS */
201
202/*
203 * Values to send to the POST hardware.
204 */
205#define MP_BOOTADDRESS_POST 0x10
206#define MP_PROBE_POST 0x11
207#define MPTABLE_PASS1_POST 0x12
208
209#define MP_START_POST 0x13
210#define MP_ENABLE_POST 0x14
211#define MPTABLE_PASS2_POST 0x15
212
213#define START_ALL_APS_POST 0x16
214#define INSTALL_AP_TRAMP_POST 0x17
215#define START_AP_POST 0x18
216
217#define MP_ANNOUNCE_POST 0x19
218
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219static int need_hyperthreading_fixup;
220static u_int logical_cpus;
48add334 221u_int logical_cpus_mask;
984263bc 222
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223static int madt_probe_test;
224TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
225
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226/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227int current_postcode;
228
229/** XXX FIXME: what system files declare these??? */
230extern struct region_descriptor r_gdt, r_idt;
231
232int bsp_apic_ready = 0; /* flags useability of BSP apic */
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233int mp_naps; /* # of Applications processors */
234int mp_nbusses; /* # of busses */
97359a5b 235#ifdef APIC_IO
984263bc 236int mp_napics; /* # of IO APICs */
97359a5b 237#endif
984263bc 238vm_offset_t cpu_apic_address;
97359a5b 239#ifdef APIC_IO
984263bc 240vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
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241u_int32_t *io_apic_versions;
242#endif
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243extern int nkpt;
244
245u_int32_t cpu_apic_versions[MAXCPU];
374133e3 246int64_t tsc0_offset;
0b698dca 247extern int64_t tsc_offsets[];
984263bc 248
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249extern u_long ebda_addr;
250
97359a5b 251#ifdef APIC_IO
8a8d5d85 252struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 253#endif
984263bc 254
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255/*
256 * APIC ID logical/physical mapping structures.
257 * We oversize these to simplify boot-time config.
258 */
259int cpu_num_to_apic_id[NAPICID];
97359a5b 260#ifdef APIC_IO
984263bc 261int io_num_to_apic_id[NAPICID];
97359a5b 262#endif
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263int apic_id_to_logical[NAPICID];
264
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265/* AP uses this during bootstrap. Do not staticize. */
266char *bootSTK;
267static int bootAP;
268
269/* Hotwire a 0->4MB V==P mapping */
270extern pt_entry_t *KPTphys;
271
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272/*
273 * SMP page table page. Setup by locore to point to a page table
274 * page from which we allocate per-cpu privatespace areas io_apics,
275 * and so forth.
276 */
277
278#define IO_MAPPING_START_INDEX \
279 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
280
984263bc 281extern pt_entry_t *SMPpt;
f13b5eec 282static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
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283
284struct pcb stoppcbs[MAXCPU];
285
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286/*
287 * Local data and functions.
288 */
289
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290static u_int boot_address;
291static u_int base_memory;
41a01a4d 292static int mp_finish;
984263bc 293
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294static void mp_enable(u_int boot_addr);
295
cb00b5c4 296static int mptable_probe(void);
3aba8f73 297static int mptable_search_sig(u_int32_t target, int count);
984263bc 298static void mptable_hyperthread_fixup(u_int id_mask);
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299static void mptable_pass1(struct mptable_pos *);
300static int mptable_pass2(struct mptable_pos *);
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301static void mptable_default(int type);
302static void mptable_fix(void);
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303static void mptable_map(struct mptable_pos *, vm_paddr_t);
304static void mptable_unmap(struct mptable_pos *);
3aba8f73 305
97359a5b 306#ifdef APIC_IO
984263bc 307static void setup_apic_irq_mapping(void);
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308static int apic_int_is_bus_type(int intr, int bus_type);
309#endif
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310static int start_all_aps(u_int boot_addr);
311static void install_ap_tramp(u_int boot_addr);
0f7a3396 312static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
984263bc 313
41a01a4d 314static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
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315cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
316SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
317
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318/*
319 * Calculate usable address in base memory for AP trampoline code.
320 */
321u_int
322mp_bootaddress(u_int basemem)
323{
324 POSTCODE(MP_BOOTADDRESS_POST);
325
c0c5de70 326 base_memory = basemem;
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327
328 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
329 if ((base_memory - boot_address) < bootMP_size)
330 boot_address -= 4096; /* not enough, lower by 4k */
331
332 return boot_address;
333}
334
335
336/*
337 * Look for an Intel MP spec table (ie, SMP capable hardware).
338 */
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339static int
340mptable_probe(void)
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341{
342 int x;
984263bc 343 u_int32_t target;
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344
345 /*
346 * Make sure our SMPpt[] page table is big enough to hold all the
347 * mappings we need.
348 */
349 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
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350
351 POSTCODE(MP_PROBE_POST);
352
353 /* see if EBDA exists */
1876681a 354 if (ebda_addr != 0) {
984263bc 355 /* search first 1K of EBDA */
1876681a 356 target = (u_int32_t)ebda_addr;
3aba8f73 357 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 358 return x;
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359 } else {
360 /* last 1K of base memory, effective 'top of base' passed in */
aeb48299 361 target = (u_int32_t)(base_memory - 0x400);
3aba8f73 362 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 363 return x;
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364 }
365
366 /* search the BIOS */
aeb48299 367 target = (u_int32_t)BIOS_BASE;
3aba8f73 368 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
aeb48299 369 return x;
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370
371 /* nothing found */
984263bc 372 return 0;
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373}
374
375
376/*
377 * Startup the SMP processors.
378 */
379void
380mp_start(void)
381{
382 POSTCODE(MP_START_POST);
50bc991e 383 mp_enable(boot_address);
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384}
385
386
387/*
388 * Print various information about the SMP system hardware and setup.
389 */
390void
391mp_announce(void)
392{
393 int x;
394
395 POSTCODE(MP_ANNOUNCE_POST);
396
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397 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
398 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
399 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
400 kprintf(", at 0x%08x\n", cpu_apic_address);
984263bc 401 for (x = 1; x <= mp_naps; ++x) {
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402 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
403 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
404 kprintf(", at 0x%08x\n", cpu_apic_address);
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405 }
406
407#if defined(APIC_IO)
408 for (x = 0; x < mp_napics; ++x) {
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409 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
410 kprintf(", version: 0x%08x", io_apic_versions[x]);
411 kprintf(", at 0x%08x\n", io_apic_address[x]);
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412 }
413#else
26be20a0 414 kprintf(" Warning: APIC I/O disabled\n");
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415#endif /* APIC_IO */
416}
417
418/*
419 * AP cpu's call this to sync up protected mode.
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420 *
421 * WARNING! We must ensure that the cpu is sufficiently initialized to
422 * be able to use to the FP for our optimized bzero/bcopy code before
423 * we enter more mainstream C code.
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424 *
425 * WARNING! %fs is not set up on entry. This routine sets up %fs.
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426 */
427void
428init_secondary(void)
429{
430 int gsel_tss;
431 int x, myid = bootAP;
432 u_int cr0;
8a8d5d85 433 struct mdglobaldata *md;
0f7a3396 434 struct privatespace *ps;
984263bc 435
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436 ps = &CPU_prvspace[myid];
437
438 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 439 gdt_segs[GPROC0_SEL].ssd_base =
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440 (int) &ps->mdglobaldata.gd_common_tss;
441 ps->mdglobaldata.mi.gd_prvspace = ps;
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442
443 for (x = 0; x < NGDT; x++) {
444 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
445 }
446
447 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
448 r_gdt.rd_base = (int) &gdt[myid * NGDT];
449 lgdt(&r_gdt); /* does magic intra-segment return */
450
451 lidt(&r_idt);
452
453 lldt(_default_ldt);
7b95be2a 454 mdcpu->gd_currentldt = _default_ldt;
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455
456 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
457 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 458
0f7a3396 459 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
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460
461 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
462 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
463 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
464 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
465 md->gd_common_tssd = *md->gd_tss_gdt;
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466 ltr(gsel_tss);
467
468 /*
469 * Set to a known state:
470 * Set by mpboot.s: CR0_PG, CR0_PE
471 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
472 */
473 cr0 = rcr0();
474 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
475 load_cr0(cr0);
7160572f 476 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 477
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478 /* set up CPU registers and state */
479 cpu_setregs();
480
481 /* set up FPU state on the AP */
482 npxinit(__INITIAL_NPXCW__);
483
484 /* set up SSE registers */
485 enable_sse();
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486}
487
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488/*******************************************************************
489 * local functions and data
490 */
491
492/*
493 * start the SMP system
494 */
495static void
496mp_enable(u_int boot_addr)
497{
498 int x;
499#if defined(APIC_IO)
500 int apic;
501 u_int ux;
502#endif /* APIC_IO */
981bebd1 503 vm_paddr_t mpfps_paddr;
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504
505 POSTCODE(MP_ENABLE_POST);
506
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507 if (madt_probe_test)
508 mpfps_paddr = 0;
509 else
510 mpfps_paddr = mptable_probe();
85fd9f87 511
a26bbcd5 512 if (mpfps_paddr) {
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513 struct mptable_pos mpt;
514
a26bbcd5 515 mptable_map(&mpt, mpfps_paddr);
0f85efa2 516
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517 /*
518 * We can safely map physical memory into SMPpt after
519 * mptable_pass1() completes.
520 */
521 mptable_pass1(&mpt);
984263bc 522
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523 if (cpu_apic_address == 0)
524 panic("mp_enable: no local apic (mptable)!\n");
f9c3b04f 525
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526 /*
527 * Examine the MP table for needed info
528 */
529 x = mptable_pass2(&mpt);
f9c3b04f 530
a26bbcd5 531 mptable_unmap(&mpt);
984263bc 532
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533 /* Local apic is mapped on last page */
534 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
535 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
984263bc 536
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537 /*
538 * Can't process default configs till the
539 * CPU APIC is pmapped
540 */
541 if (x)
542 mptable_default(x);
f9c3b04f 543
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544 /* Post scan cleanup */
545 mptable_fix();
546 } else {
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547 vm_paddr_t madt_paddr;
548 int bsp_apic_id;
549
550 madt_paddr = madt_probe();
551 if (madt_paddr == 0)
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552 panic("mp_enable: madt_probe failed\n");
553
223bf214 554 cpu_apic_address = madt_pass1(madt_paddr);
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555 if (cpu_apic_address == 0)
556 panic("mp_enable: no local apic (madt)!\n");
984263bc 557
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558 /* Local apic is mapped on last page */
559 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
560 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
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561
562 bsp_apic_id = (lapic.id & 0xff000000) >> 24;
563 if (madt_pass2(madt_paddr, bsp_apic_id))
564 panic("mp_enable: madt_pass2 failed\n");
a26bbcd5 565 }
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566
567#if defined(APIC_IO)
568
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569 setup_apic_irq_mapping();
570
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571 /* fill the LOGICAL io_apic_versions table */
572 for (apic = 0; apic < mp_napics; ++apic) {
573 ux = io_apic_read(apic, IOAPIC_VER);
574 io_apic_versions[apic] = ux;
575 io_apic_set_id(apic, IO_TO_ID(apic));
576 }
577
578 /* program each IO APIC in the system */
579 for (apic = 0; apic < mp_napics; ++apic)
580 if (io_apic_setup(apic) < 0)
581 panic("IO APIC setup failure");
582
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583#endif /* APIC_IO */
584
585 /*
586 * These are required for SMP operation
587 */
588
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589 /* install a 'Spurious INTerrupt' vector */
590 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
592
593 /* install an inter-CPU IPI for TLB invalidation */
594 setidt(XINVLTLB_OFFSET, Xinvltlb,
595 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
596
96728c05
MD
597 /* install an inter-CPU IPI for IPIQ messaging */
598 setidt(XIPIQ_OFFSET, Xipiq,
599 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
78ea5a2a
SZ
600
601 /* install a timer vector */
602 setidt(XTIMER_OFFSET, Xtimer,
603 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc 604
984263bc
MD
605 /* install an inter-CPU IPI for CPU stop/restart */
606 setidt(XCPUSTOP_OFFSET, Xcpustop,
607 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
608
984263bc
MD
609 /* start each Application Processor */
610 start_all_aps(boot_addr);
611}
612
613
614/*
615 * look for the MP spec signature
616 */
617
618/* string defined by the Intel MP Spec as identifying the MP table */
619#define MP_SIG 0x5f504d5f /* _MP_ */
620#define NEXT(X) ((X) += 4)
621static int
3aba8f73 622mptable_search_sig(u_int32_t target, int count)
984263bc 623{
0f85efa2
SZ
624 vm_size_t map_size;
625 u_int32_t *addr;
626 int x, ret;
984263bc 627
aeb48299
SZ
628 KKASSERT(target != 0);
629
0f85efa2
SZ
630 map_size = count * sizeof(u_int32_t);
631 addr = pmap_mapdev((vm_paddr_t)target, map_size);
984263bc 632
aeb48299 633 ret = 0;
0f85efa2
SZ
634 for (x = 0; x < count; NEXT(x)) {
635 if (addr[x] == MP_SIG) {
636 /* make array index a byte index */
637 ret = target + (x * sizeof(u_int32_t));
638 break;
639 }
640 }
aeb48299 641
0f85efa2
SZ
642 pmap_unmapdev((vm_offset_t)addr, map_size);
643 return ret;
984263bc
MD
644}
645
646
647static basetable_entry basetable_entry_types[] =
648{
649 {0, 20, "Processor"},
650 {1, 8, "Bus"},
651 {2, 8, "I/O APIC"},
652 {3, 8, "I/O INT"},
653 {4, 8, "Local INT"}
654};
655
656typedef struct BUSDATA {
657 u_char bus_id;
658 enum busTypes bus_type;
659} bus_datum;
660
661typedef struct INTDATA {
662 u_char int_type;
663 u_short int_flags;
664 u_char src_bus_id;
665 u_char src_bus_irq;
666 u_char dst_apic_id;
667 u_char dst_apic_int;
668 u_char int_vector;
669} io_int, local_int;
670
671typedef struct BUSTYPENAME {
672 u_char type;
673 char name[7];
674} bus_type_name;
675
676static bus_type_name bus_type_table[] =
677{
678 {CBUS, "CBUS"},
679 {CBUSII, "CBUSII"},
680 {EISA, "EISA"},
681 {MCA, "MCA"},
682 {UNKNOWN_BUSTYPE, "---"},
683 {ISA, "ISA"},
684 {MCA, "MCA"},
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {PCI, "PCI"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {XPRESS, "XPRESS"},
696 {UNKNOWN_BUSTYPE, "---"}
697};
698/* from MP spec v1.4, table 5-1 */
699static int default_data[7][5] =
700{
701/* nbus, id0, type0, id1, type1 */
702 {1, 0, ISA, 255, 255},
703 {1, 0, EISA, 255, 255},
704 {1, 0, EISA, 255, 255},
705 {1, 0, MCA, 255, 255},
706 {2, 0, ISA, 1, PCI},
707 {2, 0, EISA, 1, PCI},
708 {2, 0, MCA, 1, PCI}
709};
710
711
712/* the bus data */
713static bus_datum *bus_data;
714
97359a5b 715#ifdef APIC_IO
984263bc
MD
716/* the IO INT data, one entry per possible APIC INTerrupt */
717static io_int *io_apic_ints;
984263bc 718static int nintrs;
97359a5b 719#endif
984263bc 720
3ae0cd58
RG
721static int processor_entry (proc_entry_ptr entry, int cpu);
722static int bus_entry (bus_entry_ptr entry, int bus);
97359a5b 723#ifdef APIC_IO
3ae0cd58
RG
724static int io_apic_entry (io_apic_entry_ptr entry, int apic);
725static int int_entry (int_entry_ptr entry, int intr);
97359a5b 726#endif
3ae0cd58 727static int lookup_bus_type (char *name);
984263bc
MD
728
729
730/*
731 * 1st pass on motherboard's Intel MP specification table.
732 *
984263bc
MD
733 * determines:
734 * cpu_apic_address (common to all CPUs)
735 * io_apic_address[N]
736 * mp_naps
737 * mp_nbusses
738 * mp_napics
739 * nintrs
0ae734b5
SZ
740 * need_hyperthreading_fixup
741 * logical_cpus
984263bc
MD
742 */
743static void
981bebd1 744mptable_pass1(struct mptable_pos *mpt)
984263bc 745{
97359a5b 746#ifdef APIC_IO
984263bc 747 int x;
97359a5b 748#endif
981bebd1 749 mpfps_t fps;
984263bc
MD
750 mpcth_t cth;
751 int totalSize;
752 void* position;
753 int count;
754 int type;
984263bc 755 u_int id_mask;
984263bc
MD
756
757 POSTCODE(MPTABLE_PASS1_POST);
758
981bebd1
SZ
759 fps = mpt->mp_fps;
760 KKASSERT(fps != NULL);
f9c3b04f 761
97359a5b 762#ifdef APIC_IO
984263bc
MD
763 /* clear various tables */
764 for (x = 0; x < NAPICID; ++x) {
765 io_apic_address[x] = ~0; /* IO APIC address table */
766 }
97359a5b 767#endif
984263bc
MD
768
769 /* init everything to empty */
770 mp_naps = 0;
771 mp_nbusses = 0;
97359a5b 772#ifdef APIC_IO
984263bc
MD
773 mp_napics = 0;
774 nintrs = 0;
97359a5b 775#endif
984263bc 776 id_mask = 0;
984263bc
MD
777
778 /* check for use of 'default' configuration */
981bebd1 779 if (fps->mpfb1 != 0) {
984263bc
MD
780 /* use default addresses */
781 cpu_apic_address = DEFAULT_APIC_BASE;
97359a5b 782#ifdef APIC_IO
984263bc 783 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
97359a5b 784#endif
984263bc
MD
785
786 /* fill in with defaults */
787 mp_naps = 2; /* includes BSP */
981bebd1 788 mp_nbusses = default_data[fps->mpfb1 - 1][0];
984263bc
MD
789#if defined(APIC_IO)
790 mp_napics = 1;
791 nintrs = 16;
792#endif /* APIC_IO */
793 }
794 else {
981bebd1
SZ
795 cth = mpt->mp_cth;
796 if (cth == NULL)
984263bc
MD
797 panic("MP Configuration Table Header MISSING!");
798
799 cpu_apic_address = (vm_offset_t) cth->apic_address;
800
801 /* walk the table, recording info of interest */
802 totalSize = cth->base_table_length - sizeof(struct MPCTH);
803 position = (u_char *) cth + sizeof(struct MPCTH);
804 count = cth->entry_count;
805
806 while (count--) {
807 switch (type = *(u_char *) position) {
808 case 0: /* processor_entry */
809 if (((proc_entry_ptr)position)->cpu_flags
810 & PROCENTRY_FLAG_EN) {
811 ++mp_naps;
984263bc
MD
812 id_mask |= 1 <<
813 ((proc_entry_ptr)position)->apic_id;
984263bc
MD
814 }
815 break;
816 case 1: /* bus_entry */
817 ++mp_nbusses;
818 break;
819 case 2: /* io_apic_entry */
97359a5b 820#ifdef APIC_IO
984263bc
MD
821 if (((io_apic_entry_ptr)position)->apic_flags
822 & IOAPICENTRY_FLAG_EN)
823 io_apic_address[mp_napics++] =
824 (vm_offset_t)((io_apic_entry_ptr)
825 position)->apic_address;
97359a5b 826#endif
984263bc
MD
827 break;
828 case 3: /* int_entry */
97359a5b 829#ifdef APIC_IO
984263bc 830 ++nintrs;
97359a5b 831#endif
984263bc
MD
832 break;
833 case 4: /* int_entry */
834 break;
835 default:
836 panic("mpfps Base Table HOSED!");
837 /* NOTREACHED */
838 }
839
840 totalSize -= basetable_entry_types[type].length;
7a9b7292
JS
841 position = (uint8_t *)position +
842 basetable_entry_types[type].length;
984263bc
MD
843 }
844 }
845
846 /* qualify the numbers */
847 if (mp_naps > MAXCPU) {
26be20a0 848 kprintf("Warning: only using %d of %d available CPUs!\n",
984263bc
MD
849 MAXCPU, mp_naps);
850 mp_naps = MAXCPU;
851 }
852
984263bc
MD
853 /* See if we need to fixup HT logical CPUs. */
854 mptable_hyperthread_fixup(id_mask);
984263bc
MD
855
856 --mp_naps; /* subtract the BSP */
857}
858
859
860/*
861 * 2nd pass on motherboard's Intel MP specification table.
862 *
863 * sets:
0ae734b5 864 * logical_cpus_mask
984263bc
MD
865 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
866 * CPU_TO_ID(N), logical CPU to APIC ID table
867 * IO_TO_ID(N), logical IO to APIC ID table
868 * bus_data[N]
869 * io_apic_ints[N]
870 */
871static int
981bebd1 872mptable_pass2(struct mptable_pos *mpt)
984263bc 873{
984263bc 874 struct PROCENTRY proc;
984263bc 875 int x;
981bebd1 876 mpfps_t fps;
984263bc
MD
877 mpcth_t cth;
878 int totalSize;
879 void* position;
880 int count;
881 int type;
882 int apic, bus, cpu, intr;
f13b5eec 883 int i;
984263bc
MD
884
885 POSTCODE(MPTABLE_PASS2_POST);
886
981bebd1
SZ
887 fps = mpt->mp_fps;
888 KKASSERT(fps != NULL);
889
984263bc
MD
890 /* Initialize fake proc entry for use with HT fixup. */
891 bzero(&proc, sizeof(proc));
892 proc.type = 0;
893 proc.cpu_flags = PROCENTRY_FLAG_EN;
984263bc 894
97359a5b 895#ifdef APIC_IO
984263bc
MD
896 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
897 M_DEVBUF, M_WAITOK);
898 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
e7b4468c 899 M_DEVBUF, M_WAITOK | M_ZERO);
1439c090 900 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984263bc 901 M_DEVBUF, M_WAITOK);
97359a5b 902#endif
984263bc
MD
903 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
904 M_DEVBUF, M_WAITOK);
905
97359a5b 906#ifdef APIC_IO
984263bc 907 for (i = 0; i < mp_napics; i++) {
f13b5eec 908 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
984263bc 909 }
97359a5b 910#endif
984263bc
MD
911
912 /* clear various tables */
913 for (x = 0; x < NAPICID; ++x) {
984263bc 914 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
97359a5b
MD
915#ifdef APIC_IO
916 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
984263bc 917 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
97359a5b 918#endif
984263bc
MD
919 }
920
921 /* clear bus data table */
922 for (x = 0; x < mp_nbusses; ++x)
923 bus_data[x].bus_id = 0xff;
924
97359a5b 925#ifdef APIC_IO
984263bc
MD
926 /* clear IO APIC INT table */
927 for (x = 0; x < (nintrs + 1); ++x) {
928 io_apic_ints[x].int_type = 0xff;
929 io_apic_ints[x].int_vector = 0xff;
930 }
97359a5b 931#endif
984263bc 932
984263bc 933 /* record whether PIC or virtual-wire mode */
981bebd1 934 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
984263bc
MD
935
936 /* check for use of 'default' configuration */
981bebd1
SZ
937 if (fps->mpfb1 != 0)
938 return fps->mpfb1; /* return default configuration type */
984263bc 939
981bebd1
SZ
940 cth = mpt->mp_cth;
941 if (cth == NULL)
984263bc
MD
942 panic("MP Configuration Table Header MISSING!");
943
944 /* walk the table, recording info of interest */
945 totalSize = cth->base_table_length - sizeof(struct MPCTH);
946 position = (u_char *) cth + sizeof(struct MPCTH);
947 count = cth->entry_count;
948 apic = bus = intr = 0;
949 cpu = 1; /* pre-count the BSP */
950
951 while (count--) {
952 switch (type = *(u_char *) position) {
953 case 0:
954 if (processor_entry(position, cpu))
955 ++cpu;
956
984263bc
MD
957 if (need_hyperthreading_fixup) {
958 /*
959 * Create fake mptable processor entries
960 * and feed them to processor_entry() to
961 * enumerate the logical CPUs.
962 */
963 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
964 for (i = 1; i < logical_cpus; i++) {
965 proc.apic_id++;
09e6e929 966 processor_entry(&proc, cpu);
48add334 967 logical_cpus_mask |= (1 << cpu);
984263bc
MD
968 cpu++;
969 }
970 }
984263bc
MD
971 break;
972 case 1:
973 if (bus_entry(position, bus))
974 ++bus;
975 break;
976 case 2:
97359a5b 977#ifdef APIC_IO
984263bc
MD
978 if (io_apic_entry(position, apic))
979 ++apic;
97359a5b 980#endif
984263bc
MD
981 break;
982 case 3:
97359a5b 983#ifdef APIC_IO
984263bc
MD
984 if (int_entry(position, intr))
985 ++intr;
97359a5b 986#endif
984263bc
MD
987 break;
988 case 4:
989 /* int_entry(position); */
990 break;
991 default:
992 panic("mpfps Base Table HOSED!");
993 /* NOTREACHED */
994 }
995
996 totalSize -= basetable_entry_types[type].length;
7a9b7292 997 position = (uint8_t *)position + basetable_entry_types[type].length;
984263bc
MD
998 }
999
bd8aa7e2 1000 if (CPU_TO_ID(0) < 0)
984263bc
MD
1001 panic("NO BSP found!");
1002
1003 /* report fact that its NOT a default configuration */
1004 return 0;
1005}
1006
984263bc
MD
1007/*
1008 * Check if we should perform a hyperthreading "fix-up" to
1009 * enumerate any logical CPU's that aren't already listed
1010 * in the table.
1011 *
1012 * XXX: We assume that all of the physical CPUs in the
1013 * system have the same number of logical CPUs.
1014 *
1015 * XXX: We assume that APIC ID's are allocated such that
1016 * the APIC ID's for a physical processor are aligned
1017 * with the number of logical CPU's in the processor.
1018 */
1019static void
1020mptable_hyperthread_fixup(u_int id_mask)
1021{
7ea07fd2 1022 int i, id, lcpus_max;
984263bc 1023
984263bc
MD
1024 if ((cpu_feature & CPUID_HTT) == 0)
1025 return;
7ea07fd2
SZ
1026
1027 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1028 if (lcpus_max <= 1)
984263bc
MD
1029 return;
1030
7ea07fd2
SZ
1031 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1032 /*
1033 * INSTRUCTION SET REFERENCE, A-M (#253666)
1034 * Page 3-181, Table 3-20
1035 * "The nearest power-of-2 integer that is not smaller
1036 * than EBX[23:16] is the number of unique initial APIC
1037 * IDs reserved for addressing different logical
1038 * processors in a physical package."
1039 */
1040 for (i = 0; ; ++i) {
1041 if ((1 << i) >= lcpus_max) {
1042 lcpus_max = 1 << i;
1043 break;
1044 }
1045 }
1046 }
1047
1048 if (mp_naps == lcpus_max) {
1049 /* We have nothing to fix */
1050 return;
1051 } else if (mp_naps == 1) {
1052 /* XXX this may be incorrect */
1053 logical_cpus = lcpus_max;
1054 } else {
1055 int cur, prev, dist;
1056
1057 /*
1058 * Calculate the distances between two nearest
1059 * APIC IDs. If all such distances are same,
1060 * then it is the number of missing cpus that
1061 * we are going to fill later.
1062 */
1063 dist = cur = prev = -1;
1064 for (id = 0; id < MAXCPU; ++id) {
1065 if ((id_mask & 1 << id) == 0)
1066 continue;
1067
1068 cur = id;
1069 if (prev >= 0) {
1070 int new_dist = cur - prev;
1071
1072 if (dist < 0)
1073 dist = new_dist;
1074
1075 /*
1076 * Make sure that all distances
1077 * between two nearest APIC IDs
1078 * are same.
1079 */
1080 if (dist != new_dist)
1081 return;
1082 }
1083 prev = cur;
1084 }
1085 if (dist == 1)
1086 return;
1087
1088 /* Must be power of 2 */
1089 if (dist & (dist - 1))
1090 return;
1091
1092 /* Can't exceed CPU package capacity */
1093 if (dist > lcpus_max)
1094 logical_cpus = lcpus_max;
1095 else
1096 logical_cpus = dist;
1097 }
1098
984263bc
MD
1099 /*
1100 * For each APIC ID of a CPU that is set in the mask,
1101 * scan the other candidate APIC ID's for this
1102 * physical processor. If any of those ID's are
1103 * already in the table, then kill the fixup.
1104 */
7ea07fd2 1105 for (id = 0; id < MAXCPU; id++) {
984263bc
MD
1106 if ((id_mask & 1 << id) == 0)
1107 continue;
1108 /* First, make sure we are on a logical_cpus boundary. */
1109 if (id % logical_cpus != 0)
1110 return;
1111 for (i = id + 1; i < id + logical_cpus; i++)
1112 if ((id_mask & 1 << i) != 0)
1113 return;
1114 }
1115
1116 /*
1117 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1118 * mp_naps right now.
1119 */
1120 need_hyperthreading_fixup = 1;
1121 mp_naps *= logical_cpus;
1122}
984263bc 1123
981bebd1
SZ
1124static void
1125mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1126{
1127 mpfps_t fps = NULL;
1128 mpcth_t cth = NULL;
1129 vm_size_t cth_mapsz = 0;
1130
1131 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1132 if (fps->pap != 0) {
1133 /*
1134 * Map configuration table header to get
1135 * the base table size
1136 */
1137 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1138 cth_mapsz = cth->base_table_length;
1139 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1140
1141 /*
1142 * Map the base table
1143 */
1144 cth = pmap_mapdev(fps->pap, cth_mapsz);
1145 }
1146
1147 mpt->mp_fps = fps;
1148 mpt->mp_cth = cth;
1149 mpt->mp_cth_mapsz = cth_mapsz;
1150}
1151
1152static void
1153mptable_unmap(struct mptable_pos *mpt)
1154{
1155 if (mpt->mp_cth != NULL) {
1156 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1157 mpt->mp_cth = NULL;
1158 mpt->mp_cth_mapsz = 0;
1159 }
1160 if (mpt->mp_fps != NULL) {
1161 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1162 mpt->mp_fps = NULL;
1163 }
1164}
1165
97359a5b
MD
1166#ifdef APIC_IO
1167
984263bc
MD
1168void
1169assign_apic_irq(int apic, int intpin, int irq)
1170{
1171 int x;
1172
1173 if (int_to_apicintpin[irq].ioapic != -1)
1174 panic("assign_apic_irq: inconsistent table");
1175
1176 int_to_apicintpin[irq].ioapic = apic;
1177 int_to_apicintpin[irq].int_pin = intpin;
1178 int_to_apicintpin[irq].apic_address = ioapic[apic];
1179 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1180
1181 for (x = 0; x < nintrs; x++) {
1182 if ((io_apic_ints[x].int_type == 0 ||
1183 io_apic_ints[x].int_type == 3) &&
1184 io_apic_ints[x].int_vector == 0xff &&
1185 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1186 io_apic_ints[x].dst_apic_int == intpin)
1187 io_apic_ints[x].int_vector = irq;
1188 }
1189}
1190
1191void
1192revoke_apic_irq(int irq)
1193{
1194 int x;
1195 int oldapic;
1196 int oldintpin;
1197
1198 if (int_to_apicintpin[irq].ioapic == -1)
1199 panic("revoke_apic_irq: inconsistent table");
1200
1201 oldapic = int_to_apicintpin[irq].ioapic;
1202 oldintpin = int_to_apicintpin[irq].int_pin;
1203
1204 int_to_apicintpin[irq].ioapic = -1;
1205 int_to_apicintpin[irq].int_pin = 0;
1206 int_to_apicintpin[irq].apic_address = NULL;
1207 int_to_apicintpin[irq].redirindex = 0;
1208
1209 for (x = 0; x < nintrs; x++) {
1210 if ((io_apic_ints[x].int_type == 0 ||
1211 io_apic_ints[x].int_type == 3) &&
1212 io_apic_ints[x].int_vector != 0xff &&
1213 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1214 io_apic_ints[x].dst_apic_int == oldintpin)
1215 io_apic_ints[x].int_vector = 0xff;
1216 }
1217}
1218
1439c090
MD
1219/*
1220 * Allocate an IRQ
1221 */
984263bc
MD
1222static void
1223allocate_apic_irq(int intr)
1224{
1225 int apic;
1226 int intpin;
1227 int irq;
1228
1229 if (io_apic_ints[intr].int_vector != 0xff)
1230 return; /* Interrupt handler already assigned */
1231
1232 if (io_apic_ints[intr].int_type != 0 &&
1233 (io_apic_ints[intr].int_type != 3 ||
1234 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1235 io_apic_ints[intr].dst_apic_int == 0)))
1236 return; /* Not INT or ExtInt on != (0, 0) */
1237
1238 irq = 0;
1239 while (irq < APIC_INTMAPSIZE &&
1240 int_to_apicintpin[irq].ioapic != -1)
1241 irq++;
1242
1243 if (irq >= APIC_INTMAPSIZE)
1244 return; /* No free interrupt handlers */
1245
1246 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1247 intpin = io_apic_ints[intr].dst_apic_int;
1248
1249 assign_apic_irq(apic, intpin, irq);
1250 io_apic_setup_intpin(apic, intpin);
1251}
1252
1253
1254static void
1255swap_apic_id(int apic, int oldid, int newid)
1256{
1257 int x;
1258 int oapic;
1259
1260
1261 if (oldid == newid)
1262 return; /* Nothing to do */
1263
26be20a0 1264 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
984263bc
MD
1265 apic, oldid, newid);
1266
1267 /* Swap physical APIC IDs in interrupt entries */
1268 for (x = 0; x < nintrs; x++) {
1269 if (io_apic_ints[x].dst_apic_id == oldid)
1270 io_apic_ints[x].dst_apic_id = newid;
1271 else if (io_apic_ints[x].dst_apic_id == newid)
1272 io_apic_ints[x].dst_apic_id = oldid;
1273 }
1274
1275 /* Swap physical APIC IDs in IO_TO_ID mappings */
1276 for (oapic = 0; oapic < mp_napics; oapic++)
1277 if (IO_TO_ID(oapic) == newid)
1278 break;
1279
1280 if (oapic < mp_napics) {
26be20a0 1281 kprintf("Changing APIC ID for IO APIC #%d from "
984263bc
MD
1282 "%d to %d in MP table\n",
1283 oapic, newid, oldid);
1284 IO_TO_ID(oapic) = oldid;
1285 }
1286 IO_TO_ID(apic) = newid;
1287}
1288
1289
1290static void
1291fix_id_to_io_mapping(void)
1292{
1293 int x;
1294
1295 for (x = 0; x < NAPICID; x++)
1296 ID_TO_IO(x) = -1;
1297
1298 for (x = 0; x <= mp_naps; x++)
1299 if (CPU_TO_ID(x) < NAPICID)
1300 ID_TO_IO(CPU_TO_ID(x)) = x;
1301
1302 for (x = 0; x < mp_napics; x++)
1303 if (IO_TO_ID(x) < NAPICID)
1304 ID_TO_IO(IO_TO_ID(x)) = x;
1305}
1306
1307
1308static int
1309first_free_apic_id(void)
1310{
1311 int freeid, x;
1312
1313 for (freeid = 0; freeid < NAPICID; freeid++) {
1314 for (x = 0; x <= mp_naps; x++)
1315 if (CPU_TO_ID(x) == freeid)
1316 break;
1317 if (x <= mp_naps)
1318 continue;
1319 for (x = 0; x < mp_napics; x++)
1320 if (IO_TO_ID(x) == freeid)
1321 break;
1322 if (x < mp_napics)
1323 continue;
1324 return freeid;
1325 }
1326 return freeid;
1327}
1328
1329
1330static int
1331io_apic_id_acceptable(int apic, int id)
1332{
1333 int cpu; /* Logical CPU number */
1334 int oapic; /* Logical IO APIC number for other IO APIC */
1335
1336 if (id >= NAPICID)
1337 return 0; /* Out of range */
1338
1339 for (cpu = 0; cpu <= mp_naps; cpu++)
1340 if (CPU_TO_ID(cpu) == id)
1341 return 0; /* Conflict with CPU */
1342
1343 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1344 if (IO_TO_ID(oapic) == id)
1345 return 0; /* Conflict with other APIC */
1346
1347 return 1; /* ID is acceptable for IO APIC */
1348}
1349
1439c090
MD
1350static
1351io_int *
1352io_apic_find_int_entry(int apic, int pin)
1353{
1354 int x;
1355
1356 /* search each of the possible INTerrupt sources */
1357 for (x = 0; x < nintrs; ++x) {
1358 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1359 (pin == io_apic_ints[x].dst_apic_int))
1360 return (&io_apic_ints[x]);
1361 }
1362 return NULL;
1363}
1364
97359a5b 1365#endif
984263bc
MD
1366
1367/*
1368 * parse an Intel MP specification table
1369 */
1370static void
3aba8f73 1371mptable_fix(void)
984263bc
MD
1372{
1373 int x;
97359a5b 1374#ifdef APIC_IO
984263bc 1375 int id;
984263bc
MD
1376 int apic; /* IO APIC unit number */
1377 int freeid; /* Free physical APIC ID */
1378 int physid; /* Current physical IO APIC ID */
1439c090 1379 io_int *io14;
97359a5b
MD
1380#endif
1381 int bus_0 = 0; /* Stop GCC warning */
1382 int bus_pci = 0; /* Stop GCC warning */
1383 int num_pci_bus;
984263bc
MD
1384
1385 /*
1386 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1387 * did it wrong. The MP spec says that when more than 1 PCI bus
1388 * exists the BIOS must begin with bus entries for the PCI bus and use
1389 * actual PCI bus numbering. This implies that when only 1 PCI bus
1390 * exists the BIOS can choose to ignore this ordering, and indeed many
1391 * MP motherboards do ignore it. This causes a problem when the PCI
1392 * sub-system makes requests of the MP sub-system based on PCI bus
1393 * numbers. So here we look for the situation and renumber the
1394 * busses and associated INTs in an effort to "make it right".
1395 */
1396
1397 /* find bus 0, PCI bus, count the number of PCI busses */
1398 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1399 if (bus_data[x].bus_id == 0) {
1400 bus_0 = x;
1401 }
1402 if (bus_data[x].bus_type == PCI) {
1403 ++num_pci_bus;
1404 bus_pci = x;
1405 }
1406 }
1407 /*
1408 * bus_0 == slot of bus with ID of 0
1409 * bus_pci == slot of last PCI bus encountered
1410 */
1411
1412 /* check the 1 PCI bus case for sanity */
1413 /* if it is number 0 all is well */
1414 if (num_pci_bus == 1 &&
1415 bus_data[bus_pci].bus_id != 0) {
1416
1417 /* mis-numbered, swap with whichever bus uses slot 0 */
1418
1419 /* swap the bus entry types */
1420 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1421 bus_data[bus_0].bus_type = PCI;
1422
97359a5b 1423#ifdef APIC_IO
984263bc
MD
1424 /* swap each relavant INTerrupt entry */
1425 id = bus_data[bus_pci].bus_id;
1426 for (x = 0; x < nintrs; ++x) {
1427 if (io_apic_ints[x].src_bus_id == id) {
1428 io_apic_ints[x].src_bus_id = 0;
1429 }
1430 else if (io_apic_ints[x].src_bus_id == 0) {
1431 io_apic_ints[x].src_bus_id = id;
1432 }
1433 }
97359a5b 1434#endif
984263bc
MD
1435 }
1436
97359a5b 1437#ifdef APIC_IO
984263bc
MD
1438 /* Assign IO APIC IDs.
1439 *
1440 * First try the existing ID. If a conflict is detected, try
1441 * the ID in the MP table. If a conflict is still detected, find
1442 * a free id.
1443 *
1444 * We cannot use the ID_TO_IO table before all conflicts has been
1445 * resolved and the table has been corrected.
1446 */
1447 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1448
1449 /* First try to use the value set by the BIOS */
1450 physid = io_apic_get_id(apic);
1451 if (io_apic_id_acceptable(apic, physid)) {
1452 if (IO_TO_ID(apic) != physid)
1453 swap_apic_id(apic, IO_TO_ID(apic), physid);
1454 continue;
1455 }
1456
1457 /* Then check if the value in the MP table is acceptable */
1458 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1459 continue;
1460
1461 /* Last resort, find a free APIC ID and use it */
1462 freeid = first_free_apic_id();
1463 if (freeid >= NAPICID)
1464 panic("No free physical APIC IDs found");
1465
1466 if (io_apic_id_acceptable(apic, freeid)) {
1467 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1468 continue;
1469 }
1470 panic("Free physical APIC ID not usable");
1471 }
1472 fix_id_to_io_mapping();
97359a5b 1473#endif
984263bc 1474
97359a5b 1475#ifdef APIC_IO
984263bc
MD
1476 /* detect and fix broken Compaq MP table */
1477 if (apic_int_type(0, 0) == -1) {
26be20a0 1478 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
984263bc
MD
1479 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1480 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1481 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1482 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1483 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1484 nintrs++;
ad12f88c 1485 } else if (apic_int_type(0, 0) == 0) {
26be20a0 1486 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
ad12f88c
HP
1487 for (x = 0; x < nintrs; ++x)
1488 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1489 (0 == io_apic_ints[x].dst_apic_int)) {
1490 io_apic_ints[x].int_type = 3;
1491 io_apic_ints[x].int_vector = 0xff;
1492 break;
1493 }
984263bc 1494 }
1439c090
MD
1495
1496 /*
1497 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1498 * controllers universally come in pairs. If IRQ 14 is specified
1499 * as an ISA interrupt, then IRQ 15 had better be too.
1500 *
1501 * [ Shuttle XPC / AMD Athlon X2 ]
1502 * The MPTable is missing an entry for IRQ 15. Note that the
1503 * ACPI table has an entry for both 14 and 15.
1504 */
1505 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
26be20a0 1506 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439c090
MD
1507 io14 = io_apic_find_int_entry(0, 14);
1508 io_apic_ints[nintrs] = *io14;
1509 io_apic_ints[nintrs].src_bus_irq = 15;
1510 io_apic_ints[nintrs].dst_apic_int = 15;
1511 nintrs++;
1512 }
97359a5b 1513#endif
984263bc
MD
1514}
1515
97359a5b 1516#ifdef APIC_IO
984263bc
MD
1517
1518/* Assign low level interrupt handlers */
1519static void
1520setup_apic_irq_mapping(void)
1521{
1522 int x;
1523 int int_vector;
1524
1525 /* Clear array */
1526 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1527 int_to_apicintpin[x].ioapic = -1;
1528 int_to_apicintpin[x].int_pin = 0;
1529 int_to_apicintpin[x].apic_address = NULL;
1530 int_to_apicintpin[x].redirindex = 0;
1531 }
1532
1533 /* First assign ISA/EISA interrupts */
1534 for (x = 0; x < nintrs; x++) {
1535 int_vector = io_apic_ints[x].src_bus_irq;
1536 if (int_vector < APIC_INTMAPSIZE &&
1537 io_apic_ints[x].int_vector == 0xff &&
1538 int_to_apicintpin[int_vector].ioapic == -1 &&
1539 (apic_int_is_bus_type(x, ISA) ||
1540 apic_int_is_bus_type(x, EISA)) &&
1541 io_apic_ints[x].int_type == 0) {
1542 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1543 io_apic_ints[x].dst_apic_int,
1544 int_vector);
1545 }
1546 }
1547
1548 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1549 for (x = 0; x < nintrs; x++) {
1550 if (io_apic_ints[x].dst_apic_int == 0 &&
1551 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1552 io_apic_ints[x].int_vector == 0xff &&
1553 int_to_apicintpin[0].ioapic == -1 &&
1554 io_apic_ints[x].int_type == 3) {
1555 assign_apic_irq(0, 0, 0);
1556 break;
1557 }
1558 }
1559 /* PCI interrupt assignment is deferred */
1560}
1561
97359a5b 1562#endif
984263bc 1563
a9112655
SZ
1564void
1565mp_set_cpuids(int cpu_id, int apic_id)
1566{
1567 CPU_TO_ID(cpu_id) = apic_id;
1568 ID_TO_CPU(apic_id) = cpu_id;
1569}
1570
984263bc
MD
1571static int
1572processor_entry(proc_entry_ptr entry, int cpu)
1573{
bd8aa7e2
SZ
1574 KKASSERT(cpu > 0);
1575
984263bc
MD
1576 /* check for usability */
1577 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1578 return 0;
1579
1580 if(entry->apic_id >= NAPICID)
1581 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1582 /* check for BSP flag */
1583 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
a9112655 1584 mp_set_cpuids(0, entry->apic_id);
984263bc
MD
1585 return 0; /* its already been counted */
1586 }
1587
1588 /* add another AP to list, if less than max number of CPUs */
1589 else if (cpu < MAXCPU) {
a9112655 1590 mp_set_cpuids(cpu, entry->apic_id);
984263bc
MD
1591 return 1;
1592 }
1593
1594 return 0;
1595}
1596
1597
1598static int
1599bus_entry(bus_entry_ptr entry, int bus)
1600{
1601 int x;
1602 char c, name[8];
1603
1604 /* encode the name into an index */
1605 for (x = 0; x < 6; ++x) {
1606 if ((c = entry->bus_type[x]) == ' ')
1607 break;
1608 name[x] = c;
1609 }
1610 name[x] = '\0';
1611
1612 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1613 panic("unknown bus type: '%s'", name);
1614
1615 bus_data[bus].bus_id = entry->bus_id;
1616 bus_data[bus].bus_type = x;
1617
1618 return 1;
1619}
1620
97359a5b 1621#ifdef APIC_IO
984263bc
MD
1622
1623static int
1624io_apic_entry(io_apic_entry_ptr entry, int apic)
1625{
1626 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1627 return 0;
1628
1629 IO_TO_ID(apic) = entry->apic_id;
1630 if (entry->apic_id < NAPICID)
1631 ID_TO_IO(entry->apic_id) = apic;
1632
1633 return 1;
1634}
1635
97359a5b 1636#endif
984263bc
MD
1637
1638static int
1639lookup_bus_type(char *name)
1640{
1641 int x;
1642
1643 for (x = 0; x < MAX_BUSTYPE; ++x)
1644 if (strcmp(bus_type_table[x].name, name) == 0)
1645 return bus_type_table[x].type;
1646
1647 return UNKNOWN_BUSTYPE;
1648}
1649
97359a5b 1650#ifdef APIC_IO
984263bc
MD
1651
1652static int
1653int_entry(int_entry_ptr entry, int intr)
1654{
1655 int apic;
1656
1657 io_apic_ints[intr].int_type = entry->int_type;
1658 io_apic_ints[intr].int_flags = entry->int_flags;
1659 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1660 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1661 if (entry->dst_apic_id == 255) {
1662 /* This signal goes to all IO APICS. Select an IO APIC
1663 with sufficient number of interrupt pins */
1664 for (apic = 0; apic < mp_napics; apic++)
1665 if (((io_apic_read(apic, IOAPIC_VER) &
1666 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1667 entry->dst_apic_int)
1668 break;
1669 if (apic < mp_napics)
1670 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1671 else
1672 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1673 } else
1674 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1675 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1676
1677 return 1;
1678}
1679
984263bc
MD
1680static int
1681apic_int_is_bus_type(int intr, int bus_type)
1682{
1683 int bus;
1684
1685 for (bus = 0; bus < mp_nbusses; ++bus)
1686 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1687 && ((int) bus_data[bus].bus_type == bus_type))
1688 return 1;
1689
1690 return 0;
1691}
1692
984263bc
MD
1693/*
1694 * Given a traditional ISA INT mask, return an APIC mask.
1695 */
1696u_int
1697isa_apic_mask(u_int isa_mask)
1698{
1699 int isa_irq;
1700 int apic_pin;
1701
1702#if defined(SKIP_IRQ15_REDIRECT)
1703 if (isa_mask == (1 << 15)) {
26be20a0 1704 kprintf("skipping ISA IRQ15 redirect\n");
984263bc
MD
1705 return isa_mask;
1706 }
1707#endif /* SKIP_IRQ15_REDIRECT */
1708
1709 isa_irq = ffs(isa_mask); /* find its bit position */
1710 if (isa_irq == 0) /* doesn't exist */
1711 return 0;
1712 --isa_irq; /* make it zero based */
1713
1714 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1715 if (apic_pin == -1)
1716 return 0;
1717
1718 return (1 << apic_pin); /* convert pin# to a mask */
1719}
1720
984263bc
MD
1721/*
1722 * Determine which APIC pin an ISA/EISA INT is attached to.
1723 */
1724#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1725#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1726#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1727#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1728
1729#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1730int
1731isa_apic_irq(int isa_irq)
1732{
1733 int intr;
1734
1735 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1736 if (INTTYPE(intr) == 0) { /* standard INT */
1737 if (SRCBUSIRQ(intr) == isa_irq) {
1738 if (apic_int_is_bus_type(intr, ISA) ||
1739 apic_int_is_bus_type(intr, EISA)) {
1740 if (INTIRQ(intr) == 0xff)
1741 return -1; /* unassigned */
1742 return INTIRQ(intr); /* found */
1743 }
1744 }
1745 }
1746 }
1747 return -1; /* NOT found */
1748}
1749
1750
1751/*
1752 * Determine which APIC pin a PCI INT is attached to.
1753 */
1754#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1755#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1756#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1757int
1758pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1759{
1760 int intr;
1761
1762 --pciInt; /* zero based */
1763
1439c090 1764 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
984263bc
MD
1765 if ((INTTYPE(intr) == 0) /* standard INT */
1766 && (SRCBUSID(intr) == pciBus)
1767 && (SRCBUSDEVICE(intr) == pciDevice)
1439c090 1768 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
984263bc
MD
1769 if (apic_int_is_bus_type(intr, PCI)) {
1770 if (INTIRQ(intr) == 0xff)
1771 allocate_apic_irq(intr);
1772 if (INTIRQ(intr) == 0xff)
1773 return -1; /* unassigned */
1774 return INTIRQ(intr); /* exact match */
1775 }
1439c090
MD
1776 }
1777 }
984263bc
MD
1778
1779 return -1; /* NOT found */
1780}
1781
1782int
1783next_apic_irq(int irq)
1784{
1785 int intr, ointr;
1786 int bus, bustype;
1787
1788 bus = 0;
1789 bustype = 0;
1790 for (intr = 0; intr < nintrs; intr++) {
1791 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1792 continue;
1793 bus = SRCBUSID(intr);
1794 bustype = apic_bus_type(bus);
1795 if (bustype != ISA &&
1796 bustype != EISA &&
1797 bustype != PCI)
1798 continue;
1799 break;
1800 }
1801 if (intr >= nintrs) {
1802 return -1;
1803 }
1804 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1805 if (INTTYPE(ointr) != 0)
1806 continue;
1807 if (bus != SRCBUSID(ointr))
1808 continue;
1809 if (bustype == PCI) {
1810 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1811 continue;
1812 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1813 continue;
1814 }
1815 if (bustype == ISA || bustype == EISA) {
1816 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1817 continue;
1818 }
1819 if (INTPIN(intr) == INTPIN(ointr))
1820 continue;
1821 break;
1822 }
1823 if (ointr >= nintrs) {
1824 return -1;
1825 }
1826 return INTIRQ(ointr);
1827}
1828#undef SRCBUSLINE
1829#undef SRCBUSDEVICE
1830#undef SRCBUSID
1831#undef SRCBUSIRQ
1832
1833#undef INTPIN
1834#undef INTIRQ
1835#undef INTAPIC
1836#undef INTTYPE
1837
97359a5b 1838#endif
984263bc
MD
1839
1840/*
1841 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1842 *
1843 * XXX FIXME:
1844 * Exactly what this means is unclear at this point. It is a solution
1845 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1846 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1847 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1848 * option.
1849 */
1850int
1851undirect_isa_irq(int rirq)
1852{
1853#if defined(READY)
1854 if (bootverbose)
26be20a0 1855 kprintf("Freeing redirected ISA irq %d.\n", rirq);
984263bc 1856 /** FIXME: tickle the MB redirector chip */
c044141b 1857 return /* XXX */;
984263bc
MD
1858#else
1859 if (bootverbose)
26be20a0 1860 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
984263bc
MD
1861 return 0;
1862#endif /* READY */
1863}
1864
1865
1866/*
1867 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1868 */
1869int
1870undirect_pci_irq(int rirq)
1871{
1872#if defined(READY)
1873 if (bootverbose)
26be20a0 1874 kprintf("Freeing redirected PCI irq %d.\n", rirq);
984263bc
MD
1875
1876 /** FIXME: tickle the MB redirector chip */
c044141b 1877 return /* XXX */;
984263bc
MD
1878#else
1879 if (bootverbose)
26be20a0 1880 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
984263bc
MD
1881 rirq);
1882 return 0;
1883#endif /* READY */
1884}
1885
1886
1887/*
1888 * given a bus ID, return:
1889 * the bus type if found
1890 * -1 if NOT found
1891 */
1892int
1893apic_bus_type(int id)
1894{
1895 int x;
1896
1897 for (x = 0; x < mp_nbusses; ++x)
1898 if (bus_data[x].bus_id == id)
1899 return bus_data[x].bus_type;
1900
1901 return -1;
1902}
1903
97359a5b 1904#ifdef APIC_IO
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MD
1905
1906/*
1907 * given a LOGICAL APIC# and pin#, return:
1908 * the associated src bus ID if found
1909 * -1 if NOT found
1910 */
1911int
1912apic_src_bus_id(int apic, int pin)
1913{
1914 int x;
1915
1916 /* search each of the possible INTerrupt sources */
1917 for (x = 0; x < nintrs; ++x)
1918 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1919 (pin == io_apic_ints[x].dst_apic_int))
1920 return (io_apic_ints[x].src_bus_id);
1921
1922 return -1; /* NOT found */
1923}
1924
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MD
1925/*
1926 * given a LOGICAL APIC# and pin#, return:
1927 * the associated src bus IRQ if found
1928 * -1 if NOT found
1929 */
1930int
1931apic_src_bus_irq(int apic, int pin)
1932{
1933 int x;
1934
1935 for (x = 0; x < nintrs; x++)
1936 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1937 (pin == io_apic_ints[x].dst_apic_int))
1938 return (io_apic_ints[x].src_bus_irq);
1939
1940 return -1; /* NOT found */
1941}
1942
1943
1944/*
1945 * given a LOGICAL APIC# and pin#, return:
1946 * the associated INTerrupt type if found
1947 * -1 if NOT found
1948 */
1949int
1950apic_int_type(int apic, int pin)
1951{
1952 int x;
1953
1954 /* search each of the possible INTerrupt sources */
1439c090 1955 for (x = 0; x < nintrs; ++x) {
984263bc
MD
1956 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1957 (pin == io_apic_ints[x].dst_apic_int))
1958 return (io_apic_ints[x].int_type);
1439c090 1959 }
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MD
1960 return -1; /* NOT found */
1961}
1962
1439c090
MD
1963/*
1964 * Return the IRQ associated with an APIC pin
1965 */
984263bc
MD
1966int
1967apic_irq(int apic, int pin)
1968{
1969 int x;
1970 int res;
1971
1439c090 1972 for (x = 0; x < nintrs; ++x) {
984263bc
MD
1973 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1974 (pin == io_apic_ints[x].dst_apic_int)) {
1975 res = io_apic_ints[x].int_vector;
1976 if (res == 0xff)
1977 return -1;
1978 if (apic != int_to_apicintpin[res].ioapic)
1439c090 1979 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
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MD
1980 if (pin != int_to_apicintpin[res].int_pin)
1981 panic("apic_irq inconsistent table (2)");
1982 return res;
1983 }
1439c090 1984 }
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MD
1985 return -1;
1986}
1987
1988
1989/*
1990 * given a LOGICAL APIC# and pin#, return:
1991 * the associated trigger mode if found
1992 * -1 if NOT found
1993 */
1994int
1995apic_trigger(int apic, int pin)
1996{
1997 int x;
1998
1999 /* search each of the possible INTerrupt sources */
2000 for (x = 0; x < nintrs; ++x)
2001 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2002 (pin == io_apic_ints[x].dst_apic_int))
2003 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2004
2005 return -1; /* NOT found */
2006}
2007
2008
2009/*
2010 * given a LOGICAL APIC# and pin#, return:
2011 * the associated 'active' level if found
2012 * -1 if NOT found
2013 */
2014int
2015apic_polarity(int apic, int pin)
2016{
2017 int x;
2018
2019 /* search each of the possible INTerrupt sources */
2020 for (x = 0; x < nintrs; ++x)
2021 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2022 (pin == io_apic_ints[x].dst_apic_int))
2023 return (io_apic_ints[x].int_flags & 0x03);
2024
2025 return -1; /* NOT found */
2026}
2027
97359a5b 2028#endif
984263bc
MD
2029
2030/*
2031 * set data according to MP defaults
2032 * FIXME: probably not complete yet...
2033 */
2034static void
3aba8f73 2035mptable_default(int type)
984263bc 2036{
bd8aa7e2 2037 int ap_cpu_id, boot_cpu_id;
984263bc
MD
2038#if defined(APIC_IO)
2039 int io_apic_id;
2040 int pin;
2041#endif /* APIC_IO */
2042
2043#if 0
26be20a0 2044 kprintf(" MP default config type: %d\n", type);
984263bc
MD
2045 switch (type) {
2046 case 1:
26be20a0 2047 kprintf(" bus: ISA, APIC: 82489DX\n");
984263bc
MD
2048 break;
2049 case 2:
26be20a0 2050 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2051 break;
2052 case 3:
26be20a0 2053 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2054 break;
2055 case 4:
26be20a0 2056 kprintf(" bus: MCA, APIC: 82489DX\n");
984263bc
MD
2057 break;
2058 case 5:
26be20a0 2059 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
984263bc
MD
2060 break;
2061 case 6:
26be20a0 2062 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
984263bc
MD
2063 break;
2064 case 7:
26be20a0 2065 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
984263bc
MD
2066 break;
2067 default:
26be20a0 2068 kprintf(" future type\n");
984263bc
MD
2069 break;
2070 /* NOTREACHED */
2071 }
2072#endif /* 0 */
2073
2074 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
2075 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2076
2077 /* BSP */
2078 CPU_TO_ID(0) = boot_cpu_id;
2079 ID_TO_CPU(boot_cpu_id) = 0;
2080
2081 /* one and only AP */
2082 CPU_TO_ID(1) = ap_cpu_id;
2083 ID_TO_CPU(ap_cpu_id) = 1;
2084
2085#if defined(APIC_IO)
2086 /* one and only IO APIC */
2087 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2088
2089 /*
2090 * sanity check, refer to MP spec section 3.6.6, last paragraph
2091 * necessary as some hardware isn't properly setting up the IO APIC
2092 */
2093#if defined(REALLY_ANAL_IOAPICID_VALUE)
2094 if (io_apic_id != 2) {
2095#else
2096 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2097#endif /* REALLY_ANAL_IOAPICID_VALUE */
2098 io_apic_set_id(0, 2);
2099 io_apic_id = 2;
2100 }
2101 IO_TO_ID(0) = io_apic_id;
2102 ID_TO_IO(io_apic_id) = 0;
2103#endif /* APIC_IO */
2104
2105 /* fill out bus entries */
2106 switch (type) {
2107 case 1:
2108 case 2:
2109 case 3:
2110 case 4:
2111 case 5:
2112 case 6:
2113 case 7:
2114 bus_data[0].bus_id = default_data[type - 1][1];
2115 bus_data[0].bus_type = default_data[type - 1][2];
2116 bus_data[1].bus_id = default_data[type - 1][3];
2117 bus_data[1].bus_type = default_data[type - 1][4];
2118 break;
2119
2120 /* case 4: case 7: MCA NOT supported */
2121 default: /* illegal/reserved */
2122 panic("BAD default MP config: %d", type);
2123 /* NOTREACHED */
2124 }
2125
2126#if defined(APIC_IO)
2127 /* general cases from MP v1.4, table 5-2 */
2128 for (pin = 0; pin < 16; ++pin) {
2129 io_apic_ints[pin].int_type = 0;
2130 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2131 io_apic_ints[pin].src_bus_id = 0;
2132 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2133 io_apic_ints[pin].dst_apic_id = io_apic_id;
2134 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2135 }
2136
2137 /* special cases from MP v1.4, table 5-2 */
2138 if (type == 2) {
2139 io_apic_ints[2].int_type = 0xff; /* N/C */
2140 io_apic_ints[13].int_type = 0xff; /* N/C */
2141#if !defined(APIC_MIXED_MODE)
2142 /** FIXME: ??? */
2143 panic("sorry, can't support type 2 default yet");
2144#endif /* APIC_MIXED_MODE */
2145 }
2146 else
2147 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2148
2149 if (type == 7)
2150 io_apic_ints[0].int_type = 0xff; /* N/C */
2151 else
2152 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2153#endif /* APIC_IO */
2154}
2155
984263bc 2156/*
f13b5eec
MD
2157 * Map a physical memory address representing I/O into KVA. The I/O
2158 * block is assumed not to cross a page boundary.
2159 */
2160void *
2161permanent_io_mapping(vm_paddr_t pa)
2162{
2163 vm_offset_t vaddr;
2164 int pgeflag;
2165 int i;
2166
2167 KKASSERT(pa < 0x100000000LL);
2168
2169 pgeflag = 0; /* not used for SMP yet */
2170
2171 /*
2172 * If the requested physical address has already been incidently
2173 * mapped, just use the existing mapping. Otherwise create a new
2174 * mapping.
2175 */
2176 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2177 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2178 ((vm_offset_t)pa & PG_FRAME)) {
2179 break;
2180 }
2181 }
2182 if (i == SMPpt_alloc_index) {
2183 if (i == NPTEPG - 2) {
2184 panic("permanent_io_mapping: We ran out of space"
2185 " in SMPpt[]!");
2186 }
2187 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2188 ((vm_offset_t)pa & PG_FRAME));
2189 ++SMPpt_alloc_index;
2190 }
2191 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2192 ((vm_offset_t)pa & PAGE_MASK);
2193 return ((void *)vaddr);
2194}
2195
2196/*
984263bc
MD
2197 * start each AP in our list
2198 */
2199static int
2200start_all_aps(u_int boot_addr)
2201{
b45759e1
MD
2202 int x, i, pg;
2203 int shift;
984263bc
MD
2204 u_char mpbiosreason;
2205 u_long mpbioswarmvec;
8a8d5d85 2206 struct mdglobaldata *gd;
0f7a3396 2207 struct privatespace *ps;
984263bc
MD
2208 char *stack;
2209 uintptr_t kptbase;
2210
2211 POSTCODE(START_ALL_APS_POST);
2212
b52c8db0
SZ
2213 /* Initialize BSP's local APIC */
2214 apic_initialize(TRUE);
984263bc
MD
2215 bsp_apic_ready = 1;
2216
2217 /* install the AP 1st level boot code */
2218 install_ap_tramp(boot_addr);
2219
2220
2221 /* save the current value of the warm-start vector */
2222 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD
2223 outb(CMOS_REG, BIOS_RESET);
2224 mpbiosreason = inb(CMOS_DATA);
984263bc 2225
984263bc
MD
2226 /* set up temporary P==V mapping for AP boot */
2227 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2228 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 2229 for (x = 0; x < NKPT; x++) {
984263bc
MD
2230 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2231 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 2232 }
0f7a3396 2233 cpu_invltlb();
984263bc
MD
2234
2235 /* start each AP */
2236 for (x = 1; x <= mp_naps; ++x) {
2237
2238 /* This is a bit verbose, it will go away soon. */
2239
2240 /* first page of AP's private space */
2241 pg = x * i386_btop(sizeof(struct privatespace));
2242
81c04d07 2243 /* allocate new private data page(s) */
e4846942 2244 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 2245 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 2246 /* wire it into the private page table page */
81c04d07
MD
2247 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2248 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2249 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2250 }
2251 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2252
2253 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2254 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2255 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2256 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD
2257
2258 /* allocate and set up an idle stack data page */
e4846942 2259 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2260 for (i = 0; i < UPAGES; i++) {
81c04d07 2261 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 2262 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 2263 }
984263bc 2264
8a8d5d85
MD
2265 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2266 bzero(gd, sizeof(*gd));
0f7a3396 2267 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 2268
984263bc 2269 /* prime data page for it to use */
8a8d5d85 2270 mi_gdinit(&gd->mi, x);
8ad65e08 2271 cpu_gdinit(gd, x);
81c04d07
MD
2272 gd->gd_CMAP1 = &SMPpt[pg + 0];
2273 gd->gd_CMAP2 = &SMPpt[pg + 1];
2274 gd->gd_CMAP3 = &SMPpt[pg + 2];
2275 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD
2276 gd->gd_CADDR1 = ps->CPAGE1;
2277 gd->gd_CADDR2 = ps->CPAGE2;
2278 gd->gd_CADDR3 = ps->CPAGE3;
2279 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
e4846942 2280 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 2281 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc
MD
2282
2283 /* setup a vector to our boot code */
2284 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2285 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
984263bc
MD
2286 outb(CMOS_REG, BIOS_RESET);
2287 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
984263bc 2288
8a8d5d85
MD
2289 /*
2290 * Setup the AP boot stack
2291 */
0f7a3396 2292 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
2293 bootAP = x;
2294
2295 /* attempt to start the Application Processor */
2296 CHECK_INIT(99); /* setup checkpoints */
0f7a3396 2297 if (!start_ap(gd, boot_addr)) {
26be20a0 2298 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD
2299 CHECK_PRINT("trace"); /* show checkpoints */
2300 /* better panic as the AP may be running loose */
26be20a0 2301 kprintf("panic y/n? [y] ");
984263bc
MD
2302 if (cngetc() != 'n')
2303 panic("bye-bye");
2304 }
2305 CHECK_PRINT("trace"); /* show checkpoints */
2306
2307 /* record its version info */
2308 cpu_apic_versions[x] = cpu_apic_versions[0];
984263bc
MD
2309 }
2310
0f7a3396
MD
2311 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2312 ncpus = x;
2313
b45759e1
MD
2314 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2315 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2316 ;
2317 --shift;
2318 ncpus2_shift = shift;
2319 ncpus2 = 1 << shift;
90100055
JH
2320 ncpus2_mask = ncpus2 - 1;
2321
b45759e1
MD
2322 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2323 if ((1 << shift) < ncpus)
2324 ++shift;
2325 ncpus_fit = 1 << shift;
2326 ncpus_fit_mask = ncpus_fit - 1;
2327
984263bc 2328 /* build our map of 'other' CPUs */
0f7a3396 2329 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
e4846942 2330 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 2331 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD
2332
2333 /* fill in our (BSP) APIC version */
2334 cpu_apic_versions[0] = lapic.version;
2335
2336 /* restore the warmstart vector */
2337 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD
2338 outb(CMOS_REG, BIOS_RESET);
2339 outb(CMOS_DATA, mpbiosreason);
984263bc
MD
2340
2341 /*
8a8d5d85
MD
2342 * NOTE! The idlestack for the BSP was setup by locore. Finish
2343 * up, clean out the P==V mapping we did earlier.
984263bc 2344 */
984263bc
MD
2345 for (x = 0; x < NKPT; x++)
2346 PTD[x] = 0;
2347 pmap_set_opt();
2348
2349 /* number of APs actually started */
8a8d5d85 2350 return ncpus - 1;
984263bc
MD
2351}
2352
2353
2354/*
2355 * load the 1st level AP boot code into base memory.
2356 */
2357
2358/* targets for relocation */
2359extern void bigJump(void);
2360extern void bootCodeSeg(void);
2361extern void bootDataSeg(void);
2362extern void MPentry(void);
2363extern u_int MP_GDT;
2364extern u_int mp_gdtbase;
2365
2366static void
2367install_ap_tramp(u_int boot_addr)
2368{
2369 int x;
2370 int size = *(int *) ((u_long) & bootMP_size);
2371 u_char *src = (u_char *) ((u_long) bootMP);
2372 u_char *dst = (u_char *) boot_addr + KERNBASE;
2373 u_int boot_base = (u_int) bootMP;
2374 u_int8_t *dst8;
2375 u_int16_t *dst16;
2376 u_int32_t *dst32;
2377
2378 POSTCODE(INSTALL_AP_TRAMP_POST);
2379
2380 for (x = 0; x < size; ++x)
2381 *dst++ = *src++;
2382
2383 /*
2384 * modify addresses in code we just moved to basemem. unfortunately we
2385 * need fairly detailed info about mpboot.s for this to work. changes
2386 * to mpboot.s might require changes here.
2387 */
2388
2389 /* boot code is located in KERNEL space */
2390 dst = (u_char *) boot_addr + KERNBASE;
2391
2392 /* modify the lgdt arg */
2393 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2394 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2395
2396 /* modify the ljmp target for MPentry() */
2397 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2398 *dst32 = ((u_int) MPentry - KERNBASE);
2399
2400 /* modify the target for boot code segment */
2401 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2402 dst8 = (u_int8_t *) (dst16 + 1);
2403 *dst16 = (u_int) boot_addr & 0xffff;
2404 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2405
2406 /* modify the target for boot data segment */
2407 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2408 dst8 = (u_int8_t *) (dst16 + 1);
2409 *dst16 = (u_int) boot_addr & 0xffff;
2410 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2411}
2412
2413
2414/*
2415 * this function starts the AP (application processor) identified
2416 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2417 * to accomplish this. This is necessary because of the nuances
2418 * of the different hardware we might encounter. It ain't pretty,
2419 * but it seems to work.
a108bf71
MD
2420 *
2421 * NOTE: eventually an AP gets to ap_init(), which is called just
2422 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD
2423 */
2424static int
0f7a3396 2425start_ap(struct mdglobaldata *gd, u_int boot_addr)
984263bc
MD
2426{
2427 int physical_cpu;
2428 int vector;
984263bc
MD
2429 u_long icr_lo, icr_hi;
2430
2431 POSTCODE(START_AP_POST);
2432
2433 /* get the PHYSICAL APIC ID# */
0f7a3396 2434 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD
2435
2436 /* calculate the vector */
2437 vector = (boot_addr >> 12) & 0xff;
2438
8a8d5d85
MD
2439 /* Make sure the target cpu sees everything */
2440 wbinvd();
984263bc
MD
2441
2442 /*
2443 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2444 * and running the target CPU. OR this INIT IPI might be latched (P5
2445 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2446 * ignored.
2447 */
2448
2449 /* setup the address for the target AP */
2450 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2451 icr_hi |= (physical_cpu << 24);
2452 lapic.icr_hi = icr_hi;
2453
2454 /* do an INIT IPI: assert RESET */
2455 icr_lo = lapic.icr_lo & 0xfff00000;
2456 lapic.icr_lo = icr_lo | 0x0000c500;
2457
2458 /* wait for pending status end */
2459 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2460 /* spin */ ;
2461
2462 /* do an INIT IPI: deassert RESET */
2463 lapic.icr_lo = icr_lo | 0x00008500;
2464
2465 /* wait for pending status end */
2466 u_sleep(10000); /* wait ~10mS */
2467 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2468 /* spin */ ;
2469
2470 /*
2471 * next we do a STARTUP IPI: the previous INIT IPI might still be
2472 * latched, (P5 bug) this 1st STARTUP would then terminate
2473 * immediately, and the previously started INIT IPI would continue. OR
2474 * the previous INIT IPI has already run. and this STARTUP IPI will
2475 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2476 * will run.
2477 */
2478
2479 /* do a STARTUP IPI */
2480 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2481 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2482 /* spin */ ;
2483 u_sleep(200); /* wait ~200uS */
2484
2485 /*
2486 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2487 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2488 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2489 * recognized after hardware RESET or INIT IPI.
2490 */
2491
2492 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2493 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2494 /* spin */ ;
2495 u_sleep(200); /* wait ~200uS */
2496
8a8d5d85 2497 /* wait for it to start, see ap_init() */
984263bc 2498 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 2499 while (read_apic_timer()) {
0f7a3396 2500 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
984263bc 2501 return 1; /* return SUCCESS */
8a8d5d85 2502 }
984263bc
MD
2503 return 0; /* return FAILURE */
2504}
2505
2506
2507/*
0f7a3396 2508 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 2509 *
0f7a3396
MD
2510 * If for some reason we were unable to start all cpus we cannot safely
2511 * use broadcast IPIs.
984263bc
MD
2512 */
2513void
2514smp_invltlb(void)
2515{
97359a5b 2516#ifdef SMP
0f7a3396 2517 if (smp_startup_mask == smp_active_mask) {
984263bc 2518 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396
MD
2519 } else {
2520 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2521 APIC_DELMODE_FIXED);
2522 }
97359a5b 2523#endif
984263bc
MD
2524}
2525
984263bc
MD
2526/*
2527 * When called the executing CPU will send an IPI to all other CPUs
2528 * requesting that they halt execution.
2529 *
2530 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2531 *
2532 * - Signals all CPUs in map to stop.
2533 * - Waits for each to stop.
2534 *
2535 * Returns:
2536 * -1: error
2537 * 0: NA
2538 * 1: ok
2539 *
2540 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2541 * from executing at same time.
2542 */
2543int
2544stop_cpus(u_int map)
2545{
0f7a3396 2546 map &= smp_active_mask;
984263bc
MD
2547
2548 /* send the Xcpustop IPI to all CPUs in map */
2549 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2550
2551 while ((stopped_cpus & map) != map)
2552 /* spin */ ;
2553
2554 return 1;
2555}
2556
2557
2558/*
2559 * Called by a CPU to restart stopped CPUs.
2560 *
2561 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2562 *
2563 * - Signals all CPUs in map to restart.
2564 * - Waits for each to restart.
2565 *
2566 * Returns:
2567 * -1: error
2568 * 0: NA
2569 * 1: ok
2570 */
2571int
2572restart_cpus(u_int map)
2573{
0f7a3396
MD
2574 /* signal other cpus to restart */
2575 started_cpus = map & smp_active_mask;
984263bc
MD
2576
2577 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2578 /* spin */ ;
2579
2580 return 1;
2581}
2582
984263bc 2583/*
8a8d5d85
MD
2584 * This is called once the mpboot code has gotten us properly relocated
2585 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2586 * and when it returns the scheduler will call the real cpu_idle() main
2587 * loop for the idlethread. Interrupts are disabled on entry and should
2588 * remain disabled at return.
984263bc 2589 */
984263bc 2590void
8a8d5d85 2591ap_init(void)
984263bc
MD
2592{
2593 u_int apic_id;
2594
8a8d5d85 2595 /*
0f7a3396
MD
2596 * Adjust smp_startup_mask to signal the BSP that we have started
2597 * up successfully. Note that we do not yet hold the BGL. The BSP
2598 * is waiting for our signal.
2599 *
2600 * We can't set our bit in smp_active_mask yet because we are holding
2601 * interrupts physically disabled and remote cpus could deadlock
2602 * trying to send us an IPI.
8a8d5d85 2603 */
0f7a3396 2604 smp_startup_mask |= 1 << mycpu->gd_cpuid;
35238fa5 2605 cpu_mfence();
8a8d5d85
MD
2606
2607 /*
41a01a4d
MD
2608 * Interlock for finalization. Wait until mp_finish is non-zero,
2609 * then get the MP lock.
2610 *
2611 * Note: We are in a critical section.
2612 *
2613 * Note: We have to synchronize td_mpcount to our desired MP state
2614 * before calling cpu_try_mplock().
2615 *
2616 * Note: we are the idle thread, we can only spin.
2617 *
35238fa5
MD
2618 * Note: The load fence is memory volatile and prevents the compiler
2619 * from improperly caching mp_finish, and the cpu from improperly
2620 * caching it.
8a8d5d85 2621 */
41a01a4d 2622 while (mp_finish == 0)
35238fa5 2623 cpu_lfence();
d9ebdce5 2624 ++curthread->td_mpcount;
8a8d5d85
MD
2625 while (cpu_try_mplock() == 0)
2626 ;
2627
374133e3
MD
2628 if (cpu_feature & CPUID_TSC) {
2629 /*
2630 * The BSP is constantly updating tsc0_offset, figure out the
2631 * relative difference to synchronize ktrdump.
2632 */
2633 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2634 }
2635
984263bc
MD
2636 /* BSP may have changed PTD while we're waiting for the lock */
2637 cpu_invltlb();
2638
984263bc
MD
2639#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2640 lidt(&r_idt);
2641#endif
2642
2643 /* Build our map of 'other' CPUs. */
0f7a3396 2644 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
984263bc 2645
26be20a0 2646 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc 2647
984263bc
MD
2648 /* A quick check from sanity claus */
2649 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85 2650 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW
2651 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2652 kprintf("SMP: apic_id = %d\n", apic_id);
2653 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD
2654 panic("cpuid mismatch! boom!!");
2655 }
2656
b52c8db0
SZ
2657 /* Initialize AP's local APIC for irq's */
2658 apic_initialize(FALSE);
984263bc
MD
2659
2660 /* Set memory range attributes for this CPU to match the BSP */
2661 mem_range_AP_init();
2662
a2a5ad0d 2663 /*
4c9f5a7f
MD
2664 * Once we go active we must process any IPIQ messages that may
2665 * have been queued, because no actual IPI will occur until we
2666 * set our bit in the smp_active_mask. If we don't the IPI
2667 * message interlock could be left set which would also prevent
2668 * further IPIs.
2669 *
8a8d5d85
MD
2670 * The idle loop doesn't expect the BGL to be held and while
2671 * lwkt_switch() normally cleans things up this is a special case
2672 * because we returning almost directly into the idle loop.
41a01a4d
MD
2673 *
2674 * The idle thread is never placed on the runq, make sure
4c9f5a7f 2675 * nothing we've done put it there.
8a8d5d85 2676 */
96728c05 2677 KKASSERT(curthread->td_mpcount == 1);
41a01a4d 2678 smp_active_mask |= 1 << mycpu->gd_cpuid;
d19f6edf
MD
2679
2680 /*
2681 * Enable interrupts here. idle_restore will also do it, but
2682 * doing it here lets us clean up any strays that got posted to
2683 * the CPU during the AP boot while we are still in a critical
2684 * section.
2685 */
2686 __asm __volatile("sti; pause; pause"::);
2687 mdcpu->gd_fpending = 0;
2688 mdcpu->gd_ipending = 0;
2689
4a19580d 2690 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 2691 lwkt_process_ipiq();
d19f6edf
MD
2692
2693 /*
2694 * Releasing the mp lock lets the BSP finish up the SMP init
2695 */
96728c05 2696 rel_mplock();
41a01a4d 2697 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD
2698}
2699
41a01a4d
MD
2700/*
2701 * Get SMP fully working before we start initializing devices.
2702 */
2703static
2704void
2705ap_finish(void)
2706{
2707 mp_finish = 1;
2708 if (bootverbose)
26be20a0 2709 kprintf("Finish MP startup\n");
374133e3
MD
2710 if (cpu_feature & CPUID_TSC)
2711 tsc0_offset = rdtsc();
2712 tsc_offsets[0] = 0;
41a01a4d 2713 rel_mplock();
374133e3 2714 while (smp_active_mask != smp_startup_mask) {
35238fa5 2715 cpu_lfence();
374133e3
MD
2716 if (cpu_feature & CPUID_TSC)
2717 tsc0_offset = rdtsc();
2718 }
4da43e1f 2719 while (try_mplock() == 0)
41a01a4d
MD
2720 ;
2721 if (bootverbose)
26be20a0 2722 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD
2723}
2724
ba39e2e0 2725SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 2726
96728c05
MD
2727void
2728cpu_send_ipiq(int dcpu)
2729{
41a01a4d
MD
2730 if ((1 << dcpu) & smp_active_mask)
2731 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 2732}
41a01a4d
MD
2733
2734#if 0 /* single_apic_ipi_passive() not working yet */
2735/*
2736 * Returns 0 on failure, 1 on success
2737 */
2738int
2739cpu_send_ipiq_passive(int dcpu)
2740{
2741 int r = 0;
2742 if ((1 << dcpu) & smp_active_mask) {
2743 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2744 APIC_DELMODE_FIXED);
2745 }
2746 return(r);
2747}
2748#endif
2749