AHCI - Port multiplier plug/unplug work, tuning, cleanup, bug fixes.
[dragonfly.git] / sys / dev / disk / ahci / ahci_attach.c
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1/*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 *
17 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
18 *
19 * This code is derived from software contributed to The DragonFly Project
20 * by Matthew Dillon <dillon@backplane.com>
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * 2. Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * 3. Neither the name of The DragonFly Project nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific, prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
39 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
40 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
41 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
46 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * SUCH DAMAGE.
48 *
49 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
50 */
51
52#include "ahci.h"
53
54static int ahci_vt8251_attach(device_t);
55static int ahci_ati_sb600_attach(device_t);
56static int ahci_nvidia_mcp_attach(device_t);
57static int ahci_pci_attach(device_t);
58static int ahci_pci_detach(device_t);
59
60static const struct ahci_device ahci_devices[] = {
61 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
62 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
63 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
64 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
65 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
66 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
71 { 0, 0,
72 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
73};
74
75u_int32_t AhciForceGen1 = 0; /* XXX add sysctl/kenv support */
76
77/*
78 * Match during probe and attach. The device does not yet have a softc.
79 */
80const struct ahci_device *
81ahci_lookup_device(device_t dev)
82{
83 const struct ahci_device *ad;
84 u_int16_t vendor = pci_get_vendor(dev);
85 u_int16_t product = pci_get_device(dev);
86 u_int8_t class = pci_get_class(dev);
87 u_int8_t subclass = pci_get_subclass(dev);
88 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
89
90 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
91 if (ad->ad_vendor == vendor && ad->ad_product == product)
92 return (ad);
93 }
94
95 /*
96 * Last ad is the default match if the PCI device matches SATA.
97 */
98 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
99 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
100 kprintf("match generic sata\n");
101 return (ad);
102 }
103
104 return (NULL);
105}
106
107/*
108 * Attach functions. They all eventually fall through to ahci_pci_attach().
109 */
110static int
111ahci_vt8251_attach(device_t dev)
112{
113 struct ahci_softc *sc = device_get_softc(dev);
114
115 sc->sc_flags |= AHCI_F_NO_NCQ;
116 return (ahci_pci_attach(dev));
117}
118
119static int
120ahci_ati_sb600_attach(device_t dev)
121{
122 struct ahci_softc *sc = device_get_softc(dev);
123 pcireg_t magic;
124 u_int8_t subclass = pci_get_subclass(dev);
125 u_int8_t revid;
126
127 if (subclass == PCIS_STORAGE_IDE) {
128 revid = pci_read_config(dev, PCIR_REVID, 1);
129 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
130 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
131 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
132 pci_write_config(dev, PCIR_REVID,
133 (PCIC_STORAGE << 24) |
134 (PCIS_STORAGE_SATA << 16) |
135 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
136 revid, 4);
137 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
138 }
139
140 sc->sc_flags |= AHCI_F_IGN_FR;
141 return (ahci_pci_attach(dev));
142}
143
144static int
145ahci_nvidia_mcp_attach(device_t dev)
146{
147 struct ahci_softc *sc = device_get_softc(dev);
148
149 sc->sc_flags |= AHCI_F_IGN_FR;
150 return (ahci_pci_attach(dev));
151}
152
153static int
154ahci_pci_attach(device_t dev)
155{
156 struct ahci_softc *sc = device_get_softc(dev);
f4553de1 157 struct ahci_port *ap;
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158 const char *gen;
159 u_int32_t cap, pi, reg;
160 bus_addr_t addr;
161 int i;
162 int error;
163 const char *revision;
164
165 /*
166 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
167 */
168 sc->sc_dev = dev;
169 sc->sc_rid_irq = AHCI_IRQ_RID;
170 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
171 RF_SHAREABLE | RF_ACTIVE);
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172 if (sc->sc_irq == NULL) {
173 device_printf(dev, "unable to map interrupt\n");
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174 ahci_pci_detach(dev);
175 return (ENXIO);
176 }
177
178 /*
179 * When mapping the register window store the tag and handle
180 * separately so we can use the tag with per-port bus handle
181 * sub-spaces.
182 */
183 sc->sc_rid_regs = PCIR_BAR(5);
184 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
185 &sc->sc_rid_regs, RF_ACTIVE);
186 if (sc->sc_regs == NULL) {
187 device_printf(dev, "unable to map registers\n");
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188 ahci_pci_detach(dev);
189 return (ENXIO);
190 }
191 sc->sc_iot = rman_get_bustag(sc->sc_regs);
192 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
193
194 /*
195 * Initialize the chipset and then set the interrupt vector up
196 */
197 error = ahci_init(sc);
198 if (error) {
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199 ahci_pci_detach(dev);
200 return (ENXIO);
201 }
202
203 /*
204 * Get the AHCI capabilities and max number of concurrent
205 * command tags and set up the DMA tags.
206 */
207 cap = ahci_read(sc, AHCI_REG_CAP);
208 if (sc->sc_flags & AHCI_F_NO_NCQ)
209 cap &= ~AHCI_REG_CAP_SNCQ;
210 sc->sc_cap = cap;
211 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
212
213 addr = (cap & AHCI_REG_CAP_S64A) ?
214 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
215
216 /*
217 * DMA tags for allocation of DMA memory buffers, lists, and so
218 * forth. These are typically per-port.
219 */
220 error = 0;
221 error += bus_dma_tag_create(
222 NULL, /* parent tag */
223 256, /* alignment */
224 PAGE_SIZE, /* boundary */
225 addr, /* loaddr? */
226 BUS_SPACE_MAXADDR, /* hiaddr */
227 NULL, /* filter */
228 NULL, /* filterarg */
229 sizeof(struct ahci_rfis), /* [max]size */
230 1, /* maxsegs */
231 sizeof(struct ahci_rfis), /* maxsegsz */
232 0, /* flags */
233 &sc->sc_tag_rfis); /* return tag */
234
235 error += bus_dma_tag_create(
236 NULL, /* parent tag */
237 32, /* alignment */
238 4096 * 1024, /* boundary */
239 addr, /* loaddr? */
240 BUS_SPACE_MAXADDR, /* hiaddr */
241 NULL, /* filter */
242 NULL, /* filterarg */
243 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
244 1, /* maxsegs */
245 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
246 0, /* flags */
247 &sc->sc_tag_cmdh); /* return tag */
248
249 /*
250 * NOTE: ahci_cmd_table is sized to a power of 2
251 */
252 error += bus_dma_tag_create(
253 NULL, /* parent tag */
254 sizeof(struct ahci_cmd_table), /* alignment */
255 4096 * 1024, /* boundary */
256 addr, /* loaddr? */
257 BUS_SPACE_MAXADDR, /* hiaddr */
258 NULL, /* filter */
259 NULL, /* filterarg */
260 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
261 1, /* maxsegs */
262 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
263 0, /* flags */
264 &sc->sc_tag_cmdt); /* return tag */
265
266 /*
267 * The data tag is used for later dmamaps and not immediately
268 * allocated.
269 */
270 error += bus_dma_tag_create(
271 NULL, /* parent tag */
272 4, /* alignment */
273 0, /* boundary */
274 addr, /* loaddr? */
275 BUS_SPACE_MAXADDR, /* hiaddr */
276 NULL, /* filter */
277 NULL, /* filterarg */
278 4096 * 1024, /* maxiosize */
279 AHCI_MAX_PRDT, /* maxsegs */
280 65536, /* maxsegsz */
281 0, /* flags */
282 &sc->sc_tag_data); /* return tag */
283
284 if (error) {
285 device_printf(dev, "unable to create dma tags\n");
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286 ahci_pci_detach(dev);
287 return (ENXIO);
288 }
289
290 switch (cap & AHCI_REG_CAP_ISS) {
291 case AHCI_REG_CAP_ISS_G1:
292 gen = "1 (1.5Gbps)";
293 break;
294 case AHCI_REG_CAP_ISS_G1_2:
295 gen = "1 (1.5Gbps) and 2 (3Gbps)";
296 break;
297 default:
298 gen = "unknown";
299 break;
300 }
301
302 /* check the revision */
303 reg = ahci_read(sc, AHCI_REG_VS);
304 switch (reg) {
305 case AHCI_REG_VS_0_95:
306 revision = "AHCI 0.95";
307 break;
308 case AHCI_REG_VS_1_0:
309 revision = "AHCI 1.0";
310 break;
311 case AHCI_REG_VS_1_1:
312 revision = "AHCI 1.1";
313 break;
314 case AHCI_REG_VS_1_2:
315 revision = "AHCI 1.2";
316 break;
317 default:
318 device_printf(sc->sc_dev,
319 "Warning: Unknown AHCI revision 0x%08x\n", reg);
320 revision = "AHCI <unknown>";
321 break;
322 }
323
324 device_printf(dev,
325 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n",
326 revision,
327 cap, AHCI_FMT_CAP,
328 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
329
330 pi = ahci_read(sc, AHCI_REG_PI);
331 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
332 DEVNAME(sc), pi);
333
334#ifdef AHCI_COALESCE
335 /* Naive coalescing support - enable for all ports. */
336 if (cap & AHCI_REG_CAP_CCCS) {
337 u_int16_t ccc_timeout = 20;
338 u_int8_t ccc_numcomplete = 12;
339 u_int32_t ccc_ctl;
340
341 /* disable coalescing during reconfiguration. */
342 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
343 ccc_ctl &= ~0x00000001;
344 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
345
346 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
347 if (pi & sc->sc_ccc_mask) {
348 /* A conflict with the implemented port list? */
349 printf("%s: coalescing interrupt/implemented port list "
350 "conflict, PI: %08x, ccc_mask: %08x\n",
351 DEVNAME(sc), pi, sc->sc_ccc_mask);
352 sc->sc_ccc_mask = 0;
353 goto noccc;
354 }
355
356 /* ahci_port_start will enable each port when it starts. */
357 sc->sc_ccc_ports = pi;
358 sc->sc_ccc_ports_cur = 0;
359
360 /* program thresholds and enable overall coalescing. */
361 ccc_ctl &= ~0xffffff00;
362 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
363 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
364 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
365 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
366 }
367noccc:
368#endif
369 /*
370 * Allocate per-port resources
371 *
372 * Ignore attach errors, leave the port intact for
373 * rescan and continue the loop.
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374 *
375 * All ports are attached in parallel but the CAM scan-bus
376 * is held up until all ports are attached so we get a deterministic
377 * order.
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378 */
379 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
380 if ((pi & (1 << i)) == 0) {
381 /* dont allocate stuff if the port isnt implemented */
382 continue;
383 }
384 error = ahci_port_alloc(sc, i);
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385 }
386
387 /*
388 * Setup the interrupt vector and enable interrupts. Note that
389 * since the irq may be shared we do not set it up until we are
390 * ready to go.
391 */
392 if (error == 0) {
393 error = bus_setup_intr(dev, sc->sc_irq, 0, ahci_intr, sc,
f4553de1 394 &sc->sc_irq_handle, NULL);
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395 }
396
397 if (error) {
398 device_printf(dev, "unable to install interrupt\n");
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399 ahci_pci_detach(dev);
400 return (ENXIO);
401 }
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402
403 /*
404 * Master interrupt enable, and call ahci_intr() in case we race
405 * our AHCI_F_INT_GOOD flag.
406 */
407 crit_enter();
258223a3 408 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
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409 sc->sc_flags |= AHCI_F_INT_GOOD;
410 crit_exit();
411 ahci_intr(sc);
412
413 /*
414 * All ports are probing in parallel. Wait for them to finish
415 * and then issue the cam attachment and bus scan serially so
416 * the 'da' assignments are deterministic.
417 */
418 for (i = 0; i < AHCI_MAX_PORTS; i++) {
419 if ((ap = sc->sc_ports[i]) != NULL) {
420 while (ap->ap_signal & AP_SIGF_INIT)
421 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
831bc9e3 422 ahci_os_lock_port(ap);
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423 if (ahci_cam_attach(ap) == 0) {
424 ahci_cam_changed(ap, NULL, -1);
831bc9e3 425 ahci_os_unlock_port(ap);
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426 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
427 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
428 }
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429 } else {
430 ahci_os_unlock_port(ap);
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431 }
432 }
433 }
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434
435 return(0);
436}
437
438/*
439 * Device unload / detachment
440 */
441static int
442ahci_pci_detach(device_t dev)
443{
444 struct ahci_softc *sc = device_get_softc(dev);
445 struct ahci_port *ap;
446 int i;
447
448 /*
449 * Disable the controller and de-register the interrupt, if any.
450 *
f4553de1 451 * XXX interlock last interrupt?
258223a3 452 */
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453 sc->sc_flags &= ~AHCI_F_INT_GOOD;
454 if (sc->sc_regs)
258223a3 455 ahci_write(sc, AHCI_REG_GHC, 0);
f4553de1 456
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457 if (sc->sc_irq_handle) {
458 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
459 sc->sc_irq_handle = NULL;
460 }
461
462 /*
463 * Free port structures and DMA memory
464 */
465 for (i = 0; i < AHCI_MAX_PORTS; i++) {
466 ap = sc->sc_ports[i];
467 if (ap) {
468 ahci_cam_detach(ap);
469 ahci_port_free(sc, i);
470 }
471 }
472
473 /*
474 * Clean up the bus space
475 */
476 if (sc->sc_irq) {
477 bus_release_resource(dev, SYS_RES_IRQ,
478 sc->sc_rid_irq, sc->sc_irq);
479 sc->sc_irq = NULL;
480 }
481 if (sc->sc_regs) {
482 bus_release_resource(dev, SYS_RES_MEMORY,
483 sc->sc_rid_regs, sc->sc_regs);
484 sc->sc_regs = NULL;
485 }
486
487 if (sc->sc_tag_rfis) {
488 bus_dma_tag_destroy(sc->sc_tag_rfis);
489 sc->sc_tag_rfis = NULL;
490 }
491 if (sc->sc_tag_cmdh) {
492 bus_dma_tag_destroy(sc->sc_tag_cmdh);
493 sc->sc_tag_cmdh = NULL;
494 }
495 if (sc->sc_tag_cmdt) {
496 bus_dma_tag_destroy(sc->sc_tag_cmdt);
497 sc->sc_tag_cmdt = NULL;
498 }
499 if (sc->sc_tag_data) {
500 bus_dma_tag_destroy(sc->sc_tag_data);
501 sc->sc_tag_data = NULL;
502 }
503
504 return (0);
505}