bge: Add missing bit of commit f47afe1
[dragonfly.git] / sys / dev / netif / bge / if_bgereg.h
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
011c0f93 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
591dfc77 34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
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35 */
36
37/*
38 * BCM570x memory map. The internal memory layout varies somewhat
39 * depending on whether or not we have external SSRAM attached.
40 * The BCM5700 can have up to 16MB of external memory. The BCM5701
41 * is apparently not designed to use external SSRAM. The mappings
42 * up to the first 4 send rings are the same for both internal and
43 * external memory configurations. Note that mini RX ring space is
44 * only available with external SSRAM configurations, which means
45 * the mini RX ring is not supported on the BCM5701.
46 *
47 * The NIC's memory can be accessed by the host in one of 3 ways:
48 *
49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
50 * registers in PCI config space can be used to read any 32-bit
51 * address within the NIC's memory.
52 *
53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
54 * space can be used in conjunction with the memory window in the
55 * device register space at offset 0x8000 to read any 32K chunk
56 * of NIC memory.
57 *
58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
59 * set, the device I/O mapping consumes 32MB of host address space,
60 * allowing all of the registers and internal NIC memory to be
61 * accessed directly. NIC memory addresses are offset by 0x01000000.
62 * Flat mode consumes so much host address space that it is not
63 * recommended.
64 */
65#define BGE_PAGE_ZERO 0x00000000
66#define BGE_PAGE_ZERO_END 0x000000FF
67#define BGE_SEND_RING_RCB 0x00000100
68#define BGE_SEND_RING_RCB_END 0x000001FF
69#define BGE_RX_RETURN_RING_RCB 0x00000200
70#define BGE_RX_RETURN_RING_RCB_END 0x000002FF
71#define BGE_STATS_BLOCK 0x00000300
72#define BGE_STATS_BLOCK_END 0x00000AFF
73#define BGE_STATUS_BLOCK 0x00000B00
74#define BGE_STATUS_BLOCK_END 0x00000B4F
75#define BGE_SOFTWARE_GENCOMM 0x00000B50
76#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
77#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
78#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
79#define BGE_UNMAPPED 0x00001000
80#define BGE_UNMAPPED_END 0x00001FFF
81#define BGE_DMA_DESCRIPTORS 0x00002000
82#define BGE_DMA_DESCRIPTORS_END 0x00003FFF
83#define BGE_SEND_RING_1_TO_4 0x00004000
84#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
85
86/* Mappings for internal memory configuration */
87#define BGE_STD_RX_RINGS 0x00006000
88#define BGE_STD_RX_RINGS_END 0x00006FFF
89#define BGE_JUMBO_RX_RINGS 0x00007000
90#define BGE_JUMBO_RX_RINGS_END 0x00007FFF
91#define BGE_BUFFPOOL_1 0x00008000
92#define BGE_BUFFPOOL_1_END 0x0000FFFF
93#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
94#define BGE_BUFFPOOL_2_END 0x00017FFF
95#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
96#define BGE_BUFFPOOL_3_END 0x0001FFFF
97
98/* Mappings for external SSRAM configurations */
99#define BGE_SEND_RING_5_TO_6 0x00006000
100#define BGE_SEND_RING_5_TO_6_END 0x00006FFF
101#define BGE_SEND_RING_7_TO_8 0x00007000
102#define BGE_SEND_RING_7_TO_8_END 0x00007FFF
103#define BGE_SEND_RING_9_TO_16 0x00008000
104#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
105#define BGE_EXT_STD_RX_RINGS 0x0000C000
106#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
107#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
108#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
109#define BGE_MINI_RX_RINGS 0x0000E000
110#define BGE_MINI_RX_RINGS_END 0x0000FFFF
111#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
112#define BGE_AVAIL_REGION1_END 0x00017FFF
113#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
114#define BGE_AVAIL_REGION2_END 0x0001FFFF
115#define BGE_EXT_SSRAM 0x00020000
116#define BGE_EXT_SSRAM_END 0x000FFFFF
117
118
119/*
120 * BCM570x register offsets. These are memory mapped registers
121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
122 * Each register must be accessed using 32 bit operations.
123 *
124 * All registers are accessed through a 32K shared memory block.
125 * The first group of registers are actually copies of the PCI
126 * configuration space registers.
127 */
128
129/*
130 * PCI registers defined in the PCI 2.2 spec.
131 */
132#define BGE_PCI_VID 0x00
133#define BGE_PCI_DID 0x02
134#define BGE_PCI_CMD 0x04
135#define BGE_PCI_STS 0x06
136#define BGE_PCI_REV 0x08
137#define BGE_PCI_CLASS 0x09
138#define BGE_PCI_CACHESZ 0x0C
139#define BGE_PCI_LATTIMER 0x0D
140#define BGE_PCI_HDRTYPE 0x0E
141#define BGE_PCI_BIST 0x0F
142#define BGE_PCI_BAR0 0x10
143#define BGE_PCI_BAR1 0x14
144#define BGE_PCI_SUBSYS 0x2C
145#define BGE_PCI_SUBVID 0x2E
146#define BGE_PCI_ROMBASE 0x30
147#define BGE_PCI_CAPPTR 0x34
148#define BGE_PCI_INTLINE 0x3C
149#define BGE_PCI_INTPIN 0x3D
150#define BGE_PCI_MINGNT 0x3E
151#define BGE_PCI_MAXLAT 0x3F
152#define BGE_PCI_PCIXCAP 0x40
153#define BGE_PCI_NEXTPTR_PM 0x41
154#define BGE_PCI_PCIX_CMD 0x42
155#define BGE_PCI_PCIX_STS 0x44
156#define BGE_PCI_PWRMGMT_CAPID 0x48
157#define BGE_PCI_NEXTPTR_VPD 0x49
158#define BGE_PCI_PWRMGMT_CAPS 0x4A
159#define BGE_PCI_PWRMGMT_CMD 0x4C
160#define BGE_PCI_PWRMGMT_STS 0x4D
161#define BGE_PCI_PWRMGMT_DATA 0x4F
162#define BGE_PCI_VPD_CAPID 0x50
163#define BGE_PCI_NEXTPTR_MSI 0x51
164#define BGE_PCI_VPD_ADDR 0x52
165#define BGE_PCI_VPD_DATA 0x54
166#define BGE_PCI_MSI_CAPID 0x58
167#define BGE_PCI_NEXTPTR_NONE 0x59
168#define BGE_PCI_MSI_CTL 0x5A
169#define BGE_PCI_MSI_ADDR_HI 0x5C
170#define BGE_PCI_MSI_ADDR_LO 0x60
171#define BGE_PCI_MSI_DATA 0x64
172
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173/* PCI MSI. ??? */
174#define BGE_PCIE_CAPID_REG 0xD0
175#define BGE_PCIE_CAPID 0x10
9a6ee7e2 176
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177/*
178 * PCI registers specific to the BCM570x family.
179 */
180#define BGE_PCI_MISC_CTL 0x68
181#define BGE_PCI_DMA_RW_CTL 0x6C
182#define BGE_PCI_PCISTATE 0x70
183#define BGE_PCI_CLKCTL 0x74
184#define BGE_PCI_REG_BASEADDR 0x78
185#define BGE_PCI_MEMWIN_BASEADDR 0x7C
186#define BGE_PCI_REG_DATA 0x80
187#define BGE_PCI_MEMWIN_DATA 0x84
188#define BGE_PCI_MODECTL 0x88
189#define BGE_PCI_MISC_CFG 0x8C
190#define BGE_PCI_MISC_LOCALCTL 0x90
191#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
192#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
193#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
194#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
195#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
196#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
197#define BGE_PCI_ISR_MBX_HI 0xB0
198#define BGE_PCI_ISR_MBX_LO 0xB4
f47afe1a 199#define BGE_PCI_PRODID_ASICREV 0xBC
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200
201/* PCI Misc. Host control register */
202#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
203#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
204#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
205#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
206#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
207#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
208#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
209#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
210#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
f47afe1a 211#define BGE_PCIMISCCTL_ASICREV_SHIFT 16
984263bc 212
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213#if BYTE_ORDER == LITTLE_ENDIAN
214#define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\
215 BGE_MODECTL_BYTESWAP_DATA | \
216 BGE_MODECTL_WORDSWAP_DATA)
217#else
218#define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\
219 BGE_MODECTL_BYTESWAP_NONFRAME |\
220 BGE_MODECTL_BYTESWAP_DATA |
221 BGE_MODECTL_WORDSWAP_DATA)
222#endif
984263bc 223
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224#define BGE_HIF_SWAP_OPTIONS BGE_PCIMISCCTL_ENDIAN_WORDSWAP
225#define BGE_INIT (BGE_HIF_SWAP_OPTIONS | \
226 BGE_PCIMISCCTL_CLEAR_INTA | \
227 BGE_PCIMISCCTL_MASK_PCI_INTR | \
228 BGE_PCIMISCCTL_INDIRECT_ACCESS)
984263bc 229
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230#define BGE_CHIPID_TIGON_I 0x4000
231#define BGE_CHIPID_TIGON_II 0x6000
232#define BGE_CHIPID_BCM5700_A0 0x7000
233#define BGE_CHIPID_BCM5700_A1 0x7001
234#define BGE_CHIPID_BCM5700_B0 0x7100
235#define BGE_CHIPID_BCM5700_B1 0x7101
236#define BGE_CHIPID_BCM5700_B2 0x7102
237#define BGE_CHIPID_BCM5700_B3 0x7103
238#define BGE_CHIPID_BCM5700_ALTIMA 0x7104
239#define BGE_CHIPID_BCM5700_C0 0x7200
240#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
241#define BGE_CHIPID_BCM5701_B0 0x0100
242#define BGE_CHIPID_BCM5701_B2 0x0102
243#define BGE_CHIPID_BCM5701_B5 0x0105
244#define BGE_CHIPID_BCM5703_A0 0x1000
245#define BGE_CHIPID_BCM5703_A1 0x1001
246#define BGE_CHIPID_BCM5703_A2 0x1002
247#define BGE_CHIPID_BCM5703_A3 0x1003
248#define BGE_CHIPID_BCM5703_B0 0x1100
249#define BGE_CHIPID_BCM5704_A0 0x2000
250#define BGE_CHIPID_BCM5704_A1 0x2001
251#define BGE_CHIPID_BCM5704_A2 0x2002
252#define BGE_CHIPID_BCM5704_A3 0x2003
253#define BGE_CHIPID_BCM5704_B0 0x2100
254#define BGE_CHIPID_BCM5705_A0 0x3000
255#define BGE_CHIPID_BCM5705_A1 0x3001
256#define BGE_CHIPID_BCM5705_A2 0x3002
257#define BGE_CHIPID_BCM5705_A3 0x3003
258#define BGE_CHIPID_BCM5750_A0 0x4000
259#define BGE_CHIPID_BCM5750_A1 0x4001
260#define BGE_CHIPID_BCM5750_A3 0x4003
261#define BGE_CHIPID_BCM5750_B0 0x4100
262#define BGE_CHIPID_BCM5750_B1 0x4101
263#define BGE_CHIPID_BCM5750_C0 0x4200
264#define BGE_CHIPID_BCM5750_C1 0x4201
265#define BGE_CHIPID_BCM5750_C2 0x4202
266#define BGE_CHIPID_BCM5714_A0 0x5000
267#define BGE_CHIPID_BCM5752_A0 0x6000
268#define BGE_CHIPID_BCM5752_A1 0x6001
269#define BGE_CHIPID_BCM5752_A2 0x6002
270#define BGE_CHIPID_BCM5714_B0 0x8000
271#define BGE_CHIPID_BCM5714_B3 0x8003
272#define BGE_CHIPID_BCM5715_A0 0x9000
273#define BGE_CHIPID_BCM5715_A1 0x9001
274#define BGE_CHIPID_BCM5715_A3 0x9003
275#define BGE_CHIPID_BCM5722_A0 0xa200
276#define BGE_CHIPID_BCM5755_A0 0xa000
277#define BGE_CHIPID_BCM5755_A1 0xa001
278#define BGE_CHIPID_BCM5755_A2 0xa002
279#define BGE_CHIPID_BCM5754_A0 0xb000
280#define BGE_CHIPID_BCM5754_A1 0xb001
281#define BGE_CHIPID_BCM5754_A2 0xb002
282#define BGE_CHIPID_BCM5761_A0 0x5761000
283#define BGE_CHIPID_BCM5761_A1 0x5761100
284#define BGE_CHIPID_BCM5784_A0 0x5784000
285#define BGE_CHIPID_BCM5784_A1 0x5784100
286#define BGE_CHIPID_BCM5787_A0 0xb000
287#define BGE_CHIPID_BCM5787_A1 0xb001
288#define BGE_CHIPID_BCM5787_A2 0xb002
289#define BGE_CHIPID_BCM5906_A1 0xc001
290#define BGE_CHIPID_BCM5906_A2 0xc002
291#define BGE_CHIPID_BCM57780_A0 0x57780000
292#define BGE_CHIPID_BCM57780_A1 0x57780001
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293
294/* shorthand one */
f47afe1a 295#define BGE_ASICREV(x) ((x) >> 12)
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296#define BGE_ASICREV_BCM5701 0x00
297#define BGE_ASICREV_BCM5703 0x01
298#define BGE_ASICREV_BCM5704 0x02
7e40b8c5 299#define BGE_ASICREV_BCM5705 0x03
9a6ee7e2 300#define BGE_ASICREV_BCM5750 0x04
0ecb11d7 301#define BGE_ASICREV_BCM5714_A0 0x05
bae5fe9a 302#define BGE_ASICREV_BCM5752 0x06
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303#define BGE_ASICREV_BCM5700 0x07
304#define BGE_ASICREV_BCM5780 0x08
305#define BGE_ASICREV_BCM5714 0x09
306#define BGE_ASICREV_BCM5755 0x0a
307#define BGE_ASICREV_BCM5754 0x0b
308#define BGE_ASICREV_BCM5787 0x0b
309#define BGE_ASICREV_BCM5906 0x0c
984263bc 310
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311/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
312#define BGE_ASICREV_USE_PRODID_REG 0x0f
313/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
314#define BGE_ASICREV_BCM5761 0x5761
315#define BGE_ASICREV_BCM5784 0x5784
316#define BGE_ASICREV_BCM5785 0x5785
317#define BGE_ASICREV_BCM57780 0x57780
318
984263bc 319/* chip revisions */
f47afe1a 320#define BGE_CHIPREV(x) ((x) >> 8)
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321#define BGE_CHIPREV_5700_AX 0x70
322#define BGE_CHIPREV_5700_BX 0x71
323#define BGE_CHIPREV_5700_CX 0x72
324#define BGE_CHIPREV_5701_AX 0x00
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325#define BGE_CHIPREV_5703_AX 0x10
326#define BGE_CHIPREV_5704_AX 0x20
327#define BGE_CHIPREV_5704_BX 0x21
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328#define BGE_CHIPREV_5750_AX 0x40
329#define BGE_CHIPREV_5750_BX 0x41
330/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
331#define BGE_CHIPREV_5761_AX 0x57611
332#define BGE_CHIPREV_5784_AX 0x57841
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333
334/* PCI DMA Read/Write Control register */
335#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
336#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
337#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
338#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
339#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
340# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
341#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
342# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
343#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
344#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
345#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
346# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
347#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
348# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
349
350#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
351#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
352#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
353#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
354#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
355#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
356#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
357#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
358
359#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
360#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
361#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
362#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
363#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
364#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
365#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
366#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
367
368/*
369 * PCI state register -- note, this register is read only
370 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
371 * register is set.
372 */
373#define BGE_PCISTATE_FORCE_RESET 0x00000001
374#define BGE_PCISTATE_INTR_STATE 0x00000002
375#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
0ecb11d7 376#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
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377#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
378#define BGE_PCISTATE_WANT_EXPROM 0x00000020
379#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
380#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
381#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
382
383/*
384 * PCI Clock Control register -- note, this register is read only
385 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
386 * register is set.
387 */
388#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
389#define BGE_PCICLOCKCTL_M66EN 0x00000080
390#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
391#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
392#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
393#define BGE_PCICLOCKCTL_ALTCLK 0x00001000
394#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
395#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
396#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
397#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
398
399
400#ifndef PCIM_CMD_MWIEN
401#define PCIM_CMD_MWIEN 0x0010
402#endif
403
404/*
405 * High priority mailbox registers
406 * Each mailbox is 64-bits wide, though we only use the
407 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
408 * first. The NIC will load the mailbox after the lower 32 bit word
409 * has been updated.
410 */
411#define BGE_MBX_IRQ0_HI 0x0200
412#define BGE_MBX_IRQ0_LO 0x0204
413#define BGE_MBX_IRQ1_HI 0x0208
414#define BGE_MBX_IRQ1_LO 0x020C
415#define BGE_MBX_IRQ2_HI 0x0210
416#define BGE_MBX_IRQ2_LO 0x0214
417#define BGE_MBX_IRQ3_HI 0x0218
418#define BGE_MBX_IRQ3_LO 0x021C
419#define BGE_MBX_GEN0_HI 0x0220
420#define BGE_MBX_GEN0_LO 0x0224
421#define BGE_MBX_GEN1_HI 0x0228
422#define BGE_MBX_GEN1_LO 0x022C
423#define BGE_MBX_GEN2_HI 0x0230
424#define BGE_MBX_GEN2_LO 0x0234
425#define BGE_MBX_GEN3_HI 0x0228
426#define BGE_MBX_GEN3_LO 0x022C
427#define BGE_MBX_GEN4_HI 0x0240
428#define BGE_MBX_GEN4_LO 0x0244
429#define BGE_MBX_GEN5_HI 0x0248
430#define BGE_MBX_GEN5_LO 0x024C
431#define BGE_MBX_GEN6_HI 0x0250
432#define BGE_MBX_GEN6_LO 0x0254
433#define BGE_MBX_GEN7_HI 0x0258
434#define BGE_MBX_GEN7_LO 0x025C
435#define BGE_MBX_RELOAD_STATS_HI 0x0260
436#define BGE_MBX_RELOAD_STATS_LO 0x0264
437#define BGE_MBX_RX_STD_PROD_HI 0x0268
438#define BGE_MBX_RX_STD_PROD_LO 0x026C
439#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
440#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
441#define BGE_MBX_RX_MINI_PROD_HI 0x0278
442#define BGE_MBX_RX_MINI_PROD_LO 0x027C
443#define BGE_MBX_RX_CONS0_HI 0x0280
444#define BGE_MBX_RX_CONS0_LO 0x0284
445#define BGE_MBX_RX_CONS1_HI 0x0288
446#define BGE_MBX_RX_CONS1_LO 0x028C
447#define BGE_MBX_RX_CONS2_HI 0x0290
448#define BGE_MBX_RX_CONS2_LO 0x0294
449#define BGE_MBX_RX_CONS3_HI 0x0298
450#define BGE_MBX_RX_CONS3_LO 0x029C
451#define BGE_MBX_RX_CONS4_HI 0x02A0
452#define BGE_MBX_RX_CONS4_LO 0x02A4
453#define BGE_MBX_RX_CONS5_HI 0x02A8
454#define BGE_MBX_RX_CONS5_LO 0x02AC
455#define BGE_MBX_RX_CONS6_HI 0x02B0
456#define BGE_MBX_RX_CONS6_LO 0x02B4
457#define BGE_MBX_RX_CONS7_HI 0x02B8
458#define BGE_MBX_RX_CONS7_LO 0x02BC
459#define BGE_MBX_RX_CONS8_HI 0x02C0
460#define BGE_MBX_RX_CONS8_LO 0x02C4
461#define BGE_MBX_RX_CONS9_HI 0x02C8
462#define BGE_MBX_RX_CONS9_LO 0x02CC
463#define BGE_MBX_RX_CONS10_HI 0x02D0
464#define BGE_MBX_RX_CONS10_LO 0x02D4
465#define BGE_MBX_RX_CONS11_HI 0x02D8
466#define BGE_MBX_RX_CONS11_LO 0x02DC
467#define BGE_MBX_RX_CONS12_HI 0x02E0
468#define BGE_MBX_RX_CONS12_LO 0x02E4
469#define BGE_MBX_RX_CONS13_HI 0x02E8
470#define BGE_MBX_RX_CONS13_LO 0x02EC
471#define BGE_MBX_RX_CONS14_HI 0x02F0
472#define BGE_MBX_RX_CONS14_LO 0x02F4
473#define BGE_MBX_RX_CONS15_HI 0x02F8
474#define BGE_MBX_RX_CONS15_LO 0x02FC
475#define BGE_MBX_TX_HOST_PROD0_HI 0x0300
476#define BGE_MBX_TX_HOST_PROD0_LO 0x0304
477#define BGE_MBX_TX_HOST_PROD1_HI 0x0308
478#define BGE_MBX_TX_HOST_PROD1_LO 0x030C
479#define BGE_MBX_TX_HOST_PROD2_HI 0x0310
480#define BGE_MBX_TX_HOST_PROD2_LO 0x0314
481#define BGE_MBX_TX_HOST_PROD3_HI 0x0318
482#define BGE_MBX_TX_HOST_PROD3_LO 0x031C
483#define BGE_MBX_TX_HOST_PROD4_HI 0x0320
484#define BGE_MBX_TX_HOST_PROD4_LO 0x0324
485#define BGE_MBX_TX_HOST_PROD5_HI 0x0328
486#define BGE_MBX_TX_HOST_PROD5_LO 0x032C
487#define BGE_MBX_TX_HOST_PROD6_HI 0x0330
488#define BGE_MBX_TX_HOST_PROD6_LO 0x0334
489#define BGE_MBX_TX_HOST_PROD7_HI 0x0338
490#define BGE_MBX_TX_HOST_PROD7_LO 0x033C
491#define BGE_MBX_TX_HOST_PROD8_HI 0x0340
492#define BGE_MBX_TX_HOST_PROD8_LO 0x0344
493#define BGE_MBX_TX_HOST_PROD9_HI 0x0348
494#define BGE_MBX_TX_HOST_PROD9_LO 0x034C
495#define BGE_MBX_TX_HOST_PROD10_HI 0x0350
496#define BGE_MBX_TX_HOST_PROD10_LO 0x0354
497#define BGE_MBX_TX_HOST_PROD11_HI 0x0358
498#define BGE_MBX_TX_HOST_PROD11_LO 0x035C
499#define BGE_MBX_TX_HOST_PROD12_HI 0x0360
500#define BGE_MBX_TX_HOST_PROD12_LO 0x0364
501#define BGE_MBX_TX_HOST_PROD13_HI 0x0368
502#define BGE_MBX_TX_HOST_PROD13_LO 0x036C
503#define BGE_MBX_TX_HOST_PROD14_HI 0x0370
504#define BGE_MBX_TX_HOST_PROD14_LO 0x0374
505#define BGE_MBX_TX_HOST_PROD15_HI 0x0378
506#define BGE_MBX_TX_HOST_PROD15_LO 0x037C
507#define BGE_MBX_TX_NIC_PROD0_HI 0x0380
508#define BGE_MBX_TX_NIC_PROD0_LO 0x0384
509#define BGE_MBX_TX_NIC_PROD1_HI 0x0388
510#define BGE_MBX_TX_NIC_PROD1_LO 0x038C
511#define BGE_MBX_TX_NIC_PROD2_HI 0x0390
512#define BGE_MBX_TX_NIC_PROD2_LO 0x0394
513#define BGE_MBX_TX_NIC_PROD3_HI 0x0398
514#define BGE_MBX_TX_NIC_PROD3_LO 0x039C
515#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
516#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
517#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
518#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
519#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
520#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
521#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
522#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
523#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
524#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
525#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
526#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
527#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
528#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
529#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
530#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
531#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
532#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
533#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
534#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
535#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
536#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
537#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
538#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
539
540#define BGE_TX_RINGS_MAX 4
541#define BGE_TX_RINGS_EXTSSRAM_MAX 16
542#define BGE_RX_RINGS_MAX 16
543
544/* Ethernet MAC control registers */
545#define BGE_MAC_MODE 0x0400
546#define BGE_MAC_STS 0x0404
547#define BGE_MAC_EVT_ENB 0x0408
548#define BGE_MAC_LED_CTL 0x040C
549#define BGE_MAC_ADDR1_LO 0x0410
550#define BGE_MAC_ADDR1_HI 0x0414
551#define BGE_MAC_ADDR2_LO 0x0418
552#define BGE_MAC_ADDR2_HI 0x041C
553#define BGE_MAC_ADDR3_LO 0x0420
554#define BGE_MAC_ADDR3_HI 0x0424
555#define BGE_MAC_ADDR4_LO 0x0428
556#define BGE_MAC_ADDR4_HI 0x042C
557#define BGE_WOL_PATPTR 0x0430
558#define BGE_WOL_PATCFG 0x0434
559#define BGE_TX_RANDOM_BACKOFF 0x0438
560#define BGE_RX_MTU 0x043C
561#define BGE_GBIT_PCS_TEST 0x0440
562#define BGE_TX_TBI_AUTONEG 0x0444
563#define BGE_RX_TBI_AUTONEG 0x0448
564#define BGE_MI_COMM 0x044C
565#define BGE_MI_STS 0x0450
566#define BGE_MI_MODE 0x0454
567#define BGE_AUTOPOLL_STS 0x0458
568#define BGE_TX_MODE 0x045C
569#define BGE_TX_STS 0x0460
570#define BGE_TX_LENGTHS 0x0464
571#define BGE_RX_MODE 0x0468
572#define BGE_RX_STS 0x046C
573#define BGE_MAR0 0x0470
574#define BGE_MAR1 0x0474
575#define BGE_MAR2 0x0478
576#define BGE_MAR3 0x047C
577#define BGE_RX_BD_RULES_CTL0 0x0480
578#define BGE_RX_BD_RULES_MASKVAL0 0x0484
579#define BGE_RX_BD_RULES_CTL1 0x0488
580#define BGE_RX_BD_RULES_MASKVAL1 0x048C
581#define BGE_RX_BD_RULES_CTL2 0x0490
582#define BGE_RX_BD_RULES_MASKVAL2 0x0494
583#define BGE_RX_BD_RULES_CTL3 0x0498
584#define BGE_RX_BD_RULES_MASKVAL3 0x049C
585#define BGE_RX_BD_RULES_CTL4 0x04A0
586#define BGE_RX_BD_RULES_MASKVAL4 0x04A4
587#define BGE_RX_BD_RULES_CTL5 0x04A8
588#define BGE_RX_BD_RULES_MASKVAL5 0x04AC
589#define BGE_RX_BD_RULES_CTL6 0x04B0
590#define BGE_RX_BD_RULES_MASKVAL6 0x04B4
591#define BGE_RX_BD_RULES_CTL7 0x04B8
592#define BGE_RX_BD_RULES_MASKVAL7 0x04BC
593#define BGE_RX_BD_RULES_CTL8 0x04C0
594#define BGE_RX_BD_RULES_MASKVAL8 0x04C4
595#define BGE_RX_BD_RULES_CTL9 0x04C8
596#define BGE_RX_BD_RULES_MASKVAL9 0x04CC
597#define BGE_RX_BD_RULES_CTL10 0x04D0
598#define BGE_RX_BD_RULES_MASKVAL10 0x04D4
599#define BGE_RX_BD_RULES_CTL11 0x04D8
600#define BGE_RX_BD_RULES_MASKVAL11 0x04DC
601#define BGE_RX_BD_RULES_CTL12 0x04E0
602#define BGE_RX_BD_RULES_MASKVAL12 0x04E4
603#define BGE_RX_BD_RULES_CTL13 0x04E8
604#define BGE_RX_BD_RULES_MASKVAL13 0x04EC
605#define BGE_RX_BD_RULES_CTL14 0x04F0
606#define BGE_RX_BD_RULES_MASKVAL14 0x04F4
607#define BGE_RX_BD_RULES_CTL15 0x04F8
608#define BGE_RX_BD_RULES_MASKVAL15 0x04FC
609#define BGE_RX_RULES_CFG 0x0500
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610#define BGE_SERDES_CFG 0x0590
611#define BGE_SERDES_STS 0x0594
612#define BGE_SGDIG_CFG 0x05B0
613#define BGE_SGDIG_STS 0x05B4
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614#define BGE_RX_STATS 0x0800
615#define BGE_TX_STATS 0x0880
616
617/* Ethernet MAC Mode register */
618#define BGE_MACMODE_RESET 0x00000001
619#define BGE_MACMODE_HALF_DUPLEX 0x00000002
620#define BGE_MACMODE_PORTMODE 0x0000000C
621#define BGE_MACMODE_LOOPBACK 0x00000010
622#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
623#define BGE_MACMODE_TX_BURST_ENB 0x00000100
624#define BGE_MACMODE_MAX_DEFER 0x00000200
625#define BGE_MACMODE_LINK_POLARITY 0x00000400
626#define BGE_MACMODE_RX_STATS_ENB 0x00000800
627#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
628#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
629#define BGE_MACMODE_TX_STATS_ENB 0x00004000
630#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
631#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
632#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
633#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
634#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
635#define BGE_MACMODE_MIP_ENB 0x00100000
636#define BGE_MACMODE_TXDMA_ENB 0x00200000
637#define BGE_MACMODE_RXDMA_ENB 0x00400000
638#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
639
640#define BGE_PORTMODE_NONE 0x00000000
641#define BGE_PORTMODE_MII 0x00000004
642#define BGE_PORTMODE_GMII 0x00000008
643#define BGE_PORTMODE_TBI 0x0000000C
644
645/* MAC Status register */
646#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
647#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
648#define BGE_MACSTAT_RX_CFG 0x00000004
649#define BGE_MACSTAT_CFG_CHANGED 0x00000008
650#define BGE_MACSTAT_SYNC_CHANGED 0x00000010
651#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
652#define BGE_MACSTAT_LINK_CHANGED 0x00001000
653#define BGE_MACSTAT_MI_COMPLETE 0x00400000
654#define BGE_MACSTAT_MI_INTERRUPT 0x00800000
655#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
656#define BGE_MACSTAT_ODI_ERROR 0x02000000
657#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
658#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
659
660/* MAC Event Enable Register */
661#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
662#define BGE_EVTENB_LINK_CHANGED 0x00001000
663#define BGE_EVTENB_MI_COMPLETE 0x00400000
664#define BGE_EVTENB_MI_INTERRUPT 0x00800000
665#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
666#define BGE_EVTENB_ODI_ERROR 0x02000000
667#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
668#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
669
670/* LED Control Register */
671#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
672#define BGE_LEDCTL_1000MBPS_LED 0x00000002
673#define BGE_LEDCTL_100MBPS_LED 0x00000004
674#define BGE_LEDCTL_10MBPS_LED 0x00000008
675#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
676#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
677#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
678#define BGE_LEDCTL_1000MBPS_STS 0x00000080
679#define BGE_LEDCTL_100MBPS_STS 0x00000100
680#define BGE_LEDCTL_10MBPS_STS 0x00000200
681#define BGE_LEDCTL_TRADLED_STS 0x00000400
682#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
683#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
684
685/* TX backoff seed register */
686#define BGE_TX_BACKOFF_SEED_MASK 0x3F
687
688/* Autopoll status register */
689#define BGE_AUTOPOLLSTS_ERROR 0x00000001
690
691/* Transmit MAC mode register */
692#define BGE_TXMODE_RESET 0x00000001
693#define BGE_TXMODE_ENABLE 0x00000002
694#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
695#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
696#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
697
698/* Transmit MAC status register */
699#define BGE_TXSTAT_RX_XOFFED 0x00000001
700#define BGE_TXSTAT_SENT_XOFF 0x00000002
701#define BGE_TXSTAT_SENT_XON 0x00000004
702#define BGE_TXSTAT_LINK_UP 0x00000008
703#define BGE_TXSTAT_ODI_UFLOW 0x00000010
704#define BGE_TXSTAT_ODI_OFLOW 0x00000020
705
706/* Transmit MAC lengths register */
707#define BGE_TXLEN_SLOTTIME 0x000000FF
708#define BGE_TXLEN_IPG 0x00000F00
709#define BGE_TXLEN_CRS 0x00003000
710
711/* Receive MAC mode register */
712#define BGE_RXMODE_RESET 0x00000001
713#define BGE_RXMODE_ENABLE 0x00000002
714#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
715#define BGE_RXMODE_RX_GIANTS 0x00000020
716#define BGE_RXMODE_RX_RUNTS 0x00000040
717#define BGE_RXMODE_8022_LENCHECK 0x00000080
718#define BGE_RXMODE_RX_PROMISC 0x00000100
719#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
720#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
721
722/* Receive MAC status register */
723#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
724#define BGE_RXSTAT_RCVD_XOFF 0x00000002
725#define BGE_RXSTAT_RCVD_XON 0x00000004
726
727/* Receive Rules Control register */
728#define BGE_RXRULECTL_OFFSET 0x000000FF
729#define BGE_RXRULECTL_CLASS 0x00001F00
730#define BGE_RXRULECTL_HDRTYPE 0x0000E000
731#define BGE_RXRULECTL_COMPARE_OP 0x00030000
732#define BGE_RXRULECTL_MAP 0x01000000
733#define BGE_RXRULECTL_DISCARD 0x02000000
734#define BGE_RXRULECTL_MASK 0x04000000
735#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
736#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
737#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
738#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
739
740/* Receive Rules Mask register */
741#define BGE_RXRULEMASK_VALUE 0x0000FFFF
742#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
743
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JS
744/* SERDES configuration register */
745#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
746#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
747#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
748#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
749#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
750#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
751#define BGE_SERDESCFG_TXMODE 0x00001000
752#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
753#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
754#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
755#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
756#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
757#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
758#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
759#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
760#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
761
762/* SERDES status register */
763#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
764#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
765
766/* SGDIG config (not documented) */
767#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
768#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
769#define BGE_SGDIGCFG_SEND 0x40000000
770#define BGE_SGDIGCFG_AUTO 0x80000000
771
772/* SGDIG status (not documented) */
773#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
774#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
775#define BGE_SGDIGSTS_DONE 0x00000002
776
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MD
777/* MI communication register */
778#define BGE_MICOMM_DATA 0x0000FFFF
779#define BGE_MICOMM_REG 0x001F0000
780#define BGE_MICOMM_PHY 0x03E00000
781#define BGE_MICOMM_CMD 0x0C000000
782#define BGE_MICOMM_READFAIL 0x10000000
783#define BGE_MICOMM_BUSY 0x20000000
784
785#define BGE_MIREG(x) ((x & 0x1F) << 16)
786#define BGE_MIPHY(x) ((x & 0x1F) << 21)
787#define BGE_MICMD_WRITE 0x04000000
788#define BGE_MICMD_READ 0x08000000
789
790/* MI status register */
791#define BGE_MISTS_LINK 0x00000001
792#define BGE_MISTS_10MBPS 0x00000002
793
794#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
795#define BGE_MIMODE_AUTOPOLL 0x00000010
796#define BGE_MIMODE_CLKCNT 0x001F0000
797
798
799/*
800 * Send data initiator control registers.
801 */
802#define BGE_SDI_MODE 0x0C00
803#define BGE_SDI_STATUS 0x0C04
804#define BGE_SDI_STATS_CTL 0x0C08
805#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
806#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
807#define BGE_LOCSTATS_COS0 0x0C80
808#define BGE_LOCSTATS_COS1 0x0C84
809#define BGE_LOCSTATS_COS2 0x0C88
810#define BGE_LOCSTATS_COS3 0x0C8C
811#define BGE_LOCSTATS_COS4 0x0C90
812#define BGE_LOCSTATS_COS5 0x0C84
813#define BGE_LOCSTATS_COS6 0x0C98
814#define BGE_LOCSTATS_COS7 0x0C9C
815#define BGE_LOCSTATS_COS8 0x0CA0
816#define BGE_LOCSTATS_COS9 0x0CA4
817#define BGE_LOCSTATS_COS10 0x0CA8
818#define BGE_LOCSTATS_COS11 0x0CAC
819#define BGE_LOCSTATS_COS12 0x0CB0
820#define BGE_LOCSTATS_COS13 0x0CB4
821#define BGE_LOCSTATS_COS14 0x0CB8
822#define BGE_LOCSTATS_COS15 0x0CBC
823#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
824#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
825#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
826#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
827#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
828#define BGE_LOCSTATS_IRQS 0x0CD4
829#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
830#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
831
832/* Send Data Initiator mode register */
833#define BGE_SDIMODE_RESET 0x00000001
834#define BGE_SDIMODE_ENABLE 0x00000002
835#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
836
837/* Send Data Initiator stats register */
838#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
839
840/* Send Data Initiator stats control register */
841#define BGE_SDISTATSCTL_ENABLE 0x00000001
842#define BGE_SDISTATSCTL_FASTER 0x00000002
843#define BGE_SDISTATSCTL_CLEAR 0x00000004
844#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
845#define BGE_SDISTATSCTL_FORCEZERO 0x00000010
846
847/*
848 * Send Data Completion Control registers
849 */
850#define BGE_SDC_MODE 0x1000
851#define BGE_SDC_STATUS 0x1004
852
853/* Send Data completion mode register */
854#define BGE_SDCMODE_RESET 0x00000001
855#define BGE_SDCMODE_ENABLE 0x00000002
856#define BGE_SDCMODE_ATTN 0x00000004
f47afe1a 857#define BGE_SDCMODE_CDELAY 0x00000010
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858
859/* Send Data completion status register */
860#define BGE_SDCSTAT_ATTN 0x00000004
861
862/*
863 * Send BD Ring Selector Control registers
864 */
865#define BGE_SRS_MODE 0x1400
866#define BGE_SRS_STATUS 0x1404
867#define BGE_SRS_HWDIAG 0x1408
868#define BGE_SRS_LOC_NIC_CONS0 0x1440
869#define BGE_SRS_LOC_NIC_CONS1 0x1444
870#define BGE_SRS_LOC_NIC_CONS2 0x1448
871#define BGE_SRS_LOC_NIC_CONS3 0x144C
872#define BGE_SRS_LOC_NIC_CONS4 0x1450
873#define BGE_SRS_LOC_NIC_CONS5 0x1454
874#define BGE_SRS_LOC_NIC_CONS6 0x1458
875#define BGE_SRS_LOC_NIC_CONS7 0x145C
876#define BGE_SRS_LOC_NIC_CONS8 0x1460
877#define BGE_SRS_LOC_NIC_CONS9 0x1464
878#define BGE_SRS_LOC_NIC_CONS10 0x1468
879#define BGE_SRS_LOC_NIC_CONS11 0x146C
880#define BGE_SRS_LOC_NIC_CONS12 0x1470
881#define BGE_SRS_LOC_NIC_CONS13 0x1474
882#define BGE_SRS_LOC_NIC_CONS14 0x1478
883#define BGE_SRS_LOC_NIC_CONS15 0x147C
884
885/* Send BD Ring Selector Mode register */
886#define BGE_SRSMODE_RESET 0x00000001
887#define BGE_SRSMODE_ENABLE 0x00000002
888#define BGE_SRSMODE_ATTN 0x00000004
889
890/* Send BD Ring Selector Status register */
891#define BGE_SRSSTAT_ERROR 0x00000004
892
893/* Send BD Ring Selector HW Diagnostics register */
894#define BGE_SRSHWDIAG_STATE 0x0000000F
895#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
896#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
897#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
898
899/*
900 * Send BD Initiator Selector Control registers
901 */
902#define BGE_SBDI_MODE 0x1800
903#define BGE_SBDI_STATUS 0x1804
904#define BGE_SBDI_LOC_NIC_PROD0 0x1808
905#define BGE_SBDI_LOC_NIC_PROD1 0x180C
906#define BGE_SBDI_LOC_NIC_PROD2 0x1810
907#define BGE_SBDI_LOC_NIC_PROD3 0x1814
908#define BGE_SBDI_LOC_NIC_PROD4 0x1818
909#define BGE_SBDI_LOC_NIC_PROD5 0x181C
910#define BGE_SBDI_LOC_NIC_PROD6 0x1820
911#define BGE_SBDI_LOC_NIC_PROD7 0x1824
912#define BGE_SBDI_LOC_NIC_PROD8 0x1828
913#define BGE_SBDI_LOC_NIC_PROD9 0x182C
914#define BGE_SBDI_LOC_NIC_PROD10 0x1830
915#define BGE_SBDI_LOC_NIC_PROD11 0x1834
916#define BGE_SBDI_LOC_NIC_PROD12 0x1838
917#define BGE_SBDI_LOC_NIC_PROD13 0x183C
918#define BGE_SBDI_LOC_NIC_PROD14 0x1840
919#define BGE_SBDI_LOC_NIC_PROD15 0x1844
920
921/* Send BD Initiator Mode register */
922#define BGE_SBDIMODE_RESET 0x00000001
923#define BGE_SBDIMODE_ENABLE 0x00000002
924#define BGE_SBDIMODE_ATTN 0x00000004
925
926/* Send BD Initiator Status register */
927#define BGE_SBDISTAT_ERROR 0x00000004
928
929/*
930 * Send BD Completion Control registers
931 */
932#define BGE_SBDC_MODE 0x1C00
933#define BGE_SBDC_STATUS 0x1C04
934
935/* Send BD Completion Control Mode register */
936#define BGE_SBDCMODE_RESET 0x00000001
937#define BGE_SBDCMODE_ENABLE 0x00000002
938#define BGE_SBDCMODE_ATTN 0x00000004
939
940/* Send BD Completion Control Status register */
941#define BGE_SBDCSTAT_ATTN 0x00000004
942
943/*
944 * Receive List Placement Control registers
945 */
946#define BGE_RXLP_MODE 0x2000
947#define BGE_RXLP_STATUS 0x2004
948#define BGE_RXLP_SEL_LIST_LOCK 0x2008
949#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
950#define BGE_RXLP_CFG 0x2010
951#define BGE_RXLP_STATS_CTL 0x2014
952#define BGE_RXLP_STATS_ENABLE_MASK 0x2018
953#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
954#define BGE_RXLP_HEAD0 0x2100
955#define BGE_RXLP_TAIL0 0x2104
956#define BGE_RXLP_COUNT0 0x2108
957#define BGE_RXLP_HEAD1 0x2110
958#define BGE_RXLP_TAIL1 0x2114
959#define BGE_RXLP_COUNT1 0x2118
960#define BGE_RXLP_HEAD2 0x2120
961#define BGE_RXLP_TAIL2 0x2124
962#define BGE_RXLP_COUNT2 0x2128
963#define BGE_RXLP_HEAD3 0x2130
964#define BGE_RXLP_TAIL3 0x2134
965#define BGE_RXLP_COUNT3 0x2138
966#define BGE_RXLP_HEAD4 0x2140
967#define BGE_RXLP_TAIL4 0x2144
968#define BGE_RXLP_COUNT4 0x2148
969#define BGE_RXLP_HEAD5 0x2150
970#define BGE_RXLP_TAIL5 0x2154
971#define BGE_RXLP_COUNT5 0x2158
972#define BGE_RXLP_HEAD6 0x2160
973#define BGE_RXLP_TAIL6 0x2164
974#define BGE_RXLP_COUNT6 0x2168
975#define BGE_RXLP_HEAD7 0x2170
976#define BGE_RXLP_TAIL7 0x2174
977#define BGE_RXLP_COUNT7 0x2178
978#define BGE_RXLP_HEAD8 0x2180
979#define BGE_RXLP_TAIL8 0x2184
980#define BGE_RXLP_COUNT8 0x2188
981#define BGE_RXLP_HEAD9 0x2190
982#define BGE_RXLP_TAIL9 0x2194
983#define BGE_RXLP_COUNT9 0x2198
984#define BGE_RXLP_HEAD10 0x21A0
985#define BGE_RXLP_TAIL10 0x21A4
986#define BGE_RXLP_COUNT10 0x21A8
987#define BGE_RXLP_HEAD11 0x21B0
988#define BGE_RXLP_TAIL11 0x21B4
989#define BGE_RXLP_COUNT11 0x21B8
990#define BGE_RXLP_HEAD12 0x21C0
991#define BGE_RXLP_TAIL12 0x21C4
992#define BGE_RXLP_COUNT12 0x21C8
993#define BGE_RXLP_HEAD13 0x21D0
994#define BGE_RXLP_TAIL13 0x21D4
995#define BGE_RXLP_COUNT13 0x21D8
996#define BGE_RXLP_HEAD14 0x21E0
997#define BGE_RXLP_TAIL14 0x21E4
998#define BGE_RXLP_COUNT14 0x21E8
999#define BGE_RXLP_HEAD15 0x21F0
1000#define BGE_RXLP_TAIL15 0x21F4
1001#define BGE_RXLP_COUNT15 0x21F8
1002#define BGE_RXLP_LOCSTAT_COS0 0x2200
1003#define BGE_RXLP_LOCSTAT_COS1 0x2204
1004#define BGE_RXLP_LOCSTAT_COS2 0x2208
1005#define BGE_RXLP_LOCSTAT_COS3 0x220C
1006#define BGE_RXLP_LOCSTAT_COS4 0x2210
1007#define BGE_RXLP_LOCSTAT_COS5 0x2214
1008#define BGE_RXLP_LOCSTAT_COS6 0x2218
1009#define BGE_RXLP_LOCSTAT_COS7 0x221C
1010#define BGE_RXLP_LOCSTAT_COS8 0x2220
1011#define BGE_RXLP_LOCSTAT_COS9 0x2224
1012#define BGE_RXLP_LOCSTAT_COS10 0x2228
1013#define BGE_RXLP_LOCSTAT_COS11 0x222C
1014#define BGE_RXLP_LOCSTAT_COS12 0x2230
1015#define BGE_RXLP_LOCSTAT_COS13 0x2234
1016#define BGE_RXLP_LOCSTAT_COS14 0x2238
1017#define BGE_RXLP_LOCSTAT_COS15 0x223C
1018#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1019#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1020#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1021#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1022#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1023#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1024#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1025
1026
1027/* Receive List Placement mode register */
1028#define BGE_RXLPMODE_RESET 0x00000001
1029#define BGE_RXLPMODE_ENABLE 0x00000002
1030#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1031#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1032#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1033
1034/* Receive List Placement Status register */
1035#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1036#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1037#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1038
1039/*
1040 * Receive Data and Receive BD Initiator Control Registers
1041 */
1042#define BGE_RDBDI_MODE 0x2400
1043#define BGE_RDBDI_STATUS 0x2404
1044#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1045#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1046#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1047#define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1048#define BGE_RX_STD_RCB_HADDR_HI 0x2450
1049#define BGE_RX_STD_RCB_HADDR_LO 0x2454
1050#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1051#define BGE_RX_STD_RCB_NICADDR 0x245C
1052#define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1053#define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1054#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1055#define BGE_RX_MINI_RCB_NICADDR 0x246C
1056#define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1057#define BGE_RDBDI_STD_RX_CONS 0x2474
1058#define BGE_RDBDI_MINI_RX_CONS 0x2478
1059#define BGE_RDBDI_RETURN_PROD0 0x2480
1060#define BGE_RDBDI_RETURN_PROD1 0x2484
1061#define BGE_RDBDI_RETURN_PROD2 0x2488
1062#define BGE_RDBDI_RETURN_PROD3 0x248C
1063#define BGE_RDBDI_RETURN_PROD4 0x2490
1064#define BGE_RDBDI_RETURN_PROD5 0x2494
1065#define BGE_RDBDI_RETURN_PROD6 0x2498
1066#define BGE_RDBDI_RETURN_PROD7 0x249C
1067#define BGE_RDBDI_RETURN_PROD8 0x24A0
1068#define BGE_RDBDI_RETURN_PROD9 0x24A4
1069#define BGE_RDBDI_RETURN_PROD10 0x24A8
1070#define BGE_RDBDI_RETURN_PROD11 0x24AC
1071#define BGE_RDBDI_RETURN_PROD12 0x24B0
1072#define BGE_RDBDI_RETURN_PROD13 0x24B4
1073#define BGE_RDBDI_RETURN_PROD14 0x24B8
1074#define BGE_RDBDI_RETURN_PROD15 0x24BC
1075#define BGE_RDBDI_HWDIAG 0x24C0
1076
1077
1078/* Receive Data and Receive BD Initiator Mode register */
1079#define BGE_RDBDIMODE_RESET 0x00000001
1080#define BGE_RDBDIMODE_ENABLE 0x00000002
1081#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1082#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1083#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1084
1085/* Receive Data and Receive BD Initiator Status register */
1086#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1087#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1088#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1089
1090
1091/*
1092 * Receive Data Completion Control registers
1093 */
1094#define BGE_RDC_MODE 0x2800
1095
1096/* Receive Data Completion Mode register */
1097#define BGE_RDCMODE_RESET 0x00000001
1098#define BGE_RDCMODE_ENABLE 0x00000002
1099#define BGE_RDCMODE_ATTN 0x00000004
1100
1101/*
1102 * Receive BD Initiator Control registers
1103 */
1104#define BGE_RBDI_MODE 0x2C00
1105#define BGE_RBDI_STATUS 0x2C04
1106#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1107#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1108#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1109#define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1110#define BGE_RBDI_STD_REPL_THRESH 0x2C18
1111#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1112
1113/* Receive BD Initiator Mode register */
1114#define BGE_RBDIMODE_RESET 0x00000001
1115#define BGE_RBDIMODE_ENABLE 0x00000002
1116#define BGE_RBDIMODE_ATTN 0x00000004
1117
1118/* Receive BD Initiator Status register */
1119#define BGE_RBDISTAT_ATTN 0x00000004
1120
1121/*
1122 * Receive BD Completion Control registers
1123 */
1124#define BGE_RBDC_MODE 0x3000
1125#define BGE_RBDC_STATUS 0x3004
1126#define BGE_RBDC_JUMBO_BD_PROD 0x3008
1127#define BGE_RBDC_STD_BD_PROD 0x300C
1128#define BGE_RBDC_MINI_BD_PROD 0x3010
1129
1130/* Receive BD completion mode register */
1131#define BGE_RBDCMODE_RESET 0x00000001
1132#define BGE_RBDCMODE_ENABLE 0x00000002
1133#define BGE_RBDCMODE_ATTN 0x00000004
1134
1135/* Receive BD completion status register */
1136#define BGE_RBDCSTAT_ERROR 0x00000004
1137
1138/*
1139 * Receive List Selector Control registers
1140 */
1141#define BGE_RXLS_MODE 0x3400
1142#define BGE_RXLS_STATUS 0x3404
1143
1144/* Receive List Selector Mode register */
1145#define BGE_RXLSMODE_RESET 0x00000001
1146#define BGE_RXLSMODE_ENABLE 0x00000002
1147#define BGE_RXLSMODE_ATTN 0x00000004
1148
1149/* Receive List Selector Status register */
1150#define BGE_RXLSSTAT_ERROR 0x00000004
1151
1152/*
1153 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1154 */
1155#define BGE_MBCF_MODE 0x3800
1156#define BGE_MBCF_STATUS 0x3804
1157
1158/* Mbuf Cluster Free mode register */
1159#define BGE_MBCFMODE_RESET 0x00000001
1160#define BGE_MBCFMODE_ENABLE 0x00000002
1161#define BGE_MBCFMODE_ATTN 0x00000004
1162
1163/* Mbuf Cluster Free status register */
1164#define BGE_MBCFSTAT_ERROR 0x00000004
1165
1166/*
1167 * Host Coalescing Control registers
1168 */
1169#define BGE_HCC_MODE 0x3C00
1170#define BGE_HCC_STATUS 0x3C04
1171#define BGE_HCC_RX_COAL_TICKS 0x3C08
1172#define BGE_HCC_TX_COAL_TICKS 0x3C0C
1173#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1174#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1175#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1176#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1177#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
7e40b8c5 1178#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
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MD
1179#define BGE_HCC_STATS_TICKS 0x3C28
1180#define BGE_HCC_STATS_ADDR_HI 0x3C30
1181#define BGE_HCC_STATS_ADDR_LO 0x3C34
1182#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1183#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1184#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1185#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1186#define BGE_FLOW_ATTN 0x3C48
1187#define BGE_HCC_JUMBO_BD_CONS 0x3C50
1188#define BGE_HCC_STD_BD_CONS 0x3C54
1189#define BGE_HCC_MINI_BD_CONS 0x3C58
1190#define BGE_HCC_RX_RETURN_PROD0 0x3C80
1191#define BGE_HCC_RX_RETURN_PROD1 0x3C84
1192#define BGE_HCC_RX_RETURN_PROD2 0x3C88
1193#define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1194#define BGE_HCC_RX_RETURN_PROD4 0x3C90
1195#define BGE_HCC_RX_RETURN_PROD5 0x3C94
1196#define BGE_HCC_RX_RETURN_PROD6 0x3C98
1197#define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1198#define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1199#define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1200#define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1201#define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1202#define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1203#define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1204#define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1205#define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1206#define BGE_HCC_TX_BD_CONS0 0x3CC0
1207#define BGE_HCC_TX_BD_CONS1 0x3CC4
1208#define BGE_HCC_TX_BD_CONS2 0x3CC8
1209#define BGE_HCC_TX_BD_CONS3 0x3CCC
1210#define BGE_HCC_TX_BD_CONS4 0x3CD0
1211#define BGE_HCC_TX_BD_CONS5 0x3CD4
1212#define BGE_HCC_TX_BD_CONS6 0x3CD8
1213#define BGE_HCC_TX_BD_CONS7 0x3CDC
1214#define BGE_HCC_TX_BD_CONS8 0x3CE0
1215#define BGE_HCC_TX_BD_CONS9 0x3CE4
1216#define BGE_HCC_TX_BD_CONS10 0x3CE8
1217#define BGE_HCC_TX_BD_CONS11 0x3CEC
1218#define BGE_HCC_TX_BD_CONS12 0x3CF0
1219#define BGE_HCC_TX_BD_CONS13 0x3CF4
1220#define BGE_HCC_TX_BD_CONS14 0x3CF8
1221#define BGE_HCC_TX_BD_CONS15 0x3CFC
1222
1223
1224/* Host coalescing mode register */
1225#define BGE_HCCMODE_RESET 0x00000001
1226#define BGE_HCCMODE_ENABLE 0x00000002
1227#define BGE_HCCMODE_ATTN 0x00000004
1228#define BGE_HCCMODE_COAL_NOW 0x00000008
1229#define BGE_HCCMODE_MSI_BITS 0x0x000070
1230#define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1231
1232#define BGE_STATBLKSZ_FULL 0x00000000
1233#define BGE_STATBLKSZ_64BYTE 0x00000080
1234#define BGE_STATBLKSZ_32BYTE 0x00000100
1235
1236/* Host coalescing status register */
1237#define BGE_HCCSTAT_ERROR 0x00000004
1238
1239/* Flow attention register */
1240#define BGE_FLOWATTN_MB_LOWAT 0x00000040
1241#define BGE_FLOWATTN_MEMARB 0x00000080
1242#define BGE_FLOWATTN_HOSTCOAL 0x00008000
1243#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1244#define BGE_FLOWATTN_RCB_INVAL 0x00020000
1245#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1246#define BGE_FLOWATTN_RDBDI 0x00080000
1247#define BGE_FLOWATTN_RXLS 0x00100000
1248#define BGE_FLOWATTN_RXLP 0x00200000
1249#define BGE_FLOWATTN_RBDC 0x00400000
1250#define BGE_FLOWATTN_RBDI 0x00800000
1251#define BGE_FLOWATTN_SDC 0x08000000
1252#define BGE_FLOWATTN_SDI 0x10000000
1253#define BGE_FLOWATTN_SRS 0x20000000
1254#define BGE_FLOWATTN_SBDC 0x40000000
1255#define BGE_FLOWATTN_SBDI 0x80000000
1256
1257/*
1258 * Memory arbiter registers
1259 */
1260#define BGE_MARB_MODE 0x4000
1261#define BGE_MARB_STATUS 0x4004
1262#define BGE_MARB_TRAPADDR_HI 0x4008
1263#define BGE_MARB_TRAPADDR_LO 0x400C
1264
1265/* Memory arbiter mode register */
1266#define BGE_MARBMODE_RESET 0x00000001
1267#define BGE_MARBMODE_ENABLE 0x00000002
1268#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1269#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1270#define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1271#define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1272#define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1273#define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1274#define BGE_MARBMODE_PCI_TRAP 0x00000100
1275#define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1276#define BGE_MARBMODE_RXQ_TRAP 0x00000400
1277#define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1278#define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1279#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1280#define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1281#define BGE_MARBMODE_MBUF_TRAP 0x00008000
1282#define BGE_MARBMODE_TXDI_TRAP 0x00010000
1283#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1284#define BGE_MARBMODE_TXBD_TRAP 0x00040000
1285#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1286#define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1287#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1288#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1289#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1290#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1291#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1292
1293/* Memory arbiter status register */
1294#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1295#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1296#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1297#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1298#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1299#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1300#define BGE_MARBSTAT_PCI_TRAP 0x00000100
1301#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1302#define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1303#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1304#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1305#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1306#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1307#define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1308#define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1309#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1310#define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1311#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1312#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1313#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1314#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1315#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1316#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1317#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1318
1319/*
1320 * Buffer manager control registers
1321 */
1322#define BGE_BMAN_MODE 0x4400
1323#define BGE_BMAN_STATUS 0x4404
1324#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1325#define BGE_BMAN_MBUFPOOL_LEN 0x440C
1326#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1327#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1328#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1329#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1330#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1331#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1332#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1333#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1334#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1335#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1336#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1337#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1338#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1339#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1340#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1341#define BGE_BMAN_HWDIAG_1 0x444C
1342#define BGE_BMAN_HWDIAG_2 0x4450
1343#define BGE_BMAN_HWDIAG_3 0x4454
1344
1345/* Buffer manager mode register */
1346#define BGE_BMANMODE_RESET 0x00000001
1347#define BGE_BMANMODE_ENABLE 0x00000002
1348#define BGE_BMANMODE_ATTN 0x00000004
1349#define BGE_BMANMODE_TESTMODE 0x00000008
1350#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1351
1352/* Buffer manager status register */
1353#define BGE_BMANSTAT_ERRO 0x00000004
1354#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1355
1356
1357/*
1358 * Read DMA Control registers
1359 */
1360#define BGE_RDMA_MODE 0x4800
1361#define BGE_RDMA_STATUS 0x4804
1362
1363/* Read DMA mode register */
1364#define BGE_RDMAMODE_RESET 0x00000001
1365#define BGE_RDMAMODE_ENABLE 0x00000002
1366#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1367#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1368#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1369#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1370#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1371#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1372#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1373#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1374#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
f47afe1a
MN
1375#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1376#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1377#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
671bd7ed
SZ
1378#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1379#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
984263bc
MD
1380
1381/* Read DMA status register */
1382#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1383#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1384#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1385#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1386#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1387#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1388#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1389#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1390
1391/*
1392 * Write DMA control registers
1393 */
1394#define BGE_WDMA_MODE 0x4C00
1395#define BGE_WDMA_STATUS 0x4C04
1396
1397/* Write DMA mode register */
1398#define BGE_WDMAMODE_RESET 0x00000001
1399#define BGE_WDMAMODE_ENABLE 0x00000002
1400#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1401#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1402#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1403#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1404#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1405#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1406#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1407#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1408#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
832863d2 1409#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
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MD
1410
1411/* Write DMA status register */
1412#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1413#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1414#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1415#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1416#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1417#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1418#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1419#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1420
1421
1422/*
1423 * RX CPU registers
1424 */
1425#define BGE_RXCPU_MODE 0x5000
1426#define BGE_RXCPU_STATUS 0x5004
1427#define BGE_RXCPU_PC 0x501C
1428
1429/* RX CPU mode register */
1430#define BGE_RXCPUMODE_RESET 0x00000001
1431#define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1432#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1433#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1434#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1435#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1436#define BGE_RXCPUMODE_ROMFAIL 0x00000040
1437#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1438#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1439#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1440#define BGE_RXCPUMODE_HALTCPU 0x00000400
1441#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1442#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1443#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1444
1445/* RX CPU status register */
1446#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1447#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1448#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1449#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1450#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1451#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1452#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1453#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1454#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1455#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1456#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1457#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1458#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1459#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1460#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1461#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1462#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1463
591dfc77
SZ
1464/*
1465 * V? CPU registers
1466 */
1467#define BGE_VCPU_STATUS 0x5100
1468#define BGE_VCPU_EXT_CTRL 0x6890
1469
1470#define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1471#define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1472
1473#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1474#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1475
984263bc
MD
1476
1477/*
1478 * TX CPU registers
1479 */
1480#define BGE_TXCPU_MODE 0x5400
1481#define BGE_TXCPU_STATUS 0x5404
1482#define BGE_TXCPU_PC 0x541C
1483
1484/* TX CPU mode register */
1485#define BGE_TXCPUMODE_RESET 0x00000001
1486#define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1487#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1488#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1489#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1490#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1491#define BGE_TXCPUMODE_ROMFAIL 0x00000040
1492#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1493#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1494#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1495#define BGE_TXCPUMODE_HALTCPU 0x00000400
1496#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1497#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1498
1499/* TX CPU status register */
1500#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1501#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1502#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1503#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1504#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1505#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1506#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1507#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1508#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1509#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1510#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1511#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1512#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1513#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1514#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1515#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1516#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1517
1518
1519/*
1520 * Low priority mailbox registers
1521 */
1522#define BGE_LPMBX_IRQ0_HI 0x5800
1523#define BGE_LPMBX_IRQ0_LO 0x5804
1524#define BGE_LPMBX_IRQ1_HI 0x5808
1525#define BGE_LPMBX_IRQ1_LO 0x580C
1526#define BGE_LPMBX_IRQ2_HI 0x5810
1527#define BGE_LPMBX_IRQ2_LO 0x5814
1528#define BGE_LPMBX_IRQ3_HI 0x5818
1529#define BGE_LPMBX_IRQ3_LO 0x581C
1530#define BGE_LPMBX_GEN0_HI 0x5820
1531#define BGE_LPMBX_GEN0_LO 0x5824
1532#define BGE_LPMBX_GEN1_HI 0x5828
1533#define BGE_LPMBX_GEN1_LO 0x582C
1534#define BGE_LPMBX_GEN2_HI 0x5830
1535#define BGE_LPMBX_GEN2_LO 0x5834
1536#define BGE_LPMBX_GEN3_HI 0x5828
1537#define BGE_LPMBX_GEN3_LO 0x582C
1538#define BGE_LPMBX_GEN4_HI 0x5840
1539#define BGE_LPMBX_GEN4_LO 0x5844
1540#define BGE_LPMBX_GEN5_HI 0x5848
1541#define BGE_LPMBX_GEN5_LO 0x584C
1542#define BGE_LPMBX_GEN6_HI 0x5850
1543#define BGE_LPMBX_GEN6_LO 0x5854
1544#define BGE_LPMBX_GEN7_HI 0x5858
1545#define BGE_LPMBX_GEN7_LO 0x585C
1546#define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1547#define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1548#define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1549#define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1550#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1551#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1552#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1553#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1554#define BGE_LPMBX_RX_CONS0_HI 0x5880
1555#define BGE_LPMBX_RX_CONS0_LO 0x5884
1556#define BGE_LPMBX_RX_CONS1_HI 0x5888
1557#define BGE_LPMBX_RX_CONS1_LO 0x588C
1558#define BGE_LPMBX_RX_CONS2_HI 0x5890
1559#define BGE_LPMBX_RX_CONS2_LO 0x5894
1560#define BGE_LPMBX_RX_CONS3_HI 0x5898
1561#define BGE_LPMBX_RX_CONS3_LO 0x589C
1562#define BGE_LPMBX_RX_CONS4_HI 0x58A0
1563#define BGE_LPMBX_RX_CONS4_LO 0x58A4
1564#define BGE_LPMBX_RX_CONS5_HI 0x58A8
1565#define BGE_LPMBX_RX_CONS5_LO 0x58AC
1566#define BGE_LPMBX_RX_CONS6_HI 0x58B0
1567#define BGE_LPMBX_RX_CONS6_LO 0x58B4
1568#define BGE_LPMBX_RX_CONS7_HI 0x58B8
1569#define BGE_LPMBX_RX_CONS7_LO 0x58BC
1570#define BGE_LPMBX_RX_CONS8_HI 0x58C0
1571#define BGE_LPMBX_RX_CONS8_LO 0x58C4
1572#define BGE_LPMBX_RX_CONS9_HI 0x58C8
1573#define BGE_LPMBX_RX_CONS9_LO 0x58CC
1574#define BGE_LPMBX_RX_CONS10_HI 0x58D0
1575#define BGE_LPMBX_RX_CONS10_LO 0x58D4
1576#define BGE_LPMBX_RX_CONS11_HI 0x58D8
1577#define BGE_LPMBX_RX_CONS11_LO 0x58DC
1578#define BGE_LPMBX_RX_CONS12_HI 0x58E0
1579#define BGE_LPMBX_RX_CONS12_LO 0x58E4
1580#define BGE_LPMBX_RX_CONS13_HI 0x58E8
1581#define BGE_LPMBX_RX_CONS13_LO 0x58EC
1582#define BGE_LPMBX_RX_CONS14_HI 0x58F0
1583#define BGE_LPMBX_RX_CONS14_LO 0x58F4
1584#define BGE_LPMBX_RX_CONS15_HI 0x58F8
1585#define BGE_LPMBX_RX_CONS15_LO 0x58FC
1586#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1587#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1588#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1589#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1590#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1591#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1592#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1593#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1594#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1595#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1596#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1597#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1598#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1599#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1600#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1601#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1602#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1603#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1604#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1605#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1606#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1607#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1608#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1609#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1610#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1611#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1612#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1613#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1614#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1615#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1616#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1617#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1618#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1619#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1620#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1621#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1622#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1623#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1624#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1625#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1626#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1627#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1628#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1629#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1630#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1631#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1632#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1633#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1634#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1635#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1636#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1637#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1638#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1639#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1640#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1641#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1642#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1643#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1644#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1645#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1646#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1647#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1648#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1649#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1650
1651/*
1652 * Flow throw Queue reset register
1653 */
1654#define BGE_FTQ_RESET 0x5C00
1655
1656#define BGE_FTQRESET_DMAREAD 0x00000002
1657#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1658#define BGE_FTQRESET_DMADONE 0x00000010
1659#define BGE_FTQRESET_SBDC 0x00000020
1660#define BGE_FTQRESET_SDI 0x00000040
1661#define BGE_FTQRESET_WDMA 0x00000080
1662#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1663#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1664#define BGE_FTQRESET_SDC 0x00000400
1665#define BGE_FTQRESET_HCC 0x00000800
1666#define BGE_FTQRESET_TXFIFO 0x00001000
1667#define BGE_FTQRESET_MBC 0x00002000
1668#define BGE_FTQRESET_RBDC 0x00004000
1669#define BGE_FTQRESET_RXLP 0x00008000
1670#define BGE_FTQRESET_RDBDI 0x00010000
1671#define BGE_FTQRESET_RDC 0x00020000
1672#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1673
1674/*
1675 * Message Signaled Interrupt registers
1676 */
1677#define BGE_MSI_MODE 0x6000
1678#define BGE_MSI_STATUS 0x6004
1679#define BGE_MSI_FIFOACCESS 0x6008
1680
1681/* MSI mode register */
1682#define BGE_MSIMODE_RESET 0x00000001
1683#define BGE_MSIMODE_ENABLE 0x00000002
1684#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1685#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1686#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1687#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1688#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1689
1690/* MSI status register */
1691#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1692#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1693#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1694#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1695#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1696
1697
1698/*
1699 * DMA Completion registers
1700 */
1701#define BGE_DMAC_MODE 0x6400
1702
1703/* DMA Completion mode register */
1704#define BGE_DMACMODE_RESET 0x00000001
1705#define BGE_DMACMODE_ENABLE 0x00000002
1706
1707
1708/*
1709 * General control registers.
1710 */
1711#define BGE_MODE_CTL 0x6800
1712#define BGE_MISC_CFG 0x6804
1713#define BGE_MISC_LOCAL_CTL 0x6808
1714#define BGE_EE_ADDR 0x6838
1715#define BGE_EE_DATA 0x683C
1716#define BGE_EE_CTL 0x6840
1717#define BGE_MDI_CTL 0x6844
1718#define BGE_EE_DELAY 0x6848
0ecb11d7 1719#define BGE_FASTBOOT_PC 0x6894
984263bc 1720
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1721/*
1722 * NVRAM Control registers
1723 */
1724#define BGE_NVRAM_CMD 0x7000
1725#define BGE_NVRAM_STAT 0x7004
1726#define BGE_NVRAM_WRDATA 0x7008
1727#define BGE_NVRAM_ADDR 0x700c
1728#define BGE_NVRAM_RDDATA 0x7010
1729#define BGE_NVRAM_CFG1 0x7014
1730#define BGE_NVRAM_CFG2 0x7018
1731#define BGE_NVRAM_CFG3 0x701c
1732#define BGE_NVRAM_SWARB 0x7020
1733#define BGE_NVRAM_ACCESS 0x7024
1734#define BGE_NVRAM_WRITE1 0x7028
1735
1736#define BGE_NVRAMCMD_RESET 0x00000001
1737#define BGE_NVRAMCMD_DONE 0x00000008
1738#define BGE_NVRAMCMD_START 0x00000010
1739#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1740#define BGE_NVRAMCMD_ERASE 0x00000040
1741#define BGE_NVRAMCMD_FIRST 0x00000080
1742#define BGE_NVRAMCMD_LAST 0x00000100
1743
1744#define BGE_NVRAM_READCMD \
1745 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1746 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1747#define BGE_NVRAM_WRITECMD \
1748 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1749 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1750
1751#define BGE_NVRAMSWARB_SET0 0x00000001
1752#define BGE_NVRAMSWARB_SET1 0x00000002
1753#define BGE_NVRAMSWARB_SET2 0x00000003
1754#define BGE_NVRAMSWARB_SET3 0x00000004
1755#define BGE_NVRAMSWARB_CLR0 0x00000010
1756#define BGE_NVRAMSWARB_CLR1 0x00000020
1757#define BGE_NVRAMSWARB_CLR2 0x00000040
1758#define BGE_NVRAMSWARB_CLR3 0x00000080
1759#define BGE_NVRAMSWARB_GNT0 0x00000100
1760#define BGE_NVRAMSWARB_GNT1 0x00000200
1761#define BGE_NVRAMSWARB_GNT2 0x00000400
1762#define BGE_NVRAMSWARB_GNT3 0x00000800
1763#define BGE_NVRAMSWARB_REQ0 0x00001000
1764#define BGE_NVRAMSWARB_REQ1 0x00002000
1765#define BGE_NVRAMSWARB_REQ2 0x00004000
1766#define BGE_NVRAMSWARB_REQ3 0x00008000
1767
1768#define BGE_NVRAMACC_ENABLE 0x00000001
1769#define BGE_NVRAMACC_WRENABLE 0x00000002
1770
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1771/* Mode control register */
1772#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1773#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1774#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1775#define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1776#define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1777#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1778#define BGE_MODECTL_NO_RX_CRC 0x00000400
1779#define BGE_MODECTL_RX_BADFRAMES 0x00000800
1780#define BGE_MODECTL_NO_TX_INTR 0x00002000
1781#define BGE_MODECTL_NO_RX_INTR 0x00004000
1782#define BGE_MODECTL_FORCE_PCI32 0x00008000
1783#define BGE_MODECTL_STACKUP 0x00010000
1784#define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1785#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1786#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1787#define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1788#define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1789#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1790#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1791#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1792#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1793#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1794
1795/* Misc. config register */
1796#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1797#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
591dfc77 1798#define BGE_MISCCFG_EPHY_IDDQ 0x00200000
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1799
1800#define BGE_32BITTIME_66MHZ (0x41 << 1)
1801
1802/* Misc. Local Control */
1803#define BGE_MLC_INTR_STATE 0x00000001
1804#define BGE_MLC_INTR_CLR 0x00000002
1805#define BGE_MLC_INTR_SET 0x00000004
1806#define BGE_MLC_INTR_ONATTN 0x00000008
1807#define BGE_MLC_MISCIO_IN0 0x00000100
1808#define BGE_MLC_MISCIO_IN1 0x00000200
1809#define BGE_MLC_MISCIO_IN2 0x00000400
1810#define BGE_MLC_MISCIO_OUTEN0 0x00000800
1811#define BGE_MLC_MISCIO_OUTEN1 0x00001000
1812#define BGE_MLC_MISCIO_OUTEN2 0x00002000
1813#define BGE_MLC_MISCIO_OUT0 0x00004000
1814#define BGE_MLC_MISCIO_OUT1 0x00008000
1815#define BGE_MLC_MISCIO_OUT2 0x00010000
1816#define BGE_MLC_EXTRAM_ENB 0x00020000
1817#define BGE_MLC_SRAM_SIZE 0x001C0000
1818#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1819#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1820#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1821#define BGE_MLC_AUTO_EEPROM 0x01000000
1822
1823#define BGE_SSRAMSIZE_256KB 0x00000000
1824#define BGE_SSRAMSIZE_512KB 0x00040000
1825#define BGE_SSRAMSIZE_1MB 0x00080000
1826#define BGE_SSRAMSIZE_2MB 0x000C0000
1827#define BGE_SSRAMSIZE_4MB 0x00100000
1828#define BGE_SSRAMSIZE_8MB 0x00140000
1829#define BGE_SSRAMSIZE_16M 0x00180000
1830
1831/* EEPROM address register */
1832#define BGE_EEADDR_ADDRESS 0x0000FFFC
1833#define BGE_EEADDR_HALFCLK 0x01FF0000
1834#define BGE_EEADDR_START 0x02000000
1835#define BGE_EEADDR_DEVID 0x1C000000
1836#define BGE_EEADDR_RESET 0x20000000
1837#define BGE_EEADDR_DONE 0x40000000
1838#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1839
1840#define BGE_EEDEVID(x) ((x & 7) << 26)
1841#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1842#define BGE_HALFCLK_384SCL 0x60
1843#define BGE_EE_READCMD \
1844 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1845 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1846#define BGE_EE_WRCMD \
1847 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1848 BGE_EEADDR_START|BGE_EEADDR_DONE)
1849
1850/* EEPROM Control register */
1851#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1852#define BGE_EECTL_CLKOUT 0x00000002
1853#define BGE_EECTL_CLKIN 0x00000004
1854#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1855#define BGE_EECTL_DATAOUT 0x00000010
1856#define BGE_EECTL_DATAIN 0x00000020
1857
1858/* MDI (MII/GMII) access register */
1859#define BGE_MDI_DATA 0x00000001
1860#define BGE_MDI_DIR 0x00000002
1861#define BGE_MDI_SEL 0x00000004
1862#define BGE_MDI_CLK 0x00000008
1863
1864#define BGE_MEMWIN_START 0x00008000
1865#define BGE_MEMWIN_END 0x0000FFFF
1866
1867
1868#define BGE_MEMWIN_READ(sc, x, val) \
1869 do { \
1870 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1871 (0xFFFF0000 & x), 4); \
1872 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1873 } while(0)
1874
1875#define BGE_MEMWIN_WRITE(sc, x, val) \
1876 do { \
1877 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1878 (0xFFFF0000 & x), 4); \
1879 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1880 } while(0)
1881
1882/*
0ecb11d7
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1883 * This magic number is written to the firmware mailbox at 0xb50
1884 * before a software reset is issued. After the internal firmware
1885 * has completed its initialization it will write the opposite of
1886 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1887 * driver to synchronize with the firmware.
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1888 */
1889#define BGE_MAGIC_NUMBER 0x4B657654
1890
1891typedef struct {
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1892 uint32_t bge_addr_hi;
1893 uint32_t bge_addr_lo;
984263bc 1894} bge_hostaddr;
20c9a969 1895
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1896#define BGE_HOSTADDR(x, y) \
1897 do { \
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1898 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
1899 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
7e40b8c5 1900 } while(0)
984263bc 1901
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1902#define BGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
1903#define BGE_ADDR_HI(y) ((uint64_t) (y) >> 32)
1904
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1905/* Ring control block structure */
1906struct bge_rcb {
1907 bge_hostaddr bge_hostaddr;
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1908 uint32_t bge_maxlen_flags;
1909 uint32_t bge_nicaddr;
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1910};
1911#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
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1912#define RCB_WRITE_4(sc, rcb, offset, val) \
1913 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
1914 rcb + offsetof(struct bge_rcb, offset), val)
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1915
1916#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1917#define BGE_RCB_FLAG_RING_DISABLED 0x0002
1918
1919struct bge_tx_bd {
1920 bge_hostaddr bge_addr;
20c9a969 1921#if BYTE_ORDER == LITTLE_ENDIAN
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1922 uint16_t bge_flags;
1923 uint16_t bge_len;
1924 uint16_t bge_vlan_tag;
1925 uint16_t bge_rsvd;
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1926#else
1927 uint16_t bge_len;
1928 uint16_t bge_flags;
1929 uint16_t bge_rsvd;
1930 uint16_t bge_vlan_tag;
1931#endif
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1932};
1933
1934#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1935#define BGE_TXBDFLAG_IP_CSUM 0x0002
1936#define BGE_TXBDFLAG_END 0x0004
1937#define BGE_TXBDFLAG_IP_FRAG 0x0008
1938#define BGE_TXBDFLAG_IP_FRAG_END 0x0010
1939#define BGE_TXBDFLAG_VLAN_TAG 0x0040
1940#define BGE_TXBDFLAG_COAL_NOW 0x0080
1941#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
1942#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
1943#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
1944#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
1945#define BGE_TXBDFLAG_NO_CRC 0x8000
1946
1947#define BGE_NIC_TXRING_ADDR(ringno, size) \
1948 BGE_SEND_RING_1_TO_4 + \
1949 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1950
1951struct bge_rx_bd {
1952 bge_hostaddr bge_addr;
20c9a969 1953#if BYTE_ORDER == LITTLE_ENDIAN
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1954 uint16_t bge_len;
1955 uint16_t bge_idx;
1956 uint16_t bge_flags;
1957 uint16_t bge_type;
1958 uint16_t bge_tcp_udp_csum;
1959 uint16_t bge_ip_csum;
1960 uint16_t bge_vlan_tag;
1961 uint16_t bge_error_flag;
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1962#else
1963 uint16_t bge_idx;
1964 uint16_t bge_len;
1965 uint16_t bge_type;
1966 uint16_t bge_flags;
1967 uint16_t bge_ip_csum;
1968 uint16_t bge_tcp_udp_csum;
1969 uint16_t bge_error_flag;
1970 uint16_t bge_vlan_tag;
1971#endif
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1972 uint32_t bge_rsvd;
1973 uint32_t bge_opaque;
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MD
1974};
1975
1976#define BGE_RXBDFLAG_END 0x0004
1977#define BGE_RXBDFLAG_JUMBO_RING 0x0020
1978#define BGE_RXBDFLAG_VLAN_TAG 0x0040
1979#define BGE_RXBDFLAG_ERROR 0x0400
1980#define BGE_RXBDFLAG_MINI_RING 0x0800
1981#define BGE_RXBDFLAG_IP_CSUM 0x1000
1982#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
1983#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
1984
1985#define BGE_RXERRFLAG_BAD_CRC 0x0001
1986#define BGE_RXERRFLAG_COLL_DETECT 0x0002
1987#define BGE_RXERRFLAG_LINK_LOST 0x0004
1988#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
1989#define BGE_RXERRFLAG_MAC_ABORT 0x0010
1990#define BGE_RXERRFLAG_RUNT 0x0020
1991#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
1992#define BGE_RXERRFLAG_GIANT 0x0080
1993
1994struct bge_sts_idx {
20c9a969 1995#if BYTE_ORDER == LITTLE_ENDIAN
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1996 uint16_t bge_rx_prod_idx;
1997 uint16_t bge_tx_cons_idx;
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SZ
1998#else
1999 uint16_t bge_tx_cons_idx;
2000 uint16_t bge_rx_prod_idx;
2001#endif
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2002};
2003
2004struct bge_status_block {
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2005 uint32_t bge_status;
2006 uint32_t bge_rsvd0;
20c9a969 2007#if BYTE_ORDER == LITTLE_ENDIAN
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2008 uint16_t bge_rx_jumbo_cons_idx;
2009 uint16_t bge_rx_std_cons_idx;
2010 uint16_t bge_rx_mini_cons_idx;
2011 uint16_t bge_rsvd1;
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2012#else
2013 uint16_t bge_rx_std_cons_idx;
2014 uint16_t bge_rx_jumbo_cons_idx;
2015 uint16_t bge_rsvd1;
2016 uint16_t bge_rx_mini_cons_idx;
2017#endif
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2018 struct bge_sts_idx bge_idx[16];
2019};
2020
2021#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
2022#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
2023
2024#define BGE_STATFLAG_UPDATED 0x00000001
2025#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2026#define BGE_STATFLAG_ERROR 0x00000004
2027
2028
2029/*
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MD
2030 * Offset of MAC address inside EEPROM.
2031 */
2032#define BGE_EE_MAC_OFFSET 0x7C
591dfc77 2033#define BGE_EE_MAC_OFFSET_5906 0x10
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2034#define BGE_EE_HWCFG_OFFSET 0xC8
2035
2036#define BGE_HWCFG_VOLTAGE 0x00000003
2037#define BGE_HWCFG_PHYLED_MODE 0x0000000C
2038#define BGE_HWCFG_MEDIA 0x00000030
2039
2040#define BGE_VOLTAGE_1POINT3 0x00000000
2041#define BGE_VOLTAGE_1POINT8 0x00000001
2042
2043#define BGE_PHYLEDMODE_UNSPEC 0x00000000
2044#define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2045#define BGE_PHYLEDMODE_SINGLELED 0x00000008
2046
2047#define BGE_MEDIA_UNSPEC 0x00000000
2048#define BGE_MEDIA_COPPER 0x00000010
2049#define BGE_MEDIA_FIBER 0x00000020
2050
2051#define BGE_PCI_READ_CMD 0x06000000
2052#define BGE_PCI_WRITE_CMD 0x70000000
2053
2054#define BGE_TICKS_PER_SEC 1000000
2055
2056/*
2057 * Ring size constants.
2058 */
2059#define BGE_EVENT_RING_CNT 256
2060#define BGE_CMD_RING_CNT 64
2061#define BGE_STD_RX_RING_CNT 512
2062#define BGE_JUMBO_RX_RING_CNT 256
2063#define BGE_MINI_RX_RING_CNT 1024
2064#define BGE_RETURN_RING_CNT 1024
2065
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2066/* 5705 has smaller return ring size */
2067
2068#define BGE_RETURN_RING_CNT_5705 512
2069
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2070/*
2071 * Possible TX ring sizes.
2072 */
2073#define BGE_TX_RING_CNT_128 128
2074#define BGE_TX_RING_BASE_128 0x3800
2075
2076#define BGE_TX_RING_CNT_256 256
2077#define BGE_TX_RING_BASE_256 0x3000
2078
2079#define BGE_TX_RING_CNT_512 512
2080#define BGE_TX_RING_BASE_512 0x2000
2081
2082#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2083#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2084
2085/*
2086 * Tigon III statistics counters.
2087 */
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2088/* Statistics maintained MAC Receive block. */
2089struct bge_rx_mac_stats {
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2090 bge_hostaddr ifHCInOctets;
2091 bge_hostaddr Reserved1;
2092 bge_hostaddr etherStatsFragments;
2093 bge_hostaddr ifHCInUcastPkts;
2094 bge_hostaddr ifHCInMulticastPkts;
2095 bge_hostaddr ifHCInBroadcastPkts;
2096 bge_hostaddr dot3StatsFCSErrors;
2097 bge_hostaddr dot3StatsAlignmentErrors;
2098 bge_hostaddr xonPauseFramesReceived;
2099 bge_hostaddr xoffPauseFramesReceived;
2100 bge_hostaddr macControlFramesReceived;
2101 bge_hostaddr xoffStateEntered;
2102 bge_hostaddr dot3StatsFramesTooLong;
2103 bge_hostaddr etherStatsJabbers;
2104 bge_hostaddr etherStatsUndersizePkts;
2105 bge_hostaddr inRangeLengthError;
2106 bge_hostaddr outRangeLengthError;
2107 bge_hostaddr etherStatsPkts64Octets;
2108 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2109 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2110 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2111 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2112 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2113 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2114 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2115 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2116 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
7e40b8c5 2117};
984263bc 2118
984263bc 2119
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2120/* Statistics maintained MAC Transmit block. */
2121struct bge_tx_mac_stats {
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2122 bge_hostaddr ifHCOutOctets;
2123 bge_hostaddr Reserved2;
2124 bge_hostaddr etherStatsCollisions;
2125 bge_hostaddr outXonSent;
2126 bge_hostaddr outXoffSent;
2127 bge_hostaddr flowControlDone;
2128 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2129 bge_hostaddr dot3StatsSingleCollisionFrames;
2130 bge_hostaddr dot3StatsMultipleCollisionFrames;
2131 bge_hostaddr dot3StatsDeferredTransmissions;
2132 bge_hostaddr Reserved3;
2133 bge_hostaddr dot3StatsExcessiveCollisions;
2134 bge_hostaddr dot3StatsLateCollisions;
2135 bge_hostaddr dot3Collided2Times;
2136 bge_hostaddr dot3Collided3Times;
2137 bge_hostaddr dot3Collided4Times;
2138 bge_hostaddr dot3Collided5Times;
2139 bge_hostaddr dot3Collided6Times;
2140 bge_hostaddr dot3Collided7Times;
2141 bge_hostaddr dot3Collided8Times;
2142 bge_hostaddr dot3Collided9Times;
2143 bge_hostaddr dot3Collided10Times;
2144 bge_hostaddr dot3Collided11Times;
2145 bge_hostaddr dot3Collided12Times;
2146 bge_hostaddr dot3Collided13Times;
2147 bge_hostaddr dot3Collided14Times;
2148 bge_hostaddr dot3Collided15Times;
2149 bge_hostaddr ifHCOutUcastPkts;
2150 bge_hostaddr ifHCOutMulticastPkts;
2151 bge_hostaddr ifHCOutBroadcastPkts;
2152 bge_hostaddr dot3StatsCarrierSenseErrors;
2153 bge_hostaddr ifOutDiscards;
2154 bge_hostaddr ifOutErrors;
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2155};
2156
2157/* Stats counters access through registers */
2158struct bge_mac_stats_regs {
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2159 uint32_t ifHCOutOctets;
2160 uint32_t Reserved0;
2161 uint32_t etherStatsCollisions;
2162 uint32_t outXonSent;
2163 uint32_t outXoffSent;
2164 uint32_t Reserved1;
2165 uint32_t dot3StatsInternalMacTransmitErrors;
2166 uint32_t dot3StatsSingleCollisionFrames;
2167 uint32_t dot3StatsMultipleCollisionFrames;
2168 uint32_t dot3StatsDeferredTransmissions;
2169 uint32_t Reserved2;
2170 uint32_t dot3StatsExcessiveCollisions;
2171 uint32_t dot3StatsLateCollisions;
2172 uint32_t Reserved3[14];
2173 uint32_t ifHCOutUcastPkts;
2174 uint32_t ifHCOutMulticastPkts;
2175 uint32_t ifHCOutBroadcastPkts;
2176 uint32_t Reserved4[2];
2177 uint32_t ifHCInOctets;
2178 uint32_t Reserved5;
2179 uint32_t etherStatsFragments;
2180 uint32_t ifHCInUcastPkts;
2181 uint32_t ifHCInMulticastPkts;
2182 uint32_t ifHCInBroadcastPkts;
2183 uint32_t dot3StatsFCSErrors;
2184 uint32_t dot3StatsAlignmentErrors;
2185 uint32_t xonPauseFramesReceived;
2186 uint32_t xoffPauseFramesReceived;
2187 uint32_t macControlFramesReceived;
2188 uint32_t xoffStateEntered;
2189 uint32_t dot3StatsFramesTooLong;
2190 uint32_t etherStatsJabbers;
2191 uint32_t etherStatsUndersizePkts;
7e40b8c5
HP
2192};
2193
2194struct bge_stats {
33c39a69 2195 uint8_t Reserved0[256];
7e40b8c5
HP
2196
2197 /* Statistics maintained by Receive MAC. */
2198 struct bge_rx_mac_stats rxstats;
2199
2200 bge_hostaddr Unused1[37];
2201
2202 /* Statistics maintained by Transmit MAC. */
2203 struct bge_tx_mac_stats txstats;
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MD
2204
2205 bge_hostaddr Unused2[31];
2206
2207 /* Statistics maintained by Receive List Placement. */
2208 bge_hostaddr COSIfHCInPkts[16];
2209 bge_hostaddr COSFramesDroppedDueToFilters;
2210 bge_hostaddr nicDmaWriteQueueFull;
2211 bge_hostaddr nicDmaWriteHighPriQueueFull;
2212 bge_hostaddr nicNoMoreRxBDs;
2213 bge_hostaddr ifInDiscards;
2214 bge_hostaddr ifInErrors;
2215 bge_hostaddr nicRecvThresholdHit;
2216
2217 bge_hostaddr Unused3[9];
2218
2219 /* Statistics maintained by Send Data Initiator. */
2220 bge_hostaddr COSIfHCOutPkts[16];
2221 bge_hostaddr nicDmaReadQueueFull;
2222 bge_hostaddr nicDmaReadHighPriQueueFull;
2223 bge_hostaddr nicSendDataCompQueueFull;
2224
2225 /* Statistics maintained by Host Coalescing. */
2226 bge_hostaddr nicRingSetSendProdIndex;
2227 bge_hostaddr nicRingStatusUpdate;
2228 bge_hostaddr nicInterrupts;
2229 bge_hostaddr nicAvoidedInterrupts;
2230 bge_hostaddr nicSendThresholdHit;
2231
33c39a69 2232 uint8_t Reserved4[320];
984263bc
MD
2233};
2234
2235/*
2236 * Tigon general information block. This resides in host memory
2237 * and contains the status counters, ring control blocks and
2238 * producer pointers.
2239 */
2240
2241struct bge_gib {
2242 struct bge_stats bge_stats;
2243 struct bge_rcb bge_tx_rcb[16];
2244 struct bge_rcb bge_std_rx_rcb;
2245 struct bge_rcb bge_jumbo_rx_rcb;
2246 struct bge_rcb bge_mini_rx_rcb;
2247 struct bge_rcb bge_return_rcb;
2248};
2249
2250/*
2251 * NOTE! On the Alpha, we have an alignment constraint.
2252 * The first thing in the packet is a 14-byte Ethernet header.
2253 * This means that the packet is misaligned. To compensate,
2254 * we actually offset the data 2 bytes into the cluster. This
2255 * alignes the packet after the Ethernet header at a 32-bit
2256 * boundary.
2257 */
2258
2259#define ETHER_ALIGN 2
2260
2261#define BGE_FRAMELEN 1518
2262#define BGE_MAX_FRAMELEN 1536
2263#define BGE_JUMBO_FRAMELEN 9018
2264#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2265#define BGE_PAGE_SIZE PAGE_SIZE
1585cbac 2266#define BGE_MIN_FRAMELEN 60
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MD
2267
2268/*
2269 * Other utility macros.
2270 */
2271#define BGE_INC(x, y) (x) = (x + 1) % y
2272
2273/*
2274 * Vital product data and structures.
2275 */
2276#define BGE_VPD_FLAG 0x8000
2277
2278/* VPD structures */
2279struct vpd_res {
33c39a69
JS
2280 uint8_t vr_id;
2281 uint8_t vr_len;
2282 uint8_t vr_pad;
984263bc
MD
2283};
2284
2285struct vpd_key {
2286 char vk_key[2];
33c39a69 2287 uint8_t vk_len;
984263bc
MD
2288};
2289
2290#define VPD_RES_ID 0x82 /* ID string */
2291#define VPD_RES_READ 0x90 /* start of read only area */
2292#define VPD_RES_WRITE 0x81 /* start of read/write area */
2293#define VPD_RES_END 0x78 /* end tag */
2294
2295
2296/*
2297 * Register access macros. The Tigon always uses memory mapped register
2298 * accesses and all registers must be accessed with 32 bit operations.
2299 */
2300
2301#define CSR_WRITE_4(sc, reg, val) \
2302 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
2303
2304#define CSR_READ_4(sc, reg) \
2305 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
2306
2307#define BGE_SETBIT(sc, reg, x) \
2308 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
2309#define BGE_CLRBIT(sc, reg, x) \
2310 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
2311
2312#define PCI_SETBIT(dev, reg, x, s) \
2313 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
2314#define PCI_CLRBIT(dev, reg, x, s) \
2315 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
2316
2317/*
2318 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2319 * values are tuneable. They control the actual amount of buffers
2320 * allocated for the standard, mini and jumbo receive rings.
2321 */
2322
2323#define BGE_SSLOTS 256
2324#define BGE_MSLOTS 256
2325#define BGE_JSLOTS 384
2326
369211d4
JS
2327#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2328#define BGE_JLEN (BGE_JRAWLEN + \
2329 (sizeof(uint64_t) - BGE_JRAWLEN % sizeof(uint64_t)))
984263bc
MD
2330#define BGE_JPAGESZ PAGE_SIZE
2331#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2332#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2333
2aa9b12f
JS
2334struct bge_softc;
2335
984263bc 2336struct bge_jslot {
2aa9b12f
JS
2337 struct bge_softc *bge_sc;
2338 void *bge_buf;
20c9a969 2339 bus_addr_t bge_paddr;
2aa9b12f
JS
2340 int bge_inuse;
2341 int bge_slot;
2342 SLIST_ENTRY(bge_jslot) jslot_link;
984263bc
MD
2343};
2344
2345/*
2346 * Ring structures. Most of these reside in host memory and we tell
2347 * the NIC where they are via the ring control blocks. The exceptions
2348 * are the tx and command rings, which live in NIC memory and which
2349 * we access via the shared memory window.
2350 */
2351struct bge_ring_data {
20c9a969
SZ
2352 struct bge_rx_bd *bge_rx_std_ring;
2353 bus_addr_t bge_rx_std_ring_paddr;
2354 struct bge_rx_bd *bge_rx_jumbo_ring;
2355 bus_addr_t bge_rx_jumbo_ring_paddr;
2356 struct bge_rx_bd *bge_rx_return_ring;
2357 bus_addr_t bge_rx_return_ring_paddr;
2358 struct bge_tx_bd *bge_tx_ring;
2359 bus_addr_t bge_tx_ring_paddr;
2360 struct bge_status_block *bge_status_block;
2361 bus_addr_t bge_status_block_paddr;
2362 struct bge_stats *bge_stats;
2363 bus_addr_t bge_stats_paddr;
2364 void *bge_jumbo_buf;
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MD
2365 struct bge_gib bge_info;
2366};
2367
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SZ
2368#define BGE_STD_RX_RING_SZ \
2369 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2370#define BGE_JUMBO_RX_RING_SZ \
2371 (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT)
2372#define BGE_TX_RING_SZ \
2373 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2374#define BGE_RX_RTN_RING_SZ(x) \
2375 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2376
2377#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2378
2379#define BGE_STATS_SZ sizeof (struct bge_stats)
2380
1436f9a0
SZ
2381struct bge_rxchain {
2382 struct mbuf *bge_mbuf;
2383 bus_addr_t bge_paddr;
2384};
2385
984263bc
MD
2386/*
2387 * Mbuf pointers. We need these to keep track of the virtual addresses
2388 * of our mbuf chains since we can only convert from physical to virtual,
2389 * not the other way around.
2390 */
2391struct bge_chain_data {
20c9a969
SZ
2392 bus_dma_tag_t bge_parent_tag;
2393 bus_dma_tag_t bge_rx_std_ring_tag;
2394 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2395 bus_dma_tag_t bge_rx_return_ring_tag;
2396 bus_dma_tag_t bge_tx_ring_tag;
2397 bus_dma_tag_t bge_status_tag;
2398 bus_dma_tag_t bge_stats_tag;
2399 bus_dma_tag_t bge_jumbo_tag;
ddca511d
SZ
2400 bus_dma_tag_t bge_tx_mtag; /* TX mbuf DMA tag */
2401 bus_dma_tag_t bge_rx_mtag; /* RX mbuf DMA tag */
1436f9a0 2402 bus_dmamap_t bge_rx_tmpmap;
20c9a969
SZ
2403 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2404 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2405 bus_dmamap_t bge_rx_std_ring_map;
2406 bus_dmamap_t bge_rx_jumbo_ring_map;
2407 bus_dmamap_t bge_tx_ring_map;
2408 bus_dmamap_t bge_rx_return_ring_map;
2409 bus_dmamap_t bge_status_map;
2410 bus_dmamap_t bge_stats_map;
2411 bus_dmamap_t bge_jumbo_map;
984263bc 2412 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
1436f9a0
SZ
2413 struct bge_rxchain bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2414 struct bge_rxchain bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
984263bc
MD
2415 /* Stick the jumbo mem management stuff here too. */
2416 struct bge_jslot bge_jslots[BGE_JSLOTS];
20c9a969
SZ
2417};
2418
984263bc 2419struct bge_type {
33c39a69
JS
2420 uint16_t bge_vid;
2421 uint16_t bge_did;
984263bc
MD
2422 char *bge_name;
2423};
2424
2425#define BGE_HWREV_TIGON 0x01
2426#define BGE_HWREV_TIGON_II 0x02
591dfc77 2427#define BGE_TIMEOUT 5000
d880f7b3 2428#define BGE_FIRMWARE_TIMEOUT 20000
591dfc77 2429#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
984263bc 2430
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MD
2431struct bge_bcom_hack {
2432 int reg;
2433 int val;
2434};
2435
2436struct bge_softc {
2437 struct arpcom arpcom; /* interface info */
2438 device_t bge_dev;
2439 device_t bge_miibus;
2440 bus_space_handle_t bge_bhandle;
984263bc
MD
2441 bus_space_tag_t bge_btag;
2442 void *bge_intrhand;
2443 struct resource *bge_irq;
2444 struct resource *bge_res;
2445 struct ifmedia bge_ifmedia; /* TBI media info */
0ecb11d7
SZ
2446 uint32_t bge_flags;
2447#define BGE_FLAG_TBI 0x00000001
2448#define BGE_FLAG_JUMBO 0x00000002
2449#define BGE_FLAG_ETH_WIRESPEED 0x00000004
2450#define BGE_FLAG_MSI 0x00000100 /* unused */
2451#define BGE_FLAG_PCIX 0x00000200
2452#define BGE_FLAG_PCIE 0x00000400
2453#define BGE_FLAG_5700_FAMILY 0x00001000
2454#define BGE_FLAG_5705_PLUS 0x00002000
2455#define BGE_FLAG_5714_FAMILY 0x00004000
2456#define BGE_FLAG_575X_PLUS 0x00008000
f47afe1a 2457#define BGE_FLAG_5755_PLUS 0x00010000
0ecb11d7
SZ
2458#define BGE_FLAG_RX_ALIGNBUG 0x00100000
2459#define BGE_FLAG_NO_3LED 0x00200000
2460#define BGE_FLAG_ADC_BUG 0x00400000
2461#define BGE_FLAG_5704_A0_BUG 0x00800000
2462#define BGE_FLAG_JITTER_BUG 0x01000000
2463#define BGE_FLAG_BER_BUG 0x02000000
2464#define BGE_FLAG_ADJUST_TRIM 0x04000000
591dfc77
SZ
2465#define BGE_FLAG_CRC_BUG 0x08000000
2466#define BGE_FLAG_NO_EEPROM 0x10000000
33c39a69 2467 uint32_t bge_chipid;
f47afe1a
MN
2468 uint32_t bge_asicrev;
2469 uint32_t bge_chiprev;
20c9a969 2470 struct bge_ring_data bge_ldata; /* rings */
984263bc 2471 struct bge_chain_data bge_cdata; /* mbufs */
33c39a69
JS
2472 uint16_t bge_tx_saved_considx;
2473 uint16_t bge_rx_saved_considx;
2474 uint16_t bge_ev_saved_considx;
2475 uint16_t bge_return_ring_cnt;
2476 uint16_t bge_std; /* current std ring head */
2477 uint16_t bge_jumbo; /* current jumo ring head */
2aa9b12f 2478 SLIST_HEAD(__bge_jfreehead, bge_jslot) bge_jfree_listhead;
16dca0df 2479 struct lwkt_serialize bge_jslot_serializer;
33c39a69
JS
2480 uint32_t bge_stat_ticks;
2481 uint32_t bge_rx_coal_ticks;
2482 uint32_t bge_tx_coal_ticks;
94db8384 2483 uint32_t bge_tx_prodidx;
33c39a69
JS
2484 uint32_t bge_rx_max_coal_bds;
2485 uint32_t bge_tx_max_coal_bds;
2486 uint32_t bge_tx_buf_ratio;
984263bc
MD
2487 int bge_if_flags;
2488 int bge_txcnt;
2489 int bge_link;
db861466 2490 int bge_link_evt;
263489fb 2491 struct callout bge_stat_timer;
db861466 2492
055d06f0
SZ
2493 struct sysctl_ctx_list bge_sysctl_ctx;
2494 struct sysctl_oid *bge_sysctl_tree;
2495
2496 uint32_t bge_coal_chg;
2497#define BGE_RX_COAL_TICKS_CHG 0x1
2498#define BGE_TX_COAL_TICKS_CHG 0x2
2499#define BGE_RX_MAX_COAL_BDS_CHG 0x4
2500#define BGE_TX_MAX_COAL_BDS_CHG 0x8
2501
db861466
SZ
2502 void (*bge_link_upd)(struct bge_softc *, uint32_t);
2503 uint32_t bge_link_chg;
984263bc 2504};
20c9a969
SZ
2505
2506#define BGE_NSEG_NEW 32
2507#define BGE_NSEG_SPARE 5
2508#define BGE_NSEG_RSVD 16