Rename printf -> kprintf in sys/ and add some defines where necessary
[dragonfly.git] / sys / dev / sound / isa / mss.c
CommitLineData
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1/*
2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
3 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
4 * Copyright Luigi Rizzo, 1997,1998
5 * Copyright by Hannu Savolainen 1994, 1995
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
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28 *
29 * $FreeBSD: src/sys/dev/sound/isa/mss.c,v 1.48.2.11 2002/12/24 21:17:41 semenu Exp $
f8c7a42d 30 * $DragonFly: src/sys/dev/sound/isa/mss.c,v 1.8 2006/12/20 18:14:40 dillon Exp $
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31 */
32
33#include <dev/sound/pcm/sound.h>
34
f8c7a42d 35SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/isa/mss.c,v 1.8 2006/12/20 18:14:40 dillon Exp $");
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36
37/* board-specific include files */
38#include <dev/sound/isa/mss.h>
39#include <dev/sound/isa/sb.h>
40#include <dev/sound/chip.h>
41
42#include "mixer_if.h"
43
44#define MSS_DEFAULT_BUFSZ (4096)
45#define abs(x) (((x) < 0) ? -(x) : (x))
46#define MSS_INDEXED_REGS 0x20
47#define OPL_INDEXED_REGS 0x19
48
49struct mss_info;
50
51struct mss_chinfo {
52 struct mss_info *parent;
53 struct pcm_channel *channel;
54 struct snd_dbuf *buffer;
55 int dir;
56 u_int32_t fmt, blksz;
57};
58
59struct mss_info {
60 struct resource *io_base; /* primary I/O address for the board */
61 int io_rid;
62 struct resource *conf_base; /* and the opti931 also has a config space */
63 int conf_rid;
64 struct resource *irq;
65 int irq_rid;
66 struct resource *drq1; /* play */
67 int drq1_rid;
68 struct resource *drq2; /* rec */
69 int drq2_rid;
70 void *ih;
71 bus_dma_tag_t parent_dmat;
72 void *lock;
73
74 char mss_indexed_regs[MSS_INDEXED_REGS];
75 char opl_indexed_regs[OPL_INDEXED_REGS];
76 int bd_id; /* used to hold board-id info, eg. sb version,
77 * mss codec type, etc. etc.
78 */
79 int opti_offset; /* offset from config_base for opti931 */
80 u_long bd_flags; /* board-specific flags */
81 int optibase; /* base address for OPTi9xx config */
82 struct resource *indir; /* Indirect register index address */
83 int indir_rid;
84 int password; /* password for opti9xx cards */
85 int passwdreg; /* password register */
86 unsigned int bufsize;
87 struct mss_chinfo pch, rch;
88};
89
90static int mss_probe(device_t dev);
91static int mss_attach(device_t dev);
92
93static driver_intr_t mss_intr;
94
95/* prototypes for local functions */
96static int mss_detect(device_t dev, struct mss_info *mss);
97static int opti_detect(device_t dev, struct mss_info *mss);
98static char *ymf_test(device_t dev, struct mss_info *mss);
99static void ad_unmute(struct mss_info *mss);
100
101/* mixer set funcs */
102static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
103static int mss_set_recsrc(struct mss_info *mss, int mask);
104
105/* io funcs */
106static int ad_wait_init(struct mss_info *mss, int x);
107static int ad_read(struct mss_info *mss, int reg);
108static void ad_write(struct mss_info *mss, int reg, u_char data);
109static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
110static void ad_enter_MCE(struct mss_info *mss);
111static void ad_leave_MCE(struct mss_info *mss);
112
113/* OPTi-specific functions */
114static void opti_write(struct mss_info *mss, u_char reg,
115 u_char data);
116static u_char opti_read(struct mss_info *mss, u_char reg);
117static int opti_init(device_t dev, struct mss_info *mss);
118
119/* io primitives */
120static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
121static u_char conf_rd(struct mss_info *mss, u_char reg);
122
123static int pnpmss_probe(device_t dev);
124static int pnpmss_attach(device_t dev);
125
126static driver_intr_t opti931_intr;
127
128static u_int32_t mss_fmt[] = {
129 AFMT_U8,
130 AFMT_STEREO | AFMT_U8,
131 AFMT_S16_LE,
132 AFMT_STEREO | AFMT_S16_LE,
133 AFMT_MU_LAW,
134 AFMT_STEREO | AFMT_MU_LAW,
135 AFMT_A_LAW,
136 AFMT_STEREO | AFMT_A_LAW,
137 0
138};
139static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
140
141static u_int32_t guspnp_fmt[] = {
142 AFMT_U8,
143 AFMT_STEREO | AFMT_U8,
144 AFMT_S16_LE,
145 AFMT_STEREO | AFMT_S16_LE,
146 AFMT_A_LAW,
147 AFMT_STEREO | AFMT_A_LAW,
148 0
149};
150static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
151
152static u_int32_t opti931_fmt[] = {
153 AFMT_U8,
154 AFMT_STEREO | AFMT_U8,
155 AFMT_S16_LE,
156 AFMT_STEREO | AFMT_S16_LE,
157 0
158};
159static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
160
161#define MD_AD1848 0x91
162#define MD_AD1845 0x92
163#define MD_CS42XX 0xA1
164#define MD_OPTI930 0xB0
165#define MD_OPTI931 0xB1
166#define MD_OPTI925 0xB2
167#define MD_OPTI924 0xB3
168#define MD_GUSPNP 0xB8
169#define MD_GUSMAX 0xB9
170#define MD_YM0020 0xC1
171#define MD_VIVO 0xD1
172
173#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
174
175#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
176
177static void
178mss_lock(struct mss_info *mss)
179{
180 snd_mtxlock(mss->lock);
181}
182
183static void
184mss_unlock(struct mss_info *mss)
185{
186 snd_mtxunlock(mss->lock);
187}
188
189static int
190port_rd(struct resource *port, int off)
191{
192 if (port)
193 return bus_space_read_1(rman_get_bustag(port),
194 rman_get_bushandle(port),
195 off);
196 else
197 return -1;
198}
199
200static void
201port_wr(struct resource *port, int off, u_int8_t data)
202{
203 if (port)
204 bus_space_write_1(rman_get_bustag(port),
205 rman_get_bushandle(port),
206 off, data);
207}
208
209static int
210io_rd(struct mss_info *mss, int reg)
211{
212 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
213 return port_rd(mss->io_base, reg);
214}
215
216static void
217io_wr(struct mss_info *mss, int reg, u_int8_t data)
218{
219 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
220 port_wr(mss->io_base, reg, data);
221}
222
223static void
224conf_wr(struct mss_info *mss, u_char reg, u_char value)
225{
226 port_wr(mss->conf_base, 0, reg);
227 port_wr(mss->conf_base, 1, value);
228}
229
230static u_char
231conf_rd(struct mss_info *mss, u_char reg)
232{
233 port_wr(mss->conf_base, 0, reg);
234 return port_rd(mss->conf_base, 1);
235}
236
237static void
238opti_wr(struct mss_info *mss, u_char reg, u_char value)
239{
240 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
241 port_wr(mss->conf_base, mss->opti_offset + 1, value);
242}
243
244static u_char
245opti_rd(struct mss_info *mss, u_char reg)
246{
247 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
248 return port_rd(mss->conf_base, mss->opti_offset + 1);
249}
250
251static void
252gus_wr(struct mss_info *mss, u_char reg, u_char value)
253{
254 port_wr(mss->conf_base, 3, reg);
255 port_wr(mss->conf_base, 5, value);
256}
257
258static u_char
259gus_rd(struct mss_info *mss, u_char reg)
260{
261 port_wr(mss->conf_base, 3, reg);
262 return port_rd(mss->conf_base, 5);
263}
264
265static void
266mss_release_resources(struct mss_info *mss, device_t dev)
267{
268 if (mss->irq) {
269 if (mss->ih)
270 bus_teardown_intr(dev, mss->irq, mss->ih);
271 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
272 mss->irq);
273 mss->irq = 0;
274 }
275 if (mss->drq2) {
276 if (mss->drq2 != mss->drq1) {
277 isa_dma_release(rman_get_start(mss->drq2));
278 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
279 mss->drq2);
280 }
281 mss->drq2 = 0;
282 }
283 if (mss->drq1) {
284 isa_dma_release(rman_get_start(mss->drq1));
285 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
286 mss->drq1);
287 mss->drq1 = 0;
288 }
289 if (mss->io_base) {
290 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
291 mss->io_base);
292 mss->io_base = 0;
293 }
294 if (mss->conf_base) {
295 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
296 mss->conf_base);
297 mss->conf_base = 0;
298 }
299 if (mss->indir) {
300 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
301 mss->indir);
302 mss->indir = 0;
303 }
304 if (mss->parent_dmat) {
305 bus_dma_tag_destroy(mss->parent_dmat);
306 mss->parent_dmat = 0;
307 }
308 if (mss->lock) snd_mtxfree(mss->lock);
309
efda3bd0 310 kfree(mss, M_DEVBUF);
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311}
312
313static int
314mss_alloc_resources(struct mss_info *mss, device_t dev)
315{
316 int pdma, rdma, ok = 1;
317 if (!mss->io_base)
318 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
319 0, ~0, 1, RF_ACTIVE);
320 if (!mss->irq)
321 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid,
322 0, ~0, 1, RF_ACTIVE);
323 if (!mss->drq1)
324 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid,
325 0, ~0, 1, RF_ACTIVE);
326 if (mss->conf_rid >= 0 && !mss->conf_base)
327 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
328 0, ~0, 1, RF_ACTIVE);
329 if (mss->drq2_rid >= 0 && !mss->drq2)
330 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid,
331 0, ~0, 1, RF_ACTIVE);
332
333 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
334 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
335 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
336
337 if (ok) {
338 pdma = rman_get_start(mss->drq1);
339 isa_dma_acquire(pdma);
340 isa_dmainit(pdma, mss->bufsize);
341 mss->bd_flags &= ~BD_F_DUPLEX;
342 if (mss->drq2) {
343 rdma = rman_get_start(mss->drq2);
344 isa_dma_acquire(rdma);
345 isa_dmainit(rdma, mss->bufsize);
346 mss->bd_flags |= BD_F_DUPLEX;
347 } else mss->drq2 = mss->drq1;
348 }
349 return ok;
350}
351
352/*
353 * The various mixers use a variety of bitmasks etc. The Voxware
354 * driver had a very nice technique to describe a mixer and interface
355 * to it. A table defines, for each channel, which register, bits,
356 * offset, polarity to use. This procedure creates the new value
357 * using the table and the old value.
358 */
359
360static void
361change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
362{
363 u_char mask;
364 int shift;
365
366 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
367 "r %d p %d bit %d off %d\n",
368 dev, chn, newval, *regval,
369 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
370 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
371
372 if ( (*t)[dev][chn].polarity == 1) /* reverse */
373 newval = 100 - newval ;
374
375 mask = (1 << (*t)[dev][chn].nbits) - 1;
376 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
377 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
378
379 *regval &= ~(mask << shift); /* Filter out the previous value */
380 *regval |= (newval & mask) << shift; /* Set the new value */
381}
382
383/* -------------------------------------------------------------------- */
384/* only one source can be set... */
385static int
386mss_set_recsrc(struct mss_info *mss, int mask)
387{
388 u_char recdev;
389
390 switch (mask) {
391 case SOUND_MASK_LINE:
392 case SOUND_MASK_LINE3:
393 recdev = 0;
394 break;
395
396 case SOUND_MASK_CD:
397 case SOUND_MASK_LINE1:
398 recdev = 0x40;
399 break;
400
401 case SOUND_MASK_IMIX:
402 recdev = 0xc0;
403 break;
404
405 case SOUND_MASK_MIC:
406 default:
407 mask = SOUND_MASK_MIC;
408 recdev = 0x80;
409 }
410 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
411 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
412 return mask;
413}
414
415/* there are differences in the mixer depending on the actual sound card. */
416static int
417mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
418{
419 int regoffs;
420 mixer_tab *mix_d;
421 u_char old, val;
422
423 switch (mss->bd_id) {
424 case MD_OPTI931:
425 mix_d = &opti931_devices;
426 break;
427 case MD_OPTI930:
428 mix_d = &opti930_devices;
429 break;
430 default:
431 mix_d = &mix_devices;
432 }
433
434 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
435 DEB(printf("nbits = 0 for dev %d\n", dev));
436 return -1;
437 }
438
439 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
440
441 /* Set the left channel */
442
443 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
444 old = val = ad_read(mss, regoffs);
445 /* if volume is 0, mute chan. Otherwise, unmute. */
446 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
447 change_bits(mix_d, &val, dev, LEFT_CHN, left);
448 ad_write(mss, regoffs, val);
449
450 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
451 dev, regoffs, old, val));
452
453 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
454 /* Set the right channel */
455 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
456 old = val = ad_read(mss, regoffs);
457 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
458 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
459 ad_write(mss, regoffs, val);
460
461 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
462 dev, regoffs, old, val));
463 }
464 return 0; /* success */
465}
466
467/* -------------------------------------------------------------------- */
468
469static int
470mssmix_init(struct snd_mixer *m)
471{
472 struct mss_info *mss = mix_getdevinfo(m);
473
474 mix_setdevs(m, MODE2_MIXER_DEVICES);
475 mix_setrecdevs(m, MSS_REC_DEVICES);
476 switch(mss->bd_id) {
477 case MD_OPTI930:
478 mix_setdevs(m, OPTI930_MIXER_DEVICES);
479 break;
480
481 case MD_OPTI931:
482 mix_setdevs(m, OPTI931_MIXER_DEVICES);
483 mss_lock(mss);
484 ad_write(mss, 20, 0x88);
485 ad_write(mss, 21, 0x88);
486 mss_unlock(mss);
487 break;
488
489 case MD_AD1848:
490 mix_setdevs(m, MODE1_MIXER_DEVICES);
491 break;
492
493 case MD_GUSPNP:
494 case MD_GUSMAX:
495 /* this is only necessary in mode 3 ... */
496 mss_lock(mss);
497 ad_write(mss, 22, 0x88);
498 ad_write(mss, 23, 0x88);
499 mss_unlock(mss);
500 break;
501 }
502 return 0;
503}
504
505static int
506mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
507{
508 struct mss_info *mss = mix_getdevinfo(m);
509
510 mss_lock(mss);
511 mss_mixer_set(mss, dev, left, right);
512 mss_unlock(mss);
513
514 return left | (right << 8);
515}
516
517static int
518mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
519{
520 struct mss_info *mss = mix_getdevinfo(m);
521
522 mss_lock(mss);
523 src = mss_set_recsrc(mss, src);
524 mss_unlock(mss);
525 return src;
526}
527
528static kobj_method_t mssmix_mixer_methods[] = {
529 KOBJMETHOD(mixer_init, mssmix_init),
530 KOBJMETHOD(mixer_set, mssmix_set),
531 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
532 { 0, 0 }
533};
534MIXER_DECLARE(mssmix_mixer);
535
536/* -------------------------------------------------------------------- */
537
538static int
539ymmix_init(struct snd_mixer *m)
540{
541 struct mss_info *mss = mix_getdevinfo(m);
542
543 mssmix_init(m);
544 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
545 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
546 /* Set master volume */
547 mss_lock(mss);
548 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
549 conf_wr(mss, OPL3SAx_VOLUMER, 7);
550 mss_unlock(mss);
551
552 return 0;
553}
554
555static int
556ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
557{
558 struct mss_info *mss = mix_getdevinfo(m);
559 int t, l, r;
560
561 mss_lock(mss);
562 switch (dev) {
563 case SOUND_MIXER_VOLUME:
564 if (left) t = 15 - (left * 15) / 100;
565 else t = 0x80; /* mute */
566 conf_wr(mss, OPL3SAx_VOLUMEL, t);
567 if (right) t = 15 - (right * 15) / 100;
568 else t = 0x80; /* mute */
569 conf_wr(mss, OPL3SAx_VOLUMER, t);
570 break;
571
572 case SOUND_MIXER_MIC:
573 t = left;
574 if (left) t = 31 - (left * 31) / 100;
575 else t = 0x80; /* mute */
576 conf_wr(mss, OPL3SAx_MIC, t);
577 break;
578
579 case SOUND_MIXER_BASS:
580 l = (left * 7) / 100;
581 r = (right * 7) / 100;
582 t = (r << 4) | l;
583 conf_wr(mss, OPL3SAx_BASS, t);
584 break;
585
586 case SOUND_MIXER_TREBLE:
587 l = (left * 7) / 100;
588 r = (right * 7) / 100;
589 t = (r << 4) | l;
590 conf_wr(mss, OPL3SAx_TREBLE, t);
591 break;
592
593 default:
594 mss_mixer_set(mss, dev, left, right);
595 }
596 mss_unlock(mss);
597
598 return left | (right << 8);
599}
600
601static int
602ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
603{
604 struct mss_info *mss = mix_getdevinfo(m);
605 mss_lock(mss);
606 src = mss_set_recsrc(mss, src);
607 mss_unlock(mss);
608 return src;
609}
610
611static kobj_method_t ymmix_mixer_methods[] = {
612 KOBJMETHOD(mixer_init, ymmix_init),
613 KOBJMETHOD(mixer_set, ymmix_set),
614 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
615 { 0, 0 }
616};
617MIXER_DECLARE(ymmix_mixer);
618
619/* -------------------------------------------------------------------- */
620/*
621 * XXX This might be better off in the gusc driver.
622 */
623static void
624gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
625{
626 static const unsigned char irq_bits[16] = {
627 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
628 };
629 static const unsigned char dma_bits[8] = {
630 0, 1, 0, 2, 0, 3, 4, 5
631 };
632 device_t parent = device_get_parent(dev);
633 unsigned char irqctl, dmactl;
984263bc 634
b6d92ffb 635 crit_enter();
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636
637 port_wr(alt, 0x0f, 0x05);
638 port_wr(alt, 0x00, 0x0c);
639 port_wr(alt, 0x0b, 0x00);
640
641 port_wr(alt, 0x0f, 0x00);
642
643 irqctl = irq_bits[isa_get_irq(parent)];
644 /* Share the IRQ with the MIDI driver. */
645 irqctl |= 0x40;
646 dmactl = dma_bits[isa_get_drq(parent)];
647 if (device_get_flags(parent) & DV_F_DUAL_DMA)
648 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
649 << 3;
650
651 /*
652 * Set the DMA and IRQ control latches.
653 */
654 port_wr(alt, 0x00, 0x0c);
655 port_wr(alt, 0x0b, dmactl | 0x80);
656 port_wr(alt, 0x00, 0x4c);
657 port_wr(alt, 0x0b, irqctl);
658
659 port_wr(alt, 0x00, 0x0c);
660 port_wr(alt, 0x0b, dmactl);
661 port_wr(alt, 0x00, 0x4c);
662 port_wr(alt, 0x0b, irqctl);
663
664 port_wr(mss->conf_base, 2, 0);
665 port_wr(alt, 0x00, 0x0c);
666 port_wr(mss->conf_base, 2, 0);
667
b6d92ffb 668 crit_exit();
984263bc
MD
669}
670
671static int
672mss_init(struct mss_info *mss, device_t dev)
673{
674 u_char r6, r9;
675 struct resource *alt;
676 int rid, tmp;
677
678 mss->bd_flags |= BD_F_MCE_BIT;
679 switch(mss->bd_id) {
680 case MD_OPTI931:
681 /*
682 * The MED3931 v.1.0 allocates 3 bytes for the config
683 * space, whereas v.2.0 allocates 4 bytes. What I know
684 * for sure is that the upper two ports must be used,
685 * and they should end on a boundary of 4 bytes. So I
686 * need the following trick.
687 */
688 mss->opti_offset =
689 (rman_get_start(mss->conf_base) & ~3) + 2
690 - rman_get_start(mss->conf_base);
691 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
692 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
693 ad_write(mss, 10, 2); /* enable interrupts */
694 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
695 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
696 break;
697
698 case MD_GUSPNP:
699 case MD_GUSMAX:
700 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
701 DELAY(1000 * 30);
702 /* release reset and enable DAC */
703 gus_wr(mss, 0x4c /* _URSTI */, 3);
704 DELAY(1000 * 30);
705 /* end of reset */
706
707 rid = 0;
708 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
709 0, ~0, 1, RF_ACTIVE);
710 if (alt == NULL) {
711 printf("XXX couldn't init GUS PnP/MAX\n");
712 break;
713 }
714 port_wr(alt, 0, 0xC); /* enable int and dma */
715 if (mss->bd_id == MD_GUSMAX)
716 gusmax_setup(mss, dev, alt);
717 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
718
719 /*
720 * unmute left & right line. Need to go in mode3, unmute,
721 * and back to mode 2
722 */
723 tmp = ad_read(mss, 0x0c);
724 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
725 ad_write(mss, 0x19, 0); /* unmute left */
726 ad_write(mss, 0x1b, 0); /* unmute right */
727 ad_write(mss, 0x0c, tmp); /* restore old mode */
728
729 /* send codec interrupts on irq1 and only use that one */
730 gus_wr(mss, 0x5a, 0x4f);
731
732 /* enable access to hidden regs */
733 tmp = gus_rd(mss, 0x5b /* IVERI */);
734 gus_wr(mss, 0x5b, tmp | 1);
735 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
736 break;
737
738 case MD_YM0020:
739 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
740 r6 = conf_rd(mss, OPL3SAx_DMACONF);
741 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
742 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
743 /* yamaha - set volume to max */
744 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
745 conf_wr(mss, OPL3SAx_VOLUMER, 0);
746 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
747 break;
748 }
749 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
750 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
751 ad_enter_MCE(mss);
752 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
753 ad_leave_MCE(mss);
754 ad_write(mss, 10, 2); /* int enable */
755 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
756 /* the following seem required on the CS4232 */
757 ad_unmute(mss);
758 return 0;
759}
760
761
762/*
763 * main irq handler for the CS423x. The OPTi931 code is
764 * a separate one.
765 * The correct way to operate for a device with multiple internal
766 * interrupt sources is to loop on the status register and ack
767 * interrupts until all interrupts are served and none are reported. At
768 * this point the IRQ line to the ISA IRQ controller should go low
769 * and be raised at the next interrupt.
770 *
771 * Since the ISA IRQ controller is sent EOI _before_ passing control
772 * to the isr, it might happen that we serve an interrupt early, in
773 * which case the status register at the next interrupt should just
774 * say that there are no more interrupts...
775 */
776
777static void
778mss_intr(void *arg)
779{
780 struct mss_info *mss = arg;
781 u_char c = 0, served = 0;
782 int i;
783
784 DEB(printf("mss_intr\n"));
785 mss_lock(mss);
786 ad_read(mss, 11); /* fake read of status bits */
787
788 /* loop until there are interrupts, but no more than 10 times. */
789 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
790 /* get exact reason for full-duplex boards */
791 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
792 c &= ~served;
793 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
794 served |= 0x10;
795 chn_intr(mss->pch.channel);
796 }
797 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
798 served |= 0x20;
799 chn_intr(mss->rch.channel);
800 }
801 /* now ack the interrupt */
802 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
803 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
804 }
805 if (i == 10) {
806 BVDDB(printf("mss_intr: irq, but not from mss\n"));
807 } else if (served == 0) {
808 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
809 /*
810 * this should not happen... I have no idea what to do now.
811 * maybe should do a sanity check and restart dmas ?
812 */
813 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
814 }
815 mss_unlock(mss);
816}
817
818/*
819 * AD_WAIT_INIT waits if we are initializing the board and
820 * we cannot modify its settings
821 */
822static int
823ad_wait_init(struct mss_info *mss, int x)
824{
825 int arg = x, n = 0; /* to shut up the compiler... */
826 for (; x > 0; x--)
827 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
828 else return n;
829 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
830 return n;
831}
832
833static int
834ad_read(struct mss_info *mss, int reg)
835{
836 int x;
837
838 ad_wait_init(mss, 201000);
839 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
840 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
841 x = io_rd(mss, MSS_IDATA);
842 /* printf("ad_read %d, %x\n", reg, x); */
843 return x;
844}
845
846static void
847ad_write(struct mss_info *mss, int reg, u_char data)
848{
849 int x;
850
851 /* printf("ad_write %d, %x\n", reg, data); */
852 ad_wait_init(mss, 1002000);
853 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
854 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
855 io_wr(mss, MSS_IDATA, data);
856}
857
858static void
859ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
860{
861 ad_write(mss, reg+1, cnt & 0xff);
862 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
863}
864
865static void
866wait_for_calibration(struct mss_info *mss)
867{
868 int t;
869
870 /*
871 * Wait until the auto calibration process has finished.
872 *
873 * 1) Wait until the chip becomes ready (reads don't return 0x80).
874 * 2) Wait until the ACI bit of I11 gets on
875 * 3) Wait until the ACI bit of I11 gets off
876 */
877
878 t = ad_wait_init(mss, 1000000);
879 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
880
881 /*
882 * The calibration mode for chips that support it is set so that
883 * we never see ACI go on.
884 */
885 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
886 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
887 } else {
888 /*
889 * XXX This should only be enabled for cards that *really*
890 * need it. Are there any?
891 */
892 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
893 }
894 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
895}
896
897static void
898ad_unmute(struct mss_info *mss)
899{
900 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
901 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
902}
903
904static void
905ad_enter_MCE(struct mss_info *mss)
906{
907 int prev;
908
909 mss->bd_flags |= BD_F_MCE_BIT;
910 ad_wait_init(mss, 203000);
911 prev = io_rd(mss, MSS_INDEX);
912 prev &= ~MSS_TRD;
913 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
914}
915
916static void
917ad_leave_MCE(struct mss_info *mss)
918{
919 u_char prev;
920
921 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
922 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
923 return;
924 }
925
926 ad_wait_init(mss, 1000000);
927
928 mss->bd_flags &= ~BD_F_MCE_BIT;
929
930 prev = io_rd(mss, MSS_INDEX);
931 prev &= ~MSS_TRD;
932 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
933 wait_for_calibration(mss);
934}
935
936static int
937mss_speed(struct mss_chinfo *ch, int speed)
938{
939 struct mss_info *mss = ch->parent;
940 /*
941 * In the CS4231, the low 4 bits of I8 are used to hold the
942 * sample rate. Only a fixed number of values is allowed. This
943 * table lists them. The speed-setting routines scans the table
944 * looking for the closest match. This is the only supported method.
945 *
946 * In the CS4236, there is an alternate metod (which we do not
947 * support yet) which provides almost arbitrary frequency setting.
948 * In the AD1845, it looks like the sample rate can be
949 * almost arbitrary, and written directly to a register.
950 * In the OPTi931, there is a SB command which provides for
951 * almost arbitrary frequency setting.
952 *
953 */
954 ad_enter_MCE(mss);
955 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
956 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
957 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
958 /* XXX must also do something in I27 for the ad1845 */
959 } else {
960 int i, sel = 0; /* assume entry 0 does not contain -1 */
961 static int speeds[] =
962 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
963 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
964
965 for (i = 1; i < 16; i++)
966 if (speeds[i] > 0 &&
967 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
968 speed = speeds[sel];
969 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
970 }
971 ad_leave_MCE(mss);
972
973 return speed;
974}
975
976/*
977 * mss_format checks that the format is supported (or defaults to AFMT_U8)
978 * and returns the bit setting for the 1848 register corresponding to
979 * the desired format.
980 *
981 * fixed lr970724
982 */
983
984static int
985mss_format(struct mss_chinfo *ch, u_int32_t format)
986{
987 struct mss_info *mss = ch->parent;
988 int i, arg = format & ~AFMT_STEREO;
989
990 /*
991 * The data format uses 3 bits (just 2 on the 1848). For each
992 * bit setting, the following array returns the corresponding format.
993 * The code scans the array looking for a suitable format. In
994 * case it is not found, default to AFMT_U8 (not such a good
995 * choice, but let's do it for compatibility...).
996 */
997
998 static int fmts[] =
999 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1000 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1001
1002 ch->fmt = format;
1003 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1004 arg = i << 1;
1005 if (format & AFMT_STEREO) arg |= 1;
1006 arg <<= 4;
1007 ad_enter_MCE(mss);
1008 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1009 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */
1010 ad_leave_MCE(mss);
1011 return format;
1012}
1013
1014static int
1015mss_trigger(struct mss_chinfo *ch, int go)
1016{
1017 struct mss_info *mss = ch->parent;
1018 u_char m;
1019 int retry, wr, cnt, ss;
1020
1021 ss = 1;
1022 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0;
1023 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1024
1025 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1026 m = ad_read(mss, 9);
1027 switch (go) {
1028 case PCMTRIG_START:
1029 cnt = (ch->blksz / ss) - 1;
1030
1031 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1032 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1033 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1034 break;
1035
1036 case PCMTRIG_STOP:
1037 case PCMTRIG_ABORT: /* XXX check this... */
1038 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1039#if 0
1040 /*
1041 * try to disable DMA by clearing count registers. Not sure it
1042 * is needed, and it might cause false interrupts when the
1043 * DMA is re-enabled later.
1044 */
1045 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1046#endif
1047 }
1048 /* on the OPTi931 the enable bit seems hard to set... */
1049 for (retry = 10; retry > 0; retry--) {
1050 ad_write(mss, 9, m);
1051 if (ad_read(mss, 9) == m) break;
1052 }
1053 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
1054 m, ad_read(mss, 9)));
1055 return 0;
1056}
1057
1058
1059/*
1060 * the opti931 seems to miss interrupts when working in full
1061 * duplex, so we try some heuristics to catch them.
1062 */
1063static void
1064opti931_intr(void *arg)
1065{
1066 struct mss_info *mss = (struct mss_info *)arg;
1067 u_char masked = 0, i11, mc11, c = 0;
1068 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1069 int loops = 10;
1070
1071#if 0
1072 reason = io_rd(mss, MSS_STATUS);
1073 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1074 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1075 return;
1076 }
1077#endif
1078 mss_lock(mss);
1079 i11 = ad_read(mss, 11); /* XXX what's for ? */
1080 again:
1081
1082 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1083 mc11 &= 0x0c;
1084 if (c & 0x10) {
1085 DEB(printf("Warning: CD interrupt\n");)
1086 mc11 |= 0x10;
1087 }
1088 if (c & 0x20) {
1089 DEB(printf("Warning: MPU interrupt\n");)
1090 mc11 |= 0x20;
1091 }
1092 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
1093 mc11, masked));
1094 masked |= mc11;
1095 /*
1096 * the nice OPTi931 sets the IRQ line before setting the bits in
1097 * mc11. So, on some occasions I have to retry (max 10 times).
1098 */
1099 if (mc11 == 0) { /* perhaps can return ... */
1100 reason = io_rd(mss, MSS_STATUS);
1101 if (reason & 1) {
1102 DEB(printf("one more try...\n");)
1103 if (--loops) goto again;
1104 else DDB(printf("intr, but mc11 not set\n");)
1105 }
1106 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
1107 mss_unlock(mss);
1108 return;
1109 }
1110
1111 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) chn_intr(mss->rch.channel);
1112 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) chn_intr(mss->pch.channel);
1113 opti_wr(mss, 11, ~mc11); /* ack */
1114 if (--loops) goto again;
1115 mss_unlock(mss);
1116 DEB(printf("xxx too many loops\n");)
1117}
1118
1119/* -------------------------------------------------------------------- */
1120/* channel interface */
1121static void *
1122msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1123{
1124 struct mss_info *mss = devinfo;
1125 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1126
1127 ch->parent = mss;
1128 ch->channel = c;
1129 ch->buffer = b;
1130 ch->dir = dir;
1131 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) == -1) return NULL;
1132 sndbuf_isadmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1133 return ch;
1134}
1135
1136static int
1137msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1138{
1139 struct mss_chinfo *ch = data;
1140 struct mss_info *mss = ch->parent;
1141
1142 mss_lock(mss);
1143 mss_format(ch, format);
1144 mss_unlock(mss);
1145 return 0;
1146}
1147
1148static int
1149msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1150{
1151 struct mss_chinfo *ch = data;
1152 struct mss_info *mss = ch->parent;
1153 int r;
1154
1155 mss_lock(mss);
1156 r = mss_speed(ch, speed);
1157 mss_unlock(mss);
1158
1159 return r;
1160}
1161
1162static int
1163msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1164{
1165 struct mss_chinfo *ch = data;
1166
1167 ch->blksz = blocksize;
1168 sndbuf_resize(ch->buffer, 2, ch->blksz);
1169
1170 return ch->blksz;
1171}
1172
1173static int
1174msschan_trigger(kobj_t obj, void *data, int go)
1175{
1176 struct mss_chinfo *ch = data;
1177 struct mss_info *mss = ch->parent;
1178
1179 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
1180 return 0;
1181
1182 sndbuf_isadma(ch->buffer, go);
1183 mss_lock(mss);
1184 mss_trigger(ch, go);
1185 mss_unlock(mss);
1186 return 0;
1187}
1188
1189static int
1190msschan_getptr(kobj_t obj, void *data)
1191{
1192 struct mss_chinfo *ch = data;
1193 return sndbuf_isadmaptr(ch->buffer);
1194}
1195
1196static struct pcmchan_caps *
1197msschan_getcaps(kobj_t obj, void *data)
1198{
1199 struct mss_chinfo *ch = data;
1200
1201 switch(ch->parent->bd_id) {
1202 case MD_OPTI931:
1203 return &opti931_caps;
1204 break;
1205
1206 case MD_GUSPNP:
1207 case MD_GUSMAX:
1208 return &guspnp_caps;
1209 break;
1210
1211 default:
1212 return &mss_caps;
1213 break;
1214 }
1215}
1216
1217static kobj_method_t msschan_methods[] = {
1218 KOBJMETHOD(channel_init, msschan_init),
1219 KOBJMETHOD(channel_setformat, msschan_setformat),
1220 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1221 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1222 KOBJMETHOD(channel_trigger, msschan_trigger),
1223 KOBJMETHOD(channel_getptr, msschan_getptr),
1224 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1225 { 0, 0 }
1226};
1227CHANNEL_DECLARE(msschan);
1228
1229/* -------------------------------------------------------------------- */
1230
1231/*
1232 * mss_probe() is the probe routine. Note, it is not necessary to
1233 * go through this for PnP devices, since they are already
1234 * indentified precisely using their PnP id.
1235 *
1236 * The base address supplied in the device refers to the old MSS
1237 * specs where the four 4 registers in io space contain configuration
1238 * information. Some boards (as an example, early MSS boards)
1239 * has such a block of registers, whereas others (generally CS42xx)
1240 * do not. In order to distinguish between the two and do not have
1241 * to supply two separate probe routines, the flags entry in isa_device
1242 * has a bit to mark this.
1243 *
1244 */
1245
1246static int
1247mss_probe(device_t dev)
1248{
1249 u_char tmp, tmpx;
1250 int flags, irq, drq, result = ENXIO, setres = 0;
1251 struct mss_info *mss;
1252
1253 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1254
efda3bd0 1255 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
1256 if (!mss) return ENXIO;
1257
1258 mss->io_rid = 0;
1259 mss->conf_rid = -1;
1260 mss->irq_rid = 0;
1261 mss->drq1_rid = 0;
1262 mss->drq2_rid = -1;
1263 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1264 0, ~0, 8, RF_ACTIVE);
1265 if (!mss->io_base) {
1266 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
1267 mss->io_rid = 0;
1268 /* XXX verify this */
1269 setres = 1;
1270 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1271 0x530, 8);
1272 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1273 0, ~0, 8, RF_ACTIVE);
1274 }
1275 if (!mss->io_base) goto no;
1276
1277 /* got irq/dma regs? */
1278 flags = device_get_flags(dev);
1279 irq = isa_get_irq(dev);
1280 drq = isa_get_drq(dev);
1281
1282 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1283
1284 /*
1285 * Check if the IO port returns valid signature. The original MS
1286 * Sound system returns 0x04 while some cards
1287 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1288 */
1289
1290 device_set_desc(dev, "MSS");
1291 tmpx = tmp = io_rd(mss, 3);
1292 if (tmp == 0xff) { /* Bus float */
1293 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
1294 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1295 goto mss_probe_end;
1296 }
1297 tmp &= 0x3f;
1298 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
1299 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
1300 rman_get_start(mss->io_base), tmpx));
1301 goto no;
1302 }
984263bc 1303 if (irq > 11) {
984263bc
MD
1304 printf("MSS: Bad IRQ %d\n", irq);
1305 goto no;
1306 }
1307 if (!(drq == 0 || drq == 1 || drq == 3)) {
1308 printf("MSS: Bad DMA %d\n", drq);
1309 goto no;
1310 }
1311 if (tmpx & 0x80) {
1312 /* 8-bit board: only drq1/3 and irq7/9 */
1313 if (drq == 0) {
1314 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1315 goto no;
1316 }
1317 if (!(irq == 7 || irq == 9)) {
1318 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
1319 irq);
1320 goto no;
1321 }
1322 }
1323 mss_probe_end:
1324 result = mss_detect(dev, mss);
1325 no:
1326 mss_release_resources(mss, dev);
1327#if 0
1328 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1329 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1330#endif
1331 return result;
1332}
1333
1334static int
1335mss_detect(device_t dev, struct mss_info *mss)
1336{
1337 int i;
1338 u_char tmp = 0, tmp1, tmp2;
1339 char *name, *yamaha;
1340
1341 if (mss->bd_id != 0) {
1342 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1343 device_get_desc(dev));
1344 return 0;
1345 }
1346
1347 name = "AD1848";
1348 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1349
1350 if (opti_detect(dev, mss)) {
1351 switch (mss->bd_id) {
1352 case MD_OPTI924:
1353 name = "OPTi924";
1354 break;
1355 case MD_OPTI930:
1356 name = "OPTi930";
1357 break;
1358 }
1359 printf("Found OPTi device %s\n", name);
1360 if (opti_init(dev, mss) == 0) goto gotit;
1361 }
1362
1363 /*
1364 * Check that the I/O address is in use.
1365 *
1366 * bit 7 of the base I/O port is known to be 0 after the chip has
1367 * performed its power on initialization. Just assume this has
1368 * happened before the OS is starting.
1369 *
1370 * If the I/O address is unused, it typically returns 0xff.
1371 */
1372
1373 for (i = 0; i < 10; i++)
1374 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1375 else break;
1376
1377 if (i >= 10) { /* Not a AD1848 */
1378 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
1379 goto no;
1380 }
1381 /*
1382 * Test if it's possible to change contents of the indirect
1383 * registers. Registers 0 and 1 are ADC volume registers. The bit
1384 * 0x10 is read only so try to avoid using it.
1385 */
1386
1387 ad_write(mss, 0, 0xaa);
1388 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1389 tmp1 = ad_read(mss, 0);
1390 tmp2 = ad_read(mss, 1);
1391 if (tmp1 != 0xaa || tmp2 != 0x45) {
1392 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
1393 goto no;
1394 }
1395
1396 ad_write(mss, 0, 0x45);
1397 ad_write(mss, 1, 0xaa);
1398 tmp1 = ad_read(mss, 0);
1399 tmp2 = ad_read(mss, 1);
1400 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1401 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
1402 goto no;
1403 }
1404
1405 /*
1406 * The indirect register I12 has some read only bits. Lets try to
1407 * change them.
1408 */
1409
1410 tmp = ad_read(mss, 12);
1411 ad_write(mss, 12, (~tmp) & 0x0f);
1412 tmp1 = ad_read(mss, 12);
1413
1414 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1415 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
1416 goto no;
1417 }
1418
1419 /*
1420 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1421 * 0x01=RevB
1422 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1423 */
1424
1425 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
1426
1427 /*
1428 * The original AD1848/CS4248 has just 16 indirect registers. This
1429 * means that I0 and I16 should return the same value (etc.). Ensure
1430 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1431 * with new parts.
1432 */
1433
1434 ad_write(mss, 12, 0); /* Mode2=disabled */
1435#if 0
1436 for (i = 0; i < 16; i++) {
1437 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1438 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
1439 i, tmp1, tmp2));
1440 /*
1441 * note - this seems to fail on the 4232 on I11. So we just break
1442 * rather than fail. (which makes this test pointless - cg)
1443 */
1444 break; /* return 0; */
1445 }
1446 }
1447#endif
1448 /*
1449 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1450 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1451 *
1452 * On the OPTi931, however, I12 is readonly and only contains the
1453 * chip revision ID (as in the CS4231A). The upper bits return 0.
1454 */
1455
1456 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1457
1458 tmp1 = ad_read(mss, 12);
1459 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1460 if ((tmp1 & 0xf0) == 0x00) {
1461 BVDDB(printf("this should be an OPTi931\n");)
1462 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1463 /*
1464 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1465 * We want to check that this is really a CS4231
1466 * Verify that setting I0 doesn't change I16.
1467 */
1468 ad_write(mss, 16, 0); /* Set I16 to known value */
1469 ad_write(mss, 0, 0x45);
1470 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1471
1472 ad_write(mss, 0, 0xaa);
1473 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1474 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
1475 goto no;
1476 }
1477 /* Verify that some bits of I25 are read only. */
1478 tmp1 = ad_read(mss, 25); /* Original bits */
1479 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1480 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1481 int id;
1482
1483 /* It's at least CS4231 */
1484 name = "CS4231";
1485 mss->bd_id = MD_CS42XX;
1486
1487 /*
1488 * It could be an AD1845 or CS4231A as well.
1489 * CS4231 and AD1845 report the same revision info in I25
1490 * while the CS4231A reports different.
1491 */
1492
1493 id = ad_read(mss, 25) & 0xe7;
1494 /*
1495 * b7-b5 = version number;
1496 * 100 : all CS4231
1497 * 101 : CS4231A
1498 *
1499 * b2-b0 = chip id;
1500 */
1501 switch (id) {
1502
1503 case 0xa0:
1504 name = "CS4231A";
1505 mss->bd_id = MD_CS42XX;
1506 break;
1507
1508 case 0xa2:
1509 name = "CS4232";
1510 mss->bd_id = MD_CS42XX;
1511 break;
1512
1513 case 0xb2:
1514 /* strange: the 4231 data sheet says b4-b3 are XX
1515 * so this should be the same as 0xa2
1516 */
1517 name = "CS4232A";
1518 mss->bd_id = MD_CS42XX;
1519 break;
1520
1521 case 0x80:
1522 /*
1523 * It must be a CS4231 or AD1845. The register I23
1524 * of CS4231 is undefined and it appears to be read
1525 * only. AD1845 uses I23 for setting sample rate.
1526 * Assume the chip is AD1845 if I23 is changeable.
1527 */
1528
1529 tmp = ad_read(mss, 23);
1530
1531 ad_write(mss, 23, ~tmp);
1532 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1533 name = "AD1845";
1534 mss->bd_id = MD_AD1845;
1535 }
1536 ad_write(mss, 23, tmp); /* Restore */
1537
1538 yamaha = ymf_test(dev, mss);
1539 if (yamaha) {
1540 mss->bd_id = MD_YM0020;
1541 name = yamaha;
1542 }
1543 break;
1544
1545 case 0x83: /* CS4236 */
1546 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1547 name = "CS4236";
1548 mss->bd_id = MD_CS42XX;
1549 break;
1550
1551 default: /* Assume CS4231 */
1552 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
1553 mss->bd_id = MD_CS42XX;
1554 }
1555 }
1556 ad_write(mss, 25, tmp1); /* Restore bits */
1557gotit:
1558 BVDDB(printf("mss_detect() - Detected %s\n", name));
1559 device_set_desc(dev, name);
1560 device_set_flags(dev,
1561 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1562 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1563 return 0;
1564no:
1565 return ENXIO;
1566}
1567
1568static int
1569opti_detect(device_t dev, struct mss_info *mss)
1570{
1571 int c;
1572 static const struct opticard {
1573 int boardid;
1574 int passwdreg;
1575 int password;
1576 int base;
1577 int indir_reg;
1578 } cards[] = {
1579 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1580 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1581 { 0 },
1582 };
1583 mss->conf_rid = 3;
1584 mss->indir_rid = 4;
1585 for (c = 0; cards[c].base; c++) {
1586 mss->optibase = cards[c].base;
1587 mss->password = cards[c].password;
1588 mss->passwdreg = cards[c].passwdreg;
1589 mss->bd_id = cards[c].boardid;
1590
1591 if (cards[c].indir_reg)
1592 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1593 &mss->indir_rid, cards[c].indir_reg,
1594 cards[c].indir_reg+1, 1, RF_ACTIVE);
1595
1596 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1597 &mss->conf_rid, mss->optibase, mss->optibase+9,
1598 9, RF_ACTIVE);
1599
1600 if (opti_read(mss, 1) != 0xff) {
1601 return 1;
1602 } else {
1603 if (mss->indir)
1604 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1605 mss->indir = NULL;
1606 if (mss->conf_base)
1607 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1608 mss->conf_base = NULL;
1609 }
1610 }
1611 return 0;
1612}
1613
1614static char *
1615ymf_test(device_t dev, struct mss_info *mss)
1616{
1617 static int ports[] = {0x370, 0x310, 0x538};
1618 int p, i, j, version;
1619 static char *chipset[] = {
1620 NULL, /* 0 */
1621 "OPL3-SA2 (YMF711)", /* 1 */
1622 "OPL3-SA3 (YMF715)", /* 2 */
1623 "OPL3-SA3 (YMF715)", /* 3 */
1624 "OPL3-SAx (YMF719)", /* 4 */
1625 "OPL3-SAx (YMF719)", /* 5 */
1626 "OPL3-SAx (YMF719)", /* 6 */
1627 "OPL3-SAx (YMF719)", /* 7 */
1628 };
1629
1630 for (p = 0; p < 3; p++) {
1631 mss->conf_rid = 1;
1632 mss->conf_base = bus_alloc_resource(dev,
1633 SYS_RES_IOPORT,
1634 &mss->conf_rid,
1635 ports[p], ports[p] + 1, 2,
1636 RF_ACTIVE);
1637 if (!mss->conf_base) return 0;
1638
1639 /* Test the index port of the config registers */
1640 i = port_rd(mss->conf_base, 0);
1641 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1642 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1643 port_wr(mss->conf_base, 0, i);
1644 if (!j) {
1645 bus_release_resource(dev, SYS_RES_IOPORT,
1646 mss->conf_rid, mss->conf_base);
984263bc
MD
1647 mss->conf_base = 0;
1648 continue;
1649 }
1650 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1651 return chipset[version];
1652 }
1653 return NULL;
1654}
1655
1656static int
1657mss_doattach(device_t dev, struct mss_info *mss)
1658{
1659 int pdma, rdma, flags = device_get_flags(dev);
1660 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1661
1662 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1663 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1664 if (!mss_alloc_resources(mss, dev)) goto no;
1665 mss_init(mss, dev);
1666 pdma = rman_get_start(mss->drq1);
1667 rdma = rman_get_start(mss->drq2);
1668 if (flags & DV_F_TRUE_MSS) {
1669 /* has IRQ/DMA registers, set IRQ and DMA addr */
984263bc
MD
1670 static char interrupt_bits[12] =
1671 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
984263bc
MD
1672 static char pdma_bits[4] = {1, 2, -1, 3};
1673 static char valid_rdma[4] = {1, 0, -1, 0};
1674 char bits;
1675
1676 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1677 goto no;
984263bc
MD
1678 io_wr(mss, 0, bits | 0x40); /* config port */
1679 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
984263bc
MD
1680 /* Write IRQ+DMA setup */
1681 if (pdma_bits[pdma] == -1) goto no;
1682 bits |= pdma_bits[pdma];
1683 if (pdma != rdma) {
1684 if (rdma == valid_rdma[pdma]) bits |= 4;
1685 else {
1686 printf("invalid dual dma config %d:%d\n", pdma, rdma);
1687 goto no;
1688 }
1689 }
1690 io_wr(mss, 0, bits);
1691 printf("drq/irq conf %x\n", io_rd(mss, 0));
1692 }
1693 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1694 switch (mss->bd_id) {
1695 case MD_OPTI931:
e9cb6d99 1696 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, opti931_intr, mss, &mss->ih, NULL);
984263bc
MD
1697 break;
1698 default:
e9cb6d99 1699 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, mss_intr, mss, &mss->ih, NULL);
984263bc
MD
1700 }
1701 if (pdma == rdma)
1702 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1703 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1704 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1705 /*highaddr*/BUS_SPACE_MAXADDR,
1706 /*filter*/NULL, /*filterarg*/NULL,
1707 /*maxsize*/mss->bufsize, /*nsegments*/1,
1708 /*maxsegz*/0x3ffff,
1709 /*flags*/0, &mss->parent_dmat) != 0) {
1710 device_printf(dev, "unable to create dma tag\n");
1711 goto no;
1712 }
1713
1714 if (pdma != rdma)
f8c7a42d 1715 ksnprintf(status2, SND_STATUSLEN, ":%d", rdma);
984263bc
MD
1716 else
1717 status2[0] = '\0';
1718
f8c7a42d 1719 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
984263bc
MD
1720 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1721
1722 if (pcm_register(dev, mss, 1, 1)) goto no;
1723 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1724 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1725 pcm_setstatus(dev, status);
1726
1727 return 0;
1728no:
1729 mss_release_resources(mss, dev);
1730 return ENXIO;
1731}
1732
1733static int
1734mss_detach(device_t dev)
1735{
1736 int r;
1737 struct mss_info *mss;
1738
1739 r = pcm_unregister(dev);
1740 if (r)
1741 return r;
1742
1743 mss = pcm_getdevinfo(dev);
1744 mss_release_resources(mss, dev);
1745
1746 return 0;
1747}
1748
1749static int
1750mss_attach(device_t dev)
1751{
1752 struct mss_info *mss;
1753 int flags = device_get_flags(dev);
1754
efda3bd0 1755 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
1756 if (!mss) return ENXIO;
1757
1758 mss->io_rid = 0;
1759 mss->conf_rid = -1;
1760 mss->irq_rid = 0;
1761 mss->drq1_rid = 0;
1762 mss->drq2_rid = -1;
1763 if (flags & DV_F_DUAL_DMA) {
1764 bus_set_resource(dev, SYS_RES_DRQ, 1,
1765 flags & DV_F_DRQ_MASK, 1);
1766 mss->drq2_rid = 1;
1767 }
1768 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1769 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1770 return mss_doattach(dev, mss);
1771}
1772
1773/*
1774 * mss_resume() is the code to allow a laptop to resume using the sound
1775 * card.
1776 *
1777 * This routine re-sets the state of the board to the state before going
1778 * to sleep. According to the yamaha docs this is the right thing to do,
1779 * but getting DMA restarted appears to be a bit of a trick, so the device
1780 * has to be closed and re-opened to be re-used, but there is no skipping
1781 * problem, and volume, bass/treble and most other things are restored
1782 * properly.
1783 *
1784 */
1785
1786static int
1787mss_resume(device_t dev)
1788{
1789 /*
1790 * Restore the state taken below.
1791 */
1792 struct mss_info *mss;
1793 int i;
1794
1795 mss = pcm_getdevinfo(dev);
1796
1797 if (mss->bd_id == MD_YM0020)
1798 {
1799 /* This works on a Toshiba Libretto 100CT. */
1800 for (i = 0; i < MSS_INDEXED_REGS; i++)
1801 ad_write(mss, i, mss->mss_indexed_regs[i]);
1802 for (i = 0; i < OPL_INDEXED_REGS; i++)
1803 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1804 mss_intr(mss);
1805 }
1806 return 0;
1807
1808}
1809
1810/*
1811 * mss_suspend() is the code that gets called right before a laptop
1812 * suspends.
1813 *
1814 * This code saves the state of the sound card right before shutdown
1815 * so it can be restored above.
1816 *
1817 */
1818
1819static int
1820mss_suspend(device_t dev)
1821{
1822 int i;
1823 struct mss_info *mss;
1824
1825 mss = pcm_getdevinfo(dev);
1826
1827 if(mss->bd_id == MD_YM0020)
1828 {
1829 /* this stops playback. */
1830 conf_wr(mss, 0x12, 0x0c);
1831 for(i = 0; i < MSS_INDEXED_REGS; i++)
1832 mss->mss_indexed_regs[i] = ad_read(mss, i);
1833 for(i = 0; i < OPL_INDEXED_REGS; i++)
1834 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1835 mss->opl_indexed_regs[0x12] = 0x0;
1836 }
1837 return 0;
1838}
1839
1840static device_method_t mss_methods[] = {
1841 /* Device interface */
1842 DEVMETHOD(device_probe, mss_probe),
1843 DEVMETHOD(device_attach, mss_attach),
1844 DEVMETHOD(device_detach, mss_detach),
1845 DEVMETHOD(device_suspend, mss_suspend),
1846 DEVMETHOD(device_resume, mss_resume),
1847
1848 { 0, 0 }
1849};
1850
1851static driver_t mss_driver = {
1852 "pcm",
1853 mss_methods,
1854 PCM_SOFTC_SIZE,
1855};
1856
1857DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
1858MODULE_DEPEND(snd_mss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1859MODULE_VERSION(snd_mss, 1);
1860
1861static int
1862azt2320_mss_mode(struct mss_info *mss, device_t dev)
1863{
1864 struct resource *sbport;
1865 int i, ret, rid;
1866
1867 rid = 0;
1868 ret = -1;
1869 sbport = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1870 0, ~0, 1, RF_ACTIVE);
1871 if (sbport) {
1872 for (i = 0; i < 1000; i++) {
1873 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1874 DELAY((i > 100) ? 1000 : 10);
1875 else {
1876 port_wr(sbport, SBDSP_CMD, 0x09);
1877 break;
1878 }
1879 }
1880 for (i = 0; i < 1000; i++) {
1881 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1882 DELAY((i > 100) ? 1000 : 10);
1883 else {
1884 port_wr(sbport, SBDSP_CMD, 0x00);
1885 ret = 0;
1886 break;
1887 }
1888 }
1889 DELAY(1000);
1890 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1891 }
1892 return ret;
1893}
1894
1895static struct isa_pnp_id pnpmss_ids[] = {
1896 {0x0000630e, "CS423x"}, /* CSC0000 */
1897 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1898 {0x01000000, "CMI8330"}, /* @@@0001 */
1899 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1900 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1901 {0x1093143e, "OPTi931"}, /* OPT9310 */
1902 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1903 {0x0000143e, "OPTi924"}, /* OPT0924 */
1904 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1905 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1906#if 0
1907 {0x0000561e, "GusPnP"}, /* GRV0000 */
1908#endif
1909 {0},
1910};
1911
1912static int
1913pnpmss_probe(device_t dev)
1914{
1915 u_int32_t lid, vid;
1916
1917 lid = isa_get_logicalid(dev);
1918 vid = isa_get_vendorid(dev);
1919 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1920 return ENXIO;
1921 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1922}
1923
1924static int
1925pnpmss_attach(device_t dev)
1926{
1927 struct mss_info *mss;
1928
efda3bd0 1929 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
1930 if (!mss)
1931 return ENXIO;
1932
1933 mss->io_rid = 0;
1934 mss->conf_rid = -1;
1935 mss->irq_rid = 0;
1936 mss->drq1_rid = 0;
1937 mss->drq2_rid = 1;
1938 mss->bd_id = MD_CS42XX;
1939
1940 switch (isa_get_logicalid(dev)) {
1941 case 0x0000630e: /* CSC0000 */
1942 case 0x0001630e: /* CSC0100 */
1943 mss->bd_flags |= BD_F_MSS_OFFSET;
1944 break;
1945
1946 case 0x2100a865: /* YHM0021 */
1947 mss->io_rid = 1;
1948 mss->conf_rid = 4;
1949 mss->bd_id = MD_YM0020;
1950 break;
1951
1952 case 0x1110d315: /* ENS1011 */
1953 mss->io_rid = 1;
1954 mss->bd_id = MD_VIVO;
1955 break;
1956
1957 case 0x1093143e: /* OPT9310 */
1958 mss->bd_flags |= BD_F_MSS_OFFSET;
1959 mss->conf_rid = 3;
1960 mss->bd_id = MD_OPTI931;
1961 break;
1962
1963 case 0x5092143e: /* OPT9250 XXX guess */
1964 mss->io_rid = 1;
1965 mss->conf_rid = 3;
1966 mss->bd_id = MD_OPTI925;
1967 break;
1968
1969 case 0x0000143e: /* OPT0924 */
1970 mss->password = 0xe5;
1971 mss->passwdreg = 3;
1972 mss->optibase = 0xf0c;
1973 mss->io_rid = 2;
1974 mss->conf_rid = 3;
1975 mss->bd_id = MD_OPTI924;
1976 mss->bd_flags |= BD_F_924PNP;
1977 if(opti_init(dev, mss) != 0)
1978 return ENXIO;
1979 break;
1980
1981 case 0x1022b839: /* NMX2210 */
1982 mss->io_rid = 1;
1983 break;
1984
1985 case 0x01005407: /* AZT0001 */
1986 /* put into MSS mode first (snatched from NetBSD) */
1987 if (azt2320_mss_mode(mss, dev) == -1)
1988 return ENXIO;
1989
1990 mss->bd_flags |= BD_F_MSS_OFFSET;
1991 mss->io_rid = 2;
1992 break;
1993
1994#if 0
1995 case 0x0000561e: /* GRV0000 */
1996 mss->bd_flags |= BD_F_MSS_OFFSET;
1997 mss->io_rid = 2;
1998 mss->conf_rid = 1;
1999 mss->drq1_rid = 1;
2000 mss->drq2_rid = 0;
2001 mss->bd_id = MD_GUSPNP;
2002 break;
2003#endif
2004 case 0x01000000: /* @@@0001 */
2005 mss->drq2_rid = -1;
2006 break;
2007
2008 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2009 default:
2010 mss->bd_flags |= BD_F_MSS_OFFSET;
2011 break;
2012 }
2013 return mss_doattach(dev, mss);
2014}
2015
2016static int
2017opti_init(device_t dev, struct mss_info *mss)
2018{
2019 int flags = device_get_flags(dev);
2020 int basebits = 0;
2021
2022 if (!mss->conf_base) {
2023 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2024 mss->optibase, 0x9);
2025
2026 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2027 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2028 0x9, RF_ACTIVE);
2029 }
2030
2031 if (!mss->conf_base)
2032 return ENXIO;
2033
2034 if (!mss->io_base)
2035 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2036 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2037
2038 if (!mss->io_base) /* No hint specified, use 0x530 */
2039 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2040 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2041
2042 if (!mss->io_base)
2043 return ENXIO;
2044
2045 switch (rman_get_start(mss->io_base)) {
2046 case 0x530:
2047 basebits = 0x0;
2048 break;
2049 case 0xe80:
2050 basebits = 0x10;
2051 break;
2052 case 0xf40:
2053 basebits = 0x20;
2054 break;
2055 case 0x604:
2056 basebits = 0x30;
2057 break;
2058 default:
2059 printf("opti_init: invalid MSS base address!\n");
2060 return ENXIO;
2061 }
2062
2063
2064 switch (mss->bd_id) {
2065 case MD_OPTI924:
2066 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2067 opti_write(mss, 2, 0x00); /* Disable CD */
2068 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2069 opti_write(mss, 4, 0xf0);
2070 opti_write(mss, 5, 0x00);
2071 opti_write(mss, 6, 0x02); /* MPU stuff */
2072 break;
2073
2074 case MD_OPTI930:
2075 opti_write(mss, 1, 0x00 | basebits);
2076 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2077 opti_write(mss, 4, 0x52); /* Empty FIFO */
2078 opti_write(mss, 5, 0x3c); /* Mode 2 */
2079 opti_write(mss, 6, 0x02); /* Enable MSS */
2080 break;
2081 }
2082
2083 if (mss->bd_flags & BD_F_924PNP) {
2084 u_int32_t irq = isa_get_irq(dev);
2085 u_int32_t drq = isa_get_drq(dev);
2086 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2087 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2088 if (flags & DV_F_DUAL_DMA) {
2089 bus_set_resource(dev, SYS_RES_DRQ, 1,
2090 flags & DV_F_DRQ_MASK, 1);
2091 mss->drq2_rid = 1;
2092 }
2093 }
2094
2095 /* OPTixxx has I/DRQ registers */
2096
2097 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2098
2099 return 0;
2100}
2101
2102static void
2103opti_write(struct mss_info *mss, u_char reg, u_char val)
2104{
2105 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2106
2107 switch(mss->bd_id) {
2108 case MD_OPTI924:
2109 if (reg > 7) { /* Indirect register */
2110 port_wr(mss->conf_base, mss->passwdreg, reg);
2111 port_wr(mss->conf_base, mss->passwdreg,
2112 mss->password);
2113 port_wr(mss->conf_base, 9, val);
2114 return;
2115 }
2116 port_wr(mss->conf_base, reg, val);
2117 break;
2118
2119 case MD_OPTI930:
2120 port_wr(mss->indir, 0, reg);
2121 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2122 port_wr(mss->indir, 1, val);
2123 break;
2124 }
2125}
2126
2127u_char
2128opti_read(struct mss_info *mss, u_char reg)
2129{
2130 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2131
2132 switch(mss->bd_id) {
2133 case MD_OPTI924:
2134 if (reg > 7) { /* Indirect register */
2135 port_wr(mss->conf_base, mss->passwdreg, reg);
2136 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2137 return(port_rd(mss->conf_base, 9));
2138 }
2139 return(port_rd(mss->conf_base, reg));
2140 break;
2141
2142 case MD_OPTI930:
2143 port_wr(mss->indir, 0, reg);
2144 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2145 return port_rd(mss->indir, 1);
2146 break;
2147 }
2148 return -1;
2149}
2150
2151static device_method_t pnpmss_methods[] = {
2152 /* Device interface */
2153 DEVMETHOD(device_probe, pnpmss_probe),
2154 DEVMETHOD(device_attach, pnpmss_attach),
2155 DEVMETHOD(device_detach, mss_detach),
2156 DEVMETHOD(device_suspend, mss_suspend),
2157 DEVMETHOD(device_resume, mss_resume),
2158
2159 { 0, 0 }
2160};
2161
2162static driver_t pnpmss_driver = {
2163 "pcm",
2164 pnpmss_methods,
2165 PCM_SOFTC_SIZE,
2166};
2167
2168DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
2169MODULE_DEPEND(snd_pnpmss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
2170MODULE_VERSION(snd_pnpmss, 1);
2171
2172static int
2173guspcm_probe(device_t dev)
2174{
2175 struct sndcard_func *func;
2176
2177 func = device_get_ivars(dev);
2178 if (func == NULL || func->func != SCF_PCM)
2179 return ENXIO;
2180
2181 device_set_desc(dev, "GUS CS4231");
2182 return 0;
2183}
2184
2185static int
2186guspcm_attach(device_t dev)
2187{
2188 device_t parent = device_get_parent(dev);
2189 struct mss_info *mss;
2190 int base, flags;
2191 unsigned char ctl;
2192
efda3bd0 2193 mss = (struct mss_info *)kmalloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
984263bc
MD
2194 if (mss == NULL)
2195 return ENOMEM;
2196
2197 mss->bd_flags = BD_F_MSS_OFFSET;
2198 mss->io_rid = 2;
2199 mss->conf_rid = 1;
2200 mss->irq_rid = 0;
2201 mss->drq1_rid = 1;
2202 mss->drq2_rid = -1;
2203
2204 if (isa_get_logicalid(parent) == 0)
2205 mss->bd_id = MD_GUSMAX;
2206 else {
2207 mss->bd_id = MD_GUSPNP;
2208 mss->drq2_rid = 0;
2209 goto skip_setup;
2210 }
2211
2212 flags = device_get_flags(parent);
2213 if (flags & DV_F_DUAL_DMA)
2214 mss->drq2_rid = 0;
2215
2216 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2217 0, ~0, 8, RF_ACTIVE);
2218
2219 if (mss->conf_base == NULL) {
2220 mss_release_resources(mss, dev);
2221 return ENXIO;
2222 }
2223
2224 base = isa_get_port(parent);
2225
2226 ctl = 0x40; /* CS4231 enable */
2227 if (isa_get_drq(dev) > 3)
2228 ctl |= 0x10; /* 16-bit dma channel 1 */
2229 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2230 ctl |= 0x20; /* 16-bit dma channel 2 */
2231 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2232 port_wr(mss->conf_base, 6, ctl);
2233
2234skip_setup:
2235 return mss_doattach(dev, mss);
2236}
2237
2238static device_method_t guspcm_methods[] = {
2239 DEVMETHOD(device_probe, guspcm_probe),
2240 DEVMETHOD(device_attach, guspcm_attach),
2241 DEVMETHOD(device_detach, mss_detach),
2242
2243 { 0, 0 }
2244};
2245
2246static driver_t guspcm_driver = {
2247 "pcm",
2248 guspcm_methods,
2249 PCM_SOFTC_SIZE,
2250};
2251
2252DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
2253MODULE_DEPEND(snd_guspcm, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
2254MODULE_VERSION(snd_guspcm, 1);
2255
2256