Use mptable_iterate_entries() in mptable_pass1()
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
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27 */
28
29#include "opt_cpu.h"
984263bc 30
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31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
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34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
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39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
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45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
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51
52#include <machine/smp.h>
a9295349 53#include <machine_base/apic/apicreg.h>
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54#include <machine/atomic.h>
55#include <machine/cpufunc.h>
a9295349 56#include <machine_base/apic/mpapic.h>
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57#include <machine/psl.h>
58#include <machine/segments.h>
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59#include <machine/tss.h>
60#include <machine/specialreg.h>
61#include <machine/globaldata.h>
62
984263bc 63#include <machine/md_var.h> /* setidt() */
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64#include <machine_base/icu/icu.h> /* IPIs */
65#include <machine_base/isa/intr_machdep.h> /* IPIs */
984263bc 66
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67#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
68
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69#define WARMBOOT_TARGET 0
70#define WARMBOOT_OFF (KERNBASE + 0x0467)
71#define WARMBOOT_SEG (KERNBASE + 0x0469)
72
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73#define BIOS_BASE (0xf0000)
74#define BIOS_SIZE (0x10000)
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75#define BIOS_COUNT (BIOS_SIZE/4)
76
77#define CMOS_REG (0x70)
78#define CMOS_DATA (0x71)
79#define BIOS_RESET (0x0f)
80#define BIOS_WARM (0x0a)
81
82#define PROCENTRY_FLAG_EN 0x01
83#define PROCENTRY_FLAG_BP 0x02
84#define IOAPICENTRY_FLAG_EN 0x01
85
86
87/* MP Floating Pointer Structure */
88typedef struct MPFPS {
89 char signature[4];
981bebd1 90 u_int32_t pap;
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91 u_char length;
92 u_char spec_rev;
93 u_char checksum;
94 u_char mpfb1;
95 u_char mpfb2;
96 u_char mpfb3;
97 u_char mpfb4;
98 u_char mpfb5;
99} *mpfps_t;
100
101/* MP Configuration Table Header */
102typedef struct MPCTH {
103 char signature[4];
104 u_short base_table_length;
105 u_char spec_rev;
106 u_char checksum;
107 u_char oem_id[8];
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
111 u_short entry_count;
112 void *apic_address;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
115 u_char reserved;
116} *mpcth_t;
117
118
119typedef struct PROCENTRY {
120 u_char type;
121 u_char apic_id;
122 u_char apic_version;
123 u_char cpu_flags;
124 u_long cpu_signature;
125 u_long feature_flags;
126 u_long reserved1;
127 u_long reserved2;
128} *proc_entry_ptr;
129
130typedef struct BUSENTRY {
131 u_char type;
132 u_char bus_id;
133 char bus_type[6];
134} *bus_entry_ptr;
135
136typedef struct IOAPICENTRY {
137 u_char type;
138 u_char apic_id;
139 u_char apic_version;
140 u_char apic_flags;
141 void *apic_address;
142} *io_apic_entry_ptr;
143
144typedef struct INTENTRY {
145 u_char type;
146 u_char int_type;
147 u_short int_flags;
148 u_char src_bus_id;
149 u_char src_bus_irq;
150 u_char dst_apic_id;
151 u_char dst_apic_int;
152} *int_entry_ptr;
153
154/* descriptions of MP basetable entries */
155typedef struct BASETABLE_ENTRY {
156 u_char type;
157 u_char length;
158 char name[16];
159} basetable_entry;
160
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161struct mptable_pos {
162 mpfps_t mp_fps;
163 mpcth_t mp_cth;
164 vm_size_t mp_cth_mapsz;
165};
166
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167typedef int (*mptable_iter_func)(void *, const void *, int);
168
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169/*
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
173 *
984263bc 174 */
7d34994c 175#if defined(CHECK_POINTS)
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176#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
178
179#define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
186
187#define CHECK_PRINT(S); \
26be20a0 188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
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189 (S), \
190 CHECK_READ(0x34), \
191 CHECK_READ(0x35), \
192 CHECK_READ(0x36), \
193 CHECK_READ(0x37), \
194 CHECK_READ(0x38), \
195 CHECK_READ(0x39));
196
197#else /* CHECK_POINTS */
198
199#define CHECK_INIT(D)
200#define CHECK_PRINT(S)
201
202#endif /* CHECK_POINTS */
203
204/*
205 * Values to send to the POST hardware.
206 */
207#define MP_BOOTADDRESS_POST 0x10
208#define MP_PROBE_POST 0x11
209#define MPTABLE_PASS1_POST 0x12
210
211#define MP_START_POST 0x13
212#define MP_ENABLE_POST 0x14
213#define MPTABLE_PASS2_POST 0x15
214
215#define START_ALL_APS_POST 0x16
216#define INSTALL_AP_TRAMP_POST 0x17
217#define START_AP_POST 0x18
218
219#define MP_ANNOUNCE_POST 0x19
220
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221static int madt_probe_test;
222TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
223
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224/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225int current_postcode;
226
227/** XXX FIXME: what system files declare these??? */
228extern struct region_descriptor r_gdt, r_idt;
229
984263bc 230int mp_naps; /* # of Applications processors */
97359a5b 231#ifdef APIC_IO
4f6a8b30 232static int mp_nbusses; /* # of busses */
984263bc 233int mp_napics; /* # of IO APICs */
97359a5b 234#endif
5a16ccc3 235static vm_offset_t cpu_apic_address;
97359a5b 236#ifdef APIC_IO
984263bc 237vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
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238u_int32_t *io_apic_versions;
239#endif
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240extern int nkpt;
241
242u_int32_t cpu_apic_versions[MAXCPU];
374133e3 243int64_t tsc0_offset;
0b698dca 244extern int64_t tsc_offsets[];
984263bc 245
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246extern u_long ebda_addr;
247
97359a5b 248#ifdef APIC_IO
8a8d5d85 249struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 250#endif
984263bc 251
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252/*
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
255 */
256int cpu_num_to_apic_id[NAPICID];
97359a5b 257#ifdef APIC_IO
984263bc 258int io_num_to_apic_id[NAPICID];
97359a5b 259#endif
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260int apic_id_to_logical[NAPICID];
261
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262/* AP uses this during bootstrap. Do not staticize. */
263char *bootSTK;
264static int bootAP;
265
266/* Hotwire a 0->4MB V==P mapping */
267extern pt_entry_t *KPTphys;
268
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269/*
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
272 * and so forth.
273 */
274
275#define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277
984263bc 278extern pt_entry_t *SMPpt;
f13b5eec 279static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
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280
281struct pcb stoppcbs[MAXCPU];
282
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283static basetable_entry basetable_entry_types[] =
284{
285 {0, 20, "Processor"},
286 {1, 8, "Bus"},
287 {2, 8, "I/O APIC"},
288 {3, 8, "I/O INT"},
289 {4, 8, "Local INT"}
290};
291
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292/*
293 * Local data and functions.
294 */
295
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296static u_int boot_address;
297static u_int base_memory;
41a01a4d 298static int mp_finish;
984263bc 299
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300static void mp_enable(u_int boot_addr);
301
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302static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
cb00b5c4 304static int mptable_probe(void);
fa058384 305static int mptable_check(vm_paddr_t);
3aba8f73 306static int mptable_search_sig(u_int32_t target, int count);
44c36320 307static int mptable_hyperthread_fixup(u_int, int);
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308static void mptable_pass1(struct mptable_pos *);
309static int mptable_pass2(struct mptable_pos *);
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310static void mptable_default(int type);
311static void mptable_fix(void);
fa058384 312static int mptable_map(struct mptable_pos *, vm_paddr_t);
981bebd1 313static void mptable_unmap(struct mptable_pos *);
a0873f07 314static void mptable_lapic_enumerate(struct mptable_pos *);
322abba7 315static void mptable_lapic_default(void);
3aba8f73 316
97359a5b 317#ifdef APIC_IO
984263bc 318static void setup_apic_irq_mapping(void);
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319static int apic_int_is_bus_type(int intr, int bus_type);
320#endif
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321static int start_all_aps(u_int boot_addr);
322static void install_ap_tramp(u_int boot_addr);
0f7a3396 323static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
5a16ccc3 324static void lapic_init(vm_offset_t);
984263bc 325
41a01a4d 326static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
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327cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
328SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
329
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330/*
331 * Calculate usable address in base memory for AP trampoline code.
332 */
333u_int
334mp_bootaddress(u_int basemem)
335{
336 POSTCODE(MP_BOOTADDRESS_POST);
337
c0c5de70 338 base_memory = basemem;
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339
340 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
341 if ((base_memory - boot_address) < bootMP_size)
342 boot_address -= 4096; /* not enough, lower by 4k */
343
344 return boot_address;
345}
346
347
348/*
349 * Look for an Intel MP spec table (ie, SMP capable hardware).
350 */
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351static int
352mptable_probe(void)
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353{
354 int x;
984263bc 355 u_int32_t target;
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356
357 /*
358 * Make sure our SMPpt[] page table is big enough to hold all the
359 * mappings we need.
360 */
361 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
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362
363 POSTCODE(MP_PROBE_POST);
364
365 /* see if EBDA exists */
1876681a 366 if (ebda_addr != 0) {
984263bc 367 /* search first 1K of EBDA */
1876681a 368 target = (u_int32_t)ebda_addr;
3aba8f73 369 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 370 return x;
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371 } else {
372 /* last 1K of base memory, effective 'top of base' passed in */
aeb48299 373 target = (u_int32_t)(base_memory - 0x400);
3aba8f73 374 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 375 return x;
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376 }
377
378 /* search the BIOS */
aeb48299 379 target = (u_int32_t)BIOS_BASE;
3aba8f73 380 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
aeb48299 381 return x;
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382
383 /* nothing found */
984263bc 384 return 0;
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385}
386
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387struct mptable_check_cbarg {
388 int cpu_count;
389 int found_bsp;
390};
391
392static int
393mptable_check_callback(void *xarg, const void *pos, int type)
394{
395 const struct PROCENTRY *ent;
396 struct mptable_check_cbarg *arg = xarg;
397
398 if (type != 0)
399 return 0;
400 ent = pos;
401
402 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
403 return 0;
404 arg->cpu_count++;
405
406 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
407 if (arg->found_bsp) {
408 kprintf("more than one BSP in base MP table\n");
409 return EINVAL;
410 }
411 arg->found_bsp = 1;
412 }
413 return 0;
414}
415
416static int
417mptable_check(vm_paddr_t mpfps_paddr)
418{
419 struct mptable_pos mpt;
420 struct mptable_check_cbarg arg;
421 mpcth_t cth;
422 int error;
423
424 if (mpfps_paddr == 0)
425 return EOPNOTSUPP;
426
427 error = mptable_map(&mpt, mpfps_paddr);
428 if (error)
429 return error;
430
431 if (mpt.mp_fps->mpfb1 != 0)
432 goto done;
433
434 error = EINVAL;
435
436 cth = mpt.mp_cth;
437 if (cth == NULL)
438 goto done;
439 if (cth->apic_address == 0)
440 goto done;
441
442 bzero(&arg, sizeof(arg));
443 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
444 if (!error) {
445 if (arg.cpu_count == 0) {
446 kprintf("MP table contains no processor entries\n");
447 error = EINVAL;
448 } else if (!arg.found_bsp) {
449 kprintf("MP table does not contains BSP entry\n");
450 error = EINVAL;
451 }
452 }
453done:
454 mptable_unmap(&mpt);
455 return error;
456}
457
458static int
459mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
460{
461 int count, total_size;
462 const void *position;
463
464 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
465 total_size = cth->base_table_length - sizeof(struct MPCTH);
466 position = (const uint8_t *)cth + sizeof(struct MPCTH);
467 count = cth->entry_count;
468
469 while (count--) {
470 int type, error;
471
472 KKASSERT(total_size >= 0);
473 if (total_size == 0) {
474 kprintf("invalid base MP table, "
475 "entry count and length mismatch\n");
476 return EINVAL;
477 }
478
479 type = *(const uint8_t *)position;
480 switch (type) {
481 case 0: /* processor_entry */
482 case 1: /* bus_entry */
483 case 2: /* io_apic_entry */
484 case 3: /* int_entry */
485 case 4: /* int_entry */
486 break;
487 default:
488 kprintf("unknown base MP table entry type %d\n", type);
489 return EINVAL;
490 }
491
492 if (total_size < basetable_entry_types[type].length) {
493 kprintf("invalid base MP table length, "
494 "does not contain all entries\n");
495 return EINVAL;
496 }
497 total_size -= basetable_entry_types[type].length;
498
499 error = func(arg, position, type);
500 if (error)
501 return error;
502
503 position = (const uint8_t *)position +
504 basetable_entry_types[type].length;
505 }
506 return 0;
507}
508
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509
510/*
511 * Startup the SMP processors.
512 */
513void
514mp_start(void)
515{
516 POSTCODE(MP_START_POST);
50bc991e 517 mp_enable(boot_address);
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518}
519
520
521/*
522 * Print various information about the SMP system hardware and setup.
523 */
524void
525mp_announce(void)
526{
527 int x;
528
529 POSTCODE(MP_ANNOUNCE_POST);
530
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531 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
532 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
533 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
534 kprintf(", at 0x%08x\n", cpu_apic_address);
984263bc 535 for (x = 1; x <= mp_naps; ++x) {
26be20a0
SW
536 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
537 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
538 kprintf(", at 0x%08x\n", cpu_apic_address);
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539 }
540
541#if defined(APIC_IO)
542 for (x = 0; x < mp_napics; ++x) {
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SW
543 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
544 kprintf(", version: 0x%08x", io_apic_versions[x]);
545 kprintf(", at 0x%08x\n", io_apic_address[x]);
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546 }
547#else
26be20a0 548 kprintf(" Warning: APIC I/O disabled\n");
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549#endif /* APIC_IO */
550}
551
552/*
553 * AP cpu's call this to sync up protected mode.
7160572f
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554 *
555 * WARNING! We must ensure that the cpu is sufficiently initialized to
556 * be able to use to the FP for our optimized bzero/bcopy code before
557 * we enter more mainstream C code.
a44bdeec
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558 *
559 * WARNING! %fs is not set up on entry. This routine sets up %fs.
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560 */
561void
562init_secondary(void)
563{
564 int gsel_tss;
565 int x, myid = bootAP;
566 u_int cr0;
8a8d5d85 567 struct mdglobaldata *md;
0f7a3396 568 struct privatespace *ps;
984263bc 569
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MD
570 ps = &CPU_prvspace[myid];
571
572 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 573 gdt_segs[GPROC0_SEL].ssd_base =
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574 (int) &ps->mdglobaldata.gd_common_tss;
575 ps->mdglobaldata.mi.gd_prvspace = ps;
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576
577 for (x = 0; x < NGDT; x++) {
578 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
579 }
580
581 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
582 r_gdt.rd_base = (int) &gdt[myid * NGDT];
583 lgdt(&r_gdt); /* does magic intra-segment return */
584
585 lidt(&r_idt);
586
587 lldt(_default_ldt);
7b95be2a 588 mdcpu->gd_currentldt = _default_ldt;
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589
590 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
591 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 592
0f7a3396 593 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
8a8d5d85
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594
595 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
596 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
597 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
598 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
599 md->gd_common_tssd = *md->gd_tss_gdt;
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600 ltr(gsel_tss);
601
602 /*
603 * Set to a known state:
604 * Set by mpboot.s: CR0_PG, CR0_PE
605 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
606 */
607 cr0 = rcr0();
608 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
609 load_cr0(cr0);
7160572f 610 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 611
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612 /* set up CPU registers and state */
613 cpu_setregs();
614
615 /* set up FPU state on the AP */
616 npxinit(__INITIAL_NPXCW__);
617
618 /* set up SSE registers */
619 enable_sse();
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620}
621
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622/*******************************************************************
623 * local functions and data
624 */
625
626/*
627 * start the SMP system
628 */
629static void
630mp_enable(u_int boot_addr)
631{
632 int x;
633#if defined(APIC_IO)
634 int apic;
635 u_int ux;
636#endif /* APIC_IO */
981bebd1 637 vm_paddr_t mpfps_paddr;
984263bc
MD
638
639 POSTCODE(MP_ENABLE_POST);
640
fa058384 641 if (madt_probe_test) {
a26bbcd5 642 mpfps_paddr = 0;
fa058384 643 } else {
a26bbcd5 644 mpfps_paddr = mptable_probe();
fa058384
SZ
645 if (mptable_check(mpfps_paddr))
646 mpfps_paddr = 0;
647 }
85fd9f87 648
a26bbcd5 649 if (mpfps_paddr) {
223bf214
SZ
650 struct mptable_pos mpt;
651
a26bbcd5 652 mptable_map(&mpt, mpfps_paddr);
0f85efa2 653
a0873f07
SZ
654 mptable_lapic_enumerate(&mpt);
655
a26bbcd5
SZ
656 /*
657 * We can safely map physical memory into SMPpt after
658 * mptable_pass1() completes.
659 */
660 mptable_pass1(&mpt);
984263bc 661
a26bbcd5
SZ
662 /*
663 * Examine the MP table for needed info
664 */
665 x = mptable_pass2(&mpt);
f9c3b04f 666
a26bbcd5 667 mptable_unmap(&mpt);
984263bc 668
a26bbcd5
SZ
669 /*
670 * Can't process default configs till the
671 * CPU APIC is pmapped
672 */
673 if (x)
674 mptable_default(x);
f9c3b04f 675
a26bbcd5
SZ
676 /* Post scan cleanup */
677 mptable_fix();
678 } else {
223bf214 679 vm_paddr_t madt_paddr;
5a16ccc3 680 vm_offset_t lapic_addr;
223bf214
SZ
681 int bsp_apic_id;
682
683 madt_paddr = madt_probe();
684 if (madt_paddr == 0)
a26bbcd5
SZ
685 panic("mp_enable: madt_probe failed\n");
686
5a16ccc3
SZ
687 lapic_addr = madt_pass1(madt_paddr);
688 if (lapic_addr == 0)
a26bbcd5 689 panic("mp_enable: no local apic (madt)!\n");
984263bc 690
5a16ccc3 691 lapic_init(lapic_addr);
223bf214 692
bc021528 693 bsp_apic_id = APIC_ID(lapic.id);
223bf214
SZ
694 if (madt_pass2(madt_paddr, bsp_apic_id))
695 panic("mp_enable: madt_pass2 failed\n");
a26bbcd5 696 }
984263bc
MD
697
698#if defined(APIC_IO)
699
97359a5b
MD
700 setup_apic_irq_mapping();
701
984263bc
MD
702 /* fill the LOGICAL io_apic_versions table */
703 for (apic = 0; apic < mp_napics; ++apic) {
704 ux = io_apic_read(apic, IOAPIC_VER);
705 io_apic_versions[apic] = ux;
706 io_apic_set_id(apic, IO_TO_ID(apic));
707 }
708
709 /* program each IO APIC in the system */
710 for (apic = 0; apic < mp_napics; ++apic)
711 if (io_apic_setup(apic) < 0)
712 panic("IO APIC setup failure");
713
97359a5b
MD
714#endif /* APIC_IO */
715
716 /*
717 * These are required for SMP operation
718 */
719
984263bc
MD
720 /* install a 'Spurious INTerrupt' vector */
721 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
722 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
723
724 /* install an inter-CPU IPI for TLB invalidation */
725 setidt(XINVLTLB_OFFSET, Xinvltlb,
726 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
727
96728c05
MD
728 /* install an inter-CPU IPI for IPIQ messaging */
729 setidt(XIPIQ_OFFSET, Xipiq,
730 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
78ea5a2a
SZ
731
732 /* install a timer vector */
733 setidt(XTIMER_OFFSET, Xtimer,
734 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc 735
984263bc
MD
736 /* install an inter-CPU IPI for CPU stop/restart */
737 setidt(XCPUSTOP_OFFSET, Xcpustop,
738 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
739
984263bc
MD
740 /* start each Application Processor */
741 start_all_aps(boot_addr);
742}
743
744
745/*
746 * look for the MP spec signature
747 */
748
749/* string defined by the Intel MP Spec as identifying the MP table */
750#define MP_SIG 0x5f504d5f /* _MP_ */
751#define NEXT(X) ((X) += 4)
752static int
3aba8f73 753mptable_search_sig(u_int32_t target, int count)
984263bc 754{
0f85efa2
SZ
755 vm_size_t map_size;
756 u_int32_t *addr;
757 int x, ret;
984263bc 758
aeb48299
SZ
759 KKASSERT(target != 0);
760
0f85efa2
SZ
761 map_size = count * sizeof(u_int32_t);
762 addr = pmap_mapdev((vm_paddr_t)target, map_size);
984263bc 763
aeb48299 764 ret = 0;
0f85efa2
SZ
765 for (x = 0; x < count; NEXT(x)) {
766 if (addr[x] == MP_SIG) {
767 /* make array index a byte index */
768 ret = target + (x * sizeof(u_int32_t));
769 break;
770 }
771 }
aeb48299 772
0f85efa2
SZ
773 pmap_unmapdev((vm_offset_t)addr, map_size);
774 return ret;
984263bc
MD
775}
776
777
984263bc
MD
778typedef struct BUSDATA {
779 u_char bus_id;
780 enum busTypes bus_type;
781} bus_datum;
782
783typedef struct INTDATA {
784 u_char int_type;
785 u_short int_flags;
786 u_char src_bus_id;
787 u_char src_bus_irq;
788 u_char dst_apic_id;
789 u_char dst_apic_int;
790 u_char int_vector;
791} io_int, local_int;
792
793typedef struct BUSTYPENAME {
794 u_char type;
795 char name[7];
796} bus_type_name;
797
798static bus_type_name bus_type_table[] =
799{
800 {CBUS, "CBUS"},
801 {CBUSII, "CBUSII"},
802 {EISA, "EISA"},
803 {MCA, "MCA"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {ISA, "ISA"},
806 {MCA, "MCA"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
812 {PCI, "PCI"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {XPRESS, "XPRESS"},
818 {UNKNOWN_BUSTYPE, "---"}
819};
820/* from MP spec v1.4, table 5-1 */
821static int default_data[7][5] =
822{
823/* nbus, id0, type0, id1, type1 */
824 {1, 0, ISA, 255, 255},
825 {1, 0, EISA, 255, 255},
826 {1, 0, EISA, 255, 255},
827 {1, 0, MCA, 255, 255},
828 {2, 0, ISA, 1, PCI},
829 {2, 0, EISA, 1, PCI},
830 {2, 0, MCA, 1, PCI}
831};
832
833
4f6a8b30
SZ
834#ifdef APIC_IO
835
984263bc
MD
836/* the bus data */
837static bus_datum *bus_data;
838
839/* the IO INT data, one entry per possible APIC INTerrupt */
840static io_int *io_apic_ints;
984263bc 841static int nintrs;
4f6a8b30 842
97359a5b 843#endif
984263bc 844
a0873f07 845static int processor_entry (const struct PROCENTRY *entry, int cpu);
97359a5b 846#ifdef APIC_IO
4f6a8b30 847static int bus_entry (bus_entry_ptr entry, int bus);
3ae0cd58
RG
848static int io_apic_entry (io_apic_entry_ptr entry, int apic);
849static int int_entry (int_entry_ptr entry, int intr);
97359a5b 850#endif
3ae0cd58 851static int lookup_bus_type (char *name);
984263bc 852
8658b5be
SZ
853#ifdef APIC_IO
854
855static int
856mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
857{
858 const struct IOAPICENTRY *ioapic_ent;
859
860 switch (type) {
861 case 1: /* bus_entry */
862 ++mp_nbusses;
863 break;
864
865 case 2: /* io_apic_entry */
866 ioapic_ent = pos;
867 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
868 io_apic_address[mp_napics++] =
869 (vm_offset_t)ioapic_ent->apic_address;
870 }
871 break;
872
873 case 3: /* int_entry */
874 ++nintrs;
875 break;
876 }
877 return 0;
878}
879
880#endif /* APIC_IO */
984263bc
MD
881
882/*
883 * 1st pass on motherboard's Intel MP specification table.
884 *
984263bc 885 * determines:
984263bc 886 * io_apic_address[N]
984263bc
MD
887 * mp_nbusses
888 * mp_napics
889 * nintrs
890 */
891static void
981bebd1 892mptable_pass1(struct mptable_pos *mpt)
984263bc 893{
97359a5b 894#ifdef APIC_IO
981bebd1 895 mpfps_t fps;
8658b5be 896 int x;
984263bc
MD
897
898 POSTCODE(MPTABLE_PASS1_POST);
899
981bebd1
SZ
900 fps = mpt->mp_fps;
901 KKASSERT(fps != NULL);
f9c3b04f 902
984263bc 903 /* clear various tables */
8658b5be 904 for (x = 0; x < NAPICID; ++x)
984263bc 905 io_apic_address[x] = ~0; /* IO APIC address table */
984263bc 906
4f6a8b30 907 mp_nbusses = 0;
984263bc
MD
908 mp_napics = 0;
909 nintrs = 0;
984263bc
MD
910
911 /* check for use of 'default' configuration */
981bebd1 912 if (fps->mpfb1 != 0) {
984263bc 913 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
4f6a8b30 914 mp_nbusses = default_data[fps->mpfb1 - 1][0];
984263bc
MD
915 mp_napics = 1;
916 nintrs = 16;
8658b5be
SZ
917 } else {
918 int error;
919
920 error = mptable_iterate_entries(mpt->mp_cth,
921 mptable_ioapic_pass1_callback, NULL);
922 if (error)
923 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
984263bc 924 }
8658b5be 925#endif /* APIC_IO */
984263bc
MD
926}
927
928
929/*
930 * 2nd pass on motherboard's Intel MP specification table.
931 *
932 * sets:
984263bc 933 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
984263bc
MD
934 * IO_TO_ID(N), logical IO to APIC ID table
935 * bus_data[N]
936 * io_apic_ints[N]
937 */
938static int
981bebd1 939mptable_pass2(struct mptable_pos *mpt)
984263bc 940{
984263bc 941 int x;
981bebd1 942 mpfps_t fps;
984263bc
MD
943 mpcth_t cth;
944 int totalSize;
945 void* position;
946 int count;
947 int type;
a0873f07 948 int apic, bus, intr;
f13b5eec 949 int i;
984263bc
MD
950
951 POSTCODE(MPTABLE_PASS2_POST);
952
981bebd1
SZ
953 fps = mpt->mp_fps;
954 KKASSERT(fps != NULL);
955
97359a5b 956#ifdef APIC_IO
984263bc
MD
957 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
958 M_DEVBUF, M_WAITOK);
959 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
e7b4468c 960 M_DEVBUF, M_WAITOK | M_ZERO);
1439c090 961 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984263bc
MD
962 M_DEVBUF, M_WAITOK);
963 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
964 M_DEVBUF, M_WAITOK);
4f6a8b30 965#endif
984263bc 966
97359a5b 967#ifdef APIC_IO
984263bc 968 for (i = 0; i < mp_napics; i++) {
f13b5eec 969 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
984263bc 970 }
97359a5b 971#endif
984263bc
MD
972
973 /* clear various tables */
974 for (x = 0; x < NAPICID; ++x) {
97359a5b
MD
975#ifdef APIC_IO
976 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
984263bc 977 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
97359a5b 978#endif
984263bc
MD
979 }
980
4f6a8b30 981#ifdef APIC_IO
984263bc
MD
982 /* clear bus data table */
983 for (x = 0; x < mp_nbusses; ++x)
984 bus_data[x].bus_id = 0xff;
985
986 /* clear IO APIC INT table */
987 for (x = 0; x < (nintrs + 1); ++x) {
988 io_apic_ints[x].int_type = 0xff;
989 io_apic_ints[x].int_vector = 0xff;
990 }
97359a5b 991#endif
984263bc 992
984263bc 993 /* record whether PIC or virtual-wire mode */
981bebd1 994 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
984263bc
MD
995
996 /* check for use of 'default' configuration */
981bebd1
SZ
997 if (fps->mpfb1 != 0)
998 return fps->mpfb1; /* return default configuration type */
984263bc 999
981bebd1 1000 cth = mpt->mp_cth;
a0873f07 1001 KKASSERT(cth != NULL);
984263bc
MD
1002
1003 /* walk the table, recording info of interest */
1004 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1005 position = (u_char *) cth + sizeof(struct MPCTH);
1006 count = cth->entry_count;
1007 apic = bus = intr = 0;
984263bc
MD
1008
1009 while (count--) {
1010 switch (type = *(u_char *) position) {
1011 case 0:
984263bc
MD
1012 break;
1013 case 1:
4f6a8b30 1014#ifdef APIC_IO
984263bc
MD
1015 if (bus_entry(position, bus))
1016 ++bus;
4f6a8b30 1017#endif
984263bc
MD
1018 break;
1019 case 2:
97359a5b 1020#ifdef APIC_IO
984263bc
MD
1021 if (io_apic_entry(position, apic))
1022 ++apic;
97359a5b 1023#endif
984263bc
MD
1024 break;
1025 case 3:
97359a5b 1026#ifdef APIC_IO
984263bc
MD
1027 if (int_entry(position, intr))
1028 ++intr;
97359a5b 1029#endif
984263bc
MD
1030 break;
1031 case 4:
1032 /* int_entry(position); */
1033 break;
1034 default:
1035 panic("mpfps Base Table HOSED!");
1036 /* NOTREACHED */
1037 }
1038
1039 totalSize -= basetable_entry_types[type].length;
7a9b7292 1040 position = (uint8_t *)position + basetable_entry_types[type].length;
984263bc
MD
1041 }
1042
984263bc
MD
1043 /* report fact that its NOT a default configuration */
1044 return 0;
1045}
1046
984263bc
MD
1047/*
1048 * Check if we should perform a hyperthreading "fix-up" to
1049 * enumerate any logical CPU's that aren't already listed
1050 * in the table.
1051 *
1052 * XXX: We assume that all of the physical CPUs in the
1053 * system have the same number of logical CPUs.
1054 *
1055 * XXX: We assume that APIC ID's are allocated such that
1056 * the APIC ID's for a physical processor are aligned
1057 * with the number of logical CPU's in the processor.
1058 */
44c36320
SZ
1059static int
1060mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
984263bc 1061{
44c36320 1062 int i, id, lcpus_max, logical_cpus;
984263bc 1063
984263bc 1064 if ((cpu_feature & CPUID_HTT) == 0)
44c36320 1065 return 0;
7ea07fd2
SZ
1066
1067 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1068 if (lcpus_max <= 1)
44c36320 1069 return 0;
984263bc 1070
7ea07fd2
SZ
1071 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1072 /*
1073 * INSTRUCTION SET REFERENCE, A-M (#253666)
1074 * Page 3-181, Table 3-20
1075 * "The nearest power-of-2 integer that is not smaller
1076 * than EBX[23:16] is the number of unique initial APIC
1077 * IDs reserved for addressing different logical
1078 * processors in a physical package."
1079 */
1080 for (i = 0; ; ++i) {
1081 if ((1 << i) >= lcpus_max) {
1082 lcpus_max = 1 << i;
1083 break;
1084 }
1085 }
1086 }
1087
44c36320
SZ
1088 KKASSERT(cpu_count != 0);
1089 if (cpu_count == lcpus_max) {
7ea07fd2 1090 /* We have nothing to fix */
44c36320
SZ
1091 return 0;
1092 } else if (cpu_count == 1) {
7ea07fd2
SZ
1093 /* XXX this may be incorrect */
1094 logical_cpus = lcpus_max;
1095 } else {
1096 int cur, prev, dist;
1097
1098 /*
1099 * Calculate the distances between two nearest
1100 * APIC IDs. If all such distances are same,
1101 * then it is the number of missing cpus that
1102 * we are going to fill later.
1103 */
1104 dist = cur = prev = -1;
1105 for (id = 0; id < MAXCPU; ++id) {
1106 if ((id_mask & 1 << id) == 0)
1107 continue;
1108
1109 cur = id;
1110 if (prev >= 0) {
1111 int new_dist = cur - prev;
1112
1113 if (dist < 0)
1114 dist = new_dist;
1115
1116 /*
1117 * Make sure that all distances
1118 * between two nearest APIC IDs
1119 * are same.
1120 */
1121 if (dist != new_dist)
44c36320 1122 return 0;
7ea07fd2
SZ
1123 }
1124 prev = cur;
1125 }
1126 if (dist == 1)
44c36320 1127 return 0;
7ea07fd2
SZ
1128
1129 /* Must be power of 2 */
1130 if (dist & (dist - 1))
44c36320 1131 return 0;
7ea07fd2
SZ
1132
1133 /* Can't exceed CPU package capacity */
1134 if (dist > lcpus_max)
1135 logical_cpus = lcpus_max;
1136 else
1137 logical_cpus = dist;
1138 }
1139
984263bc
MD
1140 /*
1141 * For each APIC ID of a CPU that is set in the mask,
1142 * scan the other candidate APIC ID's for this
1143 * physical processor. If any of those ID's are
1144 * already in the table, then kill the fixup.
1145 */
7ea07fd2 1146 for (id = 0; id < MAXCPU; id++) {
984263bc
MD
1147 if ((id_mask & 1 << id) == 0)
1148 continue;
1149 /* First, make sure we are on a logical_cpus boundary. */
1150 if (id % logical_cpus != 0)
44c36320 1151 return 0;
984263bc
MD
1152 for (i = id + 1; i < id + logical_cpus; i++)
1153 if ((id_mask & 1 << i) != 0)
44c36320 1154 return 0;
984263bc 1155 }
44c36320 1156 return logical_cpus;
984263bc 1157}
984263bc 1158
fa058384 1159static int
981bebd1
SZ
1160mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1161{
1162 mpfps_t fps = NULL;
1163 mpcth_t cth = NULL;
1164 vm_size_t cth_mapsz = 0;
1165
fa058384
SZ
1166 bzero(mpt, sizeof(*mpt));
1167
981bebd1
SZ
1168 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1169 if (fps->pap != 0) {
1170 /*
1171 * Map configuration table header to get
1172 * the base table size
1173 */
1174 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1175 cth_mapsz = cth->base_table_length;
1176 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1177
fa058384
SZ
1178 if (cth_mapsz < sizeof(*cth)) {
1179 kprintf("invalid base MP table length %d\n",
1180 (int)cth_mapsz);
1181 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1182 return EINVAL;
1183 }
1184
981bebd1
SZ
1185 /*
1186 * Map the base table
1187 */
1188 cth = pmap_mapdev(fps->pap, cth_mapsz);
1189 }
1190
1191 mpt->mp_fps = fps;
1192 mpt->mp_cth = cth;
1193 mpt->mp_cth_mapsz = cth_mapsz;
fa058384
SZ
1194
1195 return 0;
981bebd1
SZ
1196}
1197
1198static void
1199mptable_unmap(struct mptable_pos *mpt)
1200{
1201 if (mpt->mp_cth != NULL) {
1202 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1203 mpt->mp_cth = NULL;
1204 mpt->mp_cth_mapsz = 0;
1205 }
1206 if (mpt->mp_fps != NULL) {
1207 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1208 mpt->mp_fps = NULL;
1209 }
1210}
1211
97359a5b
MD
1212#ifdef APIC_IO
1213
984263bc
MD
1214void
1215assign_apic_irq(int apic, int intpin, int irq)
1216{
1217 int x;
1218
1219 if (int_to_apicintpin[irq].ioapic != -1)
1220 panic("assign_apic_irq: inconsistent table");
1221
1222 int_to_apicintpin[irq].ioapic = apic;
1223 int_to_apicintpin[irq].int_pin = intpin;
1224 int_to_apicintpin[irq].apic_address = ioapic[apic];
1225 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1226
1227 for (x = 0; x < nintrs; x++) {
1228 if ((io_apic_ints[x].int_type == 0 ||
1229 io_apic_ints[x].int_type == 3) &&
1230 io_apic_ints[x].int_vector == 0xff &&
1231 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1232 io_apic_ints[x].dst_apic_int == intpin)
1233 io_apic_ints[x].int_vector = irq;
1234 }
1235}
1236
1237void
1238revoke_apic_irq(int irq)
1239{
1240 int x;
1241 int oldapic;
1242 int oldintpin;
1243
1244 if (int_to_apicintpin[irq].ioapic == -1)
1245 panic("revoke_apic_irq: inconsistent table");
1246
1247 oldapic = int_to_apicintpin[irq].ioapic;
1248 oldintpin = int_to_apicintpin[irq].int_pin;
1249
1250 int_to_apicintpin[irq].ioapic = -1;
1251 int_to_apicintpin[irq].int_pin = 0;
1252 int_to_apicintpin[irq].apic_address = NULL;
1253 int_to_apicintpin[irq].redirindex = 0;
1254
1255 for (x = 0; x < nintrs; x++) {
1256 if ((io_apic_ints[x].int_type == 0 ||
1257 io_apic_ints[x].int_type == 3) &&
1258 io_apic_ints[x].int_vector != 0xff &&
1259 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1260 io_apic_ints[x].dst_apic_int == oldintpin)
1261 io_apic_ints[x].int_vector = 0xff;
1262 }
1263}
1264
1439c090
MD
1265/*
1266 * Allocate an IRQ
1267 */
984263bc
MD
1268static void
1269allocate_apic_irq(int intr)
1270{
1271 int apic;
1272 int intpin;
1273 int irq;
1274
1275 if (io_apic_ints[intr].int_vector != 0xff)
1276 return; /* Interrupt handler already assigned */
1277
1278 if (io_apic_ints[intr].int_type != 0 &&
1279 (io_apic_ints[intr].int_type != 3 ||
1280 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1281 io_apic_ints[intr].dst_apic_int == 0)))
1282 return; /* Not INT or ExtInt on != (0, 0) */
1283
1284 irq = 0;
1285 while (irq < APIC_INTMAPSIZE &&
1286 int_to_apicintpin[irq].ioapic != -1)
1287 irq++;
1288
1289 if (irq >= APIC_INTMAPSIZE)
1290 return; /* No free interrupt handlers */
1291
1292 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1293 intpin = io_apic_ints[intr].dst_apic_int;
1294
1295 assign_apic_irq(apic, intpin, irq);
1296 io_apic_setup_intpin(apic, intpin);
1297}
1298
1299
1300static void
1301swap_apic_id(int apic, int oldid, int newid)
1302{
1303 int x;
1304 int oapic;
1305
1306
1307 if (oldid == newid)
1308 return; /* Nothing to do */
1309
26be20a0 1310 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
984263bc
MD
1311 apic, oldid, newid);
1312
1313 /* Swap physical APIC IDs in interrupt entries */
1314 for (x = 0; x < nintrs; x++) {
1315 if (io_apic_ints[x].dst_apic_id == oldid)
1316 io_apic_ints[x].dst_apic_id = newid;
1317 else if (io_apic_ints[x].dst_apic_id == newid)
1318 io_apic_ints[x].dst_apic_id = oldid;
1319 }
1320
1321 /* Swap physical APIC IDs in IO_TO_ID mappings */
1322 for (oapic = 0; oapic < mp_napics; oapic++)
1323 if (IO_TO_ID(oapic) == newid)
1324 break;
1325
1326 if (oapic < mp_napics) {
26be20a0 1327 kprintf("Changing APIC ID for IO APIC #%d from "
984263bc
MD
1328 "%d to %d in MP table\n",
1329 oapic, newid, oldid);
1330 IO_TO_ID(oapic) = oldid;
1331 }
1332 IO_TO_ID(apic) = newid;
1333}
1334
1335
1336static void
1337fix_id_to_io_mapping(void)
1338{
1339 int x;
1340
1341 for (x = 0; x < NAPICID; x++)
1342 ID_TO_IO(x) = -1;
1343
1344 for (x = 0; x <= mp_naps; x++)
1345 if (CPU_TO_ID(x) < NAPICID)
1346 ID_TO_IO(CPU_TO_ID(x)) = x;
1347
1348 for (x = 0; x < mp_napics; x++)
1349 if (IO_TO_ID(x) < NAPICID)
1350 ID_TO_IO(IO_TO_ID(x)) = x;
1351}
1352
1353
1354static int
1355first_free_apic_id(void)
1356{
1357 int freeid, x;
1358
1359 for (freeid = 0; freeid < NAPICID; freeid++) {
1360 for (x = 0; x <= mp_naps; x++)
1361 if (CPU_TO_ID(x) == freeid)
1362 break;
1363 if (x <= mp_naps)
1364 continue;
1365 for (x = 0; x < mp_napics; x++)
1366 if (IO_TO_ID(x) == freeid)
1367 break;
1368 if (x < mp_napics)
1369 continue;
1370 return freeid;
1371 }
1372 return freeid;
1373}
1374
1375
1376static int
1377io_apic_id_acceptable(int apic, int id)
1378{
1379 int cpu; /* Logical CPU number */
1380 int oapic; /* Logical IO APIC number for other IO APIC */
1381
1382 if (id >= NAPICID)
1383 return 0; /* Out of range */
1384
1385 for (cpu = 0; cpu <= mp_naps; cpu++)
1386 if (CPU_TO_ID(cpu) == id)
1387 return 0; /* Conflict with CPU */
1388
1389 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1390 if (IO_TO_ID(oapic) == id)
1391 return 0; /* Conflict with other APIC */
1392
1393 return 1; /* ID is acceptable for IO APIC */
1394}
1395
1439c090
MD
1396static
1397io_int *
1398io_apic_find_int_entry(int apic, int pin)
1399{
1400 int x;
1401
1402 /* search each of the possible INTerrupt sources */
1403 for (x = 0; x < nintrs; ++x) {
1404 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1405 (pin == io_apic_ints[x].dst_apic_int))
1406 return (&io_apic_ints[x]);
1407 }
1408 return NULL;
1409}
1410
97359a5b 1411#endif
984263bc
MD
1412
1413/*
1414 * parse an Intel MP specification table
1415 */
1416static void
3aba8f73 1417mptable_fix(void)
984263bc 1418{
97359a5b 1419#ifdef APIC_IO
4f6a8b30 1420 int x;
984263bc 1421 int id;
984263bc
MD
1422 int apic; /* IO APIC unit number */
1423 int freeid; /* Free physical APIC ID */
1424 int physid; /* Current physical IO APIC ID */
1439c090 1425 io_int *io14;
97359a5b
MD
1426 int bus_0 = 0; /* Stop GCC warning */
1427 int bus_pci = 0; /* Stop GCC warning */
1428 int num_pci_bus;
984263bc
MD
1429
1430 /*
1431 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1432 * did it wrong. The MP spec says that when more than 1 PCI bus
1433 * exists the BIOS must begin with bus entries for the PCI bus and use
1434 * actual PCI bus numbering. This implies that when only 1 PCI bus
1435 * exists the BIOS can choose to ignore this ordering, and indeed many
1436 * MP motherboards do ignore it. This causes a problem when the PCI
1437 * sub-system makes requests of the MP sub-system based on PCI bus
1438 * numbers. So here we look for the situation and renumber the
1439 * busses and associated INTs in an effort to "make it right".
1440 */
1441
1442 /* find bus 0, PCI bus, count the number of PCI busses */
1443 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1444 if (bus_data[x].bus_id == 0) {
1445 bus_0 = x;
1446 }
1447 if (bus_data[x].bus_type == PCI) {
1448 ++num_pci_bus;
1449 bus_pci = x;
1450 }
1451 }
1452 /*
1453 * bus_0 == slot of bus with ID of 0
1454 * bus_pci == slot of last PCI bus encountered
1455 */
1456
1457 /* check the 1 PCI bus case for sanity */
1458 /* if it is number 0 all is well */
1459 if (num_pci_bus == 1 &&
1460 bus_data[bus_pci].bus_id != 0) {
1461
1462 /* mis-numbered, swap with whichever bus uses slot 0 */
1463
1464 /* swap the bus entry types */
1465 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1466 bus_data[bus_0].bus_type = PCI;
1467
1468 /* swap each relavant INTerrupt entry */
1469 id = bus_data[bus_pci].bus_id;
1470 for (x = 0; x < nintrs; ++x) {
1471 if (io_apic_ints[x].src_bus_id == id) {
1472 io_apic_ints[x].src_bus_id = 0;
1473 }
1474 else if (io_apic_ints[x].src_bus_id == 0) {
1475 io_apic_ints[x].src_bus_id = id;
1476 }
1477 }
1478 }
1479
1480 /* Assign IO APIC IDs.
1481 *
1482 * First try the existing ID. If a conflict is detected, try
1483 * the ID in the MP table. If a conflict is still detected, find
1484 * a free id.
1485 *
1486 * We cannot use the ID_TO_IO table before all conflicts has been
1487 * resolved and the table has been corrected.
1488 */
1489 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1490
1491 /* First try to use the value set by the BIOS */
1492 physid = io_apic_get_id(apic);
1493 if (io_apic_id_acceptable(apic, physid)) {
1494 if (IO_TO_ID(apic) != physid)
1495 swap_apic_id(apic, IO_TO_ID(apic), physid);
1496 continue;
1497 }
1498
1499 /* Then check if the value in the MP table is acceptable */
1500 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1501 continue;
1502
1503 /* Last resort, find a free APIC ID and use it */
1504 freeid = first_free_apic_id();
1505 if (freeid >= NAPICID)
1506 panic("No free physical APIC IDs found");
1507
1508 if (io_apic_id_acceptable(apic, freeid)) {
1509 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1510 continue;
1511 }
1512 panic("Free physical APIC ID not usable");
1513 }
1514 fix_id_to_io_mapping();
1515
1516 /* detect and fix broken Compaq MP table */
1517 if (apic_int_type(0, 0) == -1) {
26be20a0 1518 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
984263bc
MD
1519 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1520 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1521 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1522 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1523 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1524 nintrs++;
ad12f88c 1525 } else if (apic_int_type(0, 0) == 0) {
26be20a0 1526 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
ad12f88c
HP
1527 for (x = 0; x < nintrs; ++x)
1528 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1529 (0 == io_apic_ints[x].dst_apic_int)) {
1530 io_apic_ints[x].int_type = 3;
1531 io_apic_ints[x].int_vector = 0xff;
1532 break;
1533 }
984263bc 1534 }
1439c090
MD
1535
1536 /*
1537 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1538 * controllers universally come in pairs. If IRQ 14 is specified
1539 * as an ISA interrupt, then IRQ 15 had better be too.
1540 *
1541 * [ Shuttle XPC / AMD Athlon X2 ]
1542 * The MPTable is missing an entry for IRQ 15. Note that the
1543 * ACPI table has an entry for both 14 and 15.
1544 */
1545 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
26be20a0 1546 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439c090
MD
1547 io14 = io_apic_find_int_entry(0, 14);
1548 io_apic_ints[nintrs] = *io14;
1549 io_apic_ints[nintrs].src_bus_irq = 15;
1550 io_apic_ints[nintrs].dst_apic_int = 15;
1551 nintrs++;
1552 }
97359a5b 1553#endif
984263bc
MD
1554}
1555
97359a5b 1556#ifdef APIC_IO
984263bc
MD
1557
1558/* Assign low level interrupt handlers */
1559static void
1560setup_apic_irq_mapping(void)
1561{
1562 int x;
1563 int int_vector;
1564
1565 /* Clear array */
1566 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1567 int_to_apicintpin[x].ioapic = -1;
1568 int_to_apicintpin[x].int_pin = 0;
1569 int_to_apicintpin[x].apic_address = NULL;
1570 int_to_apicintpin[x].redirindex = 0;
1571 }
1572
1573 /* First assign ISA/EISA interrupts */
1574 for (x = 0; x < nintrs; x++) {
1575 int_vector = io_apic_ints[x].src_bus_irq;
1576 if (int_vector < APIC_INTMAPSIZE &&
1577 io_apic_ints[x].int_vector == 0xff &&
1578 int_to_apicintpin[int_vector].ioapic == -1 &&
1579 (apic_int_is_bus_type(x, ISA) ||
1580 apic_int_is_bus_type(x, EISA)) &&
1581 io_apic_ints[x].int_type == 0) {
1582 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1583 io_apic_ints[x].dst_apic_int,
1584 int_vector);
1585 }
1586 }
1587
1588 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1589 for (x = 0; x < nintrs; x++) {
1590 if (io_apic_ints[x].dst_apic_int == 0 &&
1591 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1592 io_apic_ints[x].int_vector == 0xff &&
1593 int_to_apicintpin[0].ioapic == -1 &&
1594 io_apic_ints[x].int_type == 3) {
1595 assign_apic_irq(0, 0, 0);
1596 break;
1597 }
1598 }
1599 /* PCI interrupt assignment is deferred */
1600}
1601
97359a5b 1602#endif
984263bc 1603
a9112655
SZ
1604void
1605mp_set_cpuids(int cpu_id, int apic_id)
1606{
1607 CPU_TO_ID(cpu_id) = apic_id;
1608 ID_TO_CPU(apic_id) = cpu_id;
1609}
1610
984263bc 1611static int
a0873f07 1612processor_entry(const struct PROCENTRY *entry, int cpu)
984263bc 1613{
bd8aa7e2
SZ
1614 KKASSERT(cpu > 0);
1615
984263bc
MD
1616 /* check for usability */
1617 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1618 return 0;
1619
984263bc
MD
1620 /* check for BSP flag */
1621 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
a9112655 1622 mp_set_cpuids(0, entry->apic_id);
984263bc
MD
1623 return 0; /* its already been counted */
1624 }
1625
1626 /* add another AP to list, if less than max number of CPUs */
1627 else if (cpu < MAXCPU) {
a9112655 1628 mp_set_cpuids(cpu, entry->apic_id);
984263bc
MD
1629 return 1;
1630 }
1631
1632 return 0;
1633}
1634
4f6a8b30 1635#ifdef APIC_IO
984263bc
MD
1636
1637static int
1638bus_entry(bus_entry_ptr entry, int bus)
1639{
1640 int x;
1641 char c, name[8];
1642
1643 /* encode the name into an index */
1644 for (x = 0; x < 6; ++x) {
1645 if ((c = entry->bus_type[x]) == ' ')
1646 break;
1647 name[x] = c;
1648 }
1649 name[x] = '\0';
1650
1651 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1652 panic("unknown bus type: '%s'", name);
1653
1654 bus_data[bus].bus_id = entry->bus_id;
1655 bus_data[bus].bus_type = x;
1656
1657 return 1;
1658}
1659
984263bc
MD
1660static int
1661io_apic_entry(io_apic_entry_ptr entry, int apic)
1662{
1663 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1664 return 0;
1665
1666 IO_TO_ID(apic) = entry->apic_id;
c163176b 1667 ID_TO_IO(entry->apic_id) = apic;
984263bc
MD
1668
1669 return 1;
1670}
1671
97359a5b 1672#endif
984263bc
MD
1673
1674static int
1675lookup_bus_type(char *name)
1676{
1677 int x;
1678
1679 for (x = 0; x < MAX_BUSTYPE; ++x)
1680 if (strcmp(bus_type_table[x].name, name) == 0)
1681 return bus_type_table[x].type;
1682
1683 return UNKNOWN_BUSTYPE;
1684}
1685
97359a5b 1686#ifdef APIC_IO
984263bc
MD
1687
1688static int
1689int_entry(int_entry_ptr entry, int intr)
1690{
1691 int apic;
1692
1693 io_apic_ints[intr].int_type = entry->int_type;
1694 io_apic_ints[intr].int_flags = entry->int_flags;
1695 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1696 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1697 if (entry->dst_apic_id == 255) {
1698 /* This signal goes to all IO APICS. Select an IO APIC
1699 with sufficient number of interrupt pins */
1700 for (apic = 0; apic < mp_napics; apic++)
1701 if (((io_apic_read(apic, IOAPIC_VER) &
1702 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1703 entry->dst_apic_int)
1704 break;
1705 if (apic < mp_napics)
1706 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1707 else
1708 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1709 } else
1710 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1711 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1712
1713 return 1;
1714}
1715
984263bc
MD
1716static int
1717apic_int_is_bus_type(int intr, int bus_type)
1718{
1719 int bus;
1720
1721 for (bus = 0; bus < mp_nbusses; ++bus)
1722 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1723 && ((int) bus_data[bus].bus_type == bus_type))
1724 return 1;
1725
1726 return 0;
1727}
1728
984263bc
MD
1729/*
1730 * Given a traditional ISA INT mask, return an APIC mask.
1731 */
1732u_int
1733isa_apic_mask(u_int isa_mask)
1734{
1735 int isa_irq;
1736 int apic_pin;
1737
1738#if defined(SKIP_IRQ15_REDIRECT)
1739 if (isa_mask == (1 << 15)) {
26be20a0 1740 kprintf("skipping ISA IRQ15 redirect\n");
984263bc
MD
1741 return isa_mask;
1742 }
1743#endif /* SKIP_IRQ15_REDIRECT */
1744
1745 isa_irq = ffs(isa_mask); /* find its bit position */
1746 if (isa_irq == 0) /* doesn't exist */
1747 return 0;
1748 --isa_irq; /* make it zero based */
1749
1750 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1751 if (apic_pin == -1)
1752 return 0;
1753
1754 return (1 << apic_pin); /* convert pin# to a mask */
1755}
1756
984263bc
MD
1757/*
1758 * Determine which APIC pin an ISA/EISA INT is attached to.
1759 */
1760#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1761#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1762#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1763#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1764
1765#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1766int
1767isa_apic_irq(int isa_irq)
1768{
1769 int intr;
1770
1771 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1772 if (INTTYPE(intr) == 0) { /* standard INT */
1773 if (SRCBUSIRQ(intr) == isa_irq) {
1774 if (apic_int_is_bus_type(intr, ISA) ||
1775 apic_int_is_bus_type(intr, EISA)) {
1776 if (INTIRQ(intr) == 0xff)
1777 return -1; /* unassigned */
1778 return INTIRQ(intr); /* found */
1779 }
1780 }
1781 }
1782 }
1783 return -1; /* NOT found */
1784}
1785
1786
1787/*
1788 * Determine which APIC pin a PCI INT is attached to.
1789 */
1790#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1791#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1792#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1793int
1794pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1795{
1796 int intr;
1797
1798 --pciInt; /* zero based */
1799
1439c090 1800 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
984263bc
MD
1801 if ((INTTYPE(intr) == 0) /* standard INT */
1802 && (SRCBUSID(intr) == pciBus)
1803 && (SRCBUSDEVICE(intr) == pciDevice)
1439c090 1804 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
984263bc
MD
1805 if (apic_int_is_bus_type(intr, PCI)) {
1806 if (INTIRQ(intr) == 0xff)
1807 allocate_apic_irq(intr);
1808 if (INTIRQ(intr) == 0xff)
1809 return -1; /* unassigned */
1810 return INTIRQ(intr); /* exact match */
1811 }
1439c090
MD
1812 }
1813 }
984263bc
MD
1814
1815 return -1; /* NOT found */
1816}
1817
1818int
1819next_apic_irq(int irq)
1820{
1821 int intr, ointr;
1822 int bus, bustype;
1823
1824 bus = 0;
1825 bustype = 0;
1826 for (intr = 0; intr < nintrs; intr++) {
1827 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1828 continue;
1829 bus = SRCBUSID(intr);
1830 bustype = apic_bus_type(bus);
1831 if (bustype != ISA &&
1832 bustype != EISA &&
1833 bustype != PCI)
1834 continue;
1835 break;
1836 }
1837 if (intr >= nintrs) {
1838 return -1;
1839 }
1840 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1841 if (INTTYPE(ointr) != 0)
1842 continue;
1843 if (bus != SRCBUSID(ointr))
1844 continue;
1845 if (bustype == PCI) {
1846 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1847 continue;
1848 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1849 continue;
1850 }
1851 if (bustype == ISA || bustype == EISA) {
1852 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1853 continue;
1854 }
1855 if (INTPIN(intr) == INTPIN(ointr))
1856 continue;
1857 break;
1858 }
1859 if (ointr >= nintrs) {
1860 return -1;
1861 }
1862 return INTIRQ(ointr);
1863}
1864#undef SRCBUSLINE
1865#undef SRCBUSDEVICE
1866#undef SRCBUSID
1867#undef SRCBUSIRQ
1868
1869#undef INTPIN
1870#undef INTIRQ
1871#undef INTAPIC
1872#undef INTTYPE
1873
97359a5b 1874#endif
984263bc
MD
1875
1876/*
1877 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1878 *
1879 * XXX FIXME:
1880 * Exactly what this means is unclear at this point. It is a solution
1881 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1882 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1883 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1884 * option.
1885 */
1886int
1887undirect_isa_irq(int rirq)
1888{
1889#if defined(READY)
1890 if (bootverbose)
26be20a0 1891 kprintf("Freeing redirected ISA irq %d.\n", rirq);
984263bc 1892 /** FIXME: tickle the MB redirector chip */
c044141b 1893 return /* XXX */;
984263bc
MD
1894#else
1895 if (bootverbose)
26be20a0 1896 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
984263bc
MD
1897 return 0;
1898#endif /* READY */
1899}
1900
1901
1902/*
1903 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1904 */
1905int
1906undirect_pci_irq(int rirq)
1907{
1908#if defined(READY)
1909 if (bootverbose)
26be20a0 1910 kprintf("Freeing redirected PCI irq %d.\n", rirq);
984263bc
MD
1911
1912 /** FIXME: tickle the MB redirector chip */
c044141b 1913 return /* XXX */;
984263bc
MD
1914#else
1915 if (bootverbose)
26be20a0 1916 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
984263bc
MD
1917 rirq);
1918 return 0;
1919#endif /* READY */
1920}
1921
1922
4f6a8b30
SZ
1923#ifdef APIC_IO
1924
984263bc
MD
1925/*
1926 * given a bus ID, return:
1927 * the bus type if found
1928 * -1 if NOT found
1929 */
1930int
1931apic_bus_type(int id)
1932{
1933 int x;
1934
1935 for (x = 0; x < mp_nbusses; ++x)
1936 if (bus_data[x].bus_id == id)
1937 return bus_data[x].bus_type;
1938
1939 return -1;
1940}
1941
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MD
1942/*
1943 * given a LOGICAL APIC# and pin#, return:
1944 * the associated src bus ID if found
1945 * -1 if NOT found
1946 */
1947int
1948apic_src_bus_id(int apic, int pin)
1949{
1950 int x;
1951
1952 /* search each of the possible INTerrupt sources */
1953 for (x = 0; x < nintrs; ++x)
1954 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1955 (pin == io_apic_ints[x].dst_apic_int))
1956 return (io_apic_ints[x].src_bus_id);
1957
1958 return -1; /* NOT found */
1959}
1960
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MD
1961/*
1962 * given a LOGICAL APIC# and pin#, return:
1963 * the associated src bus IRQ if found
1964 * -1 if NOT found
1965 */
1966int
1967apic_src_bus_irq(int apic, int pin)
1968{
1969 int x;
1970
1971 for (x = 0; x < nintrs; x++)
1972 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1973 (pin == io_apic_ints[x].dst_apic_int))
1974 return (io_apic_ints[x].src_bus_irq);
1975
1976 return -1; /* NOT found */
1977}
1978
1979
1980/*
1981 * given a LOGICAL APIC# and pin#, return:
1982 * the associated INTerrupt type if found
1983 * -1 if NOT found
1984 */
1985int
1986apic_int_type(int apic, int pin)
1987{
1988 int x;
1989
1990 /* search each of the possible INTerrupt sources */
1439c090 1991 for (x = 0; x < nintrs; ++x) {
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MD
1992 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1993 (pin == io_apic_ints[x].dst_apic_int))
1994 return (io_apic_ints[x].int_type);
1439c090 1995 }
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MD
1996 return -1; /* NOT found */
1997}
1998
1439c090
MD
1999/*
2000 * Return the IRQ associated with an APIC pin
2001 */
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MD
2002int
2003apic_irq(int apic, int pin)
2004{
2005 int x;
2006 int res;
2007
1439c090 2008 for (x = 0; x < nintrs; ++x) {
984263bc
MD
2009 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2010 (pin == io_apic_ints[x].dst_apic_int)) {
2011 res = io_apic_ints[x].int_vector;
2012 if (res == 0xff)
2013 return -1;
2014 if (apic != int_to_apicintpin[res].ioapic)
1439c090 2015 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
984263bc
MD
2016 if (pin != int_to_apicintpin[res].int_pin)
2017 panic("apic_irq inconsistent table (2)");
2018 return res;
2019 }
1439c090 2020 }
984263bc
MD
2021 return -1;
2022}
2023
2024
2025/*
2026 * given a LOGICAL APIC# and pin#, return:
2027 * the associated trigger mode if found
2028 * -1 if NOT found
2029 */
2030int
2031apic_trigger(int apic, int pin)
2032{
2033 int x;
2034
2035 /* search each of the possible INTerrupt sources */
2036 for (x = 0; x < nintrs; ++x)
2037 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2038 (pin == io_apic_ints[x].dst_apic_int))
2039 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2040
2041 return -1; /* NOT found */
2042}
2043
2044
2045/*
2046 * given a LOGICAL APIC# and pin#, return:
2047 * the associated 'active' level if found
2048 * -1 if NOT found
2049 */
2050int
2051apic_polarity(int apic, int pin)
2052{
2053 int x;
2054
2055 /* search each of the possible INTerrupt sources */
2056 for (x = 0; x < nintrs; ++x)
2057 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2058 (pin == io_apic_ints[x].dst_apic_int))
2059 return (io_apic_ints[x].int_flags & 0x03);
2060
2061 return -1; /* NOT found */
2062}
2063
97359a5b 2064#endif
984263bc
MD
2065
2066/*
2067 * set data according to MP defaults
2068 * FIXME: probably not complete yet...
2069 */
2070static void
3aba8f73 2071mptable_default(int type)
984263bc 2072{
984263bc
MD
2073#if defined(APIC_IO)
2074 int io_apic_id;
2075 int pin;
2076#endif /* APIC_IO */
2077
2078#if 0
26be20a0 2079 kprintf(" MP default config type: %d\n", type);
984263bc
MD
2080 switch (type) {
2081 case 1:
26be20a0 2082 kprintf(" bus: ISA, APIC: 82489DX\n");
984263bc
MD
2083 break;
2084 case 2:
26be20a0 2085 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2086 break;
2087 case 3:
26be20a0 2088 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2089 break;
2090 case 4:
26be20a0 2091 kprintf(" bus: MCA, APIC: 82489DX\n");
984263bc
MD
2092 break;
2093 case 5:
26be20a0 2094 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
984263bc
MD
2095 break;
2096 case 6:
26be20a0 2097 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
984263bc
MD
2098 break;
2099 case 7:
26be20a0 2100 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
984263bc
MD
2101 break;
2102 default:
26be20a0 2103 kprintf(" future type\n");
984263bc
MD
2104 break;
2105 /* NOTREACHED */
2106 }
2107#endif /* 0 */
2108
984263bc
MD
2109#if defined(APIC_IO)
2110 /* one and only IO APIC */
2111 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2112
2113 /*
2114 * sanity check, refer to MP spec section 3.6.6, last paragraph
2115 * necessary as some hardware isn't properly setting up the IO APIC
2116 */
2117#if defined(REALLY_ANAL_IOAPICID_VALUE)
2118 if (io_apic_id != 2) {
2119#else
2120 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2121#endif /* REALLY_ANAL_IOAPICID_VALUE */
2122 io_apic_set_id(0, 2);
2123 io_apic_id = 2;
2124 }
2125 IO_TO_ID(0) = io_apic_id;
2126 ID_TO_IO(io_apic_id) = 0;
2127#endif /* APIC_IO */
2128
2129 /* fill out bus entries */
2130 switch (type) {
2131 case 1:
2132 case 2:
2133 case 3:
2134 case 4:
2135 case 5:
2136 case 6:
2137 case 7:
4f6a8b30 2138#ifdef APIC_IO
984263bc
MD
2139 bus_data[0].bus_id = default_data[type - 1][1];
2140 bus_data[0].bus_type = default_data[type - 1][2];
2141 bus_data[1].bus_id = default_data[type - 1][3];
2142 bus_data[1].bus_type = default_data[type - 1][4];
4f6a8b30 2143#endif
984263bc
MD
2144 break;
2145
2146 /* case 4: case 7: MCA NOT supported */
2147 default: /* illegal/reserved */
2148 panic("BAD default MP config: %d", type);
2149 /* NOTREACHED */
2150 }
2151
2152#if defined(APIC_IO)
2153 /* general cases from MP v1.4, table 5-2 */
2154 for (pin = 0; pin < 16; ++pin) {
2155 io_apic_ints[pin].int_type = 0;
2156 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2157 io_apic_ints[pin].src_bus_id = 0;
2158 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2159 io_apic_ints[pin].dst_apic_id = io_apic_id;
2160 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2161 }
2162
2163 /* special cases from MP v1.4, table 5-2 */
2164 if (type == 2) {
2165 io_apic_ints[2].int_type = 0xff; /* N/C */
2166 io_apic_ints[13].int_type = 0xff; /* N/C */
2167#if !defined(APIC_MIXED_MODE)
2168 /** FIXME: ??? */
2169 panic("sorry, can't support type 2 default yet");
2170#endif /* APIC_MIXED_MODE */
2171 }
2172 else
2173 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2174
2175 if (type == 7)
2176 io_apic_ints[0].int_type = 0xff; /* N/C */
2177 else
2178 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2179#endif /* APIC_IO */
2180}
2181
984263bc 2182/*
f13b5eec
MD
2183 * Map a physical memory address representing I/O into KVA. The I/O
2184 * block is assumed not to cross a page boundary.
2185 */
2186void *
2187permanent_io_mapping(vm_paddr_t pa)
2188{
2189 vm_offset_t vaddr;
2190 int pgeflag;
2191 int i;
2192
2193 KKASSERT(pa < 0x100000000LL);
2194
2195 pgeflag = 0; /* not used for SMP yet */
2196
2197 /*
2198 * If the requested physical address has already been incidently
2199 * mapped, just use the existing mapping. Otherwise create a new
2200 * mapping.
2201 */
2202 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2203 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2204 ((vm_offset_t)pa & PG_FRAME)) {
2205 break;
2206 }
2207 }
2208 if (i == SMPpt_alloc_index) {
2209 if (i == NPTEPG - 2) {
2210 panic("permanent_io_mapping: We ran out of space"
2211 " in SMPpt[]!");
2212 }
2213 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2214 ((vm_offset_t)pa & PG_FRAME));
2215 ++SMPpt_alloc_index;
2216 }
2217 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2218 ((vm_offset_t)pa & PAGE_MASK);
2219 return ((void *)vaddr);
2220}
2221
2222/*
984263bc
MD
2223 * start each AP in our list
2224 */
2225static int
2226start_all_aps(u_int boot_addr)
2227{
b45759e1
MD
2228 int x, i, pg;
2229 int shift;
984263bc
MD
2230 u_char mpbiosreason;
2231 u_long mpbioswarmvec;
8a8d5d85 2232 struct mdglobaldata *gd;
0f7a3396 2233 struct privatespace *ps;
984263bc
MD
2234 char *stack;
2235 uintptr_t kptbase;
2236
2237 POSTCODE(START_ALL_APS_POST);
2238
b52c8db0
SZ
2239 /* Initialize BSP's local APIC */
2240 apic_initialize(TRUE);
984263bc
MD
2241
2242 /* install the AP 1st level boot code */
2243 install_ap_tramp(boot_addr);
2244
2245
2246 /* save the current value of the warm-start vector */
2247 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD
2248 outb(CMOS_REG, BIOS_RESET);
2249 mpbiosreason = inb(CMOS_DATA);
984263bc 2250
984263bc
MD
2251 /* set up temporary P==V mapping for AP boot */
2252 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2253 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 2254 for (x = 0; x < NKPT; x++) {
984263bc
MD
2255 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2256 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 2257 }
0f7a3396 2258 cpu_invltlb();
984263bc
MD
2259
2260 /* start each AP */
2261 for (x = 1; x <= mp_naps; ++x) {
2262
2263 /* This is a bit verbose, it will go away soon. */
2264
2265 /* first page of AP's private space */
2266 pg = x * i386_btop(sizeof(struct privatespace));
2267
81c04d07 2268 /* allocate new private data page(s) */
e4846942 2269 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 2270 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 2271 /* wire it into the private page table page */
81c04d07
MD
2272 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2273 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2274 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2275 }
2276 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2277
2278 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2279 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2280 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2281 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD
2282
2283 /* allocate and set up an idle stack data page */
e4846942 2284 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2285 for (i = 0; i < UPAGES; i++) {
81c04d07 2286 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 2287 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 2288 }
984263bc 2289
8a8d5d85
MD
2290 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2291 bzero(gd, sizeof(*gd));
0f7a3396 2292 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 2293
984263bc 2294 /* prime data page for it to use */
8a8d5d85 2295 mi_gdinit(&gd->mi, x);
8ad65e08 2296 cpu_gdinit(gd, x);
81c04d07
MD
2297 gd->gd_CMAP1 = &SMPpt[pg + 0];
2298 gd->gd_CMAP2 = &SMPpt[pg + 1];
2299 gd->gd_CMAP3 = &SMPpt[pg + 2];
2300 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD
2301 gd->gd_CADDR1 = ps->CPAGE1;
2302 gd->gd_CADDR2 = ps->CPAGE2;
2303 gd->gd_CADDR3 = ps->CPAGE3;
2304 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
e4846942 2305 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 2306 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc
MD
2307
2308 /* setup a vector to our boot code */
2309 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2310 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
984263bc
MD
2311 outb(CMOS_REG, BIOS_RESET);
2312 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
984263bc 2313
8a8d5d85
MD
2314 /*
2315 * Setup the AP boot stack
2316 */
0f7a3396 2317 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
2318 bootAP = x;
2319
2320 /* attempt to start the Application Processor */
2321 CHECK_INIT(99); /* setup checkpoints */
0f7a3396 2322 if (!start_ap(gd, boot_addr)) {
26be20a0 2323 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD
2324 CHECK_PRINT("trace"); /* show checkpoints */
2325 /* better panic as the AP may be running loose */
26be20a0 2326 kprintf("panic y/n? [y] ");
984263bc
MD
2327 if (cngetc() != 'n')
2328 panic("bye-bye");
2329 }
2330 CHECK_PRINT("trace"); /* show checkpoints */
2331
2332 /* record its version info */
2333 cpu_apic_versions[x] = cpu_apic_versions[0];
984263bc
MD
2334 }
2335
0f7a3396
MD
2336 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2337 ncpus = x;
2338
b45759e1
MD
2339 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2340 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2341 ;
2342 --shift;
2343 ncpus2_shift = shift;
2344 ncpus2 = 1 << shift;
90100055
JH
2345 ncpus2_mask = ncpus2 - 1;
2346
b45759e1
MD
2347 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2348 if ((1 << shift) < ncpus)
2349 ++shift;
2350 ncpus_fit = 1 << shift;
2351 ncpus_fit_mask = ncpus_fit - 1;
2352
984263bc 2353 /* build our map of 'other' CPUs */
0f7a3396 2354 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
e4846942 2355 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 2356 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD
2357
2358 /* fill in our (BSP) APIC version */
2359 cpu_apic_versions[0] = lapic.version;
2360
2361 /* restore the warmstart vector */
2362 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD
2363 outb(CMOS_REG, BIOS_RESET);
2364 outb(CMOS_DATA, mpbiosreason);
984263bc
MD
2365
2366 /*
8a8d5d85
MD
2367 * NOTE! The idlestack for the BSP was setup by locore. Finish
2368 * up, clean out the P==V mapping we did earlier.
984263bc 2369 */
984263bc
MD
2370 for (x = 0; x < NKPT; x++)
2371 PTD[x] = 0;
2372 pmap_set_opt();
2373
2374 /* number of APs actually started */
8a8d5d85 2375 return ncpus - 1;
984263bc
MD
2376}
2377
2378
2379/*
2380 * load the 1st level AP boot code into base memory.
2381 */
2382
2383/* targets for relocation */
2384extern void bigJump(void);
2385extern void bootCodeSeg(void);
2386extern void bootDataSeg(void);
2387extern void MPentry(void);
2388extern u_int MP_GDT;
2389extern u_int mp_gdtbase;
2390
2391static void
2392install_ap_tramp(u_int boot_addr)
2393{
2394 int x;
2395 int size = *(int *) ((u_long) & bootMP_size);
2396 u_char *src = (u_char *) ((u_long) bootMP);
2397 u_char *dst = (u_char *) boot_addr + KERNBASE;
2398 u_int boot_base = (u_int) bootMP;
2399 u_int8_t *dst8;
2400 u_int16_t *dst16;
2401 u_int32_t *dst32;
2402
2403 POSTCODE(INSTALL_AP_TRAMP_POST);
2404
2405 for (x = 0; x < size; ++x)
2406 *dst++ = *src++;
2407
2408 /*
2409 * modify addresses in code we just moved to basemem. unfortunately we
2410 * need fairly detailed info about mpboot.s for this to work. changes
2411 * to mpboot.s might require changes here.
2412 */
2413
2414 /* boot code is located in KERNEL space */
2415 dst = (u_char *) boot_addr + KERNBASE;
2416
2417 /* modify the lgdt arg */
2418 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2419 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2420
2421 /* modify the ljmp target for MPentry() */
2422 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2423 *dst32 = ((u_int) MPentry - KERNBASE);
2424
2425 /* modify the target for boot code segment */
2426 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2427 dst8 = (u_int8_t *) (dst16 + 1);
2428 *dst16 = (u_int) boot_addr & 0xffff;
2429 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2430
2431 /* modify the target for boot data segment */
2432 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2433 dst8 = (u_int8_t *) (dst16 + 1);
2434 *dst16 = (u_int) boot_addr & 0xffff;
2435 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2436}
2437
2438
2439/*
2440 * this function starts the AP (application processor) identified
2441 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2442 * to accomplish this. This is necessary because of the nuances
2443 * of the different hardware we might encounter. It ain't pretty,
2444 * but it seems to work.
a108bf71
MD
2445 *
2446 * NOTE: eventually an AP gets to ap_init(), which is called just
2447 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD
2448 */
2449static int
0f7a3396 2450start_ap(struct mdglobaldata *gd, u_int boot_addr)
984263bc
MD
2451{
2452 int physical_cpu;
2453 int vector;
984263bc
MD
2454 u_long icr_lo, icr_hi;
2455
2456 POSTCODE(START_AP_POST);
2457
2458 /* get the PHYSICAL APIC ID# */
0f7a3396 2459 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD
2460
2461 /* calculate the vector */
2462 vector = (boot_addr >> 12) & 0xff;
2463
8a8d5d85
MD
2464 /* Make sure the target cpu sees everything */
2465 wbinvd();
984263bc
MD
2466
2467 /*
2468 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2469 * and running the target CPU. OR this INIT IPI might be latched (P5
2470 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2471 * ignored.
2472 */
2473
2474 /* setup the address for the target AP */
2475 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2476 icr_hi |= (physical_cpu << 24);
2477 lapic.icr_hi = icr_hi;
2478
2479 /* do an INIT IPI: assert RESET */
2480 icr_lo = lapic.icr_lo & 0xfff00000;
2481 lapic.icr_lo = icr_lo | 0x0000c500;
2482
2483 /* wait for pending status end */
2484 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2485 /* spin */ ;
2486
2487 /* do an INIT IPI: deassert RESET */
2488 lapic.icr_lo = icr_lo | 0x00008500;
2489
2490 /* wait for pending status end */
2491 u_sleep(10000); /* wait ~10mS */
2492 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2493 /* spin */ ;
2494
2495 /*
2496 * next we do a STARTUP IPI: the previous INIT IPI might still be
2497 * latched, (P5 bug) this 1st STARTUP would then terminate
2498 * immediately, and the previously started INIT IPI would continue. OR
2499 * the previous INIT IPI has already run. and this STARTUP IPI will
2500 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2501 * will run.
2502 */
2503
2504 /* do a STARTUP IPI */
2505 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2506 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2507 /* spin */ ;
2508 u_sleep(200); /* wait ~200uS */
2509
2510 /*
2511 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2512 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2513 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2514 * recognized after hardware RESET or INIT IPI.
2515 */
2516
2517 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2518 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2519 /* spin */ ;
2520 u_sleep(200); /* wait ~200uS */
2521
8a8d5d85 2522 /* wait for it to start, see ap_init() */
984263bc 2523 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 2524 while (read_apic_timer()) {
0f7a3396 2525 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
984263bc 2526 return 1; /* return SUCCESS */
8a8d5d85 2527 }
984263bc
MD
2528 return 0; /* return FAILURE */
2529}
2530
2531
2532/*
0f7a3396 2533 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 2534 *
0f7a3396
MD
2535 * If for some reason we were unable to start all cpus we cannot safely
2536 * use broadcast IPIs.
984263bc
MD
2537 */
2538void
2539smp_invltlb(void)
2540{
97359a5b 2541#ifdef SMP
0f7a3396 2542 if (smp_startup_mask == smp_active_mask) {
984263bc 2543 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396
MD
2544 } else {
2545 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2546 APIC_DELMODE_FIXED);
2547 }
97359a5b 2548#endif
984263bc
MD
2549}
2550
984263bc
MD
2551/*
2552 * When called the executing CPU will send an IPI to all other CPUs
2553 * requesting that they halt execution.
2554 *
2555 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2556 *
2557 * - Signals all CPUs in map to stop.
2558 * - Waits for each to stop.
2559 *
2560 * Returns:
2561 * -1: error
2562 * 0: NA
2563 * 1: ok
2564 *
2565 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2566 * from executing at same time.
2567 */
2568int
2569stop_cpus(u_int map)
2570{
0f7a3396 2571 map &= smp_active_mask;
984263bc
MD
2572
2573 /* send the Xcpustop IPI to all CPUs in map */
2574 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2575
2576 while ((stopped_cpus & map) != map)
2577 /* spin */ ;
2578
2579 return 1;
2580}
2581
2582
2583/*
2584 * Called by a CPU to restart stopped CPUs.
2585 *
2586 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2587 *
2588 * - Signals all CPUs in map to restart.
2589 * - Waits for each to restart.
2590 *
2591 * Returns:
2592 * -1: error
2593 * 0: NA
2594 * 1: ok
2595 */
2596int
2597restart_cpus(u_int map)
2598{
0f7a3396
MD
2599 /* signal other cpus to restart */
2600 started_cpus = map & smp_active_mask;
984263bc
MD
2601
2602 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2603 /* spin */ ;
2604
2605 return 1;
2606}
2607
984263bc 2608/*
8a8d5d85
MD
2609 * This is called once the mpboot code has gotten us properly relocated
2610 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2611 * and when it returns the scheduler will call the real cpu_idle() main
2612 * loop for the idlethread. Interrupts are disabled on entry and should
2613 * remain disabled at return.
984263bc 2614 */
984263bc 2615void
8a8d5d85 2616ap_init(void)
984263bc
MD
2617{
2618 u_int apic_id;
2619
8a8d5d85 2620 /*
0f7a3396
MD
2621 * Adjust smp_startup_mask to signal the BSP that we have started
2622 * up successfully. Note that we do not yet hold the BGL. The BSP
2623 * is waiting for our signal.
2624 *
2625 * We can't set our bit in smp_active_mask yet because we are holding
2626 * interrupts physically disabled and remote cpus could deadlock
2627 * trying to send us an IPI.
8a8d5d85 2628 */
0f7a3396 2629 smp_startup_mask |= 1 << mycpu->gd_cpuid;
35238fa5 2630 cpu_mfence();
8a8d5d85
MD
2631
2632 /*
41a01a4d
MD
2633 * Interlock for finalization. Wait until mp_finish is non-zero,
2634 * then get the MP lock.
2635 *
2636 * Note: We are in a critical section.
2637 *
2638 * Note: We have to synchronize td_mpcount to our desired MP state
2639 * before calling cpu_try_mplock().
2640 *
2641 * Note: we are the idle thread, we can only spin.
2642 *
35238fa5
MD
2643 * Note: The load fence is memory volatile and prevents the compiler
2644 * from improperly caching mp_finish, and the cpu from improperly
2645 * caching it.
8a8d5d85 2646 */
41a01a4d 2647 while (mp_finish == 0)
35238fa5 2648 cpu_lfence();
d9ebdce5 2649 ++curthread->td_mpcount;
8a8d5d85
MD
2650 while (cpu_try_mplock() == 0)
2651 ;
2652
374133e3
MD
2653 if (cpu_feature & CPUID_TSC) {
2654 /*
2655 * The BSP is constantly updating tsc0_offset, figure out the
2656 * relative difference to synchronize ktrdump.
2657 */
2658 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2659 }
2660
984263bc
MD
2661 /* BSP may have changed PTD while we're waiting for the lock */
2662 cpu_invltlb();
2663
984263bc
MD
2664#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2665 lidt(&r_idt);
2666#endif
2667
2668 /* Build our map of 'other' CPUs. */
0f7a3396 2669 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
984263bc 2670
26be20a0 2671 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc 2672
984263bc
MD
2673 /* A quick check from sanity claus */
2674 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85 2675 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW
2676 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2677 kprintf("SMP: apic_id = %d\n", apic_id);
2678 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD
2679 panic("cpuid mismatch! boom!!");
2680 }
2681
b52c8db0
SZ
2682 /* Initialize AP's local APIC for irq's */
2683 apic_initialize(FALSE);
984263bc
MD
2684
2685 /* Set memory range attributes for this CPU to match the BSP */
2686 mem_range_AP_init();
2687
a2a5ad0d 2688 /*
4c9f5a7f
MD
2689 * Once we go active we must process any IPIQ messages that may
2690 * have been queued, because no actual IPI will occur until we
2691 * set our bit in the smp_active_mask. If we don't the IPI
2692 * message interlock could be left set which would also prevent
2693 * further IPIs.
2694 *
8a8d5d85
MD
2695 * The idle loop doesn't expect the BGL to be held and while
2696 * lwkt_switch() normally cleans things up this is a special case
2697 * because we returning almost directly into the idle loop.
41a01a4d
MD
2698 *
2699 * The idle thread is never placed on the runq, make sure
4c9f5a7f 2700 * nothing we've done put it there.
8a8d5d85 2701 */
96728c05 2702 KKASSERT(curthread->td_mpcount == 1);
41a01a4d 2703 smp_active_mask |= 1 << mycpu->gd_cpuid;
d19f6edf
MD
2704
2705 /*
2706 * Enable interrupts here. idle_restore will also do it, but
2707 * doing it here lets us clean up any strays that got posted to
2708 * the CPU during the AP boot while we are still in a critical
2709 * section.
2710 */
2711 __asm __volatile("sti; pause; pause"::);
2712 mdcpu->gd_fpending = 0;
2713 mdcpu->gd_ipending = 0;
2714
4a19580d 2715 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 2716 lwkt_process_ipiq();
d19f6edf
MD
2717
2718 /*
2719 * Releasing the mp lock lets the BSP finish up the SMP init
2720 */
96728c05 2721 rel_mplock();
41a01a4d 2722 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD
2723}
2724
41a01a4d
MD
2725/*
2726 * Get SMP fully working before we start initializing devices.
2727 */
2728static
2729void
2730ap_finish(void)
2731{
2732 mp_finish = 1;
2733 if (bootverbose)
26be20a0 2734 kprintf("Finish MP startup\n");
374133e3
MD
2735 if (cpu_feature & CPUID_TSC)
2736 tsc0_offset = rdtsc();
2737 tsc_offsets[0] = 0;
41a01a4d 2738 rel_mplock();
374133e3 2739 while (smp_active_mask != smp_startup_mask) {
35238fa5 2740 cpu_lfence();
374133e3
MD
2741 if (cpu_feature & CPUID_TSC)
2742 tsc0_offset = rdtsc();
2743 }
4da43e1f 2744 while (try_mplock() == 0)
41a01a4d
MD
2745 ;
2746 if (bootverbose)
26be20a0 2747 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD
2748}
2749
ba39e2e0 2750SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 2751
96728c05
MD
2752void
2753cpu_send_ipiq(int dcpu)
2754{
41a01a4d
MD
2755 if ((1 << dcpu) & smp_active_mask)
2756 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 2757}
41a01a4d
MD
2758
2759#if 0 /* single_apic_ipi_passive() not working yet */
2760/*
2761 * Returns 0 on failure, 1 on success
2762 */
2763int
2764cpu_send_ipiq_passive(int dcpu)
2765{
2766 int r = 0;
2767 if ((1 << dcpu) & smp_active_mask) {
2768 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2769 APIC_DELMODE_FIXED);
2770 }
2771 return(r);
2772}
2773#endif
2774
a0873f07
SZ
2775struct mptable_lapic_cbarg1 {
2776 int cpu_count;
44c36320
SZ
2777 int ht_fixup;
2778 u_int ht_apicid_mask;
a0873f07
SZ
2779};
2780
2781static int
2782mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2783{
2784 const struct PROCENTRY *ent;
2785 struct mptable_lapic_cbarg1 *arg = xarg;
2786
2787 if (type != 0)
2788 return 0;
2789 ent = pos;
2790
2791 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2792 return 0;
2793
2794 arg->cpu_count++;
44c36320
SZ
2795 if (ent->apic_id < 32) {
2796 arg->ht_apicid_mask |= 1 << ent->apic_id;
2797 } else if (arg->ht_fixup) {
2798 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2799 arg->ht_fixup = 0;
2800 }
a0873f07
SZ
2801 return 0;
2802}
2803
2804struct mptable_lapic_cbarg2 {
2805 int cpu;
44c36320 2806 int logical_cpus;
a0873f07
SZ
2807 int found_bsp;
2808};
2809
2810static int
2811mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2812{
2813 const struct PROCENTRY *ent;
2814 struct mptable_lapic_cbarg2 *arg = xarg;
2815
2816 if (type != 0)
2817 return 0;
2818 ent = pos;
2819
2820 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2821 KKASSERT(!arg->found_bsp);
2822 arg->found_bsp = 1;
2823 }
2824
2825 if (processor_entry(ent, arg->cpu))
2826 arg->cpu++;
2827
44c36320 2828 if (arg->logical_cpus) {
a0873f07
SZ
2829 struct PROCENTRY proc;
2830 int i;
2831
2832 /*
2833 * Create fake mptable processor entries
2834 * and feed them to processor_entry() to
2835 * enumerate the logical CPUs.
2836 */
2837 bzero(&proc, sizeof(proc));
2838 proc.type = 0;
2839 proc.cpu_flags = PROCENTRY_FLAG_EN;
2840 proc.apic_id = ent->apic_id;
2841
44c36320 2842 for (i = 1; i < arg->logical_cpus; i++) {
a0873f07
SZ
2843 proc.apic_id++;
2844 processor_entry(&proc, arg->cpu);
a0873f07
SZ
2845 arg->cpu++;
2846 }
2847 }
2848 return 0;
2849}
2850
322abba7
SZ
2851static void
2852mptable_lapic_default(void)
2853{
2854 int ap_apicid, bsp_apicid;
2855
2856 mp_naps = 1; /* exclude BSP */
2857
2858 /* Map local apic before the id field is accessed */
2859 lapic_init(DEFAULT_APIC_BASE);
2860
2861 bsp_apicid = APIC_ID(lapic.id);
2862 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2863
2864 /* BSP */
2865 mp_set_cpuids(0, bsp_apicid);
2866 /* one and only AP */
2867 mp_set_cpuids(1, ap_apicid);
2868}
2869
a0873f07
SZ
2870/*
2871 * Configure:
2872 * cpu_apic_address (common to all CPUs)
2873 * mp_naps
d787e80c 2874 * ID_TO_CPU(N), APIC ID to logical CPU table
a0873f07
SZ
2875 * CPU_TO_ID(N), logical CPU to APIC ID table
2876 */
2877static void
2878mptable_lapic_enumerate(struct mptable_pos *mpt)
2879{
322abba7
SZ
2880 struct mptable_lapic_cbarg1 arg1;
2881 struct mptable_lapic_cbarg2 arg2;
2882 mpcth_t cth;
44c36320 2883 int error, logical_cpus = 0;
5a16ccc3 2884 vm_offset_t lapic_addr;
a0873f07 2885
322abba7 2886 KKASSERT(mpt->mp_fps != NULL);
a0873f07 2887
322abba7
SZ
2888 /*
2889 * Check for use of 'default' configuration
2890 */
2891 if (mpt->mp_fps->mpfb1 != 0) {
2892 mptable_lapic_default();
2893 return;
2894 }
a0873f07 2895
322abba7
SZ
2896 cth = mpt->mp_cth;
2897 KKASSERT(cth != NULL);
a0873f07 2898
322abba7
SZ
2899 /* Save local apic address */
2900 lapic_addr = (vm_offset_t)cth->apic_address;
2901 KKASSERT(lapic_addr != 0);
a0873f07 2902
322abba7
SZ
2903 /*
2904 * Find out how many CPUs do we have
2905 */
2906 bzero(&arg1, sizeof(arg1));
44c36320
SZ
2907 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2908
322abba7
SZ
2909 error = mptable_iterate_entries(cth,
2910 mptable_lapic_pass1_callback, &arg1);
2911 if (error)
2912 panic("mptable_iterate_entries(lapic_pass1) failed\n");
322abba7 2913 KKASSERT(arg1.cpu_count != 0);
a0873f07 2914
322abba7 2915 /* See if we need to fixup HT logical CPUs. */
44c36320
SZ
2916 if (arg1.ht_fixup) {
2917 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2918 arg1.cpu_count);
2919 if (logical_cpus != 0)
2920 arg1.cpu_count *= logical_cpus;
2921 }
2922 mp_naps = arg1.cpu_count;
a0873f07 2923
44c36320 2924 /* Qualify the numbers again, after possible HT fixup */
322abba7
SZ
2925 if (mp_naps > MAXCPU) {
2926 kprintf("Warning: only using %d of %d available CPUs!\n",
2927 MAXCPU, mp_naps);
2928 mp_naps = MAXCPU;
a0873f07
SZ
2929 }
2930
322abba7 2931 --mp_naps; /* subtract the BSP */
a0873f07 2932
322abba7
SZ
2933 /*
2934 * Link logical CPU id to local apic id
2935 */
2936 bzero(&arg2, sizeof(arg2));
2937 arg2.cpu = 1;
44c36320 2938 arg2.logical_cpus = logical_cpus;
a0873f07 2939
322abba7
SZ
2940 error = mptable_iterate_entries(cth,
2941 mptable_lapic_pass2_callback, &arg2);
2942 if (error)
2943 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2944 KKASSERT(arg2.found_bsp);
a0873f07 2945
322abba7
SZ
2946 /* Map local apic */
2947 lapic_init(lapic_addr);
a0873f07 2948}
5a16ccc3
SZ
2949
2950static void
2951lapic_init(vm_offset_t lapic_addr)
2952{
2953 /* Local apic is mapped on last page */
2954 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2955 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2956
2957 /* Just for printing */
2958 cpu_apic_address = lapic_addr;
2959}