MachIntr: Add two methods to find IRQ
[dragonfly.git] / sys / platform / pc32 / apic / ioapic_abi.c
CommitLineData
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
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6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
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9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
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12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
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39 */
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/kernel.h>
44#include <sys/machintr.h>
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45#include <sys/interrupt.h>
46#include <sys/bus.h>
0f3e19b1 47#include <sys/rman.h>
9dba15ae 48#include <sys/thread2.h>
0b692e79 49
37e7efec 50#include <machine/smp.h>
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51#include <machine/segments.h>
52#include <machine/md_var.h>
87cf6827 53#include <machine/intr_machdep.h>
0b692e79 54#include <machine/globaldata.h>
be98308a 55#include <machine/msi_var.h>
0b692e79 56
58587c23 57#include <machine_base/isa/isa_intr.h>
4298586a 58#include <machine_base/icu/icu.h>
6b809ec7 59#include <machine_base/icu/icu_var.h>
4298586a 60#include <machine_base/apic/ioapic.h>
929c940f 61#include <machine_base/apic/ioapic_abi.h>
77f86d14 62#include <machine_base/apic/ioapic_ipl.h>
1e7aaefa 63#include <machine_base/apic/apicreg.h>
37e7efec 64
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65#include <dev/acpica5/acpi_sci_var.h>
66
b2150df1
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67#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
68
10ff1029 69extern inthand_t
9e0e3f85
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70 IDTVEC(ioapic_intr0),
71 IDTVEC(ioapic_intr1),
72 IDTVEC(ioapic_intr2),
73 IDTVEC(ioapic_intr3),
74 IDTVEC(ioapic_intr4),
75 IDTVEC(ioapic_intr5),
76 IDTVEC(ioapic_intr6),
77 IDTVEC(ioapic_intr7),
78 IDTVEC(ioapic_intr8),
79 IDTVEC(ioapic_intr9),
80 IDTVEC(ioapic_intr10),
81 IDTVEC(ioapic_intr11),
82 IDTVEC(ioapic_intr12),
83 IDTVEC(ioapic_intr13),
84 IDTVEC(ioapic_intr14),
85 IDTVEC(ioapic_intr15),
86 IDTVEC(ioapic_intr16),
87 IDTVEC(ioapic_intr17),
88 IDTVEC(ioapic_intr18),
89 IDTVEC(ioapic_intr19),
90 IDTVEC(ioapic_intr20),
91 IDTVEC(ioapic_intr21),
92 IDTVEC(ioapic_intr22),
93 IDTVEC(ioapic_intr23),
94 IDTVEC(ioapic_intr24),
95 IDTVEC(ioapic_intr25),
96 IDTVEC(ioapic_intr26),
97 IDTVEC(ioapic_intr27),
98 IDTVEC(ioapic_intr28),
99 IDTVEC(ioapic_intr29),
100 IDTVEC(ioapic_intr30),
101 IDTVEC(ioapic_intr31),
102 IDTVEC(ioapic_intr32),
103 IDTVEC(ioapic_intr33),
104 IDTVEC(ioapic_intr34),
105 IDTVEC(ioapic_intr35),
106 IDTVEC(ioapic_intr36),
107 IDTVEC(ioapic_intr37),
108 IDTVEC(ioapic_intr38),
109 IDTVEC(ioapic_intr39),
110 IDTVEC(ioapic_intr40),
111 IDTVEC(ioapic_intr41),
112 IDTVEC(ioapic_intr42),
113 IDTVEC(ioapic_intr43),
114 IDTVEC(ioapic_intr44),
115 IDTVEC(ioapic_intr45),
116 IDTVEC(ioapic_intr46),
117 IDTVEC(ioapic_intr47),
118 IDTVEC(ioapic_intr48),
119 IDTVEC(ioapic_intr49),
120 IDTVEC(ioapic_intr50),
121 IDTVEC(ioapic_intr51),
122 IDTVEC(ioapic_intr52),
123 IDTVEC(ioapic_intr53),
124 IDTVEC(ioapic_intr54),
125 IDTVEC(ioapic_intr55),
126 IDTVEC(ioapic_intr56),
127 IDTVEC(ioapic_intr57),
128 IDTVEC(ioapic_intr58),
129 IDTVEC(ioapic_intr59),
130 IDTVEC(ioapic_intr60),
131 IDTVEC(ioapic_intr61),
132 IDTVEC(ioapic_intr62),
133 IDTVEC(ioapic_intr63),
134 IDTVEC(ioapic_intr64),
135 IDTVEC(ioapic_intr65),
136 IDTVEC(ioapic_intr66),
137 IDTVEC(ioapic_intr67),
138 IDTVEC(ioapic_intr68),
139 IDTVEC(ioapic_intr69),
140 IDTVEC(ioapic_intr70),
141 IDTVEC(ioapic_intr71),
142 IDTVEC(ioapic_intr72),
143 IDTVEC(ioapic_intr73),
144 IDTVEC(ioapic_intr74),
145 IDTVEC(ioapic_intr75),
146 IDTVEC(ioapic_intr76),
147 IDTVEC(ioapic_intr77),
148 IDTVEC(ioapic_intr78),
149 IDTVEC(ioapic_intr79),
150 IDTVEC(ioapic_intr80),
151 IDTVEC(ioapic_intr81),
152 IDTVEC(ioapic_intr82),
153 IDTVEC(ioapic_intr83),
154 IDTVEC(ioapic_intr84),
155 IDTVEC(ioapic_intr85),
156 IDTVEC(ioapic_intr86),
157 IDTVEC(ioapic_intr87),
158 IDTVEC(ioapic_intr88),
159 IDTVEC(ioapic_intr89),
160 IDTVEC(ioapic_intr90),
161 IDTVEC(ioapic_intr91),
162 IDTVEC(ioapic_intr92),
163 IDTVEC(ioapic_intr93),
164 IDTVEC(ioapic_intr94),
165 IDTVEC(ioapic_intr95),
166 IDTVEC(ioapic_intr96),
167 IDTVEC(ioapic_intr97),
168 IDTVEC(ioapic_intr98),
169 IDTVEC(ioapic_intr99),
170 IDTVEC(ioapic_intr100),
171 IDTVEC(ioapic_intr101),
172 IDTVEC(ioapic_intr102),
173 IDTVEC(ioapic_intr103),
174 IDTVEC(ioapic_intr104),
175 IDTVEC(ioapic_intr105),
176 IDTVEC(ioapic_intr106),
177 IDTVEC(ioapic_intr107),
178 IDTVEC(ioapic_intr108),
179 IDTVEC(ioapic_intr109),
180 IDTVEC(ioapic_intr110),
181 IDTVEC(ioapic_intr111),
182 IDTVEC(ioapic_intr112),
183 IDTVEC(ioapic_intr113),
184 IDTVEC(ioapic_intr114),
185 IDTVEC(ioapic_intr115),
186 IDTVEC(ioapic_intr116),
187 IDTVEC(ioapic_intr117),
188 IDTVEC(ioapic_intr118),
189 IDTVEC(ioapic_intr119),
190 IDTVEC(ioapic_intr120),
191 IDTVEC(ioapic_intr121),
192 IDTVEC(ioapic_intr122),
193 IDTVEC(ioapic_intr123),
194 IDTVEC(ioapic_intr124),
195 IDTVEC(ioapic_intr125),
196 IDTVEC(ioapic_intr126),
197 IDTVEC(ioapic_intr127),
198 IDTVEC(ioapic_intr128),
199 IDTVEC(ioapic_intr129),
200 IDTVEC(ioapic_intr130),
201 IDTVEC(ioapic_intr131),
202 IDTVEC(ioapic_intr132),
203 IDTVEC(ioapic_intr133),
204 IDTVEC(ioapic_intr134),
205 IDTVEC(ioapic_intr135),
206 IDTVEC(ioapic_intr136),
207 IDTVEC(ioapic_intr137),
208 IDTVEC(ioapic_intr138),
209 IDTVEC(ioapic_intr139),
210 IDTVEC(ioapic_intr140),
211 IDTVEC(ioapic_intr141),
212 IDTVEC(ioapic_intr142),
213 IDTVEC(ioapic_intr143),
214 IDTVEC(ioapic_intr144),
215 IDTVEC(ioapic_intr145),
216 IDTVEC(ioapic_intr146),
217 IDTVEC(ioapic_intr147),
218 IDTVEC(ioapic_intr148),
219 IDTVEC(ioapic_intr149),
220 IDTVEC(ioapic_intr150),
221 IDTVEC(ioapic_intr151),
222 IDTVEC(ioapic_intr152),
223 IDTVEC(ioapic_intr153),
224 IDTVEC(ioapic_intr154),
225 IDTVEC(ioapic_intr155),
226 IDTVEC(ioapic_intr156),
227 IDTVEC(ioapic_intr157),
228 IDTVEC(ioapic_intr158),
229 IDTVEC(ioapic_intr159),
230 IDTVEC(ioapic_intr160),
231 IDTVEC(ioapic_intr161),
232 IDTVEC(ioapic_intr162),
233 IDTVEC(ioapic_intr163),
234 IDTVEC(ioapic_intr164),
235 IDTVEC(ioapic_intr165),
236 IDTVEC(ioapic_intr166),
237 IDTVEC(ioapic_intr167),
238 IDTVEC(ioapic_intr168),
239 IDTVEC(ioapic_intr169),
240 IDTVEC(ioapic_intr170),
241 IDTVEC(ioapic_intr171),
242 IDTVEC(ioapic_intr172),
243 IDTVEC(ioapic_intr173),
244 IDTVEC(ioapic_intr174),
245 IDTVEC(ioapic_intr175),
246 IDTVEC(ioapic_intr176),
247 IDTVEC(ioapic_intr177),
248 IDTVEC(ioapic_intr178),
249 IDTVEC(ioapic_intr179),
250 IDTVEC(ioapic_intr180),
251 IDTVEC(ioapic_intr181),
252 IDTVEC(ioapic_intr182),
253 IDTVEC(ioapic_intr183),
254 IDTVEC(ioapic_intr184),
255 IDTVEC(ioapic_intr185),
256 IDTVEC(ioapic_intr186),
257 IDTVEC(ioapic_intr187),
258 IDTVEC(ioapic_intr188),
259 IDTVEC(ioapic_intr189),
260 IDTVEC(ioapic_intr190),
261 IDTVEC(ioapic_intr191);
262
263static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
264 &IDTVEC(ioapic_intr0),
265 &IDTVEC(ioapic_intr1),
266 &IDTVEC(ioapic_intr2),
267 &IDTVEC(ioapic_intr3),
268 &IDTVEC(ioapic_intr4),
269 &IDTVEC(ioapic_intr5),
270 &IDTVEC(ioapic_intr6),
271 &IDTVEC(ioapic_intr7),
272 &IDTVEC(ioapic_intr8),
273 &IDTVEC(ioapic_intr9),
274 &IDTVEC(ioapic_intr10),
275 &IDTVEC(ioapic_intr11),
276 &IDTVEC(ioapic_intr12),
277 &IDTVEC(ioapic_intr13),
278 &IDTVEC(ioapic_intr14),
279 &IDTVEC(ioapic_intr15),
280 &IDTVEC(ioapic_intr16),
281 &IDTVEC(ioapic_intr17),
282 &IDTVEC(ioapic_intr18),
283 &IDTVEC(ioapic_intr19),
284 &IDTVEC(ioapic_intr20),
285 &IDTVEC(ioapic_intr21),
286 &IDTVEC(ioapic_intr22),
287 &IDTVEC(ioapic_intr23),
288 &IDTVEC(ioapic_intr24),
289 &IDTVEC(ioapic_intr25),
290 &IDTVEC(ioapic_intr26),
291 &IDTVEC(ioapic_intr27),
292 &IDTVEC(ioapic_intr28),
293 &IDTVEC(ioapic_intr29),
294 &IDTVEC(ioapic_intr30),
295 &IDTVEC(ioapic_intr31),
296 &IDTVEC(ioapic_intr32),
297 &IDTVEC(ioapic_intr33),
298 &IDTVEC(ioapic_intr34),
299 &IDTVEC(ioapic_intr35),
300 &IDTVEC(ioapic_intr36),
301 &IDTVEC(ioapic_intr37),
302 &IDTVEC(ioapic_intr38),
303 &IDTVEC(ioapic_intr39),
304 &IDTVEC(ioapic_intr40),
305 &IDTVEC(ioapic_intr41),
306 &IDTVEC(ioapic_intr42),
307 &IDTVEC(ioapic_intr43),
308 &IDTVEC(ioapic_intr44),
309 &IDTVEC(ioapic_intr45),
310 &IDTVEC(ioapic_intr46),
311 &IDTVEC(ioapic_intr47),
312 &IDTVEC(ioapic_intr48),
313 &IDTVEC(ioapic_intr49),
314 &IDTVEC(ioapic_intr50),
315 &IDTVEC(ioapic_intr51),
316 &IDTVEC(ioapic_intr52),
317 &IDTVEC(ioapic_intr53),
318 &IDTVEC(ioapic_intr54),
319 &IDTVEC(ioapic_intr55),
320 &IDTVEC(ioapic_intr56),
321 &IDTVEC(ioapic_intr57),
322 &IDTVEC(ioapic_intr58),
323 &IDTVEC(ioapic_intr59),
324 &IDTVEC(ioapic_intr60),
325 &IDTVEC(ioapic_intr61),
326 &IDTVEC(ioapic_intr62),
327 &IDTVEC(ioapic_intr63),
328 &IDTVEC(ioapic_intr64),
329 &IDTVEC(ioapic_intr65),
330 &IDTVEC(ioapic_intr66),
331 &IDTVEC(ioapic_intr67),
332 &IDTVEC(ioapic_intr68),
333 &IDTVEC(ioapic_intr69),
334 &IDTVEC(ioapic_intr70),
335 &IDTVEC(ioapic_intr71),
336 &IDTVEC(ioapic_intr72),
337 &IDTVEC(ioapic_intr73),
338 &IDTVEC(ioapic_intr74),
339 &IDTVEC(ioapic_intr75),
340 &IDTVEC(ioapic_intr76),
341 &IDTVEC(ioapic_intr77),
342 &IDTVEC(ioapic_intr78),
343 &IDTVEC(ioapic_intr79),
344 &IDTVEC(ioapic_intr80),
345 &IDTVEC(ioapic_intr81),
346 &IDTVEC(ioapic_intr82),
347 &IDTVEC(ioapic_intr83),
348 &IDTVEC(ioapic_intr84),
349 &IDTVEC(ioapic_intr85),
350 &IDTVEC(ioapic_intr86),
351 &IDTVEC(ioapic_intr87),
352 &IDTVEC(ioapic_intr88),
353 &IDTVEC(ioapic_intr89),
354 &IDTVEC(ioapic_intr90),
355 &IDTVEC(ioapic_intr91),
356 &IDTVEC(ioapic_intr92),
357 &IDTVEC(ioapic_intr93),
358 &IDTVEC(ioapic_intr94),
359 &IDTVEC(ioapic_intr95),
360 &IDTVEC(ioapic_intr96),
361 &IDTVEC(ioapic_intr97),
362 &IDTVEC(ioapic_intr98),
363 &IDTVEC(ioapic_intr99),
364 &IDTVEC(ioapic_intr100),
365 &IDTVEC(ioapic_intr101),
366 &IDTVEC(ioapic_intr102),
367 &IDTVEC(ioapic_intr103),
368 &IDTVEC(ioapic_intr104),
369 &IDTVEC(ioapic_intr105),
370 &IDTVEC(ioapic_intr106),
371 &IDTVEC(ioapic_intr107),
372 &IDTVEC(ioapic_intr108),
373 &IDTVEC(ioapic_intr109),
374 &IDTVEC(ioapic_intr110),
375 &IDTVEC(ioapic_intr111),
376 &IDTVEC(ioapic_intr112),
377 &IDTVEC(ioapic_intr113),
378 &IDTVEC(ioapic_intr114),
379 &IDTVEC(ioapic_intr115),
380 &IDTVEC(ioapic_intr116),
381 &IDTVEC(ioapic_intr117),
382 &IDTVEC(ioapic_intr118),
383 &IDTVEC(ioapic_intr119),
384 &IDTVEC(ioapic_intr120),
385 &IDTVEC(ioapic_intr121),
386 &IDTVEC(ioapic_intr122),
387 &IDTVEC(ioapic_intr123),
388 &IDTVEC(ioapic_intr124),
389 &IDTVEC(ioapic_intr125),
390 &IDTVEC(ioapic_intr126),
391 &IDTVEC(ioapic_intr127),
392 &IDTVEC(ioapic_intr128),
393 &IDTVEC(ioapic_intr129),
394 &IDTVEC(ioapic_intr130),
395 &IDTVEC(ioapic_intr131),
396 &IDTVEC(ioapic_intr132),
397 &IDTVEC(ioapic_intr133),
398 &IDTVEC(ioapic_intr134),
399 &IDTVEC(ioapic_intr135),
400 &IDTVEC(ioapic_intr136),
401 &IDTVEC(ioapic_intr137),
402 &IDTVEC(ioapic_intr138),
403 &IDTVEC(ioapic_intr139),
404 &IDTVEC(ioapic_intr140),
405 &IDTVEC(ioapic_intr141),
406 &IDTVEC(ioapic_intr142),
407 &IDTVEC(ioapic_intr143),
408 &IDTVEC(ioapic_intr144),
409 &IDTVEC(ioapic_intr145),
410 &IDTVEC(ioapic_intr146),
411 &IDTVEC(ioapic_intr147),
412 &IDTVEC(ioapic_intr148),
413 &IDTVEC(ioapic_intr149),
414 &IDTVEC(ioapic_intr150),
415 &IDTVEC(ioapic_intr151),
416 &IDTVEC(ioapic_intr152),
417 &IDTVEC(ioapic_intr153),
418 &IDTVEC(ioapic_intr154),
419 &IDTVEC(ioapic_intr155),
420 &IDTVEC(ioapic_intr156),
421 &IDTVEC(ioapic_intr157),
422 &IDTVEC(ioapic_intr158),
423 &IDTVEC(ioapic_intr159),
424 &IDTVEC(ioapic_intr160),
425 &IDTVEC(ioapic_intr161),
426 &IDTVEC(ioapic_intr162),
427 &IDTVEC(ioapic_intr163),
428 &IDTVEC(ioapic_intr164),
429 &IDTVEC(ioapic_intr165),
430 &IDTVEC(ioapic_intr166),
431 &IDTVEC(ioapic_intr167),
432 &IDTVEC(ioapic_intr168),
433 &IDTVEC(ioapic_intr169),
434 &IDTVEC(ioapic_intr170),
435 &IDTVEC(ioapic_intr171),
436 &IDTVEC(ioapic_intr172),
437 &IDTVEC(ioapic_intr173),
438 &IDTVEC(ioapic_intr174),
439 &IDTVEC(ioapic_intr175),
440 &IDTVEC(ioapic_intr176),
441 &IDTVEC(ioapic_intr177),
442 &IDTVEC(ioapic_intr178),
443 &IDTVEC(ioapic_intr179),
444 &IDTVEC(ioapic_intr180),
445 &IDTVEC(ioapic_intr181),
446 &IDTVEC(ioapic_intr182),
447 &IDTVEC(ioapic_intr183),
448 &IDTVEC(ioapic_intr184),
449 &IDTVEC(ioapic_intr185),
450 &IDTVEC(ioapic_intr186),
451 &IDTVEC(ioapic_intr187),
452 &IDTVEC(ioapic_intr188),
453 &IDTVEC(ioapic_intr189),
454 &IDTVEC(ioapic_intr190),
455 &IDTVEC(ioapic_intr191)
c571da4a 456};
10ff1029 457
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458#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
459
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460static struct ioapic_irqmap {
461 int im_type; /* IOAPIC_IMT_ */
462 enum intr_trigger im_trig;
f6915355 463 enum intr_polarity im_pola;
a3dd9120 464 int im_gsi;
be98308a 465 int im_msi_base;
d1ae7328 466 uint32_t im_flags; /* IOAPIC_IMF_ */
2e62e7a5 467} ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
a3dd9120 468
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469static struct lwkt_token ioapic_irqmap_tok =
470 LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token);
471
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472#define IOAPIC_IMT_UNUSED 0
473#define IOAPIC_IMT_RESERVED 1
2a32da90 474#define IOAPIC_IMT_LEGACY 2
474ba684 475#define IOAPIC_IMT_SYSCALL 3
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476#define IOAPIC_IMT_SHADOW 4
477#define IOAPIC_IMT_MSI 5
6bf6f751 478#define IOAPIC_IMT_MSIX 6
a3dd9120 479
0f3e19b1 480#define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \
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481 (map)->im_type != IOAPIC_IMT_SYSCALL && \
482 (map)->im_type != IOAPIC_IMT_SHADOW)
0f3e19b1 483
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484#define IOAPIC_IMF_CONF 0x1
485
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486extern void IOAPIC_INTREN(int);
487extern void IOAPIC_INTRDIS(int);
488
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489extern int imcr_present;
490
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491static void ioapic_abi_intr_enable(int);
492static void ioapic_abi_intr_disable(int);
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493static void ioapic_abi_intr_setup(int, int);
494static void ioapic_abi_intr_teardown(int);
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495
496static void ioapic_abi_legacy_intr_config(int,
780a6eec 497 enum intr_trigger, enum intr_polarity);
bec969af 498static int ioapic_abi_legacy_intr_cpuid(int);
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499static int ioapic_abi_legacy_intr_find(int,
500 enum intr_trigger, enum intr_polarity);
501static int ioapic_abi_legacy_intr_find_bygsi(int,
502 enum intr_trigger, enum intr_polarity);
35b2edcb 503
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504static int ioapic_abi_msi_alloc(int [], int, int);
505static void ioapic_abi_msi_release(const int [], int, int);
506static void ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int);
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507static int ioapic_abi_msix_alloc(int *, int);
508static void ioapic_abi_msix_release(int, int);
509
510static int ioapic_abi_msi_alloc_intern(int, const char *,
511 int [], int, int);
512static void ioapic_abi_msi_release_intern(int, const char *,
513 const int [], int, int);
be98308a 514
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515static void ioapic_abi_finalize(void);
516static void ioapic_abi_cleanup(void);
517static void ioapic_abi_setdefault(void);
518static void ioapic_abi_stabilize(void);
519static void ioapic_abi_initmap(void);
0f3e19b1 520static void ioapic_abi_rman_setup(struct rman *);
9e0e3f85 521
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522static int ioapic_abi_gsi_cpuid(int, int);
523
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524struct machintr_abi MachIntrABI_IOAPIC = {
525 MACHINTR_IOAPIC,
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526
527 .intr_disable = ioapic_abi_intr_disable,
528 .intr_enable = ioapic_abi_intr_enable,
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529 .intr_setup = ioapic_abi_intr_setup,
530 .intr_teardown = ioapic_abi_intr_teardown,
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531
532 .legacy_intr_config = ioapic_abi_legacy_intr_config,
533 .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid,
86d692fe
SZ
534 .legacy_intr_find = ioapic_abi_legacy_intr_find,
535 .legacy_intr_find_bygsi = ioapic_abi_legacy_intr_find_bygsi,
35b2edcb 536
be98308a
SZ
537 .msi_alloc = ioapic_abi_msi_alloc,
538 .msi_release = ioapic_abi_msi_release,
539 .msi_map = ioapic_abi_msi_map,
6bf6f751
SZ
540 .msix_alloc = ioapic_abi_msix_alloc,
541 .msix_release = ioapic_abi_msix_release,
be98308a 542
780a6eec
SZ
543 .finalize = ioapic_abi_finalize,
544 .cleanup = ioapic_abi_cleanup,
545 .setdefault = ioapic_abi_setdefault,
546 .stabilize = ioapic_abi_stabilize,
0f3e19b1
SZ
547 .initmap = ioapic_abi_initmap,
548 .rman_setup = ioapic_abi_rman_setup
37e7efec
MD
549};
550
6b809ec7 551static int ioapic_abi_extint_irq = -1;
2a32da90 552static int ioapic_abi_legacy_irq_max;
cae71b2c 553static int ioapic_abi_gsi_balance;
be98308a 554static int ioapic_abi_msi_start; /* NOTE: for testing only */
6b809ec7 555
7a54dec9 556struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
fa6eddaf
SZ
557
558static void
35b2edcb 559ioapic_abi_intr_enable(int irq)
fa6eddaf 560{
5157c933
SZ
561 const struct ioapic_irqmap *map;
562
563 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
ed20d0e3 564 ("ioapic enable, invalid irq %d", irq));
5157c933
SZ
565
566 map = &ioapic_irqmaps[mycpuid][irq];
567 KASSERT(IOAPIC_IMT_ISHWI(map),
ed20d0e3 568 ("ioapic enable, not hwi irq %d, type %d, cpu%d",
5157c933 569 irq, map->im_type, mycpuid));
2a32da90 570 if (map->im_type != IOAPIC_IMT_LEGACY)
fa6eddaf 571 return;
5157c933 572
fa6eddaf
SZ
573 IOAPIC_INTREN(irq);
574}
575
576static void
35b2edcb 577ioapic_abi_intr_disable(int irq)
fa6eddaf 578{
5157c933
SZ
579 const struct ioapic_irqmap *map;
580
581 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
ed20d0e3 582 ("ioapic disable, invalid irq %d", irq));
5157c933
SZ
583
584 map = &ioapic_irqmaps[mycpuid][irq];
585 KASSERT(IOAPIC_IMT_ISHWI(map),
ed20d0e3 586 ("ioapic disable, not hwi irq %d, type %d, cpu%d",
5157c933 587 irq, map->im_type, mycpuid));
2a32da90 588 if (map->im_type != IOAPIC_IMT_LEGACY)
fa6eddaf 589 return;
5157c933 590
fa6eddaf
SZ
591 IOAPIC_INTRDIS(irq);
592}
593
37e7efec 594static void
780a6eec 595ioapic_abi_finalize(void)
37e7efec 596{
e0918665 597 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 598 KKASSERT(ioapic_enable);
10db3cc6 599
54e1df6b
SZ
600 /*
601 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 602 * from the BSP.
54e1df6b 603 */
9d758cc4 604 if (imcr_present) {
54e1df6b
SZ
605 outb(0x22, 0x70); /* select IMCR */
606 outb(0x23, 0x01); /* disconnect 8259 */
607 }
37e7efec
MD
608}
609
0b692e79
MD
610/*
611 * This routine is called after physical interrupts are enabled but before
612 * the critical section is released. We need to clean out any interrupts
613 * that had already been posted to the cpu.
614 */
615static void
780a6eec 616ioapic_abi_cleanup(void)
0b692e79 617{
c263294b 618 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
0b692e79
MD
619}
620
7bf5fa56
SZ
621/* Must never be called */
622static void
780a6eec 623ioapic_abi_stabilize(void)
7bf5fa56 624{
ed20d0e3 625 panic("ioapic_stabilize() is called");
7bf5fa56
SZ
626}
627
f416026e
SZ
628static void
629ioapic_abi_intr_setup(int intr, int flags)
10ff1029 630{
ba66d506 631 const struct ioapic_irqmap *map;
f416026e 632 int vector, select;
54e1df6b
SZ
633 uint32_t value;
634 u_long ef;
10ff1029 635
ba66d506 636 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 637 ("ioapic setup, invalid irq %d", intr));
ba66d506
SZ
638
639 map = &ioapic_irqmaps[mycpuid][intr];
640 KASSERT(IOAPIC_IMT_ISHWI(map),
641 ("ioapic setup, not hwi irq %d, type %d, cpu%d",
642 intr, map->im_type, mycpuid));
2a32da90 643 if (map->im_type != IOAPIC_IMT_LEGACY)
ba66d506 644 return;
ba66d506
SZ
645
646 KASSERT(ioapic_irqs[intr].io_addr != NULL,
ed20d0e3 647 ("ioapic setup, no GSI information, irq %d", intr));
f416026e
SZ
648
649 ef = read_eflags();
650 cpu_disable_intr();
651
652 vector = IDT_OFFSET + intr;
f416026e
SZ
653
654 /*
655 * Now reprogram the vector in the IO APIC. In order to avoid
656 * losing an EOI for a level interrupt, which is vector based,
657 * make sure that the IO APIC is programmed for edge-triggering
658 * first, then reprogrammed with the new vector. This should
659 * clear the IRR bit.
660 */
661 imen_lock();
662
663 select = ioapic_irqs[intr].io_idx;
664 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
665 value |= IOART_INTMSET;
666
667 ioapic_write(ioapic_irqs[intr].io_addr, select,
668 (value & ~APIC_TRIGMOD_MASK));
669 ioapic_write(ioapic_irqs[intr].io_addr, select,
670 (value & ~IOART_INTVEC) | vector);
671
672 imen_unlock();
673
eaeca813 674 IOAPIC_INTREN(intr);
f416026e
SZ
675
676 write_eflags(ef);
677}
678
679static void
680ioapic_abi_intr_teardown(int intr)
681{
ba66d506 682 const struct ioapic_irqmap *map;
f416026e
SZ
683 int vector, select;
684 uint32_t value;
685 u_long ef;
10ff1029 686
ba66d506 687 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 688 ("ioapic teardown, invalid irq %d", intr));
ba66d506
SZ
689
690 map = &ioapic_irqmaps[mycpuid][intr];
691 KASSERT(IOAPIC_IMT_ISHWI(map),
692 ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
693 intr, map->im_type, mycpuid));
2a32da90 694 if (map->im_type != IOAPIC_IMT_LEGACY)
ba66d506 695 return;
ba66d506
SZ
696
697 KASSERT(ioapic_irqs[intr].io_addr != NULL,
ed20d0e3 698 ("ioapic teardown, no GSI information, irq %d", intr));
7a54dec9 699
54e1df6b
SZ
700 ef = read_eflags();
701 cpu_disable_intr();
10ff1029 702
f416026e
SZ
703 /*
704 * Teardown an interrupt vector. The vector should already be
705 * installed in the cpu's IDT, but make sure.
706 */
eaeca813 707 IOAPIC_INTRDIS(intr);
35408d22 708
f416026e 709 vector = IDT_OFFSET + intr;
f416026e
SZ
710
711 /*
712 * In order to avoid losing an EOI for a level interrupt, which
713 * is vector based, make sure that the IO APIC is programmed for
714 * edge-triggering first, then reprogrammed with the new vector.
715 * This should clear the IRR bit.
716 */
717 imen_lock();
718
719 select = ioapic_irqs[intr].io_idx;
720 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
721
722 ioapic_write(ioapic_irqs[intr].io_addr, select,
723 (value & ~APIC_TRIGMOD_MASK));
724 ioapic_write(ioapic_irqs[intr].io_addr, select,
725 (value & ~IOART_INTVEC) | vector);
726
727 imen_unlock();
10ff1029 728
54e1df6b 729 write_eflags(ef);
54e1df6b 730}
06f5be02 731
10db3cc6 732static void
780a6eec 733ioapic_abi_setdefault(void)
10db3cc6
SZ
734{
735 int intr;
736
9e0e3f85 737 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 738 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 739 continue;
9e0e3f85 740 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
10db3cc6
SZ
741 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
742 }
743}
744
a3dd9120 745static void
780a6eec 746ioapic_abi_initmap(void)
a3dd9120 747{
2e62e7a5 748 int cpu;
a3dd9120 749
cae71b2c
SZ
750 kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
751
be98308a
SZ
752 kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start);
753 ioapic_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */
754
2e62e7a5
SZ
755 /*
756 * NOTE: ncpus is not ready yet
757 */
758 for (cpu = 0; cpu < MAXCPU; ++cpu) {
759 int i;
760
be98308a 761 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
2e62e7a5 762 ioapic_irqmaps[cpu][i].im_gsi = -1;
be98308a
SZ
763 ioapic_irqmaps[cpu][i].im_msi_base = -1;
764 }
2e62e7a5
SZ
765 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
766 IOAPIC_IMT_SYSCALL;
767 }
a3dd9120
SZ
768}
769
929c940f 770void
027bbbfe 771ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
929c940f
SZ
772 enum intr_polarity pola)
773{
7a54dec9 774 struct ioapic_irqinfo *info;
929c940f
SZ
775 struct ioapic_irqmap *map;
776 void *ioaddr;
9dba15ae 777 int pin, cpuid;
929c940f
SZ
778
779 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
780 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ
781
782 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
2a32da90
SZ
783 if (irq > ioapic_abi_legacy_irq_max)
784 ioapic_abi_legacy_irq_max = irq;
512ddf89 785
2e62e7a5
SZ
786 cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
787
788 map = &ioapic_irqmaps[cpuid][irq];
929c940f
SZ
789
790 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
2a32da90 791 map->im_type = IOAPIC_IMT_LEGACY;
929c940f
SZ
792
793 map->im_gsi = gsi;
794 map->im_trig = trig;
795 map->im_pola = pola;
796
797 if (bootverbose) {
4ecd5d4d
SZ
798 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
799 irq, map->im_gsi,
800 intr_str_trigger(map->im_trig),
801 intr_str_polarity(map->im_pola));
929c940f
SZ
802 }
803
d1ae7328
SZ
804 pin = ioapic_gsi_pin(map->im_gsi);
805 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 806
7a54dec9 807 info = &ioapic_irqs[irq];
929c940f 808
7bceaa10
SZ
809 imen_lock();
810
7a54dec9
SZ
811 info->io_addr = ioaddr;
812 info->io_idx = IOAPIC_REDTBL + (2 * pin);
813 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 814 if (map->im_trig == INTR_TRIGGER_LEVEL)
7a54dec9 815 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
SZ
816
817 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
9dba15ae 818 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
819
820 imen_unlock();
d1ae7328
SZ
821}
822
4a913811 823void
027bbbfe 824ioapic_fixup_legacy_irqmaps(void)
4a913811 825{
2e62e7a5
SZ
826 int cpu;
827
2a32da90
SZ
828 ioapic_abi_legacy_irq_max += 1;
829 if (bootverbose) {
830 kprintf("IOAPIC: legacy irq max %d\n",
831 ioapic_abi_legacy_irq_max);
832 }
1973dfbc 833
2e62e7a5
SZ
834 for (cpu = 0; cpu < ncpus; ++cpu) {
835 int i;
4a913811 836
2a32da90 837 for (i = 0; i < ioapic_abi_legacy_irq_max; ++i) {
2e62e7a5 838 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
4a913811 839
2e62e7a5
SZ
840 if (map->im_type == IOAPIC_IMT_UNUSED) {
841 map->im_type = IOAPIC_IMT_RESERVED;
842 if (bootverbose) {
843 kprintf("IOAPIC: "
844 "cpu%d irq %d reserved\n", cpu, i);
845 }
846 }
4a913811
SZ
847 }
848 }
849}
850
86d692fe
SZ
851static int
852ioapic_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig,
027bbbfe 853 enum intr_polarity pola)
e90e7ac4 854{
2e62e7a5 855 int cpu;
e90e7ac4 856
86d692fe
SZ
857#ifdef INVARIANTS
858 if (trig == INTR_TRIGGER_CONFORM) {
859 KKASSERT(pola == INTR_POLARITY_CONFORM);
860 } else {
861 KKASSERT(trig == INTR_TRIGGER_EDGE ||
862 trig == INTR_TRIGGER_LEVEL);
863 KKASSERT(pola == INTR_POLARITY_HIGH ||
864 pola == INTR_POLARITY_LOW);
865 }
866#endif
e90e7ac4 867
2e62e7a5
SZ
868 for (cpu = 0; cpu < ncpus; ++cpu) {
869 int irq;
e90e7ac4 870
2a32da90 871 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) {
2e62e7a5
SZ
872 const struct ioapic_irqmap *map =
873 &ioapic_irqmaps[cpu][irq];
e90e7ac4 874
2e62e7a5 875 if (map->im_gsi == gsi) {
2a32da90 876 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY);
2e62e7a5 877
86d692fe
SZ
878 if ((map->im_flags & IOAPIC_IMF_CONF) &&
879 trig != INTR_TRIGGER_CONFORM &&
880 pola != INTR_POLARITY_CONFORM) {
2e62e7a5
SZ
881 if (map->im_trig != trig ||
882 map->im_pola != pola)
883 return -1;
884 }
885 return irq;
e90e7ac4 886 }
e90e7ac4
SZ
887 }
888 }
889 return -1;
890}
891
86d692fe
SZ
892static int
893ioapic_abi_legacy_intr_find(int irq, enum intr_trigger trig,
027bbbfe 894 enum intr_polarity pola)
e90e7ac4 895{
2e62e7a5 896 int cpu;
e90e7ac4 897
86d692fe
SZ
898#ifdef INVARIANTS
899 if (trig == INTR_TRIGGER_CONFORM) {
900 KKASSERT(pola == INTR_POLARITY_CONFORM);
901 } else {
902 KKASSERT(trig == INTR_TRIGGER_EDGE ||
903 trig == INTR_TRIGGER_LEVEL);
904 KKASSERT(pola == INTR_POLARITY_HIGH ||
905 pola == INTR_POLARITY_LOW);
906 }
907#endif
e90e7ac4 908
2a32da90 909 if (irq < 0 || irq >= ioapic_abi_legacy_irq_max)
e90e7ac4 910 return -1;
e90e7ac4 911
2e62e7a5
SZ
912 for (cpu = 0; cpu < ncpus; ++cpu) {
913 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
e90e7ac4 914
2a32da90 915 if (map->im_type == IOAPIC_IMT_LEGACY) {
86d692fe
SZ
916 if ((map->im_flags & IOAPIC_IMF_CONF) &&
917 trig != INTR_TRIGGER_CONFORM &&
918 pola != INTR_POLARITY_CONFORM) {
2e62e7a5
SZ
919 if (map->im_trig != trig ||
920 map->im_pola != pola)
921 return -1;
922 }
923 return irq;
924 }
e90e7ac4 925 }
2e62e7a5 926 return -1;
e90e7ac4
SZ
927}
928
d1ae7328 929static void
bec969af
SZ
930ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig,
931 enum intr_polarity pola)
d1ae7328 932{
7a54dec9 933 struct ioapic_irqinfo *info;
2e62e7a5 934 struct ioapic_irqmap *map = NULL;
d1ae7328 935 void *ioaddr;
9dba15ae 936 int pin, cpuid;
d1ae7328 937
d1ae7328
SZ
938 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
939 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328 940
2a32da90 941 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
2e62e7a5
SZ
942 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
943 map = &ioapic_irqmaps[cpuid][irq];
2a32da90 944 if (map->im_type == IOAPIC_IMT_LEGACY)
2e62e7a5
SZ
945 break;
946 }
947 KKASSERT(cpuid < ncpus);
d1ae7328 948
7962296e 949#ifdef notyet
d1ae7328
SZ
950 if (map->im_flags & IOAPIC_IMF_CONF) {
951 if (trig != map->im_trig) {
ed20d0e3 952 panic("ioapic_intr_config: trig %s -> %s",
4ecd5d4d
SZ
953 intr_str_trigger(map->im_trig),
954 intr_str_trigger(trig));
d1ae7328
SZ
955 }
956 if (pola != map->im_pola) {
ed20d0e3 957 panic("ioapic_intr_config: pola %s -> %s",
4ecd5d4d
SZ
958 intr_str_polarity(map->im_pola),
959 intr_str_polarity(pola));
d1ae7328
SZ
960 }
961 return;
962 }
7962296e 963#endif
d1ae7328
SZ
964 map->im_flags |= IOAPIC_IMF_CONF;
965
966 if (trig == map->im_trig && pola == map->im_pola)
967 return;
968
969 if (bootverbose) {
4ecd5d4d
SZ
970 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
971 irq, map->im_gsi,
972 intr_str_trigger(map->im_trig),
973 intr_str_polarity(map->im_pola),
974 intr_str_trigger(trig),
975 intr_str_polarity(pola));
d1ae7328 976 }
d1ae7328
SZ
977 map->im_trig = trig;
978 map->im_pola = pola;
979
980 pin = ioapic_gsi_pin(map->im_gsi);
981 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
982
7a54dec9 983 info = &ioapic_irqs[irq];
d1ae7328 984
7bceaa10
SZ
985 imen_lock();
986
7a54dec9 987 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 988 if (map->im_trig == INTR_TRIGGER_LEVEL)
7a54dec9 989 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 990
ecec8ddc 991 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
9dba15ae 992 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
993
994 imen_unlock();
929c940f
SZ
995}
996
6b809ec7 997int
027bbbfe 998ioapic_conf_legacy_extint(int irq)
6b809ec7 999{
7a54dec9 1000 struct ioapic_irqinfo *info;
6b809ec7
SZ
1001 struct ioapic_irqmap *map;
1002 void *ioaddr;
1003 int pin, error, vec;
1004
9dba15ae
SZ
1005 /* XXX only irq0 is allowed */
1006 KKASSERT(irq == 0);
1007
6b809ec7
SZ
1008 vec = IDT_OFFSET + irq;
1009
1010 if (ioapic_abi_extint_irq == irq)
1011 return 0;
1012 else if (ioapic_abi_extint_irq >= 0)
1013 return EEXIST;
1014
1015 error = icu_ioapic_extint(irq, vec);
1016 if (error)
1017 return error;
1018
2e62e7a5
SZ
1019 /* ExtINT is always targeted to cpu0 */
1020 map = &ioapic_irqmaps[0][irq];
6b809ec7
SZ
1021
1022 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
2a32da90
SZ
1023 map->im_type == IOAPIC_IMT_LEGACY);
1024 if (map->im_type == IOAPIC_IMT_LEGACY) {
6b809ec7
SZ
1025 if (map->im_flags & IOAPIC_IMF_CONF)
1026 return EEXIST;
1027 }
1028 ioapic_abi_extint_irq = irq;
1029
2a32da90 1030 map->im_type = IOAPIC_IMT_LEGACY;
6b809ec7
SZ
1031 map->im_trig = INTR_TRIGGER_EDGE;
1032 map->im_pola = INTR_POLARITY_HIGH;
1033 map->im_flags = IOAPIC_IMF_CONF;
1034
1035 map->im_gsi = ioapic_extpin_gsi();
1036 KKASSERT(map->im_gsi >= 0);
1037
1038 if (bootverbose) {
4ecd5d4d
SZ
1039 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
1040 irq, map->im_gsi,
1041 intr_str_trigger(map->im_trig),
1042 intr_str_polarity(map->im_pola));
6b809ec7
SZ
1043 }
1044
1045 pin = ioapic_gsi_pin(map->im_gsi);
1046 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1047
7a54dec9 1048 info = &ioapic_irqs[irq];
6b809ec7
SZ
1049
1050 imen_lock();
1051
7a54dec9
SZ
1052 info->io_addr = ioaddr;
1053 info->io_idx = IOAPIC_REDTBL + (2 * pin);
1054 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ
1055
1056 ioapic_extpin_setup(ioaddr, pin, vec);
1057
1058 imen_unlock();
1059
1060 return 0;
1061}
a05c798c
SZ
1062
1063static int
bec969af 1064ioapic_abi_legacy_intr_cpuid(int irq)
a05c798c 1065{
2e62e7a5
SZ
1066 const struct ioapic_irqmap *map = NULL;
1067 int cpuid;
9dba15ae 1068
2a32da90 1069 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
9dba15ae 1070
2e62e7a5
SZ
1071 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1072 map = &ioapic_irqmaps[cpuid][irq];
2a32da90 1073 if (map->im_type == IOAPIC_IMT_LEGACY)
2e62e7a5 1074 return cpuid;
9dba15ae
SZ
1075 }
1076
2e62e7a5
SZ
1077 /* XXX some drivers tries to peek at reserved IRQs */
1078 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1079 map = &ioapic_irqmaps[cpuid][irq];
1080 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1081 }
1082 return 0;
9dba15ae
SZ
1083}
1084
1085static int
1086ioapic_abi_gsi_cpuid(int irq, int gsi)
1087{
1088 char envpath[32];
1089 int cpuid = -1;
1090
1091 KKASSERT(gsi >= 0);
1092
1093 if (irq == 0 || gsi == 0) {
c80b6136
SZ
1094 if (bootverbose) {
1095 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1096 irq, gsi);
1097 }
9dba15ae
SZ
1098 return 0;
1099 }
1100
1101 if (irq == acpi_sci_irqno()) {
c80b6136
SZ
1102 if (bootverbose) {
1103 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1104 irq, gsi);
1105 }
9dba15ae
SZ
1106 return 0;
1107 }
1108
1109 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1110 kgetenv_int(envpath, &cpuid);
1111
1112 if (cpuid < 0) {
b18d6a13
SZ
1113 if (!ioapic_abi_gsi_balance) {
1114 if (bootverbose) {
1115 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1116 "(fixed)\n", irq, gsi);
1117 }
1118 return 0;
1119 }
1120
9dba15ae 1121 cpuid = gsi % ncpus;
c80b6136
SZ
1122 if (bootverbose) {
1123 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1124 irq, gsi, cpuid);
1125 }
9dba15ae
SZ
1126 } else if (cpuid >= ncpus) {
1127 cpuid = ncpus - 1;
c80b6136
SZ
1128 if (bootverbose) {
1129 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1130 irq, gsi, cpuid);
1131 }
9dba15ae 1132 } else {
c80b6136
SZ
1133 if (bootverbose) {
1134 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1135 irq, gsi, cpuid);
1136 }
9dba15ae
SZ
1137 }
1138 return cpuid;
a05c798c 1139}
0f3e19b1
SZ
1140
1141static void
1142ioapic_abi_rman_setup(struct rman *rm)
1143{
1144 int start, end, i;
1145
1146 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1147 ("invalid rman cpuid %d", rm->rm_cpuid));
1148
1149 start = end = -1;
1150 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1151 const struct ioapic_irqmap *map =
1152 &ioapic_irqmaps[rm->rm_cpuid][i];
1153
1154 if (start < 0) {
1155 if (IOAPIC_IMT_ISHWI(map))
1156 start = end = i;
1157 } else {
1158 if (IOAPIC_IMT_ISHWI(map)) {
1159 end = i;
1160 } else {
1161 KKASSERT(end >= 0);
1162 if (bootverbose) {
1163 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1164 rm->rm_cpuid, start, end);
1165 }
1166 if (rman_manage_region(rm, start, end)) {
1167 panic("rman_manage_region"
1168 "(cpu%d %d - %d)", rm->rm_cpuid,
1169 start, end);
1170 }
1171 start = end = -1;
1172 }
1173 }
1174 }
1175 if (start >= 0) {
1176 KKASSERT(end >= 0);
1177 if (bootverbose) {
1178 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1179 rm->rm_cpuid, start, end);
1180 }
1181 if (rman_manage_region(rm, start, end)) {
1182 panic("rman_manage_region(cpu%d %d - %d)",
1183 rm->rm_cpuid, start, end);
1184 }
1185 }
1186}
be98308a
SZ
1187
1188static int
6bf6f751
SZ
1189ioapic_abi_msi_alloc_intern(int type, const char *desc,
1190 int intrs[], int count, int cpuid)
be98308a
SZ
1191{
1192 int i, error;
1193
1194 KASSERT(cpuid >= 0 && cpuid < ncpus,
1195 ("invalid cpuid %d", cpuid));
1196
ed20d0e3 1197 KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
be98308a 1198 KASSERT((count & (count - 1)) == 0,
ed20d0e3 1199 ("count %d is not power of 2", count));
be98308a
SZ
1200
1201 lwkt_gettoken(&ioapic_irqmap_tok);
1202
1203 /*
1204 * NOTE:
1205 * Since IDT_OFFSET is 32, which is the maximum valid 'count',
1206 * we do not need to find out the first properly aligned
1207 * interrupt vector.
1208 */
1209
1210 error = EMSGSIZE;
1211 for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) {
1212 int j;
1213
1214 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED)
1215 continue;
1216
1217 for (j = 1; j < count; ++j) {
1218 if (ioapic_irqmaps[cpuid][i + j].im_type !=
1219 IOAPIC_IMT_UNUSED)
1220 break;
1221 }
1222 if (j != count)
1223 continue;
1224
1225 for (j = 0; j < count; ++j) {
1226 int intr = i + j, cpu;
1227
1228 for (cpu = 0; cpu < ncpus; ++cpu) {
1229 struct ioapic_irqmap *map;
1230
1231 map = &ioapic_irqmaps[cpu][intr];
1232 KASSERT(map->im_msi_base < 0,
ed20d0e3 1233 ("intr %d cpu%d, stale %s-base %d",
6bf6f751 1234 intr, cpu, desc, map->im_msi_base));
be98308a 1235 KASSERT(map->im_type == IOAPIC_IMT_UNUSED,
ed20d0e3 1236 ("intr %d cpu%d, already allocated",
be98308a
SZ
1237 intr, cpu));
1238
1239 if (cpu == cpuid) {
6bf6f751 1240 map->im_type = type;
be98308a
SZ
1241 map->im_msi_base = i;
1242 } else {
1243 map->im_type = IOAPIC_IMT_SHADOW;
1244 }
1245 }
1246
1247 intrs[j] = intr;
1248 msi_setup(intr);
1249
1250 if (bootverbose) {
6bf6f751
SZ
1251 kprintf("alloc %s intr %d on cpu%d\n",
1252 desc, intr, cpuid);
be98308a
SZ
1253 }
1254 }
1255 error = 0;
1256 break;
1257 }
1258
1259 lwkt_reltoken(&ioapic_irqmap_tok);
1260
1261 return error;
1262}
1263
1264static void
6bf6f751
SZ
1265ioapic_abi_msi_release_intern(int type, const char *desc,
1266 const int intrs[], int count, int cpuid)
be98308a
SZ
1267{
1268 int i, msi_base = -1, intr_next = -1, mask;
1269
1270 KASSERT(cpuid >= 0 && cpuid < ncpus,
1271 ("invalid cpuid %d", cpuid));
1272
ed20d0e3 1273 KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
be98308a
SZ
1274
1275 mask = count - 1;
ed20d0e3 1276 KASSERT((count & mask) == 0, ("count %d is not power of 2", count));
be98308a
SZ
1277
1278 lwkt_gettoken(&ioapic_irqmap_tok);
1279
1280 for (i = 0; i < count; ++i) {
1281 int intr = intrs[i], cpu;
1282
1283 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 1284 ("invalid intr %d", intr));
be98308a
SZ
1285
1286 for (cpu = 0; cpu < ncpus; ++cpu) {
1287 struct ioapic_irqmap *map;
1288
1289 map = &ioapic_irqmaps[cpu][intr];
1290
1291 if (cpu == cpuid) {
6bf6f751 1292 KASSERT(map->im_type == type,
ed20d0e3
SW
1293 ("trying to release non-%s intr %d cpu%d, "
1294 "type %d", desc, intr, cpu,
6bf6f751 1295 map->im_type));
be98308a
SZ
1296 KASSERT(map->im_msi_base >= 0 &&
1297 map->im_msi_base <= intr,
ed20d0e3 1298 ("intr %d cpu%d, invalid %s-base %d",
6bf6f751 1299 intr, cpu, desc, map->im_msi_base));
be98308a 1300 KASSERT((map->im_msi_base & mask) == 0,
6bf6f751 1301 ("intr %d cpu%d, %s-base %d is "
ed20d0e3 1302 "not properly aligned %d",
6bf6f751 1303 intr, cpu, desc, map->im_msi_base, count));
be98308a
SZ
1304
1305 if (msi_base < 0) {
1306 msi_base = map->im_msi_base;
1307 } else {
1308 KASSERT(map->im_msi_base == msi_base,
1309 ("intr %d cpu%d, "
6bf6f751 1310 "inconsistent %s-base, "
ed20d0e3 1311 "was %d, now %d",
6bf6f751 1312 intr, cpu, desc,
be98308a
SZ
1313 msi_base, map->im_msi_base));
1314 }
1315 map->im_msi_base = -1;
1316 } else {
1317 KASSERT(map->im_type == IOAPIC_IMT_SHADOW,
ed20d0e3
SW
1318 ("trying to release non-%ssh intr %d cpu%d, "
1319 "type %d", desc, intr, cpu,
6bf6f751 1320 map->im_type));
be98308a 1321 KASSERT(map->im_msi_base < 0,
ed20d0e3 1322 ("intr %d cpu%d, invalid %ssh-base %d",
6bf6f751 1323 intr, cpu, desc, map->im_msi_base));
be98308a
SZ
1324 }
1325 map->im_type = IOAPIC_IMT_UNUSED;
1326 }
1327
1328 if (intr_next < intr)
1329 intr_next = intr;
1330
6bf6f751
SZ
1331 if (bootverbose) {
1332 kprintf("release %s intr %d on cpu%d\n",
1333 desc, intr, cpuid);
1334 }
be98308a
SZ
1335 }
1336
1337 KKASSERT(intr_next > 0);
1338 KKASSERT(msi_base >= 0);
1339
1340 ++intr_next;
1341 if (intr_next < IOAPIC_HWI_VECTORS) {
1342 int cpu;
1343
1344 for (cpu = 0; cpu < ncpus; ++cpu) {
1345 const struct ioapic_irqmap *map =
1346 &ioapic_irqmaps[cpu][intr_next];
1347
6bf6f751 1348 if (map->im_type == type) {
be98308a 1349 KASSERT(map->im_msi_base != msi_base,
ed20d0e3 1350 ("more than %d %s was allocated",
6bf6f751 1351 count, desc));
be98308a
SZ
1352 }
1353 }
1354 }
1355
1356 lwkt_reltoken(&ioapic_irqmap_tok);
1357}
1358
6bf6f751
SZ
1359static int
1360ioapic_abi_msi_alloc(int intrs[], int count, int cpuid)
1361{
1362 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSI, "MSI",
1363 intrs, count, cpuid);
1364}
1365
1366static void
1367ioapic_abi_msi_release(const int intrs[], int count, int cpuid)
1368{
1369 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSI, "MSI",
1370 intrs, count, cpuid);
1371}
1372
1373static int
1374ioapic_abi_msix_alloc(int *intr, int cpuid)
1375{
1376 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSIX, "MSI-X",
1377 intr, 1, cpuid);
1378}
1379
1380static void
1381ioapic_abi_msix_release(int intr, int cpuid)
1382{
1383 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSIX, "MSI-X",
1384 &intr, 1, cpuid);
1385}
1386
be98308a
SZ
1387static void
1388ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
1389{
1390 const struct ioapic_irqmap *map;
1391
1392 KASSERT(cpuid >= 0 && cpuid < ncpus,
1393 ("invalid cpuid %d", cpuid));
1394
1395 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 1396 ("invalid intr %d", intr));
be98308a
SZ
1397
1398 lwkt_gettoken(&ioapic_irqmap_tok);
1399
1400 map = &ioapic_irqmaps[cpuid][intr];
6bf6f751
SZ
1401 KASSERT(map->im_type == IOAPIC_IMT_MSI ||
1402 map->im_type == IOAPIC_IMT_MSIX,
ed20d0e3 1403 ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type));
be98308a 1404 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
ed20d0e3 1405 ("intr %d, invalid %s-base %d", intr,
6bf6f751
SZ
1406 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X",
1407 map->im_msi_base));
be98308a
SZ
1408
1409 msi_map(map->im_msi_base, addr, data, cpuid);
1410
6bf6f751
SZ
1411 if (bootverbose) {
1412 kprintf("map %s intr %d on cpu%d\n",
1413 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X",
1414 intr, cpuid);
1415 }
be98308a
SZ
1416
1417 lwkt_reltoken(&ioapic_irqmap_tok);
1418}