MachIntr: Add two methods to find IRQ
[dragonfly.git] / sys / platform / pc32 / isa / clock.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 */
39
40/*
41 * Routines to handle clock hardware.
42 */
43
44/*
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47 *
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 */
50
1f2de5d4 51#include "use_apm.h"
984263bc 52#include "opt_clock.h"
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53
54#include <sys/param.h>
55#include <sys/systm.h>
13194089 56#include <sys/eventhandler.h>
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57#include <sys/time.h>
58#include <sys/kernel.h>
e126caf1 59#include <sys/bus.h>
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60#ifndef SMP
61#include <sys/lock.h>
62#endif
63#include <sys/sysctl.h>
64#include <sys/cons.h>
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65#include <sys/systimer.h>
66#include <sys/globaldata.h>
67#include <sys/thread2.h>
68#include <sys/systimer.h>
37e7efec 69#include <sys/machintr.h>
1b505979 70#include <sys/interrupt.h>
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71
72#include <machine/clock.h>
73#ifdef CLK_CALIBRATION_LOOP
74#endif
75#include <machine/cputypes.h>
76#include <machine/frame.h>
77#include <machine/ipl.h>
78#include <machine/limits.h>
79#include <machine/md_var.h>
80#include <machine/psl.h>
984263bc 81#include <machine/segments.h>
984263bc 82#include <machine/smp.h>
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83#include <machine/specialreg.h>
84
ed4d621d 85#include <machine_base/apic/ioapic.h>
6b809ec7 86#include <machine_base/apic/ioapic_abi.h>
a9295349 87#include <machine_base/icu/icu.h>
21ce0dfa 88#include <bus/isa/isa.h>
1f2de5d4 89#include <bus/isa/rtc.h>
a9295349 90#include <machine_base/isa/timerreg.h>
984263bc 91
87cf6827 92#include <machine/intr_machdep.h>
984263bc 93
88c4d2f6 94static void i8254_restore(void);
e63ac55d 95static void resettodr_on_shutdown(void *arg __unused);
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96
97/*
98 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
99 * can use a simple formula for leap years.
100 */
101#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
102#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
103
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104#ifndef TIMER_FREQ
105#define TIMER_FREQ 1193182
106#endif
984263bc 107
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108static uint8_t i8254_walltimer_sel;
109static uint16_t i8254_walltimer_cntr;
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110
111int adjkerntz; /* local offset from GMT in seconds */
984263bc 112int disable_rtc_set; /* disable resettodr() if != 0 */
8b3ec75a 113int tsc_present;
374133e3 114int64_t tsc_frequency;
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115int tsc_is_broken;
116int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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117int timer0_running;
118enum tstate { RELEASED, ACQUIRED };
119enum tstate timer0_state;
120enum tstate timer1_state;
121enum tstate timer2_state;
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122
123static int beeping = 0;
984263bc 124static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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125static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
126static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
e63ac55d 127static int rtc_loaded;
984263bc 128
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129static int i8254_cputimer_div;
130
ef612539 131static int i8254_nointr;
4d517764 132static int i8254_intr_disable = 1;
e87376d9
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133TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
134
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135static struct callout sysbeepstop_ch;
136
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137static sysclock_t i8254_cputimer_count(void);
138static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
139static void i8254_cputimer_destruct(struct cputimer *cputimer);
140
141static struct cputimer i8254_cputimer = {
d8fdd978 142 SLIST_ENTRY_INITIALIZER,
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143 "i8254",
144 CPUTIMER_PRI_8254,
145 0,
146 i8254_cputimer_count,
147 cputimer_default_fromhz,
148 cputimer_default_fromus,
149 i8254_cputimer_construct,
150 i8254_cputimer_destruct,
151 TIMER_FREQ,
5ee041ae 152 0, 0, 0
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153};
154
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155static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
156static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
157static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
158
159static struct cputimer_intr i8254_cputimer_intr = {
160 .freq = TIMER_FREQ,
161 .reload = i8254_intr_reload,
162 .enable = cputimer_intr_default_enable,
163 .config = i8254_intr_config,
164 .restart = cputimer_intr_default_restart,
165 .pmfixup = cputimer_intr_default_pmfixup,
166 .initclock = i8254_intr_initclock,
167 .next = SLIST_ENTRY_INITIALIZER,
168 .name = "i8254",
169 .type = CPUTIMER_INTR_8254,
170 .prio = CPUTIMER_INTR_PRIO_8254,
171 .caps = CPUTIMER_INTR_CAP_PS
172};
173
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174/*
175 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
176 * counting as of this interrupt. We use timer1 in free-running mode (not
177 * generating any interrupts) as our main counter. Each cpu has timeouts
178 * pending.
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179 *
180 * This code is INTR_MPSAFE and may be called without the BGL held.
88c4d2f6 181 */
984263bc 182static void
477d3c1c 183clkintr(void *dummy, void *frame_arg)
984263bc 184{
ec4812b0 185 static sysclock_t sysclock_count; /* NOTE! Must be static */
88c4d2f6 186 struct globaldata *gd = mycpu;
b8a98473 187#ifdef SMP
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188 struct globaldata *gscan;
189 int n;
b8a98473 190#endif
9a47427a 191
b505872f 192 /*
88c4d2f6 193 * SWSTROBE mode is a one-shot, the timer is no longer running
b505872f 194 */
88c4d2f6 195 timer0_running = 0;
b505872f 196
88c4d2f6 197 /*
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198 * XXX the dispatcher needs work. right now we call systimer_intr()
199 * directly or via IPI for any cpu with systimers queued, which is
ec4812b0 200 * usually *ALL* of them. We need to use the LAPIC timer for this.
88c4d2f6 201 */
ec4812b0 202 sysclock_count = sys_cputimer->count();
b8a98473 203#ifdef SMP
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204 for (n = 0; n < ncpus; ++n) {
205 gscan = globaldata_find(n);
774fc796 206 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
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207 continue;
208 if (gscan != gd) {
b8a98473 209 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
96d52ac8 210 &sysclock_count, 1);
88c4d2f6 211 } else {
ec4812b0 212 systimer_intr(&sysclock_count, 0, frame_arg);
88c4d2f6 213 }
984263bc 214 }
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215#else
216 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
ec4812b0 217 systimer_intr(&sysclock_count, 0, frame_arg);
b8a98473 218#endif
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219}
220
88c4d2f6 221
984263bc 222/*
88c4d2f6 223 * NOTE! not MP safe.
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224 */
225int
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226acquire_timer2(int mode)
227{
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228 if (timer2_state != RELEASED)
229 return (-1);
230 timer2_state = ACQUIRED;
231
232 /*
233 * This access to the timer registers is as atomic as possible
234 * because it is a single instruction. We could do better if we
88c4d2f6 235 * knew the rate.
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236 */
237 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
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238 return (0);
239}
240
241int
09e6e929 242release_timer2(void)
984263bc 243{
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244 if (timer2_state != ACQUIRED)
245 return (-1);
984263bc 246 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
88c4d2f6 247 timer2_state = RELEASED;
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248 return (0);
249}
250
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251#include "opt_ddb.h"
252#ifdef DDB
253#include <ddb/ddb.h>
254
255DB_SHOW_COMMAND(rtc, rtc)
256{
26be20a0 257 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
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258 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
259 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
260 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
261}
262#endif /* DDB */
263
88c4d2f6 264/*
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265 * Return the current cpu timer count as a 32 bit integer.
266 */
044ee7c4 267static
88c4d2f6 268sysclock_t
044ee7c4 269i8254_cputimer_count(void)
88c4d2f6 270{
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271 static __uint16_t cputimer_last;
272 __uint16_t count;
273 sysclock_t ret;
984263bc 274
88c4d2f6 275 clock_lock();
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276 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
277 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
278 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
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279 count = -count; /* -> countup */
280 if (count < cputimer_last) /* rollover */
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281 i8254_cputimer.base += 0x00010000;
282 ret = i8254_cputimer.base | count;
88c4d2f6 283 cputimer_last = count;
8a8d5d85 284 clock_unlock();
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285 return(ret);
286}
287
288/*
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289 * This function is called whenever the system timebase changes, allowing
290 * us to calculate what is needed to convert a system timebase tick
291 * into an 8254 tick for the interrupt timer. If we can convert to a
292 * simple shift, multiplication, or division, we do so. Otherwise 64
293 * bit arithmatic is required every time the interrupt timer is reloaded.
294 */
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295static void
296i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
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297{
298 int freq;
299 int div;
300
301 /*
302 * Will a simple divide do the trick?
303 */
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304 div = (timer->freq + (cti->freq / 2)) / cti->freq;
305 freq = cti->freq * div;
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306
307 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
308 i8254_cputimer_div = div;
309 else
310 i8254_cputimer_div = 0;
311}
312
313/*
88c4d2f6
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314 * Reload for the next timeout. It is possible for the reload value
315 * to be 0 or negative, indicating that an immediate timer interrupt
316 * is desired. For now make the minimum 2 ticks.
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317 *
318 * We may have to convert from the system timebase to the 8254 timebase.
88c4d2f6 319 */
c5c70fac 320static void
ef612539 321i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
88c4d2f6
MD
322{
323 __uint16_t count;
324
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MD
325 if (i8254_cputimer_div)
326 reload /= i8254_cputimer_div;
327 else
ef612539 328 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
5ee041ae 329
88c4d2f6
MD
330 if ((int)reload < 2)
331 reload = 2;
332
333 clock_lock();
334 if (timer0_running) {
335 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
336 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
337 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
338 if (reload < count) {
339 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
340 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
341 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
342 }
343 } else {
344 timer0_running = 1;
345 if (reload > 0xFFFF)
346 reload = 0; /* full count */
347 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
348 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
349 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
350 }
351 clock_unlock();
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352}
353
354/*
dbcd0c9b
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355 * DELAY(usec) - Spin for the specified number of microseconds.
356 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
357 * but do a thread switch in the loop
358 *
88c4d2f6 359 * Relies on timer 1 counting down from (cputimer_freq / hz)
984263bc
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360 * Note: timer had better have been programmed before this is first used!
361 */
dbcd0c9b
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362static void
363DODELAY(int n, int doswitch)
984263bc
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364{
365 int delta, prev_tick, tick, ticks_left;
366
367#ifdef DELAYDEBUG
368 int getit_calls = 1;
369 int n1;
370 static int state = 0;
371
372 if (state == 0) {
373 state = 1;
374 for (n1 = 1; n1 <= 10000000; n1 *= 10)
375 DELAY(n1);
376 state = 2;
377 }
378 if (state == 1)
26be20a0 379 kprintf("DELAY(%d)...", n);
984263bc
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380#endif
381 /*
382 * Guard against the timer being uninitialized if we are called
383 * early for console i/o.
384 */
88c4d2f6
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385 if (timer0_state == RELEASED)
386 i8254_restore();
984263bc
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387
388 /*
389 * Read the counter first, so that the rest of the setup overhead is
1636ba19
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390 * counted. Then calculate the number of hardware timer ticks
391 * required, rounding up to be sure we delay at least the requested
392 * number of microseconds.
984263bc 393 */
044ee7c4 394 prev_tick = sys_cputimer->count();
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395 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
396 1000000;
397
984263bc 398 /*
1636ba19 399 * Loop until done.
984263bc 400 */
984263bc 401 while (ticks_left > 0) {
044ee7c4 402 tick = sys_cputimer->count();
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MD
403#ifdef DELAYDEBUG
404 ++getit_calls;
405#endif
88c4d2f6 406 delta = tick - prev_tick;
984263bc 407 prev_tick = tick;
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MD
408 if (delta < 0)
409 delta = 0;
984263bc 410 ticks_left -= delta;
dbcd0c9b
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411 if (doswitch && ticks_left > 0)
412 lwkt_switch();
c5724852 413 cpu_pause();
984263bc
MD
414 }
415#ifdef DELAYDEBUG
416 if (state == 1)
26be20a0 417 kprintf(" %d calls to getit() at %d usec each\n",
984263bc
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418 getit_calls, (n + 5) / getit_calls);
419#endif
420}
421
77912481
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422/*
423 * DELAY() never switches
424 */
dbcd0c9b
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425void
426DELAY(int n)
427{
428 DODELAY(n, 0);
429}
430
d8129ed3
MD
431int
432CHECKTIMEOUT(TOTALDELAY *tdd)
433{
434 sysclock_t delta;
435 int us;
436
437 if (tdd->started == 0) {
438 if (timer0_state == RELEASED)
439 i8254_restore();
440 tdd->last_clock = sys_cputimer->count();
441 tdd->started = 1;
442 return(0);
443 }
444 delta = sys_cputimer->count() - tdd->last_clock;
445 us = (u_int64_t)delta * (u_int64_t)1000000 /
446 (u_int64_t)sys_cputimer->freq;
447 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
448 1000000;
449 tdd->us -= us;
450 return (tdd->us < 0);
451}
452
77912481
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453/*
454 * DRIVERSLEEP() does not switch if called with a spinlock held or
455 * from a hard interrupt.
456 */
dbcd0c9b
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457void
458DRIVERSLEEP(int usec)
459{
460 globaldata_t gd = mycpu;
461
8f165b8c 462 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
dbcd0c9b
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463 DODELAY(usec, 0);
464 } else {
465 DODELAY(usec, 1);
466 }
467}
468
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469static void
470sysbeepstop(void *chan)
471{
472 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
984263bc 473 beeping = 0;
88c4d2f6 474 release_timer2();
984263bc
MD
475}
476
477int
478sysbeep(int pitch, int period)
479{
984263bc 480 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
88c4d2f6 481 return(-1);
7caeaffe
MD
482 if (sysbeep_enable == 0)
483 return(-1);
88c4d2f6
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484 /*
485 * Nobody else is using timer2, we do not need the clock lock
486 */
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487 outb(TIMER_CNTR2, pitch);
488 outb(TIMER_CNTR2, (pitch>>8));
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489 if (!beeping) {
490 /* enable counter2 output to speaker */
491 outb(IO_PPI, inb(IO_PPI) | 3);
492 beeping = period;
b02bbab0 493 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
984263bc 494 }
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495 return (0);
496}
497
498/*
499 * RTC support routines
500 */
501
502int
09e6e929 503rtcin(int reg)
984263bc 504{
984263bc
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505 u_char val;
506
9acd5bbb 507 crit_enter();
984263bc
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508 outb(IO_RTC, reg);
509 inb(0x84);
510 val = inb(IO_RTC + 1);
511 inb(0x84);
9acd5bbb 512 crit_exit();
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513 return (val);
514}
515
516static __inline void
517writertc(u_char reg, u_char val)
518{
9acd5bbb 519 crit_enter();
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520 inb(0x84);
521 outb(IO_RTC, reg);
522 inb(0x84);
523 outb(IO_RTC + 1, val);
524 inb(0x84); /* XXX work around wrong order in rtcin() */
9acd5bbb 525 crit_exit();
984263bc
MD
526}
527
528static __inline int
529readrtc(int port)
530{
531 return(bcd2bin(rtcin(port)));
532}
533
534static u_int
535calibrate_clocks(void)
536{
537 u_int64_t old_tsc;
538 u_int count, prev_count, tot_count;
539 int sec, start_sec, timeout;
540
541 if (bootverbose)
26be20a0 542 kprintf("Calibrating clock(s) ... ");
984263bc
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543 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
544 goto fail;
545 timeout = 100000000;
546
547 /* Read the mc146818A seconds counter. */
548 for (;;) {
549 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
550 sec = rtcin(RTC_SEC);
551 break;
552 }
553 if (--timeout == 0)
554 goto fail;
555 }
556
557 /* Wait for the mC146818A seconds counter to change. */
558 start_sec = sec;
559 for (;;) {
560 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
561 sec = rtcin(RTC_SEC);
562 if (sec != start_sec)
563 break;
564 }
565 if (--timeout == 0)
566 goto fail;
567 }
568
569 /* Start keeping track of the i8254 counter. */
044ee7c4 570 prev_count = sys_cputimer->count();
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571 tot_count = 0;
572
573 if (tsc_present)
574 old_tsc = rdtsc();
575 else
576 old_tsc = 0; /* shut up gcc */
577
578 /*
579 * Wait for the mc146818A seconds counter to change. Read the i8254
580 * counter for each iteration since this is convenient and only
581 * costs a few usec of inaccuracy. The timing of the final reads
582 * of the counters almost matches the timing of the initial reads,
583 * so the main cause of inaccuracy is the varying latency from
584 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
585 * rtcin(RTC_SEC) that returns a changed seconds count. The
586 * maximum inaccuracy from this cause is < 10 usec on 486's.
587 */
588 start_sec = sec;
589 for (;;) {
590 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
591 sec = rtcin(RTC_SEC);
044ee7c4 592 count = sys_cputimer->count();
88c4d2f6 593 tot_count += (int)(count - prev_count);
984263bc
MD
594 prev_count = count;
595 if (sec != start_sec)
596 break;
597 if (--timeout == 0)
598 goto fail;
599 }
600
601 /*
602 * Read the cpu cycle counter. The timing considerations are
603 * similar to those for the i8254 clock.
604 */
374133e3
MD
605 if (tsc_present) {
606 tsc_frequency = rdtsc() - old_tsc;
374133e3 607 }
984263bc 608
c17827b4 609 if (tsc_present)
870b0161 610 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
26be20a0 611 kprintf("i8254 clock: %u Hz\n", tot_count);
984263bc
MD
612 return (tot_count);
613
614fail:
26be20a0 615 kprintf("failed, using default i8254 clock of %u Hz\n",
044ee7c4
MD
616 i8254_cputimer.freq);
617 return (i8254_cputimer.freq);
984263bc
MD
618}
619
620static void
621i8254_restore(void)
622{
88c4d2f6 623 timer0_state = ACQUIRED;
e54beab0 624
044ee7c4
MD
625 clock_lock();
626
627 /*
628 * Timer0 is our fine-grained variable clock interrupt
629 */
630 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
631 outb(TIMER_CNTR0, 2); /* lsb */
632 outb(TIMER_CNTR0, 0); /* msb */
ee31250e 633 clock_unlock();
044ee7c4 634
ef612539
SZ
635 if (!i8254_nointr) {
636 cputimer_intr_register(&i8254_cputimer_intr);
637 cputimer_intr_select(&i8254_cputimer_intr, 0);
638 }
639
044ee7c4
MD
640 /*
641 * Timer1 or timer2 is our free-running clock, but only if another
642 * has not been selected.
643 */
5ee041ae
MD
644 cputimer_register(&i8254_cputimer);
645 cputimer_select(&i8254_cputimer, 0);
044ee7c4
MD
646}
647
648static void
649i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
650{
651 int which;
652
653 /*
654 * Should we use timer 1 or timer 2 ?
655 */
656 which = 0;
657 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
658 if (which != 1 && which != 2)
659 which = 2;
660
661 switch(which) {
662 case 1:
663 timer->name = "i8254_timer1";
664 timer->type = CPUTIMER_8254_SEL1;
e54beab0
JS
665 i8254_walltimer_sel = TIMER_SEL1;
666 i8254_walltimer_cntr = TIMER_CNTR1;
667 timer1_state = ACQUIRED;
044ee7c4
MD
668 break;
669 case 2:
670 timer->name = "i8254_timer2";
671 timer->type = CPUTIMER_8254_SEL2;
e54beab0
JS
672 i8254_walltimer_sel = TIMER_SEL2;
673 i8254_walltimer_cntr = TIMER_CNTR2;
674 timer2_state = ACQUIRED;
044ee7c4 675 break;
e54beab0 676 }
044ee7c4
MD
677
678 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
679
ee31250e 680 clock_lock();
e54beab0
JS
681 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
682 outb(i8254_walltimer_cntr, 0); /* lsb */
683 outb(i8254_walltimer_cntr, 0); /* msb */
88c4d2f6 684 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
ee31250e 685 clock_unlock();
044ee7c4
MD
686}
687
688static void
689i8254_cputimer_destruct(struct cputimer *timer)
690{
691 switch(timer->type) {
692 case CPUTIMER_8254_SEL1:
693 timer1_state = RELEASED;
694 break;
695 case CPUTIMER_8254_SEL2:
696 timer2_state = RELEASED;
697 break;
698 default:
699 break;
700 }
701 timer->type = 0;
984263bc
MD
702}
703
704static void
705rtc_restore(void)
706{
984263bc
MD
707 /* Restore all of the RTC's "status" (actually, control) registers. */
708 writertc(RTC_STATUSB, RTCSB_24HR);
709 writertc(RTC_STATUSA, rtc_statusa);
710 writertc(RTC_STATUSB, rtc_statusb);
711}
712
713/*
0284027e 714 * Restore all the timers.
984263bc 715 *
0d1dffdf
MD
716 * This function is called to resynchronize our core timekeeping after a
717 * long halt, e.g. from apm_default_resume() and friends. It is also
718 * called if after a BIOS call we have detected munging of the 8254.
719 * It is necessary because cputimer_count() counter's delta may have grown
720 * too large for nanouptime() and friends to handle, or (in the case of 8254
721 * munging) might cause the SYSTIMER code to prematurely trigger.
984263bc
MD
722 */
723void
724timer_restore(void)
725{
0284027e 726 crit_enter();
984263bc
MD
727 i8254_restore(); /* restore timer_freq and hz */
728 rtc_restore(); /* reenable RTC interrupts */
0284027e 729 crit_exit();
984263bc
MD
730}
731
732/*
733 * Initialize 8254 timer 0 early so that it can be used in DELAY().
984263bc
MD
734 */
735void
09e6e929 736startrtclock(void)
984263bc
MD
737{
738 u_int delta, freq;
739
88c4d2f6
MD
740 /*
741 * Can we use the TSC?
742 */
984263bc
MD
743 if (cpu_feature & CPUID_TSC)
744 tsc_present = 1;
745 else
746 tsc_present = 0;
747
88c4d2f6
MD
748 /*
749 * Initial RTC state, don't do anything unexpected
750 */
984263bc
MD
751 writertc(RTC_STATUSA, rtc_statusa);
752 writertc(RTC_STATUSB, RTCSB_24HR);
753
88c4d2f6
MD
754 /*
755 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
756 * generate an interrupt, which we will ignore for now.
757 *
758 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
759 * (so it counts a full 2^16 and repeats). We will use this timer
760 * for our counting.
761 */
762 i8254_restore();
984263bc
MD
763 freq = calibrate_clocks();
764#ifdef CLK_CALIBRATION_LOOP
765 if (bootverbose) {
26be20a0 766 kprintf(
984263bc
MD
767 "Press a key on the console to abort clock calibration\n");
768 while (cncheckc() == -1)
769 calibrate_clocks();
770 }
771#endif
772
773 /*
774 * Use the calibrated i8254 frequency if it seems reasonable.
775 * Otherwise use the default, and don't use the calibrated i586
776 * frequency.
777 */
044ee7c4
MD
778 delta = freq > i8254_cputimer.freq ?
779 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
780 if (delta < i8254_cputimer.freq / 100) {
984263bc
MD
781#ifndef CLK_USE_I8254_CALIBRATION
782 if (bootverbose)
26be20a0 783 kprintf(
984263bc 784"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
044ee7c4 785 freq = i8254_cputimer.freq;
984263bc 786#endif
ef612539
SZ
787 /*
788 * NOTE:
789 * Interrupt timer's freq must be adjusted
790 * before we change the cuptimer's frequency.
791 */
792 i8254_cputimer_intr.freq = freq;
5ee041ae 793 cputimer_set_frequency(&i8254_cputimer, freq);
984263bc
MD
794 } else {
795 if (bootverbose)
26be20a0 796 kprintf(
984263bc 797 "%d Hz differs from default of %d Hz by more than 1%%\n",
044ee7c4 798 freq, i8254_cputimer.freq);
374133e3 799 tsc_frequency = 0;
984263bc
MD
800 }
801
984263bc 802#ifndef CLK_USE_TSC_CALIBRATION
870b0161 803 if (tsc_frequency != 0) {
984263bc 804 if (bootverbose)
26be20a0 805 kprintf(
984263bc 806"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
374133e3 807 tsc_frequency = 0;
984263bc
MD
808 }
809#endif
374133e3 810 if (tsc_present && tsc_frequency == 0) {
984263bc
MD
811 /*
812 * Calibration of the i586 clock relative to the mc146818A
813 * clock failed. Do a less accurate calibration relative
814 * to the i8254 clock.
815 */
816 u_int64_t old_tsc = rdtsc();
817
818 DELAY(1000000);
374133e3 819 tsc_frequency = rdtsc() - old_tsc;
984263bc 820#ifdef CLK_USE_TSC_CALIBRATION
870b0161
MD
821 if (bootverbose) {
822 kprintf("TSC clock: %llu Hz (Method B)\n",
823 tsc_frequency);
824 }
984263bc
MD
825#endif
826 }
827
87e2fa7e 828 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
13194089 829
984263bc
MD
830#if !defined(SMP)
831 /*
832 * We can not use the TSC in SMP mode, until we figure out a
833 * cheap (impossible), reliable and precise (yeah right!) way
834 * to synchronize the TSCs of all the CPUs.
835 * Curse Intel for leaving the counter out of the I/O APIC.
836 */
837
838#if NAPM > 0
839 /*
840 * We can not use the TSC if we support APM. Precise timekeeping
841 * on an APM'ed machine is at best a fools pursuit, since
842 * any and all of the time spent in various SMM code can't
843 * be reliably accounted for. Reading the RTC is your only
844 * source of reliable time info. The i8254 looses too of course
845 * but we need to have some kind of time...
846 * We don't know at this point whether APM is going to be used
847 * or not, nor when it might be activated. Play it safe.
848 */
849 return;
850#endif /* NAPM > 0 */
851
984263bc
MD
852#endif /* !defined(SMP) */
853}
854
855/*
e63ac55d
MD
856 * Sync the time of day back to the RTC on shutdown, but only if
857 * we have already loaded it and have not crashed.
858 */
859static void
860resettodr_on_shutdown(void *arg __unused)
861{
862 if (rtc_loaded && panicstr == NULL) {
863 resettodr();
864 }
865}
866
867/*
984263bc
MD
868 * Initialize the time of day register, based on the time base which is, e.g.
869 * from a filesystem.
870 */
871void
872inittodr(time_t base)
873{
874 unsigned long sec, days;
984263bc 875 int year, month;
88c4d2f6 876 int y, m;
984263bc
MD
877 struct timespec ts;
878
879 if (base) {
984263bc
MD
880 ts.tv_sec = base;
881 ts.tv_nsec = 0;
88c4d2f6 882 set_timeofday(&ts);
984263bc
MD
883 }
884
885 /* Look if we have a RTC present and the time is valid */
886 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
887 goto wrong_time;
888
889 /* wait for time update to complete */
890 /* If RTCSA_TUP is zero, we have at least 244us before next update */
88c4d2f6 891 crit_enter();
984263bc 892 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
88c4d2f6
MD
893 crit_exit();
894 crit_enter();
984263bc
MD
895 }
896
897 days = 0;
898#ifdef USE_RTC_CENTURY
899 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
900#else
901 year = readrtc(RTC_YEAR) + 1900;
902 if (year < 1970)
903 year += 100;
904#endif
905 if (year < 1970) {
88c4d2f6 906 crit_exit();
984263bc
MD
907 goto wrong_time;
908 }
909 month = readrtc(RTC_MONTH);
910 for (m = 1; m < month; m++)
911 days += daysinmonth[m-1];
912 if ((month > 2) && LEAPYEAR(year))
913 days ++;
914 days += readrtc(RTC_DAY) - 1;
984263bc
MD
915 for (y = 1970; y < year; y++)
916 days += DAYSPERYEAR + LEAPYEAR(y);
917 sec = ((( days * 24 +
918 readrtc(RTC_HRS)) * 60 +
919 readrtc(RTC_MIN)) * 60 +
920 readrtc(RTC_SEC));
921 /* sec now contains the number of seconds, since Jan 1 1970,
922 in the local time zone */
923
924 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
925
926 y = time_second - sec;
927 if (y <= -2 || y >= 2) {
928 /* badly off, adjust it */
929 ts.tv_sec = sec;
930 ts.tv_nsec = 0;
88c4d2f6 931 set_timeofday(&ts);
984263bc 932 }
e63ac55d 933 rtc_loaded = 1;
88c4d2f6 934 crit_exit();
984263bc
MD
935 return;
936
937wrong_time:
26be20a0
SW
938 kprintf("Invalid time in real time clock.\n");
939 kprintf("Check and reset the date immediately!\n");
984263bc
MD
940}
941
942/*
943 * Write system time back to RTC
944 */
945void
09e6e929 946resettodr(void)
984263bc 947{
2f70966e
MD
948 struct timeval tv;
949 unsigned long tm;
950 int m;
951 int y;
984263bc
MD
952
953 if (disable_rtc_set)
954 return;
955
2f70966e
MD
956 microtime(&tv);
957 tm = tv.tv_sec;
984263bc 958
88c4d2f6 959 crit_enter();
984263bc
MD
960 /* Disable RTC updates and interrupts. */
961 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
962
963 /* Calculate local time to put in RTC */
964
965 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
966
967 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
968 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
969 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
970
971 /* We have now the days since 01-01-1970 in tm */
972 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
973 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
974 tm >= m;
975 y++, m = DAYSPERYEAR + LEAPYEAR(y))
976 tm -= m;
977
978 /* Now we have the years in y and the day-of-the-year in tm */
979 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
980#ifdef USE_RTC_CENTURY
981 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
982#endif
983 for (m = 0; ; m++) {
984 int ml;
985
986 ml = daysinmonth[m];
987 if (m == 1 && LEAPYEAR(y))
988 ml++;
989 if (tm < ml)
990 break;
991 tm -= ml;
992 }
993
994 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
995 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
996
997 /* Reenable RTC updates and interrupts. */
998 writertc(RTC_STATUSB, rtc_statusb);
88c4d2f6 999 crit_exit();
984263bc
MD
1000}
1001
6b809ec7
SZ
1002static int
1003i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1004{
1005 sysclock_t base;
1006 long lastcnt;
1007
1008 /*
1009 * Following code assumes the 8254 is the cpu timer,
1010 * so make sure it is.
1011 */
1012 KKASSERT(sys_cputimer == &i8254_cputimer);
1013 KKASSERT(cti == &i8254_cputimer_intr);
1014
c83c147e 1015 lastcnt = get_interrupt_counter(irq, mycpuid);
6b809ec7
SZ
1016
1017 /*
1018 * Force an 8254 Timer0 interrupt and wait 1/100s for
1019 * it to happen, then see if we got it.
1020 */
1021 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1022
1023 i8254_intr_reload(cti, 2);
1024 base = sys_cputimer->count();
1025 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1026 ; /* nothing */
1027
c83c147e 1028 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
6b809ec7
SZ
1029 return ENOENT;
1030 return 0;
1031}
1032
984263bc 1033/*
88c4d2f6
MD
1034 * Start both clocks running. DragonFly note: the stat clock is no longer
1035 * used. Instead, 8254 based systimers are used for all major clock
d426f67a 1036 * interrupts.
984263bc 1037 */
ef612539
SZ
1038static void
1039i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
984263bc 1040{
c79ae131 1041 void *clkdesc = NULL;
6b809ec7 1042 int irq = 0, mixed_mode = 0, error;
984263bc 1043
6355d931 1044 KKASSERT(mycpuid == 0);
38015462
SZ
1045 callout_init(&sysbeepstop_ch);
1046
6b809ec7
SZ
1047 if (!selected && i8254_intr_disable)
1048 goto nointr;
e87376d9 1049
d426f67a
SZ
1050 /*
1051 * The stat interrupt mask is different without the
1052 * statistics clock. Also, don't set the interrupt
1053 * flag which would normally cause the RTC to generate
1054 * interrupts.
1055 */
1056 rtc_statusb = RTCSB_24HR;
38015462 1057
984263bc 1058 /* Finish initializing 8253 timer 0. */
f45bfca0 1059 if (ioapic_enable) {
86d692fe 1060 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
6b809ec7
SZ
1061 INTR_POLARITY_HIGH);
1062 if (irq < 0) {
1063mixed_mode_setup:
027bbbfe 1064 error = ioapic_conf_legacy_extint(0);
6b809ec7 1065 if (!error) {
86d692fe 1066 irq = machintr_legacy_intr_find(0,
027bbbfe 1067 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
6b809ec7
SZ
1068 if (irq < 0)
1069 error = ENOENT;
1070 }
1071
1072 if (error) {
1073 if (!selected) {
1074 kprintf("IOAPIC: setup mixed mode for "
1075 "irq 0 failed: %d\n", error);
1076 goto nointr;
1077 } else {
1078 panic("IOAPIC: setup mixed mode for "
1079 "irq 0 failed: %d\n", error);
1080 }
1081 }
1082 mixed_mode = 1;
1083 }
1084 clkdesc = register_int(irq, clkintr, NULL, "clk",
1085 NULL,
1086 INTR_EXCL | INTR_CLOCK |
1087 INTR_NOPOLL | INTR_MPSAFE |
6355d931 1088 INTR_NOENTROPY, 0);
6ac31e9d 1089 } else {
1e7aaefa
SZ
1090 register_int(0, clkintr, NULL, "clk", NULL,
1091 INTR_EXCL | INTR_CLOCK |
1092 INTR_NOPOLL | INTR_MPSAFE |
6355d931 1093 INTR_NOENTROPY, 0);
6ac31e9d 1094 }
38015462
SZ
1095
1096 /* Initialize RTC. */
1097 writertc(RTC_STATUSA, rtc_statusa);
1098 writertc(RTC_STATUSB, RTCSB_24HR);
1099
f45bfca0 1100 if (ioapic_enable) {
6ac31e9d
SZ
1101 error = i8254_ioapic_trial(irq, cti);
1102 if (error) {
1103 if (mixed_mode) {
1104 if (!selected) {
1105 kprintf("IOAPIC: mixed mode for irq %d "
1106 "trial failed: %d\n",
1107 irq, error);
1108 goto nointr;
1109 } else {
1110 panic("IOAPIC: mixed mode for irq %d "
1111 "trial failed: %d\n", irq, error);
1112 }
6b809ec7 1113 } else {
6ac31e9d
SZ
1114 kprintf("IOAPIC: warning 8254 is not connected "
1115 "to the correct pin, try mixed mode\n");
6355d931 1116 unregister_int(clkdesc, 0);
6ac31e9d 1117 goto mixed_mode_setup;
6b809ec7 1118 }
6b809ec7
SZ
1119 }
1120 }
6b809ec7
SZ
1121 return;
1122
1123nointr:
1124 i8254_nointr = 1; /* don't try to register again */
1125 cputimer_intr_deregister(cti);
984263bc
MD
1126}
1127
984263bc
MD
1128void
1129setstatclockrate(int newhz)
1130{
1131 if (newhz == RTC_PROFRATE)
1132 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1133 else
1134 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1135 writertc(RTC_STATUSA, rtc_statusa);
1136}
1137
88c4d2f6 1138#if 0
984263bc
MD
1139static unsigned
1140tsc_get_timecount(struct timecounter *tc)
1141{
1142 return (rdtsc());
1143}
88c4d2f6 1144#endif
984263bc
MD
1145
1146#ifdef KERN_TIMESTAMP
1147#define KERN_TIMESTAMP_SIZE 16384
1148static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1149SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1150 sizeof(tsc), "LU", "Kernel timestamps");
1151void
1152_TSTMP(u_int32_t x)
1153{
1154 static int i;
1155
1156 tsc[i] = (u_int32_t)rdtsc();
1157 tsc[i+1] = x;
1158 i = i + 2;
1159 if (i >= KERN_TIMESTAMP_SIZE)
1160 i = 0;
1161 tsc[i] = 0; /* mark last entry */
1162}
6b08710e 1163#endif /* KERN_TIMESTAMP */
984263bc 1164
c17827b4
MD
1165/*
1166 *
1167 */
1168
1169static int
1170hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1171{
1172 sysclock_t count;
1173 __uint64_t tscval;
1174 char buf[32];
1175
1176 crit_enter();
044ee7c4
MD
1177 if (sys_cputimer == &i8254_cputimer)
1178 count = sys_cputimer->count();
1179 else
1180 count = 0;
c17827b4
MD
1181 if (tsc_present)
1182 tscval = rdtsc();
1183 else
1184 tscval = 0;
1185 crit_exit();
f8c7a42d 1186 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
c17827b4
MD
1187 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1188}
1189
1190SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
044ee7c4
MD
1191SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1192 "frequency");
c17827b4 1193SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
044ee7c4 1194 0, 0, hw_i8254_timestamp, "A", "");
c17827b4 1195
870b0161
MD
1196SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1197 &tsc_present, 0, "TSC Available");
1198SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1199 &tsc_frequency, 0, "TSC Frequency");
1200