ixgbe: Define missing DEBUGOUT# macros.
[dragonfly.git] / sys / dev / netif / ixgbe / ixgbe_osdep.h
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ce451236 33/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_osdep.h,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
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34
35#ifndef _IXGBE_OS_H_
36#define _IXGBE_OS_H_
37
38#include <sys/types.h>
39#include <sys/param.h>
40#include <sys/endian.h>
41#include <sys/systm.h>
42#include <sys/mbuf.h>
43#include <sys/protosw.h>
44#include <sys/socket.h>
45#include <sys/malloc.h>
46#include <sys/kernel.h>
47#include <sys/bus.h>
48#include <sys/rman.h>
49#include <vm/vm.h>
50#include <vm/pmap.h>
51#include <machine/clock.h>
52#include <bus/pci/pcivar.h>
53#include <bus/pci/pcireg.h>
54
55#define ASSERT(x) if(!(x)) panic("IXGBE: x")
ce451236 56#define EWARN(H, W, S) kprintf(W)
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57
58/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
59#define usec_delay(x) DELAY(x)
60#define msec_delay(x) DELAY(1000*(x))
61
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62#define DBG 0
63#define MSGOUT(S, A, B) kprintf(S "\n", A, B)
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64#define DEBUGFUNC(F) DEBUGOUT(F);
65#if DBG
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66 #define DEBUGOUT(S) kprintf(S "\n")
67 #define DEBUGOUT1(S,A) kprintf(S "\n",A)
68 #define DEBUGOUT2(S,A,B) kprintf(S "\n",A,B)
69 #define DEBUGOUT3(S,A,B,C) kprintf(S "\n",A,B,C)
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70 #define DEBUGOUT4(S,A,B,C,D) kprintf(S "\n",A,B,C,D)
71 #define DEBUGOUT5(S,A,B,C,D,E) kprintf(S "\n",A,B,C,D,E)
72 #define DEBUGOUT6(S,A,B,C,D,E,F) kprintf(S "\n",A,B,C,D,E,F)
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73 #define DEBUGOUT6(S,A,B,C,D,E,F) kprintf(S "\n",A,B,C,D,E,F)
74 #define DEBUGOUT7(S,A,B,C,D,E,F,G) kprintf(S "\n",A,B,C,D,E,F,G)
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75#else
76 #define DEBUGOUT(S)
77 #define DEBUGOUT1(S,A)
78 #define DEBUGOUT2(S,A,B)
79 #define DEBUGOUT3(S,A,B,C)
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80 #define DEBUGOUT4(S,A,B,C,D)
81 #define DEBUGOUT5(S,A,B,C,D,E)
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82 #define DEBUGOUT6(S,A,B,C,D,E,F)
83 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
84#endif
85
86#define FALSE 0
87#define false 0 /* shared code requires this */
88#define TRUE 1
89#define true 1
90#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
91#define PCI_COMMAND_REGISTER PCIR_COMMAND
92
93/* Bunch of defines for shared code bogosity */
94#define UNREFERENCED_PARAMETER(_p)
95#define UNREFERENCED_1PARAMETER(_p)
96#define UNREFERENCED_2PARAMETER(_p, _q)
97#define UNREFERENCED_3PARAMETER(_p, _q, _r)
98#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
99
100
101#define IXGBE_NTOHL(_i) ntohl(_i)
102#define IXGBE_NTOHS(_i) ntohs(_i)
103
104/* XXX these need to be revisited */
105#define IXGBE_CPU_TO_LE32 le32toh
106#define IXGBE_LE32_TO_CPUS le32dec
107
108typedef uint8_t u8;
109typedef int8_t s8;
110typedef uint16_t u16;
111typedef uint32_t u32;
112typedef int32_t s32;
113typedef uint64_t u64;
114#ifndef __bool_true_false_are_defined
115typedef boolean_t bool;
116#endif
117
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118/* shared code requires this */
119#define __le16 u16
120#define __le32 u32
121#define __le64 u64
122#define __be16 u16
123#define __be32 u32
124#define __be64 u64
125
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126#define le16_to_cpu
127
9407f759 128#if defined(__i386__) || defined(__amd64__)
9407f759 129#define wmb() __asm volatile("sfence" ::: "memory")
9407f759 130#else
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131#define wmb()
132#endif
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133
134#if defined(__i386__) || defined(__amd64__)
135static __inline
136void prefetch(void *x)
137{
138 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
139}
140#else
141#define prefetch(x)
142#endif
143
144struct ixgbe_osdep
145{
146 bus_space_tag_t mem_bus_space_tag;
147 bus_space_handle_t mem_bus_space_handle;
148 struct device *dev;
149};
150
151/* These routines are needed by the shared code */
152struct ixgbe_hw;
153extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32);
154#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
155
156extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16);
157#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
158
159#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
160
161#define IXGBE_READ_REG(a, reg) (\
162 bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
163 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
164 reg))
165
166#define IXGBE_WRITE_REG(a, reg, value) (\
167 bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
168 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
169 reg, value))
170
171
172#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
173 bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
174 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
175 (reg + ((offset) << 2))))
176
177#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
178 bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \
179 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \
180 (reg + ((offset) << 2)), value))
181
182
183#endif /* _IXGBE_OS_H_ */