pc32: Split out isa_intr.h and move isa/intr_machdep.h to include/
[dragonfly.git] / sys / platform / pc32 / apic / mpapic.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
b12a1521 30#include <sys/kernel.h>
72740893 31#include <machine/globaldata.h>
984263bc 32#include <machine/smp.h>
90e8a35b 33#include <machine/cputypes.h>
d595a6c0 34#include <machine/md_var.h>
ad52b37b 35#include <machine/pmap.h>
a9295349 36#include <machine_base/apic/mpapic.h>
984263bc 37#include <machine/segments.h>
96728c05 38#include <sys/thread2.h>
984263bc 39
87cf6827 40#include <machine/intr_machdep.h>
984263bc 41
ad52b37b
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42/* XXX */
43extern pt_entry_t *SMPpt;
44
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45/* EISA Edge/Level trigger control registers */
46#define ELCR0 0x4d0 /* eisa irq 0-7 */
47#define ELCR1 0x4d1 /* eisa irq 8-15 */
48
b52c8db0 49static void lapic_timer_calibrate(void);
086575e9 50static void lapic_timer_set_divisor(int);
a9e511df 51static void lapic_timer_fixup_handler(void *);
76c58571 52static void lapic_timer_restart_handler(void *);
c5b8324c 53
78ea5a2a
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54void lapic_timer_process(void);
55void lapic_timer_process_frame(struct intrframe *);
c5b8324c 56
ef612539 57static int lapic_timer_enable = 1;
c5b8324c 58TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 59
ef612539
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60static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
61static void lapic_timer_intr_enable(struct cputimer_intr *);
62static void lapic_timer_intr_restart(struct cputimer_intr *);
63static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
64
65static struct cputimer_intr lapic_cputimer_intr = {
66 .freq = 0,
67 .reload = lapic_timer_intr_reload,
68 .enable = lapic_timer_intr_enable,
69 .config = cputimer_intr_default_config,
70 .restart = lapic_timer_intr_restart,
71 .pmfixup = lapic_timer_intr_pmfixup,
72 .initclock = cputimer_intr_default_initclock,
73 .next = SLIST_ENTRY_INITIALIZER,
74 .name = "lapic",
75 .type = CPUTIMER_INTR_LAPIC,
76 .prio = CPUTIMER_INTR_PRIO_LAPIC,
77 .caps = CPUTIMER_INTR_CAP_NONE
78};
79
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80/*
81 * pointers to pmapped apic hardware.
82 */
83
984263bc 84volatile ioapic_t **ioapic;
984263bc 85
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86static int lapic_timer_divisor_idx = -1;
87static const uint32_t lapic_timer_divisors[] = {
88 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
89 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
90};
c157ff7a 91#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
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92
93
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94/*
95 * Enable APIC, configure interrupts.
96 */
97void
b52c8db0 98apic_initialize(boolean_t bsp)
984263bc 99{
78ea5a2a 100 uint32_t timer;
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101 u_int temp;
102
9d6bf2df 103 /*
97359a5b
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104 * setup LVT1 as ExtINT on the BSP. This is theoretically an
105 * aggregate interrupt input from the 8259. The INTA cycle
106 * will be routed to the external controller (the 8259) which
107 * is expected to supply the vector.
108 *
109 * Must be setup edge triggered, active high.
110 *
111 * Disable LVT1 on the APs. It doesn't matter what delivery
112 * mode we use because we leave it masked.
9d6bf2df 113 */
984263bc 114 temp = lapic.lvt_lint0;
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MD
115 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
116 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
72740893 117 if (mycpu->gd_cpuid == 0)
9d6bf2df 118 temp |= APIC_LVT_DM_EXTINT;
984263bc 119 else
97359a5b 120 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
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121 lapic.lvt_lint0 = temp;
122
9d6bf2df
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123 /*
124 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
125 */
984263bc 126 temp = lapic.lvt_lint1;
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127 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
128 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
129 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
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130 lapic.lvt_lint1 = temp;
131
d9eea1a5 132 /*
c6a1aabe 133 * Mask the apic error interrupt, apic performance counter
78ea5a2a 134 * interrupt.
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MD
135 */
136 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
137 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
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138
139 /* Set apic timer vector and mask the apic timer interrupt. */
140 timer = lapic.lvt_timer;
141 timer &= ~APIC_LVTT_VECTOR;
142 timer |= XTIMER_OFFSET;
143 timer |= APIC_LVTT_MASKED;
144 lapic.lvt_timer = timer;
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145
146 /*
d9eea1a5
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147 * Set the Task Priority Register as needed. At the moment allow
148 * interrupts on all cpus (the APs will remain CLId until they are
149 * ready to deal). We could disable all but IPIs by setting
84bf7d5a 150 * temp |= TPR_IPI for cpu != 0.
d9eea1a5 151 */
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152 temp = lapic.tpr;
153 temp &= ~APIC_TPR_PRIO; /* clear priority field */
30c5f287
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154#ifdef SMP /* APIC-IO */
155if (!apic_io_enable) {
156#endif
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157 /*
158 * If we are NOT running the IO APICs, the LAPIC will only be used
159 * for IPIs. Set the TPR to prevent any unintentional interrupts.
160 */
84bf7d5a 161 temp |= TPR_IPI;
30c5f287
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162#ifdef SMP /* APIC-IO */
163}
97359a5b 164#endif
8a8d5d85 165
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166 lapic.tpr = temp;
167
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168 /*
169 * enable the local APIC
170 */
984263bc 171 temp = lapic.svr;
9d6bf2df 172 temp |= APIC_SVR_ENABLE; /* enable the APIC */
97359a5b 173 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 174
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175 /*
176 * Set the spurious interrupt vector. The low 4 bits of the vector
177 * must be 1111.
178 */
179 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 180 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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181 temp &= ~APIC_SVR_VECTOR;
182 temp |= XSPURIOUSINT_OFFSET;
984263bc 183
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184 lapic.svr = temp;
185
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186 /*
187 * Pump out a few EOIs to clean out interrupts that got through
188 * before we were able to set the TPR.
189 */
190 lapic.eoi = 0;
191 lapic.eoi = 0;
192 lapic.eoi = 0;
193
c5b8324c 194 if (bsp) {
b52c8db0 195 lapic_timer_calibrate();
ef612539
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196 if (lapic_timer_enable) {
197 cputimer_intr_register(&lapic_cputimer_intr);
198 cputimer_intr_select(&lapic_cputimer_intr, 0);
199 }
c5b8324c 200 } else {
086575e9 201 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 202 }
b52c8db0 203
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204 if (bootverbose)
205 apic_dump("apic_initialize()");
206}
207
208
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209static void
210lapic_timer_set_divisor(int divisor_idx)
211{
212 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
213 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
214}
215
216static void
217lapic_timer_oneshot(u_int count)
218{
219 uint32_t value;
220
221 value = lapic.lvt_timer;
222 value &= ~APIC_LVTT_PERIODIC;
223 lapic.lvt_timer = value;
224 lapic.icr_timer = count;
225}
226
227static void
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228lapic_timer_oneshot_quick(u_int count)
229{
230 lapic.icr_timer = count;
231}
232
233static void
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234lapic_timer_calibrate(void)
235{
47bdf646 236 sysclock_t value;
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237
238 /* Try to calibrate the local APIC timer. */
239 for (lapic_timer_divisor_idx = 0;
240 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
241 lapic_timer_divisor_idx++) {
242 lapic_timer_set_divisor(lapic_timer_divisor_idx);
243 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
244 DELAY(2000000);
245 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
246 if (value != APIC_TIMER_MAX_COUNT)
247 break;
248 }
249 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
250 panic("lapic: no proper timer divisor?!\n");
ef612539 251 lapic_cputimer_intr.freq = value / 2;
b52c8db0 252
47bdf646 253 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 254 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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255}
256
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257static void
258lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
259{
260 sysclock_t count;
261
262 gd->gd_timer_running = 0;
263
264 count = sys_cputimer->count();
265 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
266 systimer_intr(&count, 0, frame);
267}
268
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269void
270lapic_timer_process(void)
271{
ae48d6cd 272 lapic_timer_process_oncpu(mycpu, NULL);
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273}
274
275void
276lapic_timer_process_frame(struct intrframe *frame)
277{
ae48d6cd 278 lapic_timer_process_oncpu(mycpu, frame);
b12a1521
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279}
280
c5b8324c 281static void
ef612539 282lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
c5b8324c
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283{
284 struct globaldata *gd = mycpu;
285
ef612539 286 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
c5b8324c
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287 if (reload < 2)
288 reload = 2;
289
290 if (gd->gd_timer_running) {
291 if (reload < lapic.ccr_timer)
292 lapic_timer_oneshot_quick(reload);
293 } else {
294 gd->gd_timer_running = 1;
295 lapic_timer_oneshot_quick(reload);
296 }
297}
298
ef612539
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299static void
300lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
6198c499
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301{
302 uint32_t timer;
303
304 timer = lapic.lvt_timer;
305 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
306 lapic.lvt_timer = timer;
a9e511df
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307
308 lapic_timer_fixup_handler(NULL);
309}
310
311static void
76c58571 312lapic_timer_fixup_handler(void *arg)
a9e511df 313{
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314 int *started = arg;
315
316 if (started != NULL)
317 *started = 0;
318
90e8a35b 319 if (cpu_vendor_id == CPU_VENDOR_AMD) {
a9e511df
SZ
320 /*
321 * Detect the presence of C1E capability mostly on latest
322 * dual-cores (or future) k8 family. This feature renders
323 * the local APIC timer dead, so we disable it by reading
324 * the Interrupt Pending Message register and clearing both
325 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
326 *
327 * Reference:
328 * "BIOS and Kernel Developer's Guide for AMD NPT
329 * Family 0Fh Processors"
330 * #32559 revision 3.00
331 */
332 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
333 (cpu_id & 0x0fff0000) >= 0x00040000) {
334 uint64_t msr;
335
336 msr = rdmsr(0xc0010055);
337 if (msr & 0x18000000) {
338 struct globaldata *gd = mycpu;
339
340 kprintf("cpu%d: AMD C1E detected\n",
341 gd->gd_cpuid);
342 wrmsr(0xc0010055, msr & ~0x18000000ULL);
343
344 /*
345 * We are kinda stalled;
346 * kick start again.
347 */
348 gd->gd_timer_running = 1;
349 lapic_timer_oneshot_quick(2);
76c58571
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350
351 if (started != NULL)
352 *started = 1;
a9e511df
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353 }
354 }
355 }
356}
357
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358static void
359lapic_timer_restart_handler(void *dummy __unused)
360{
361 int started;
362
363 lapic_timer_fixup_handler(&started);
364 if (!started) {
365 struct globaldata *gd = mycpu;
366
367 gd->gd_timer_running = 1;
368 lapic_timer_oneshot_quick(2);
369 }
370}
371
a9e511df
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372/*
373 * This function is called only by ACPI-CA code currently:
374 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
375 * module controls PM. So once ACPI-CA is attached, we try
376 * to apply the fixup to prevent LAPIC timer from hanging.
377 */
ef612539
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378static void
379lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 380{
ef612539
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381 lwkt_send_ipiq_mask(smp_active_mask,
382 lapic_timer_fixup_handler, NULL);
6198c499
SZ
383}
384
ef612539
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385static void
386lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 387{
76c58571
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388 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
389}
390
b52c8db0 391
984263bc
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392/*
393 * dump contents of local APIC registers
394 */
395void
396apic_dump(char* str)
397{
26be20a0
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398 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
399 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
984263bc
MD
400 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
401}
402
403
30c5f287 404#ifdef SMP /* APIC-IO */
984263bc
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405
406/*
407 * IO APIC code,
408 */
409
410#define IOAPIC_ISA_INTS 16
411#define REDIRCNT_IOAPIC(A) \
412 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
413
3ae0cd58
RG
414static int trigger (int apic, int pin, u_int32_t * flags);
415static void polarity (int apic, int pin, u_int32_t * flags, int level);
984263bc
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416
417#define DEFAULT_FLAGS \
418 ((u_int32_t) \
419 (IOART_INTMSET | \
420 IOART_DESTPHY | \
421 IOART_DELLOPRI))
422
423#define DEFAULT_ISA_FLAGS \
424 ((u_int32_t) \
425 (IOART_INTMSET | \
426 IOART_TRGREDG | \
427 IOART_INTAHI | \
428 IOART_DESTPHY | \
429 IOART_DELLOPRI))
430
431void
432io_apic_set_id(int apic, int id)
433{
434 u_int32_t ux;
435
436 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
437 if (((ux & APIC_ID_MASK) >> 24) != id) {
26be20a0 438 kprintf("Changing APIC ID for IO APIC #%d"
984263bc
MD
439 " from %d to %d on chip\n",
440 apic, ((ux & APIC_ID_MASK) >> 24), id);
441 ux &= ~APIC_ID_MASK; /* clear the ID field */
442 ux |= (id << 24);
443 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
444 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
445 if (((ux & APIC_ID_MASK) >> 24) != id)
446 panic("can't control IO APIC #%d ID, reg: 0x%08x",
447 apic, ux);
448 }
449}
450
451
452int
453io_apic_get_id(int apic)
454{
455 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
456}
457
458
459
460/*
461 * Setup the IO APIC.
462 */
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463void
464io_apic_setup_intpin(int apic, int pin)
465{
466 int bus, bustype, irq;
467 u_char select; /* the select register is 8 bits */
468 u_int32_t flags; /* the window register is 32 bits */
469 u_int32_t target; /* the window register is 32 bits */
470 u_int32_t vector; /* the window register is 32 bits */
471 int level;
db958607
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472 int cpuid;
473 char envpath[32];
984263bc 474
984263bc 475 select = pin * 2 + IOAPIC_REDTBL0; /* register */
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MD
476
477 /*
478 * Always clear an IO APIC pin before [re]programming it. This is
479 * particularly important if the pin is set up for a level interrupt
480 * as the IOART_REM_IRR bit might be set. When we reprogram the
481 * vector any EOI from pending ints on this pin could be lost and
482 * IRR might never get reset.
984263bc 483 *
65de6d19
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484 * To fix this problem, clear the vector and make sure it is
485 * programmed as an edge interrupt. This should theoretically
486 * clear IRR so we can later, safely program it as a level
487 * interrupt.
984263bc 488 */
8a8d5d85 489 imen_lock();
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490
491 flags = io_apic_read(apic, select) & IOART_RESV;
492 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
493 flags |= IOART_DESTPHY | IOART_DELFIXED;
494
495 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
496 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
497
498 vector = 0;
499
500 io_apic_write(apic, select, flags | vector);
501 io_apic_write(apic, select + 1, target);
502
8a8d5d85 503 imen_unlock();
65de6d19
MD
504
505 /*
506 * We only deal with vectored interrupts here. ? documentation is
507 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
508 * vs ExTINT, etc.
509 *
510 * This test also catches unconfigured pins.
511 */
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512 if (apic_int_type(apic, pin) != 0)
513 return;
65de6d19
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514
515 /*
516 * Leave the pin unprogrammed if it does not correspond to
517 * an IRQ.
518 */
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519 irq = apic_irq(apic, pin);
520 if (irq < 0)
521 return;
522
523 /* determine the bus type for this pin */
524 bus = apic_src_bus_id(apic, pin);
65de6d19 525 if (bus < 0)
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526 return;
527 bustype = apic_bus_type(bus);
528
529 if ((bustype == ISA) &&
530 (pin < IOAPIC_ISA_INTS) &&
531 (irq == pin) &&
532 (apic_polarity(apic, pin) == 0x1) &&
533 (apic_trigger(apic, pin) == 0x3)) {
534 /*
535 * A broken BIOS might describe some ISA
536 * interrupts as active-high level-triggered.
537 * Use default ISA flags for those interrupts.
538 */
539 flags = DEFAULT_ISA_FLAGS;
540 } else {
541 /*
542 * Program polarity and trigger mode according to
543 * interrupt entry.
544 */
545 flags = DEFAULT_FLAGS;
546 level = trigger(apic, pin, &flags);
547 if (level == 1)
0f546930 548 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
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549 polarity(apic, pin, &flags, level);
550 }
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551
552 cpuid = 0;
553 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
554 kgetenv_int(envpath, &cpuid);
555
556 /* ncpus may not be available yet */
557 if (cpuid > mp_naps)
558 cpuid = 0;
559
5737d650 560 if (bootverbose) {
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561 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
562 apic, pin, irq, cpuid);
5737d650 563 }
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564
565 /*
566 * Program the appropriate registers. This routing may be
567 * overridden when an interrupt handler for a device is
9d522d14 568 * actually added (see register_int(), which calls through
65de6d19
MD
569 * the MACHINTR ABI to set up an interrupt handler/vector).
570 *
571 * The order in which we must program the two registers for
572 * safety is unclear! XXX
573 */
8a8d5d85 574 imen_lock();
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575
576 vector = IDT_OFFSET + irq; /* IDT vec */
577 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
0c8fbc51 578 /* Deliver all interrupts to CPU0 (BSP) */
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579 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
580 IOART_HI_DEST_MASK;
65de6d19 581 flags |= io_apic_read(apic, select) & IOART_RESV;
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582 io_apic_write(apic, select, flags | vector);
583 io_apic_write(apic, select + 1, target);
65de6d19 584
8a8d5d85 585 imen_unlock();
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586}
587
588int
589io_apic_setup(int apic)
590{
591 int maxpin;
592 int pin;
593
984263bc 594 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
26be20a0 595 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
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596
597 for (pin = 0; pin < maxpin; ++pin) {
598 io_apic_setup_intpin(apic, pin);
599 }
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600 while (pin < 32) {
601 if (apic_int_type(apic, pin) >= 0) {
26be20a0 602 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
1f1464ad
MD
603 " cannot program!\n", apic, pin);
604 }
605 ++pin;
606 }
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607
608 /* return GOOD status */
609 return 0;
610}
611#undef DEFAULT_ISA_FLAGS
612#undef DEFAULT_FLAGS
613
614
615#define DEFAULT_EXTINT_FLAGS \
616 ((u_int32_t) \
617 (IOART_INTMSET | \
618 IOART_TRGREDG | \
619 IOART_INTAHI | \
620 IOART_DESTPHY | \
621 IOART_DELLOPRI))
622
623/*
db958607 624 * XXX this function is only used by 8254 setup
984263bc
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625 * Setup the source of External INTerrupts.
626 */
627int
628ext_int_setup(int apic, int intr)
629{
630 u_char select; /* the select register is 8 bits */
631 u_int32_t flags; /* the window register is 32 bits */
632 u_int32_t target; /* the window register is 32 bits */
633 u_int32_t vector; /* the window register is 32 bits */
db958607
SZ
634 int cpuid;
635 char envpath[32];
984263bc
MD
636
637 if (apic_int_type(apic, intr) != 3)
638 return -1;
639
db958607
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640 cpuid = 0;
641 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
642 kgetenv_int(envpath, &cpuid);
643
644 /* ncpus may not be available yet */
645 if (cpuid > mp_naps)
646 cpuid = 0;
647
0c8fbc51 648 /* Deliver interrupts to CPU0 (BSP) */
db958607
SZ
649 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
650 IOART_HI_DEST_MASK;
984263bc 651 select = IOAPIC_REDTBL0 + (2 * intr);
97359a5b 652 vector = IDT_OFFSET + intr;
984263bc
MD
653 flags = DEFAULT_EXTINT_FLAGS;
654
655 io_apic_write(apic, select, flags | vector);
656 io_apic_write(apic, select + 1, target);
657
658 return 0;
659}
660#undef DEFAULT_EXTINT_FLAGS
661
662
663/*
664 * Set the trigger level for an IO APIC pin.
665 */
666static int
667trigger(int apic, int pin, u_int32_t * flags)
668{
669 int id;
670 int eirq;
671 int level;
672 static int intcontrol = -1;
673
674 switch (apic_trigger(apic, pin)) {
675
676 case 0x00:
677 break;
678
679 case 0x01:
680 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
681 return 0;
682
683 case 0x03:
684 *flags |= IOART_TRGRLVL;
685 return 1;
686
687 case -1:
688 default:
689 goto bad;
690 }
691
692 if ((id = apic_src_bus_id(apic, pin)) == -1)
693 goto bad;
694
695 switch (apic_bus_type(id)) {
696 case ISA:
697 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
698 return 0;
699
700 case EISA:
701 eirq = apic_src_bus_irq(apic, pin);
702
703 if (eirq < 0 || eirq > 15) {
26be20a0 704 kprintf("EISA IRQ %d?!?!\n", eirq);
984263bc
MD
705 goto bad;
706 }
707
708 if (intcontrol == -1) {
709 intcontrol = inb(ELCR1) << 8;
710 intcontrol |= inb(ELCR0);
26be20a0 711 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
984263bc
MD
712 }
713
714 /* Use ELCR settings to determine level or edge mode */
715 level = (intcontrol >> eirq) & 1;
716
717 /*
718 * Note that on older Neptune chipset based systems, any
719 * pci interrupts often show up here and in the ELCR as well
720 * as level sensitive interrupts attributed to the EISA bus.
721 */
722
723 if (level)
724 *flags |= IOART_TRGRLVL;
725 else
726 *flags &= ~IOART_TRGRLVL;
727
728 return level;
729
730 case PCI:
731 *flags |= IOART_TRGRLVL;
732 return 1;
733
734 case -1:
735 default:
736 goto bad;
737 }
738
739bad:
740 panic("bad APIC IO INT flags");
741}
742
743
744/*
745 * Set the polarity value for an IO APIC pin.
746 */
747static void
748polarity(int apic, int pin, u_int32_t * flags, int level)
749{
750 int id;
751
752 switch (apic_polarity(apic, pin)) {
753
754 case 0x00:
755 break;
756
757 case 0x01:
758 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
759 return;
760
761 case 0x03:
762 *flags |= IOART_INTALO;
763 return;
764
765 case -1:
766 default:
767 goto bad;
768 }
769
770 if ((id = apic_src_bus_id(apic, pin)) == -1)
771 goto bad;
772
773 switch (apic_bus_type(id)) {
774 case ISA:
775 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
776 return;
777
778 case EISA:
779 /* polarity converter always gives active high */
780 *flags &= ~IOART_INTALO;
781 return;
782
783 case PCI:
784 *flags |= IOART_INTALO;
785 return;
786
787 case -1:
788 default:
789 goto bad;
790 }
791
792bad:
793 panic("bad APIC IO INT flags");
794}
795
796
797/*
ea689d1c 798 * Print contents of unmasked IRQs.
984263bc 799 */
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800void
801imen_dump(void)
802{
803 int x;
804
26be20a0 805 kprintf("SMP: enabled INTs: ");
ea689d1c
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806 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
807 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
808 kprintf("%d ", x);
809 }
810 kprintf("\n");
984263bc
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811}
812
813
814/*
815 * Inter Processor Interrupt functions.
816 */
817
30c5f287 818#endif /* SMP APIC-IO */
984263bc
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819
820/*
821 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
822 *
823 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
824 * vector is any valid SYSTEM INT vector
825 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
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826 *
827 * A backlog of requests can create a deadlock between cpus. To avoid this
828 * we have to be able to accept IPIs at the same time we are trying to send
829 * them. The critical section prevents us from attempting to send additional
830 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
831 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
832 * to occur but fortunately it does not happen too often.
984263bc 833 */
984263bc
MD
834int
835apic_ipi(int dest_type, int vector, int delivery_mode)
836{
837 u_long icr_lo;
838
96728c05
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839 crit_enter();
840 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
841 unsigned int eflags = read_eflags();
842 cpu_enable_intr();
cfaeae2a 843 DEBUG_PUSH_INFO("apic_ipi");
96728c05
MD
844 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
845 lwkt_process_ipiq();
846 }
cfaeae2a 847 DEBUG_POP_INFO();
96728c05 848 write_eflags(eflags);
984263bc 849 }
984263bc 850
9d6bf2df 851 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 852 delivery_mode | vector;
984263bc 853 lapic.icr_lo = icr_lo;
96728c05 854 crit_exit();
984263bc
MD
855 return 0;
856}
857
41a01a4d
MD
858void
859single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
MD
860{
861 u_long icr_lo;
862 u_long icr_hi;
984263bc 863
41a01a4d 864 crit_enter();
96728c05
MD
865 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
866 unsigned int eflags = read_eflags();
867 cpu_enable_intr();
cfaeae2a 868 DEBUG_PUSH_INFO("single_apic_ipi");
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MD
869 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
870 lwkt_process_ipiq();
871 }
cfaeae2a 872 DEBUG_POP_INFO();
96728c05 873 write_eflags(eflags);
984263bc 874 }
984263bc
MD
875 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
876 icr_hi |= (CPU_TO_ID(cpu) << 24);
877 lapic.icr_hi = icr_hi;
878
b2f93ae9 879 /* build ICR_LOW */
9d6bf2df 880 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
984263bc
MD
881 | APIC_DEST_DESTFLD | delivery_mode | vector;
882
883 /* write APIC ICR */
884 lapic.icr_lo = icr_lo;
41a01a4d 885 crit_exit();
984263bc
MD
886}
887
41a01a4d
MD
888#if 0
889
890/*
891 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
892 *
893 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
894 * to the target, and the scheduler does not 'poll' for IPI messages.
895 */
896int
897single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
898{
899 u_long icr_lo;
900 u_long icr_hi;
901
902 crit_enter();
903 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
904 crit_exit();
905 return(0);
906 }
907 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
908 icr_hi |= (CPU_TO_ID(cpu) << 24);
909 lapic.icr_hi = icr_hi;
910
911 /* build IRC_LOW */
912 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
913 | APIC_DEST_DESTFLD | delivery_mode | vector;
914
915 /* write APIC ICR */
916 lapic.icr_lo = icr_lo;
917 crit_exit();
918 return(1);
919}
920
921#endif
922
984263bc
MD
923/*
924 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
925 *
96728c05
MD
926 * target is a bitmask of destination cpus. Vector is any
927 * valid system INT vector. Delivery mode may be either
928 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 929 */
41a01a4d 930void
da23a592 931selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
984263bc 932{
96728c05
MD
933 crit_enter();
934 while (target) {
da23a592
MD
935 int n = BSFCPUMASK(target);
936 target &= ~CPUMASK(n);
41a01a4d 937 single_apic_ipi(n, vector, delivery_mode);
96728c05
MD
938 }
939 crit_exit();
984263bc 940}
984263bc 941
984263bc
MD
942/*
943 * Timer code, in development...
944 * - suggested by rgrimes@gndrsh.aac.dev.com
945 */
bb467734
MD
946int
947get_apic_timer_frequency(void)
948{
949 return(lapic_cputimer_intr.freq);
950}
984263bc 951
984263bc
MD
952/*
953 * Load a 'downcount time' in uSeconds.
954 */
955void
2942ed63 956set_apic_timer(int us)
984263bc 957{
2942ed63 958 u_int count;
984263bc
MD
959
960 /*
2942ed63
SZ
961 * When we reach here, lapic timer's frequency
962 * must have been calculated as well as the
963 * divisor (lapic.dcr_timer is setup during the
964 * divisor calculation).
984263bc 965 */
ef612539 966 KKASSERT(lapic_cputimer_intr.freq != 0 &&
2942ed63
SZ
967 lapic_timer_divisor_idx >= 0);
968
ef612539 969 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 970 lapic_timer_oneshot(count);
984263bc
MD
971}
972
973
974/*
975 * Read remaining time in timer.
976 */
977int
978read_apic_timer(void)
979{
980#if 0
981 /** XXX FIXME: we need to return the actual remaining time,
982 * for now we just return the remaining count.
983 */
984#else
985 return lapic.ccr_timer;
986#endif
987}
988
989
990/*
991 * Spin-style delay, set delay time in uS, spin till it drains.
992 */
993void
994u_sleep(int count)
995{
996 set_apic_timer(count);
997 while (read_apic_timer())
998 /* spin */ ;
999}
ad52b37b
SZ
1000
1001void
84cc808b 1002lapic_map(vm_offset_t lapic_addr)
ad52b37b
SZ
1003{
1004 /* Local apic is mapped on last page */
1005 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1006 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1007
d557216f 1008 kprintf("lapic: at %p\n", (void *)lapic_addr);
ad52b37b 1009}
281d9482
SZ
1010
1011static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1012 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1013
1014void
1015lapic_config(void)
1016{
1017 struct lapic_enumerator *e;
1018 int error;
1019
1020 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1021 error = e->lapic_probe(e);
1022 if (!error)
1023 break;
1024 }
1025 if (e == NULL)
1026 panic("can't config lapic\n");
1027
1028 e->lapic_enumerate(e);
1029}
1030
1031void
1032lapic_enumerator_register(struct lapic_enumerator *ne)
1033{
1034 struct lapic_enumerator *e;
1035
1036 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1037 if (e->lapic_prio < ne->lapic_prio) {
1038 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1039 return;
1040 }
1041 }
1042 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1043}