pc32: Split out isa_intr.h and move isa/intr_machdep.h to include/
[dragonfly.git] / sys / platform / pc32 / isa / npx.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
21ce0dfa 36 * $DragonFly: src/sys/platform/pc32/isa/npx.c,v 1.49 2008/08/02 01:14:43 dillon Exp $
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37 */
38
39#include "opt_cpu.h"
40#include "opt_debug_npx.h"
41#include "opt_math_emulate.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/bus.h>
46#include <sys/kernel.h>
47#include <sys/malloc.h>
48#include <sys/module.h>
49#include <sys/sysctl.h>
50#include <sys/proc.h>
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51#include <sys/rman.h>
52#ifdef NPX_DEBUG
53#include <sys/syslog.h>
54#endif
55#include <sys/signalvar.h>
684a93c4 56
bd331ffe 57#include <sys/thread2.h>
684a93c4 58#include <sys/mplock2.h>
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59
60#ifndef SMP
61#include <machine/asmacros.h>
62#endif
63#include <machine/cputypes.h>
64#include <machine/frame.h>
65#include <machine/ipl.h>
66#include <machine/md_var.h>
67#include <machine/pcb.h>
68#include <machine/psl.h>
69#ifndef SMP
70#include <machine/clock.h>
71#endif
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72#include <machine/specialreg.h>
73#include <machine/segments.h>
85100692 74#include <machine/globaldata.h>
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75
76#ifndef SMP
a9295349 77#include <machine_base/icu/icu.h>
87cf6827 78#include <machine/intr_machdep.h>
21ce0dfa 79#include <bus/isa/isa.h>
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80#endif
81
82/*
83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
84 */
85
86/* Configuration flags. */
87#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
88#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
89#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
90#define NPX_PREFER_EMULATOR (1 << 3)
91
92#ifdef __GNUC__
93
94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
95#define fnclex() __asm("fnclex")
96#define fninit() __asm("fninit")
97#define fnop() __asm("fnop")
98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
642a6e88 103#ifndef CPU_DISABLE_SSE
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104#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
105#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
106#endif
107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
108 : : "n" (CR0_TS) : "ax")
109#define stop_emulating() __asm("clts")
110
111#else /* not __GNUC__ */
112
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113void fldcw (caddr_t addr);
114void fnclex (void);
115void fninit (void);
116void fnop (void);
117void fnsave (caddr_t addr);
118void fnstcw (caddr_t addr);
119void fnstsw (caddr_t addr);
120void fp_divide_by_0 (void);
121void frstor (caddr_t addr);
642a6e88 122#ifndef CPU_DISABLE_SSE
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123void fxsave (caddr_t addr);
124void fxrstor (caddr_t addr);
984263bc 125#endif
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126void start_emulating (void);
127void stop_emulating (void);
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128
129#endif /* __GNUC__ */
130
642a6e88 131#ifndef CPU_DISABLE_SSE
65d6ce10 132#define GET_FPU_EXSW_PTR(td) \
984263bc 133 (cpu_fxsr ? \
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134 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
135 &(td)->td_savefpu->sv_87.sv_ex_sw)
642a6e88 136#else /* CPU_DISABLE_SSE */
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137#define GET_FPU_EXSW_PTR(td) \
138 (&(td)->td_savefpu->sv_87.sv_ex_sw)
642a6e88 139#endif /* CPU_DISABLE_SSE */
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140
141typedef u_char bool_t;
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142#ifndef CPU_DISABLE_SSE
143static void fpu_clean_state(void);
144#endif
145
984263bc 146
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147static int npx_attach (device_t dev);
148 void npx_intr (void *);
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149static int npx_probe (device_t dev);
150static int npx_probe1 (device_t dev);
151static void fpusave (union savefpu *);
152static void fpurstor (union savefpu *);
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153
154int hw_float; /* XXX currently just alias for npx_exists */
155
156SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
157 CTLFLAG_RD, &hw_float, 0,
158 "Floatingpoint instructions executed in hardware");
629f74cc 159#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
29ad119f 160int mmxopt = 1;
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161SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
162 "MMX/XMM optimized bcopy/copyin/copyout support");
163#endif
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164
165#ifndef SMP
38787eef 166static u_int npx0_imask;
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167static struct gate_descriptor npx_idt_probeintr;
168static int npx_intrno;
169static volatile u_int npx_intrs_while_probing;
170static volatile u_int npx_traps_while_probing;
171#endif
172
173static bool_t npx_ex16;
174static bool_t npx_exists;
175static bool_t npx_irq13;
176static int npx_irq; /* irq number */
177
178#ifndef SMP
179/*
180 * Special interrupt handlers. Someday intr0-intr15 will be used to count
181 * interrupts. We'll still need a special exception 16 handler. The busy
182 * latch stuff in probeintr() can be moved to npxprobe().
183 */
184inthand_t probeintr;
185__asm(" \n\
186 .text \n\
187 .p2align 2,0x90 \n\
188 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
189" __XSTRING(CNAME(probeintr)) ": \n\
190 ss \n\
191 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
192 pushl %eax \n\
193 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
194 outb %al,$0xa0 # IO_ICU2 \n\
195 outb %al,$0x20 # IO_ICU1 \n\
196 movb $0,%al \n\
197 outb %al,$0xf0 # clear BUSY# latch \n\
198 popl %eax \n\
199 iret \n\
200");
201
202inthand_t probetrap;
203__asm(" \n\
204 .text \n\
205 .p2align 2,0x90 \n\
206 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
207" __XSTRING(CNAME(probetrap)) ": \n\
208 ss \n\
209 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
210 fnclex \n\
211 iret \n\
212");
213#endif /* SMP */
214
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215static struct krate badfprate = { 1 };
216
984263bc 217/*
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218 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
219 * whether the device exists or not (XXX should be elsewhere). Set flags
220 * to tell npxattach() what to do. Modify device struct if npx doesn't
221 * need to use interrupts. Return 1 if device exists.
222 */
223static int
a02705a9 224npx_probe(device_t dev)
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225{
226#ifdef SMP
227
228 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
229 npx_irq = 13;
230 return npx_probe1(dev);
231
232#else /* SMP */
233
234 int result;
235 u_long save_eflags;
236 u_char save_icu1_mask;
237 u_char save_icu2_mask;
238 struct gate_descriptor save_idt_npxintr;
239 struct gate_descriptor save_idt_npxtrap;
240 /*
241 * This routine is now just a wrapper for npxprobe1(), to install
242 * special npx interrupt and trap handlers, to enable npx interrupts
243 * and to disable other interrupts. Someday isa_configure() will
244 * install suitable handlers and run with interrupts enabled so we
245 * won't need to do so much here.
246 */
247 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
248 npx_irq = 13;
97359a5b 249 npx_intrno = IDT_OFFSET + npx_irq;
984263bc 250 save_eflags = read_eflags();
8a8d5d85 251 cpu_disable_intr();
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252 save_icu1_mask = inb(IO_ICU1 + 1);
253 save_icu2_mask = inb(IO_ICU2 + 1);
254 save_idt_npxintr = idt[npx_intrno];
255 save_idt_npxtrap = idt[16];
df308fcd 256 outb(IO_ICU1 + 1, ~(1 << ICU_IRQ_SLAVE));
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257 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
258 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
259 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
260 npx_idt_probeintr = idt[npx_intrno];
8a8d5d85 261 cpu_enable_intr();
984263bc 262 result = npx_probe1(dev);
8a8d5d85 263 cpu_disable_intr();
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264 outb(IO_ICU1 + 1, save_icu1_mask);
265 outb(IO_ICU2 + 1, save_icu2_mask);
266 idt[npx_intrno] = save_idt_npxintr;
267 idt[16] = save_idt_npxtrap;
268 write_eflags(save_eflags);
269 return (result);
270
271#endif /* SMP */
272}
273
274static int
a02705a9 275npx_probe1(device_t dev)
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276{
277#ifndef SMP
278 u_short control;
279 u_short status;
280#endif
281
282 /*
283 * Partially reset the coprocessor, if any. Some BIOS's don't reset
284 * it after a warm boot.
285 */
286 outb(0xf1, 0); /* full reset on some systems, NOP on others */
287 outb(0xf0, 0); /* clear BUSY# latch */
288 /*
289 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
290 * instructions. We must set the CR0_MP bit and use the CR0_TS
291 * bit to control the trap, because setting the CR0_EM bit does
292 * not cause WAIT instructions to trap. It's important to trap
293 * WAIT instructions - otherwise the "wait" variants of no-wait
294 * control instructions would degenerate to the "no-wait" variants
295 * after FP context switches but work correctly otherwise. It's
296 * particularly important to trap WAITs when there is no NPX -
297 * otherwise the "wait" variants would always degenerate.
298 *
299 * Try setting CR0_NE to get correct error reporting on 486DX's.
300 * Setting it should fail or do nothing on lesser processors.
301 */
302 load_cr0(rcr0() | CR0_MP | CR0_NE);
303 /*
304 * But don't trap while we're probing.
305 */
306 stop_emulating();
307 /*
308 * Finish resetting the coprocessor, if any. If there is an error
309 * pending, then we may get a bogus IRQ13, but probeintr() will handle
310 * it OK. Bogus halts have never been observed, but we enabled
311 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
312 */
313 fninit();
314
b670c2c9 315 device_set_desc(dev, "math processor");
984263bc 316 /*
b670c2c9
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317 * Modern CPUs all have an FPU that uses the INT16 interface
318 * and provide a simple way to verify that, so handle the
319 * common case right away.
984263bc 320 */
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321 if (cpu_feature & CPUID_FPU) {
322 npx_irq13 = 0;
323 npx_ex16 = hw_float = npx_exists = 1;
324 return (0);
325 }
984263bc 326
b670c2c9 327#ifndef SMP
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328 /*
329 * Don't use fwait here because it might hang.
330 * Don't use fnop here because it usually hangs if there is no FPU.
331 */
332 DELAY(1000); /* wait for any IRQ13 */
333#ifdef DIAGNOSTIC
334 if (npx_intrs_while_probing != 0)
26be20a0 335 kprintf("fninit caused %u bogus npx interrupt(s)\n",
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336 npx_intrs_while_probing);
337 if (npx_traps_while_probing != 0)
26be20a0 338 kprintf("fninit caused %u bogus npx trap(s)\n",
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339 npx_traps_while_probing);
340#endif
341 /*
342 * Check for a status of mostly zero.
343 */
344 status = 0x5a5a;
345 fnstsw(&status);
346 if ((status & 0xb8ff) == 0) {
347 /*
348 * Good, now check for a proper control word.
349 */
350 control = 0x5a5a;
351 fnstcw(&control);
352 if ((control & 0x1f3f) == 0x033f) {
353 hw_float = npx_exists = 1;
354 /*
355 * We have an npx, now divide by 0 to see if exception
356 * 16 works.
357 */
358 control &= ~(1 << 2); /* enable divide by 0 trap */
359 fldcw(&control);
360 npx_traps_while_probing = npx_intrs_while_probing = 0;
361 fp_divide_by_0();
362 if (npx_traps_while_probing != 0) {
363 /*
364 * Good, exception 16 works.
365 */
366 npx_ex16 = 1;
367 return (0);
368 }
369 if (npx_intrs_while_probing != 0) {
370 int rid;
371 struct resource *r;
372 void *intr;
373 /*
374 * Bad, we are stuck with IRQ13.
375 */
376 npx_irq13 = 1;
377 /*
378 * npxattach would be too late to set npx0_imask
379 */
380 npx0_imask |= (1 << npx_irq);
381
382 /*
383 * We allocate these resources permanently,
384 * so there is no need to keep track of them.
385 */
386 rid = 0;
387 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
388 &rid, IO_NPX, IO_NPX,
389 IO_NPXSIZE, RF_ACTIVE);
390 if (r == 0)
391 panic("npx: can't get ports");
392 rid = 0;
393 r = bus_alloc_resource(dev, SYS_RES_IRQ,
394 &rid, npx_irq, npx_irq,
395 1, RF_ACTIVE);
396 if (r == 0)
397 panic("npx: can't get IRQ");
398 BUS_SETUP_INTR(device_get_parent(dev),
ee61f228 399 dev, r, 0,
e9cb6d99 400 npx_intr, 0, &intr, NULL);
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401 if (intr == 0)
402 panic("npx: can't create intr");
403
404 return (0);
405 }
406 /*
407 * Worse, even IRQ13 is broken. Use emulator.
408 */
409 }
410 }
c6fc1b92 411#endif /* SMP */
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412 /*
413 * Probe failed, but we want to get to npxattach to initialize the
414 * emulator and say that it has been installed. XXX handle devices
415 * that aren't really devices better.
416 */
417 return (0);
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418}
419
420/*
421 * Attach routine - announce which it is, and wire into system
422 */
423int
a02705a9 424npx_attach(device_t dev)
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425{
426 int flags;
427
428 if (resource_int_value("npx", 0, "flags", &flags) != 0)
429 flags = 0;
430
431 if (flags)
432 device_printf(dev, "flags 0x%x ", flags);
433 if (npx_irq13) {
434 device_printf(dev, "using IRQ 13 interface\n");
435 } else {
6f535fd5 436#if defined(MATH_EMULATE)
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437 if (npx_ex16) {
438 if (!(flags & NPX_PREFER_EMULATOR))
439 device_printf(dev, "INT 16 interface\n");
440 else {
441 device_printf(dev, "FPU exists, but flags request "
442 "emulator\n");
443 hw_float = npx_exists = 0;
444 }
445 } else if (npx_exists) {
446 device_printf(dev, "error reporting broken; using 387 emulator\n");
447 hw_float = npx_exists = 0;
448 } else
449 device_printf(dev, "387 emulator\n");
450#else
451 if (npx_ex16) {
452 device_printf(dev, "INT 16 interface\n");
453 if (flags & NPX_PREFER_EMULATOR) {
454 device_printf(dev, "emulator requested, but none compiled "
455 "into kernel, using FPU\n");
456 }
457 } else
458 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
459#endif
460 }
461 npxinit(__INITIAL_NPXCW__);
462
bd331ffe 463#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
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464 /*
465 * The asm_mmx_*() routines actually use XMM as well, so only
466 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
467 */
468 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
469 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
470 (cpu_feature & CPUID_SSE2) &&
471 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
472 ) {
473 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
474 bcopy_vector = (void **)asm_xmm_bcopy;
475 ovbcopy_vector = (void **)asm_xmm_bcopy;
476 memcpy_vector = (void **)asm_xmm_memcpy;
26be20a0 477 kprintf("Using XMM optimized bcopy/copyin/copyout\n");
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478 }
479 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
480 /* XXX */
481 }
482 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
483 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
484 ) {
485 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
486 bcopy_vector = (void **)asm_mmx_bcopy;
487 ovbcopy_vector = (void **)asm_mmx_bcopy;
488 memcpy_vector = (void **)asm_mmx_memcpy;
26be20a0 489 kprintf("Using MMX optimized bcopy/copyin/copyout\n");
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490 }
491 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
492 /* XXX */
493 }
494 }
5e9b48f4 495
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496#endif
497#if 0
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498 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
499 timezero("i586_bzero()", i586_bzero) <
500 timezero("bzero()", bzero) * 4 / 5) {
501 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
502 bcopy_vector = i586_bcopy;
503 ovbcopy_vector = i586_bcopy;
504 }
505 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
afaa1d56 506 bzero_vector = i586_bzero;
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507 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
508 copyin_vector = i586_copyin;
509 copyout_vector = i586_copyout;
510 }
511 }
512#endif
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513 return (0); /* XXX unused */
514}
515
516/*
a02705a9 517 * Initialize the floating point unit.
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518 */
519void
a02705a9 520npxinit(u_short control)
984263bc 521{
1b251f0a 522 static union savefpu dummy __aligned(16);
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523
524 if (!npx_exists)
525 return;
526 /*
527 * fninit has the same h/w bugs as fnsave. Use the detoxified
528 * fnsave to throw away any junk in the fpu. npxsave() initializes
af0bff84 529 * the fpu and sets npxthread = NULL as important side effects.
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530 */
531 npxsave(&dummy);
a02705a9 532 crit_enter();
984263bc 533 stop_emulating();
984263bc 534 fldcw(&control);
65d6ce10 535 fpusave(curthread->td_savefpu);
a02705a9 536 mdcpu->gd_npxthread = NULL;
984263bc 537 start_emulating();
a02705a9 538 crit_exit();
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539}
540
541/*
542 * Free coprocessor (if we have it).
543 */
544void
bb3cd951 545npxexit(void)
984263bc 546{
bb3cd951 547 if (curthread == mdcpu->gd_npxthread)
65d6ce10 548 npxsave(curthread->td_savefpu);
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549#ifdef NPX_DEBUG
550 if (npx_exists) {
551 u_int masked_exceptions;
552
b7c628e4 553 masked_exceptions =
65d6ce10
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554 curthread->td_savefpu->sv_87.sv_env.en_cw
555 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
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556 /*
557 * Log exceptions that would have trapped with the old
558 * control word (overflow, divide by 0, and invalid operand).
559 */
560 if (masked_exceptions & 0x0d)
561 log(LOG_ERR,
562 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
bb3cd951 563 curproc->p_pid, curproc->p_comm, masked_exceptions);
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564 }
565#endif
566}
567
568/*
569 * The following mechanism is used to ensure that the FPE_... value
570 * that is passed as a trapcode to the signal handler of the user
571 * process does not have more than one bit set.
572 *
573 * Multiple bits may be set if the user process modifies the control
574 * word while a status word bit is already set. While this is a sign
575 * of bad coding, we have no choise than to narrow them down to one
576 * bit, since we must not send a trapcode that is not exactly one of
577 * the FPE_ macros.
578 *
579 * The mechanism has a static table with 127 entries. Each combination
580 * of the 7 FPU status word exception bits directly translates to a
581 * position in this table, where a single FPE_... value is stored.
582 * This FPE_... value stored there is considered the "most important"
583 * of the exception bits and will be sent as the signal code. The
584 * precedence of the bits is based upon Intel Document "Numerical
585 * Applications", Chapter "Special Computational Situations".
586 *
587 * The macro to choose one of these values does these steps: 1) Throw
588 * away status word bits that cannot be masked. 2) Throw away the bits
589 * currently masked in the control word, assuming the user isn't
590 * interested in them anymore. 3) Reinsert status word bit 7 (stack
591 * fault) if it is set, which cannot be masked but must be presered.
592 * 4) Use the remaining bits to point into the trapcode table.
593 *
594 * The 6 maskable bits in order of their preference, as stated in the
595 * above referenced Intel manual:
596 * 1 Invalid operation (FP_X_INV)
597 * 1a Stack underflow
598 * 1b Stack overflow
599 * 1c Operand of unsupported format
600 * 1d SNaN operand.
601 * 2 QNaN operand (not an exception, irrelavant here)
602 * 3 Any other invalid-operation not mentioned above or zero divide
603 * (FP_X_INV, FP_X_DZ)
604 * 4 Denormal operand (FP_X_DNML)
605 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
606 * 6 Inexact result (FP_X_IMP)
607 */
608static char fpetable[128] = {
609 0,
610 FPE_FLTINV, /* 1 - INV */
611 FPE_FLTUND, /* 2 - DNML */
612 FPE_FLTINV, /* 3 - INV | DNML */
613 FPE_FLTDIV, /* 4 - DZ */
614 FPE_FLTINV, /* 5 - INV | DZ */
615 FPE_FLTDIV, /* 6 - DNML | DZ */
616 FPE_FLTINV, /* 7 - INV | DNML | DZ */
617 FPE_FLTOVF, /* 8 - OFL */
618 FPE_FLTINV, /* 9 - INV | OFL */
619 FPE_FLTUND, /* A - DNML | OFL */
620 FPE_FLTINV, /* B - INV | DNML | OFL */
621 FPE_FLTDIV, /* C - DZ | OFL */
622 FPE_FLTINV, /* D - INV | DZ | OFL */
623 FPE_FLTDIV, /* E - DNML | DZ | OFL */
624 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
625 FPE_FLTUND, /* 10 - UFL */
626 FPE_FLTINV, /* 11 - INV | UFL */
627 FPE_FLTUND, /* 12 - DNML | UFL */
628 FPE_FLTINV, /* 13 - INV | DNML | UFL */
629 FPE_FLTDIV, /* 14 - DZ | UFL */
630 FPE_FLTINV, /* 15 - INV | DZ | UFL */
631 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
632 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
633 FPE_FLTOVF, /* 18 - OFL | UFL */
634 FPE_FLTINV, /* 19 - INV | OFL | UFL */
635 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
636 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
637 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
638 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
639 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
640 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
641 FPE_FLTRES, /* 20 - IMP */
642 FPE_FLTINV, /* 21 - INV | IMP */
643 FPE_FLTUND, /* 22 - DNML | IMP */
644 FPE_FLTINV, /* 23 - INV | DNML | IMP */
645 FPE_FLTDIV, /* 24 - DZ | IMP */
646 FPE_FLTINV, /* 25 - INV | DZ | IMP */
647 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
648 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
649 FPE_FLTOVF, /* 28 - OFL | IMP */
650 FPE_FLTINV, /* 29 - INV | OFL | IMP */
651 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
652 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
653 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
654 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
655 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
656 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
657 FPE_FLTUND, /* 30 - UFL | IMP */
658 FPE_FLTINV, /* 31 - INV | UFL | IMP */
659 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
660 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
661 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
662 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
663 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
664 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
665 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
666 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
667 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
668 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
669 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
670 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
671 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
672 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
673 FPE_FLTSUB, /* 40 - STK */
674 FPE_FLTSUB, /* 41 - INV | STK */
675 FPE_FLTUND, /* 42 - DNML | STK */
676 FPE_FLTSUB, /* 43 - INV | DNML | STK */
677 FPE_FLTDIV, /* 44 - DZ | STK */
678 FPE_FLTSUB, /* 45 - INV | DZ | STK */
679 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
680 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
681 FPE_FLTOVF, /* 48 - OFL | STK */
682 FPE_FLTSUB, /* 49 - INV | OFL | STK */
683 FPE_FLTUND, /* 4A - DNML | OFL | STK */
684 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
685 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
686 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
687 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
688 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
689 FPE_FLTUND, /* 50 - UFL | STK */
690 FPE_FLTSUB, /* 51 - INV | UFL | STK */
691 FPE_FLTUND, /* 52 - DNML | UFL | STK */
692 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
693 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
694 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
695 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
696 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
697 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
698 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
699 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
700 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
701 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
702 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
703 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
704 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
705 FPE_FLTRES, /* 60 - IMP | STK */
706 FPE_FLTSUB, /* 61 - INV | IMP | STK */
707 FPE_FLTUND, /* 62 - DNML | IMP | STK */
708 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
709 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
710 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
711 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
712 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
713 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
714 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
715 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
716 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
717 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
718 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
719 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
720 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
721 FPE_FLTUND, /* 70 - UFL | IMP | STK */
722 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
723 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
724 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
725 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
726 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
727 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
728 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
729 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
730 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
731 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
732 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
733 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
734 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
735 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
736 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
737};
738
739/*
740 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
741 *
742 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
743 * depend on longjmp() restoring a usable state. Restoring the state
744 * or examining it might fail if we didn't clear exceptions.
745 *
746 * The error code chosen will be one of the FPE_... macros. It will be
747 * sent as the second argument to old BSD-style signal handlers and as
748 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
749 *
750 * XXX the FP state is not preserved across signal handlers. So signal
751 * handlers cannot afford to do FP unless they preserve the state or
752 * longjmp() out. Both preserving the state and longjmp()ing may be
753 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
754 * solution for signals other than SIGFPE.
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755 *
756 * The MP lock is not held on entry (see i386/i386/exception.s) and
0f963623
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757 * should not be held on exit. Interrupts are enabled. We must enter
758 * a critical section to stabilize the FP system and prevent an interrupt
759 * or preemption from changing the FP state out from under us.
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760 */
761void
a02705a9 762npx_intr(void *dummy)
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763{
764 int code;
765 u_short control;
766 struct intrframe *frame;
767 u_long *exstat;
768
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769 crit_enter();
770
771 /*
772 * This exception can only occur with CR0_TS clear, otherwise we
773 * would get a DNA exception. However, since interrupts were
774 * enabled a preemption could have sneaked in and used the FP system
775 * before we entered our critical section. If that occured, the
776 * TS bit will be set and npxthread will be NULL.
777 */
778 if (npx_exists && (rcr0() & CR0_TS)) {
779 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
780 npxdna();
781 crit_exit();
782 return;
783 }
a2a5ad0d 784 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
8a8d5d85 785 get_mplock();
26be20a0 786 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 787 mdcpu->gd_npxthread, curthread, npx_exists);
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788 panic("npxintr from nowhere");
789 }
a2a5ad0d 790 if (mdcpu->gd_npxthread != curthread) {
8a8d5d85 791 get_mplock();
26be20a0 792 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 793 mdcpu->gd_npxthread, curthread, npx_exists);
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794 panic("npxintr from non-current process");
795 }
796
65d6ce10 797 exstat = GET_FPU_EXSW_PTR(curthread);
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798 outb(0xf0, 0);
799 fnstsw(exstat);
800 fnstcw(&control);
801 fnclex();
802
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803 get_mplock();
804
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805 /*
806 * Pass exception to process.
807 */
808 frame = (struct intrframe *)&dummy; /* XXX */
809 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
810 /*
811 * Interrupt is essentially a trap, so we can afford to call
812 * the SIGFPE handler (if any) as soon as the interrupt
813 * returns.
814 *
815 * XXX little or nothing is gained from this, and plenty is
816 * lost - the interrupt frame has to contain the trap frame
817 * (this is otherwise only necessary for the rescheduling trap
818 * in doreti, and the frame for that could easily be set up
819 * just before it is used).
820 */
08f2f1bb 821 curthread->td_lwp->lwp_md.md_regs = INTR_TO_TRAPFRAME(frame);
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822 /*
823 * Encode the appropriate code for detailed information on
824 * this exception.
825 */
826 code =
827 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
08f2f1bb 828 trapsignal(curthread->td_lwp, SIGFPE, code);
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MD
829 } else {
830 /*
831 * Nested interrupt. These losers occur when:
832 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
833 * o immediately after an fnsave or frstor of an
834 * error state.
835 * o a couple of 386 instructions after
836 * "fstpl _memvar" causes a stack overflow.
837 * These are especially nasty when combined with a
838 * trace trap.
839 * o an IRQ13 occurs at the same time as another higher-
840 * priority interrupt.
841 *
842 * Treat them like a true async interrupt.
843 */
7278a846 844 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
984263bc 845 }
8a8d5d85 846 rel_mplock();
0f963623 847 crit_exit();
984263bc
MD
848}
849
850/*
a02705a9
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851 * Implement the device not available (DNA) exception. gd_npxthread had
852 * better be NULL. Restore the current thread's FP state and set gd_npxthread
853 * to curthread.
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854 *
855 * Interrupts are enabled and preemption can occur. Enter a critical
856 * section to stabilize the FP state.
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857 */
858int
a02705a9 859npxdna(void)
984263bc 860{
1b251f0a 861 thread_t td = curthread;
984263bc 862 u_long *exstat;
1b251f0a 863 int didinit = 0;
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864
865 if (!npx_exists)
866 return (0);
a2a5ad0d 867 if (mdcpu->gd_npxthread != NULL) {
26be20a0 868 kprintf("npxdna: npxthread = %p, curthread = %p\n",
1b251f0a 869 mdcpu->gd_npxthread, td);
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870 panic("npxdna");
871 }
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872
873 /*
874 * Setup the initial saved state if the thread has never before
875 * used the FP unit. This also occurs when a thread pushes a
876 * signal handler and uses FP in the handler.
877 */
aad81e48 878 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) {
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879 td->td_flags |= TDF_USINGFP;
880 npxinit(__INITIAL_NPXCW__);
881 didinit = 1;
882 }
883
a02705a9
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884 /*
885 * The setting of gd_npxthread and the call to fpurstor() must not
886 * be preempted by an interrupt thread or we will take an npxdna
887 * trap and potentially save our current fpstate (which is garbage)
888 * and then restore the garbage rather then the originally saved
889 * fpstate.
890 */
bd331ffe 891 crit_enter();
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892 stop_emulating();
893 /*
894 * Record new context early in case frstor causes an IRQ13.
895 */
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896 mdcpu->gd_npxthread = td;
897 exstat = GET_FPU_EXSW_PTR(td);
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MD
898 *exstat = 0;
899 /*
900 * The following frstor may cause an IRQ13 when the state being
901 * restored has a pending error. The error will appear to have been
902 * triggered by the current (npx) user instruction even when that
903 * instruction is a no-wait instruction that should not trigger an
904 * error (e.g., fnclex). On at least one 486 system all of the
905 * no-wait instructions are broken the same as frstor, so our
906 * treatment does not amplify the breakage. On at least one
907 * 386/Cyrix 387 system, fnclex works correctly while frstor and
908 * fnsave are broken, so our treatment breaks fnclex if it is the
909 * first FPU instruction after a context switch.
910 */
93b73c2d
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911 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
912#ifndef CPU_DISABLE_SSE
913 && cpu_fxsr
914#endif
915 ) {
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916 krateprintf(&badfprate,
917 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
918 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
919 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
09dd589d 920 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
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921 }
922 fpurstor(td->td_savefpu);
bd331ffe 923 crit_exit();
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924
925 return (1);
926}
927
928/*
a02705a9 929 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
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930 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
931 * any IRQ13 to be handled immediately, and then ignore it. This routine is
932 * often called at splhigh so it must not use many system services. In
933 * particular, it's much easier to install a special handler than to
934 * guarantee that it's safe to use npxintr() and its supporting code.
96728c05
MD
935 *
936 * WARNING! This call is made during a switch and the MP lock will be
937 * setup for the new target thread rather then the current thread, so we
938 * cannot do anything here that depends on the *_mplock() functions as
939 * we may trip over their assertions.
a02705a9
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940 *
941 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
942 * kernel will always assume that the FP state is 'safe' (will not cause
943 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
944 * setup a custom save area before actually using the FP unit, but it will
945 * not bother calling fninit. This greatly improves kernel performance when
946 * it wishes to use the FP unit.
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947 */
948void
a02705a9 949npxsave(union savefpu *addr)
984263bc 950{
642a6e88 951#if defined(SMP) || !defined(CPU_DISABLE_SSE)
984263bc 952
a02705a9 953 crit_enter();
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954 stop_emulating();
955 fpusave(addr);
a2a5ad0d 956 mdcpu->gd_npxthread = NULL;
a02705a9 957 fninit();
369f5065 958 start_emulating();
a02705a9 959 crit_exit();
984263bc 960
369f5065 961#else /* !SMP and CPU_DISABLE_SSE */
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962
963 u_char icu1_mask;
964 u_char icu2_mask;
965 u_char old_icu1_mask;
966 u_char old_icu2_mask;
967 struct gate_descriptor save_idt_npxintr;
8a8d5d85 968 u_long save_eflags;
984263bc 969
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970 save_eflags = read_eflags();
971 cpu_disable_intr();
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972 old_icu1_mask = inb(IO_ICU1 + 1);
973 old_icu2_mask = inb(IO_ICU2 + 1);
974 save_idt_npxintr = idt[npx_intrno];
df308fcd 975 outb(IO_ICU1 + 1, old_icu1_mask & ~((1 << ICU_IRQ_SLAVE) | npx0_imask));
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976 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
977 idt[npx_intrno] = npx_idt_probeintr;
8a8d5d85 978 cpu_enable_intr();
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979 stop_emulating();
980 fnsave(addr);
981 fnop();
8a8d5d85 982 cpu_disable_intr();
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983 mdcpu->gd_npxthread = NULL;
984 start_emulating();
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985 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
986 icu2_mask = inb(IO_ICU2 + 1);
987 outb(IO_ICU1 + 1,
988 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
989 outb(IO_ICU2 + 1,
990 (icu2_mask & ~(npx0_imask >> 8))
991 | (old_icu2_mask & (npx0_imask >> 8)));
992 idt[npx_intrno] = save_idt_npxintr;
8a8d5d85 993 write_eflags(save_eflags); /* back to usual state */
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994
995#endif /* SMP */
996}
997
998static void
a02705a9 999fpusave(union savefpu *addr)
984263bc 1000{
642a6e88 1001#ifndef CPU_DISABLE_SSE
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1002 if (cpu_fxsr)
1003 fxsave(addr);
1004 else
1005#endif
1006 fnsave(addr);
1007}
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1008
1009/*
1010 * Save the FP state to the mcontext structure.
1011 *
1012 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
1013 * then it MUST be 16-byte aligned. Currently this is not guarenteed.
1014 */
1015void
1016npxpush(mcontext_t *mctx)
1017{
1018 thread_t td = curthread;
1019
aad81e48
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1020 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
1021
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1022 if (td->td_flags & TDF_USINGFP) {
1023 if (mdcpu->gd_npxthread == td) {
1024 /*
1025 * XXX Note: This is a bit inefficient if the signal
1026 * handler uses floating point, extra faults will
1027 * occur.
1028 */
1029 mctx->mc_ownedfp = _MC_FPOWNED_FPU;
1030 npxsave(td->td_savefpu);
1031 } else {
1032 mctx->mc_ownedfp = _MC_FPOWNED_PCB;
1033 }
1034 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
1035 td->td_flags &= ~TDF_USINGFP;
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1036 mctx->mc_fpformat =
1037#ifndef CPU_DISABLE_SSE
1038 (cpu_fxsr) ? _MC_FPFMT_XMM :
1039#endif
1040 _MC_FPFMT_387;
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1041 } else {
1042 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
09dd589d 1043 mctx->mc_fpformat = _MC_FPFMT_NODEV;
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1044 }
1045}
1046
1047/*
1048 * Restore the FP state from the mcontext structure.
1049 */
1050void
1051npxpop(mcontext_t *mctx)
1052{
1053 thread_t td = curthread;
1054
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1055 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
1056
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1057 switch(mctx->mc_ownedfp) {
1058 case _MC_FPOWNED_NONE:
1059 /*
1060 * If the signal handler used the FP unit but the interrupted
1061 * code did not, release the FP unit. Clear TDF_USINGFP will
1062 * force the FP unit to reinit so the interrupted code sees
1063 * a clean slate.
1064 */
1065 if (td->td_flags & TDF_USINGFP) {
1066 if (td == mdcpu->gd_npxthread)
1067 npxsave(td->td_savefpu);
1068 td->td_flags &= ~TDF_USINGFP;
1069 }
1070 break;
1071 case _MC_FPOWNED_FPU:
1072 case _MC_FPOWNED_PCB:
1073 /*
1074 * Clear ownership of the FP unit and restore our saved state.
1075 *
1076 * NOTE: The signal handler may have set-up some FP state and
1077 * enabled the FP unit, so we have to restore no matter what.
1078 *
1079 * XXX: This is bit inefficient, if the code being returned
1080 * to is actively using the FP this results in multiple
1081 * kernel faults.
1082 *
1083 * WARNING: The saved state was exposed to userland and may
1084 * have to be sanitized to avoid a GP fault in the kernel.
1085 */
1086 if (td == mdcpu->gd_npxthread)
1087 npxsave(td->td_savefpu);
1088 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
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1089 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
1090#ifndef CPU_DISABLE_SSE
1091 && cpu_fxsr
1092#endif
1093 ) {
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1094 krateprintf(&badfprate,
1095 "pid %d (%s) signal return from user: "
1096 "illegal FP MXCSR %08x\n",
1097 td->td_proc->p_pid,
1098 td->td_proc->p_comm,
1099 td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
1100 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
1101 }
1102 td->td_flags |= TDF_USINGFP;
1103 break;
1104 }
1105}
984263bc 1106
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1107#ifndef CPU_DISABLE_SSE
1108/*
1109 * On AuthenticAMD processors, the fxrstor instruction does not restore
1110 * the x87's stored last instruction pointer, last data pointer, and last
1111 * opcode values, except in the rare case in which the exception summary
1112 * (ES) bit in the x87 status word is set to 1.
1113 *
1114 * In order to avoid leaking this information across processes, we clean
1115 * these values by performing a dummy load before executing fxrstor().
1116 */
1117static double dummy_variable = 0.0;
1118static void
1119fpu_clean_state(void)
1120{
1121 u_short status;
1122
1123 /*
1124 * Clear the ES bit in the x87 status word if it is currently
1125 * set, in order to avoid causing a fault in the upcoming load.
1126 */
1127 fnstsw(&status);
1128 if (status & 0x80)
1129 fnclex();
1130
1131 /*
1132 * Load the dummy variable into the x87 stack. This mangles
1133 * the x87 stack, but we don't care since we're about to call
1134 * fxrstor() anyway.
1135 */
1136 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
1137}
1138#endif /* CPU_DISABLE_SSE */
1139
984263bc 1140static void
a02705a9 1141fpurstor(union savefpu *addr)
984263bc 1142{
642a6e88 1143#ifndef CPU_DISABLE_SSE
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1144 if (cpu_fxsr) {
1145 fpu_clean_state();
984263bc 1146 fxrstor(addr);
8bfb5759 1147 } else {
984263bc 1148 frstor(addr);
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1149 }
1150#else
1151 frstor(addr);
1152#endif
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1153}
1154
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1155/*
1156 * Because npx is a static device that always exists under nexus,
1157 * and is not scanned by the nexus device, we need an identify
1158 * function to install the device.
1159 */
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1160static device_method_t npx_methods[] = {
1161 /* Device interface */
39b5d600 1162 DEVMETHOD(device_identify, bus_generic_identify),
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1163 DEVMETHOD(device_probe, npx_probe),
1164 DEVMETHOD(device_attach, npx_attach),
1165 DEVMETHOD(device_detach, bus_generic_detach),
1166 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1167 DEVMETHOD(device_suspend, bus_generic_suspend),
1168 DEVMETHOD(device_resume, bus_generic_resume),
1169
1170 { 0, 0 }
1171};
1172
1173static driver_t npx_driver = {
1174 "npx",
1175 npx_methods,
1176 1, /* no softc */
1177};
1178
1179static devclass_t npx_devclass;
1180
1181/*
1182 * We prefer to attach to the root nexus so that the usual case (exception 16)
1183 * doesn't describe the processor as being `on isa'.
1184 */
1185DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);