This commit represents a major revamping of the clock interrupt and timebase
[dragonfly.git] / sys / dev / serial / sio / sio.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/isa/sio.c,v 1.291.2.35 2003/05/18 08:51:15 murray Exp $
88c4d2f6 34 * $DragonFly: src/sys/dev/serial/sio/sio.c,v 1.13 2004/01/30 05:42:15 dillon Exp $
984263bc
MD
35 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
36 * from: i386/isa sio.c,v 1.234
37 */
38
39#include "opt_comconsole.h"
40#include "opt_compat.h"
41#include "opt_ddb.h"
42#include "opt_sio.h"
1f2de5d4 43#include "use_pci.h"
984263bc 44#ifdef __i386__
1f2de5d4 45#include "use_puc.h"
984263bc 46#endif
1f2de5d4 47#include "use_sio.h"
984263bc
MD
48
49/*
50 * Serial driver, based on 386BSD-0.1 com driver.
51 * Mostly rewritten to use pseudo-DMA.
52 * Works for National Semiconductor NS8250-NS16550AF UARTs.
53 * COM driver, based on HP dca driver.
54 *
55 * Changes for PC-Card integration:
56 * - Added PC-Card driver table and handlers
57 */
58#include <sys/param.h>
59#include <sys/systm.h>
60#include <sys/reboot.h>
61#include <sys/malloc.h>
62#include <sys/tty.h>
63#include <sys/proc.h>
64#include <sys/module.h>
65#include <sys/conf.h>
66#include <sys/dkstat.h>
67#include <sys/fcntl.h>
68#include <sys/interrupt.h>
69#include <sys/kernel.h>
70#include <sys/syslog.h>
71#include <sys/sysctl.h>
72#include <sys/bus.h>
73#include <machine/bus_pio.h>
74#include <machine/bus.h>
75#include <sys/rman.h>
76#include <sys/timepps.h>
77
78#include <machine/limits.h>
79
1f2de5d4
MD
80#include <bus/isa/isareg.h>
81#include <bus/isa/isavar.h>
984263bc 82#if NPCI > 0
1f2de5d4
MD
83#include <bus/pci/pcireg.h>
84#include <bus/pci/pcivar.h>
984263bc
MD
85#endif
86#if NPUC > 0
1f2de5d4 87#include <dev/misc/puc/pucvar.h>
984263bc
MD
88#endif
89#include <machine/lock.h>
90
91#include <machine/clock.h>
92#include <machine/ipl.h>
93#ifndef SMP
94#include <machine/lock.h>
95#endif
96#include <machine/resource.h>
97
1f2de5d4 98#include "sioreg.h"
8c5c0470 99#include "sio_private.h"
984263bc
MD
100
101#ifdef COM_ESP
1f2de5d4 102#include "../ic_layer/esp.h"
984263bc 103#endif
984263bc 104
984263bc
MD
105#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
106
107#define CALLOUT_MASK 0x80
108#define CONTROL_MASK 0x60
109#define CONTROL_INIT_STATE 0x20
110#define CONTROL_LOCK_STATE 0x40
111#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
112#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \
113 | ((mynor) & 0x1f))
114#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \
115 | ((unit) & 0x1f))
116
984263bc
MD
117#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
118
119#define sio_getreg(com, off) \
120 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
121#define sio_setreg(com, off, value) \
122 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
123
124/*
125 * com state bits.
126 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
127 * than the other bits so that they can be tested as a group without masking
128 * off the low bits.
129 *
130 * The following com and tty flags correspond closely:
131 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
132 * comstop())
133 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
134 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
135 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
136 * TS_FLUSH is not used.
137 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
138 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
139 */
140#define CS_BUSY 0x80 /* output in progress */
141#define CS_TTGO 0x40 /* output not stopped by XOFF */
142#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
143#define CS_CHECKMSR 1 /* check of MSR scheduled */
144#define CS_CTS_OFLOW 2 /* use CTS output flow control */
145#define CS_DTR_OFF 0x10 /* DTR held off */
146#define CS_ODONE 4 /* output completed */
147#define CS_RTS_IFLOW 8 /* use RTS input flow control */
148#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
149
150static char const * const error_desc[] = {
151#define CE_OVERRUN 0
152 "silo overflow",
153#define CE_INTERRUPT_BUF_OVERFLOW 1
154 "interrupt-level buffer overflow",
155#define CE_TTY_BUF_OVERFLOW 2
156 "tty-level buffer overflow",
157};
158
984263bc 159#ifdef COM_ESP
5ca58d54 160static int espattach (struct com_s *com, Port_t esp_port);
984263bc 161#endif
5ca58d54 162static int sio_isa_attach (device_t dev);
984263bc
MD
163
164static timeout_t siobusycheck;
5ca58d54 165static u_int siodivisor (u_long rclk, speed_t speed);
984263bc 166static timeout_t siodtrwakeup;
5ca58d54
RG
167static void comhardclose (struct com_s *com);
168static void sioinput (struct com_s *com);
169static void siointr1 (struct com_s *com);
170static void siointr (void *arg);
171static int commctl (struct com_s *com, int bits, int how);
172static int comparam (struct tty *tp, struct termios *t);
ef0fdad1 173static inthand2_t siopoll;
5ca58d54
RG
174static int sio_isa_probe (device_t dev);
175static void siosettimeout (void);
176static int siosetwater (struct com_s *com, speed_t speed);
177static void comstart (struct tty *tp);
178static void comstop (struct tty *tp, int rw);
984263bc 179static timeout_t comwakeup;
5ca58d54
RG
180static void disc_optim (struct tty *tp, struct termios *t,
181 struct com_s *com);
984263bc 182
984263bc 183#if NPCI > 0
5ca58d54
RG
184static int sio_pci_attach (device_t dev);
185static void sio_pci_kludge_unit (device_t dev);
186static int sio_pci_probe (device_t dev);
984263bc
MD
187#endif /* NPCI > 0 */
188
189#if NPUC > 0
5ca58d54
RG
190static int sio_puc_attach (device_t dev);
191static int sio_puc_probe (device_t dev);
984263bc
MD
192#endif /* NPUC > 0 */
193
194static char driver_name[] = "sio";
195
196/* table and macro for fast conversion from a unit number to its com struct */
8c5c0470 197devclass_t sio_devclass;
984263bc
MD
198#define com_addr(unit) ((struct com_s *) \
199 devclass_get_softc(sio_devclass, unit))
200
201static device_method_t sio_isa_methods[] = {
202 /* Device interface */
203 DEVMETHOD(device_probe, sio_isa_probe),
204 DEVMETHOD(device_attach, sio_isa_attach),
205
206 { 0, 0 }
207};
208
209static driver_t sio_isa_driver = {
210 driver_name,
211 sio_isa_methods,
212 sizeof(struct com_s),
213};
214
984263bc
MD
215#if NPCI > 0
216static device_method_t sio_pci_methods[] = {
217 /* Device interface */
218 DEVMETHOD(device_probe, sio_pci_probe),
219 DEVMETHOD(device_attach, sio_pci_attach),
220
221 { 0, 0 }
222};
223
224static driver_t sio_pci_driver = {
225 driver_name,
226 sio_pci_methods,
227 sizeof(struct com_s),
228};
229#endif /* NPCI > 0 */
230
231#if NPUC > 0
232static device_method_t sio_puc_methods[] = {
233 /* Device interface */
234 DEVMETHOD(device_probe, sio_puc_probe),
235 DEVMETHOD(device_attach, sio_puc_attach),
236
237 { 0, 0 }
238};
239
240static driver_t sio_puc_driver = {
241 driver_name,
242 sio_puc_methods,
243 sizeof(struct com_s),
244};
245#endif /* NPUC > 0 */
246
247static d_open_t sioopen;
248static d_close_t sioclose;
249static d_read_t sioread;
250static d_write_t siowrite;
251static d_ioctl_t sioioctl;
252
253#define CDEV_MAJOR 28
254static struct cdevsw sio_cdevsw = {
fabb8ceb
MD
255 /* name */ driver_name,
256 /* maj */ CDEV_MAJOR,
257 /* flags */ D_TTY | D_KQFILTER,
258 /* port */ NULL,
259 /* autoq */ 0,
260
984263bc
MD
261 /* open */ sioopen,
262 /* close */ sioclose,
263 /* read */ sioread,
264 /* write */ siowrite,
265 /* ioctl */ sioioctl,
266 /* poll */ ttypoll,
267 /* mmap */ nommap,
268 /* strategy */ nostrategy,
984263bc
MD
269 /* dump */ nodump,
270 /* psize */ nopsize,
fabb8ceb 271 /* kqfilter */ ttykqfilter
984263bc
MD
272};
273
274int comconsole = -1;
275static volatile speed_t comdefaultrate = CONSPEED;
276static u_long comdefaultrclk = DEFAULT_RCLK;
277SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
278#ifdef __alpha__
279static volatile speed_t gdbdefaultrate = CONSPEED;
280#endif
281static u_int com_events; /* input chars + weighted output completions */
282static Port_t siocniobase;
283static int siocnunit;
284static Port_t siogdbiobase;
285static int siogdbunit = -1;
286static bool_t sio_registered;
287static int sio_timeout;
288static int sio_timeouts_until_log;
289static struct callout_handle sio_timeout_handle
290 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
291static int sio_numunits;
292
293#ifdef COM_ESP
294/* XXX configure this properly. */
295static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
296static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
297#endif
298
299/*
300 * handle sysctl read/write requests for console speed
301 *
302 * In addition to setting comdefaultrate for I/O through /dev/console,
303 * also set the initial and lock values for the /dev/ttyXX device
304 * if there is one associated with the console. Finally, if the /dev/tty
305 * device has already been open, change the speed on the open running port
306 * itself.
307 */
308
309static int
310sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
311{
312 int error, s;
313 speed_t newspeed;
314 struct com_s *com;
315 struct tty *tp;
316
317 newspeed = comdefaultrate;
318
319 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
320 if (error || !req->newptr)
321 return (error);
322
323 comdefaultrate = newspeed;
324
325 if (comconsole < 0) /* serial console not selected? */
326 return (0);
327
328 com = com_addr(comconsole);
329 if (com == NULL)
330 return (ENXIO);
331
332 /*
333 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
334 * (note, the lock rates really are boolean -- if non-zero, disallow
335 * speed changes)
336 */
337 com->it_in.c_ispeed = com->it_in.c_ospeed =
338 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
339 com->it_out.c_ispeed = com->it_out.c_ospeed =
340 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
341
342 /*
343 * if we're open, change the running rate too
344 */
345 tp = com->tp;
346 if (tp && (tp->t_state & TS_ISOPEN)) {
347 tp->t_termios.c_ispeed =
348 tp->t_termios.c_ospeed = comdefaultrate;
349 s = spltty();
350 error = comparam(tp, &tp->t_termios);
351 splx(s);
352 }
353 return error;
354}
355
356SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
357 0, 0, sysctl_machdep_comdefaultrate, "I", "");
358
984263bc
MD
359#if NPCI > 0
360struct pci_ids {
361 u_int32_t type;
362 const char *desc;
363 int rid;
364};
365
366static struct pci_ids pci_ids[] = {
367 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
368 { 0x2000131f, "CyberSerial (1-port) 16550", 0x10 },
369 { 0x01101407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
370 { 0x01111407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
371 { 0x048011c1, "Lucent kermit based PCI Modem", 0x14 },
372 { 0x95211415, "Oxford Semiconductor PCI Dual Port Serial", 0x10 },
373 { 0x7101135e, "SeaLevel Ultra 530.PCI Single Port Serial", 0x18 },
374 { 0x0000151f, "SmartLink 5634PCV SurfRider", 0x10 },
375 { 0x98459710, "Netmos Nm9845 PCI Bridge with Dual UART", 0x10 },
376 { 0x00000000, NULL, 0 }
377};
378
379static int
380sio_pci_attach(dev)
381 device_t dev;
382{
383 u_int32_t type;
384 struct pci_ids *id;
385
386 type = pci_get_devid(dev);
387 id = pci_ids;
388 while (id->type && id->type != type)
389 id++;
390 if (id->desc == NULL)
391 return (ENXIO);
392 sio_pci_kludge_unit(dev);
393 return (sioattach(dev, id->rid, 0UL));
394}
395
396/*
397 * Don't cut and paste this to other drivers. It is a horrible kludge
398 * which will fail to work and also be unnecessary in future versions.
399 */
400static void
401sio_pci_kludge_unit(dev)
402 device_t dev;
403{
404 devclass_t dc;
405 int err;
406 int start;
407 int unit;
408
409 unit = 0;
410 start = 0;
411 while (resource_int_value("sio", unit, "port", &start) == 0 &&
412 start > 0)
413 unit++;
414 if (device_get_unit(dev) < unit) {
415 dc = device_get_devclass(dev);
416 while (devclass_get_device(dc, unit))
417 unit++;
418 device_printf(dev, "moving to sio%d\n", unit);
419 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
420 if (err)
421 device_printf(dev, "error moving device %d\n", err);
422 }
423}
424
425static int
426sio_pci_probe(dev)
427 device_t dev;
428{
429 u_int32_t type;
430 struct pci_ids *id;
431
432 type = pci_get_devid(dev);
433 id = pci_ids;
434 while (id->type && id->type != type)
435 id++;
436 if (id->desc == NULL)
437 return (ENXIO);
438 device_set_desc(dev, id->desc);
439 return (sioprobe(dev, id->rid, 0UL));
440}
441#endif /* NPCI > 0 */
442
443#if NPUC > 0
444static int
445sio_puc_attach(dev)
446 device_t dev;
447{
448 u_int rclk;
449
450 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
451 &rclk) != 0)
452 rclk = DEFAULT_RCLK;
453 return (sioattach(dev, 0, rclk));
454}
455
456static int
457sio_puc_probe(dev)
458 device_t dev;
459{
460 u_int rclk;
461
462 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
463 &rclk) != 0)
464 rclk = DEFAULT_RCLK;
465 return (sioprobe(dev, 0, rclk));
466}
467#endif /* NPUC */
468
469static struct isa_pnp_id sio_ids[] = {
470 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
471 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
472 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
473 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
474 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
475 /* Devices that do not have a compatid */
476 {0x12206804, NULL}, /* ACH2012 - 5634BTS 56K Video Ready Modem */
477 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
478 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
479 {0x21107905, NULL}, /* AKY1021 - 56K Plug&Play Modem */
480 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
481 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
482 {0x56159008, NULL}, /* BDP1556 - B.D. Smart One 56SPS,Voice Modem*/
483 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
484 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
485 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
486 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
487 {0x0094490a, NULL}, /* BRI9400 - Boca K56Flex PnP */
488 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
489 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
490 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
491 {0x01308c0e, NULL}, /* CTL3001 - Creative Labs Phoneblaster */
492 {0x36033610, NULL}, /* DAV0336 - DAVICOM 336PNP MODEM */
493 {0x01009416, NULL}, /* ETT0001 - E-Tech Bullet 33k6 PnP */
494 {0x0000aa1a, NULL}, /* FUJ0000 - FUJITSU Modem 33600 PNP/I2 */
495 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
496 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
497 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
498 {0x0116c31e, NULL}, /* GVC1601 - Rockwell V.34 Plug & Play Modem */
499 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
500 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
501 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
502 {0x8100e425, NULL}, /* IOD0081 - I-O DATA DEVICE,INC. IFML-560 */
503 {0x21002534, NULL}, /* MAE0021 - Jetstream Int V.90 56k Voice Series 2*/
504 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
505 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
506 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
507 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
508 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
509 {0x08804f3f, NULL}, /* OZO8008 - Zoom (33.6k Modem) */
510 {0x0f804f3f, NULL}, /* OZO800f - Zoom 2812 (56k Modem) */
511 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
512 {0x00914f3f, NULL}, /* OZO9100 - Zoom 2919 (K56 Faxmodem) */
513 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
514 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
515 {0x1200b23d, NULL}, /* RSS0012 - OMRON ME5614ISA */
516 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
517 {0x6202734a, NULL}, /* RSS0262 - 5614Jx3[G] V90+K56Flex Modem */
518 {0x1010104d, NULL}, /* SHP1010 - Rockwell 33600bps Modem */
519 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
520 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
521 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
522 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
523 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
524 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
525 {0x7016b04e, NULL}, /* SUP1670 - Supra 336i V+ Intl */
526 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
527 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
528 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
529 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
530 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
531 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
532 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
533 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
534 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
535 {0x11007256, NULL}, /* USR0011 - USR ? */
536 {0x01017256, NULL}, /* USR0101 - USR ? */
537 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
538 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
539 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
540 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
541 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
542 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
543 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
544 {0x90307256, NULL}, /* USR3090 - USR ? */
545 {0x70917256, NULL}, /* USR9170 - U.S. Robotics 56K FAX INT */
546 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
547 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
548 {0x01a0896a, NULL}, /* ZTIA001 - Zoom Internal V90 Faxmodem */
549 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
550 {0}
551};
552
553
554
555static int
556sio_isa_probe(dev)
557 device_t dev;
558{
559 /* Check isapnp ids */
560 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
561 return (ENXIO);
562 return (sioprobe(dev, 0, 0UL));
563}
564
8c5c0470 565int
984263bc
MD
566sioprobe(dev, xrid, rclk)
567 device_t dev;
568 int xrid;
569 u_long rclk;
570{
571#if 0
572 static bool_t already_init;
573 device_t xdev;
574#endif
575 struct com_s *com;
576 u_int divisor;
577 bool_t failures[10];
578 int fn;
579 device_t idev;
580 Port_t iobase;
581 intrmask_t irqmap[4];
582 intrmask_t irqs;
583 u_char mcr_image;
584 int result;
585 u_long xirq;
586 u_int flags = device_get_flags(dev);
587 int rid;
588 struct resource *port;
589
590 rid = xrid;
591 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
592 0, ~0, IO_COMSIZE, RF_ACTIVE);
593 if (!port)
594 return (ENXIO);
595
596 com = device_get_softc(dev);
597 com->bst = rman_get_bustag(port);
598 com->bsh = rman_get_bushandle(port);
599 if (rclk == 0)
600 rclk = DEFAULT_RCLK;
601 com->rclk = rclk;
602
603#if 0
604 /*
605 * XXX this is broken - when we are first called, there are no
606 * previously configured IO ports. We could hard code
607 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
608 * This code has been doing nothing since the conversion since
609 * "count" is zero the first time around.
610 */
611 if (!already_init) {
612 /*
613 * Turn off MCR_IENABLE for all likely serial ports. An unused
614 * port with its MCR_IENABLE gate open will inhibit interrupts
615 * from any used port that shares the interrupt vector.
616 * XXX the gate enable is elsewhere for some multiports.
617 */
618 device_t *devs;
619 int count, i, xioport;
620
621 devclass_get_devices(sio_devclass, &devs, &count);
622 for (i = 0; i < count; i++) {
623 xdev = devs[i];
624 if (device_is_enabled(xdev) &&
625 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
626 NULL) == 0)
627 outb(xioport + com_mcr, 0);
628 }
629 free(devs, M_TEMP);
630 already_init = TRUE;
631 }
632#endif
633
634 if (COM_LLCONSOLE(flags)) {
635 printf("sio%d: reserved for low-level i/o\n",
636 device_get_unit(dev));
637 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
638 return (ENXIO);
639 }
640
641 /*
642 * If the device is on a multiport card and has an AST/4
643 * compatible interrupt control register, initialize this
644 * register and prepare to leave MCR_IENABLE clear in the mcr.
645 * Otherwise, prepare to set MCR_IENABLE in the mcr.
646 * Point idev to the device struct giving the correct id_irq.
647 * This is the struct for the master device if there is one.
648 */
649 idev = dev;
650 mcr_image = MCR_IENABLE;
651#ifdef COM_MULTIPORT
652 if (COM_ISMULTIPORT(flags)) {
653 Port_t xiobase;
654 u_long io;
655
656 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
657 if (idev == NULL) {
658 printf("sio%d: master device %d not configured\n",
659 device_get_unit(dev), COM_MPMASTER(flags));
660 idev = dev;
661 }
662 if (!COM_NOTAST4(flags)) {
663 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
664 NULL) == 0) {
665 xiobase = io;
666 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
667 NULL, NULL) == 0)
668 outb(xiobase + com_scr, 0x80);
669 else
670 outb(xiobase + com_scr, 0);
671 }
672 mcr_image = 0;
673 }
674 }
675#endif /* COM_MULTIPORT */
676 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
677 mcr_image = 0;
678
679 bzero(failures, sizeof failures);
680 iobase = rman_get_start(port);
681
682 /*
683 * We don't want to get actual interrupts, just masked ones.
684 * Interrupts from this line should already be masked in the ICU,
685 * but mask them in the processor as well in case there are some
686 * (misconfigured) shared interrupts.
687 */
8a8d5d85 688 com_lock();
984263bc
MD
689/* EXTRA DELAY? */
690
691 /*
692 * For the TI16754 chips, set prescaler to 1 (4 is often the
693 * default after-reset value) as otherwise it's impossible to
694 * get highest baudrates.
695 */
696 if (COM_TI16754(flags)) {
697 u_char cfcr, efr;
698
699 cfcr = sio_getreg(com, com_cfcr);
700 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
701 efr = sio_getreg(com, com_efr);
702 /* Unlock extended features to turn off prescaler. */
703 sio_setreg(com, com_efr, efr | EFR_EFE);
704 /* Disable EFR. */
705 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
706 /* Turn off prescaler. */
707 sio_setreg(com, com_mcr,
708 sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
709 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
710 sio_setreg(com, com_efr, efr);
711 sio_setreg(com, com_cfcr, cfcr);
712 }
713
714 /*
715 * Initialize the speed and the word size and wait long enough to
716 * drain the maximum of 16 bytes of junk in device output queues.
717 * The speed is undefined after a master reset and must be set
718 * before relying on anything related to output. There may be
719 * junk after a (very fast) soft reboot and (apparently) after
720 * master reset.
721 * XXX what about the UART bug avoided by waiting in comparam()?
722 * We don't want to to wait long enough to drain at 2 bps.
723 */
724 if (iobase == siocniobase)
725 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
726 else {
727 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
728 divisor = siodivisor(rclk, SIO_TEST_SPEED);
729 sio_setreg(com, com_dlbl, divisor & 0xff);
730 sio_setreg(com, com_dlbh, divisor >> 8);
731 sio_setreg(com, com_cfcr, CFCR_8BITS);
732 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
733 }
734
735 /*
736 * Enable the interrupt gate and disable device interupts. This
737 * should leave the device driving the interrupt line low and
738 * guarantee an edge trigger if an interrupt can be generated.
739 */
740/* EXTRA DELAY? */
741 sio_setreg(com, com_mcr, mcr_image);
742 sio_setreg(com, com_ier, 0);
743 DELAY(1000); /* XXX */
744 irqmap[0] = isa_irq_pending();
745
746 /*
747 * Attempt to set loopback mode so that we can send a null byte
748 * without annoying any external device.
749 */
750/* EXTRA DELAY? */
751 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
752
753 /*
754 * Attempt to generate an output interrupt. On 8250's, setting
755 * IER_ETXRDY generates an interrupt independent of the current
756 * setting and independent of whether the THR is empty. On 16450's,
757 * setting IER_ETXRDY generates an interrupt independent of the
758 * current setting. On 16550A's, setting IER_ETXRDY only
759 * generates an interrupt when IER_ETXRDY is not already set.
760 */
761 sio_setreg(com, com_ier, IER_ETXRDY);
762
763 /*
764 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
765 * an interrupt. They'd better generate one for actually doing
766 * output. Loopback may be broken on the same incompatibles but
767 * it's unlikely to do more than allow the null byte out.
768 */
769 sio_setreg(com, com_data, 0);
770 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
771
772 /*
773 * Turn off loopback mode so that the interrupt gate works again
774 * (MCR_IENABLE was hidden). This should leave the device driving
775 * an interrupt line high. It doesn't matter if the interrupt
776 * line oscillates while we are not looking at it, since interrupts
777 * are disabled.
778 */
779/* EXTRA DELAY? */
780 sio_setreg(com, com_mcr, mcr_image);
781
782 /*
783 * Some pcmcia cards have the "TXRDY bug", so we check everyone
784 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
785 */
786 if (COM_NOPROBE(flags)) {
787 /* Reading IIR register twice */
788 for (fn = 0; fn < 2; fn ++) {
789 DELAY(10000);
790 failures[6] = sio_getreg(com, com_iir);
791 }
792 /* Check IIR_TXRDY clear ? */
793 result = 0;
794 if (failures[6] & IIR_TXRDY) {
795 /* Nop, Double check with clearing IER */
796 sio_setreg(com, com_ier, 0);
797 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
798 /* Ok. we're familia this gang */
799 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
800 } else {
801 /* Unknown, Just omit this chip.. XXX */
802 result = ENXIO;
803 sio_setreg(com, com_mcr, 0);
804 }
805 } else {
806 /* OK. this is well-known guys */
807 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
808 }
809 sio_setreg(com, com_ier, 0);
810 sio_setreg(com, com_cfcr, CFCR_8BITS);
8a8d5d85 811 com_unlock();
984263bc
MD
812 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
813 return (iobase == siocniobase ? 0 : result);
814 }
815
816 /*
817 * Check that
818 * o the CFCR, IER and MCR in UART hold the values written to them
819 * (the values happen to be all distinct - this is good for
820 * avoiding false positive tests from bus echoes).
821 * o an output interrupt is generated and its vector is correct.
822 * o the interrupt goes away when the IIR in the UART is read.
823 */
824/* EXTRA DELAY? */
825 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
826 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
827 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
828 DELAY(10000); /* Some internal modems need this time */
829 irqmap[1] = isa_irq_pending();
830 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
831 DELAY(1000); /* XXX */
832 irqmap[2] = isa_irq_pending();
833 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
834
835 /*
836 * Turn off all device interrupts and check that they go off properly.
837 * Leave MCR_IENABLE alone. For ports without a master port, it gates
838 * the OUT2 output of the UART to
839 * the ICU input. Closing the gate would give a floating ICU input
840 * (unless there is another device driving it) and spurious interrupts.
841 * (On the system that this was first tested on, the input floats high
842 * and gives a (masked) interrupt as soon as the gate is closed.)
843 */
844 sio_setreg(com, com_ier, 0);
845 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
846 failures[7] = sio_getreg(com, com_ier);
847 DELAY(1000); /* XXX */
848 irqmap[3] = isa_irq_pending();
849 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
850
8a8d5d85 851 com_unlock();
984263bc
MD
852
853 irqs = irqmap[1] & ~irqmap[0];
854 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
855 ((1 << xirq) & irqs) == 0)
856 printf(
857 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
858 device_get_unit(dev), xirq, irqs);
859 if (bootverbose)
860 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
861 device_get_unit(dev),
862 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
863
864 result = 0;
865 for (fn = 0; fn < sizeof failures; ++fn)
866 if (failures[fn]) {
867 sio_setreg(com, com_mcr, 0);
868 result = ENXIO;
869 if (bootverbose) {
870 printf("sio%d: probe failed test(s):",
871 device_get_unit(dev));
872 for (fn = 0; fn < sizeof failures; ++fn)
873 if (failures[fn])
874 printf(" %d", fn);
875 printf("\n");
876 }
877 break;
878 }
879 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
880 return (iobase == siocniobase ? 0 : result);
881}
882
883#ifdef COM_ESP
884static int
885espattach(com, esp_port)
886 struct com_s *com;
887 Port_t esp_port;
888{
889 u_char dips;
890 u_char val;
891
892 /*
893 * Check the ESP-specific I/O port to see if we're an ESP
894 * card. If not, return failure immediately.
895 */
896 if ((inb(esp_port) & 0xf3) == 0) {
897 printf(" port 0x%x is not an ESP board?\n", esp_port);
898 return (0);
899 }
900
901 /*
902 * We've got something that claims to be a Hayes ESP card.
903 * Let's hope so.
904 */
905
906 /* Get the dip-switch configuration */
907 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
908 dips = inb(esp_port + ESP_STATUS1);
909
910 /*
911 * Bits 0,1 of dips say which COM port we are.
912 */
913 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
914 printf(" : ESP");
915 else {
916 printf(" esp_port has com %d\n", dips & 0x03);
917 return (0);
918 }
919
920 /*
921 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
922 */
923 outb(esp_port + ESP_CMD1, ESP_GETTEST);
924 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
925 val = inb(esp_port + ESP_STATUS2);
926 if ((val & 0x70) < 0x20) {
927 printf("-old (%o)", val & 0x70);
928 return (0);
929 }
930
931 /*
932 * Check for ability to emulate 16550: bit 7 == 1
933 */
934 if ((dips & 0x80) == 0) {
935 printf(" slave");
936 return (0);
937 }
938
939 /*
940 * Okay, we seem to be a Hayes ESP card. Whee.
941 */
942 com->esp = TRUE;
943 com->esp_port = esp_port;
944 return (1);
945}
946#endif /* COM_ESP */
947
948static int
949sio_isa_attach(dev)
950 device_t dev;
951{
952 return (sioattach(dev, 0, 0UL));
953}
954
8c5c0470 955int
984263bc
MD
956sioattach(dev, xrid, rclk)
957 device_t dev;
958 int xrid;
959 u_long rclk;
960{
961 struct com_s *com;
962#ifdef COM_ESP
963 Port_t *espp;
964#endif
965 Port_t iobase;
966 int minorbase;
967 int unit;
968 u_int flags;
969 int rid;
970 struct resource *port;
971 int ret;
972
973 rid = xrid;
974 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
975 0, ~0, IO_COMSIZE, RF_ACTIVE);
976 if (!port)
977 return (ENXIO);
978
979 iobase = rman_get_start(port);
980 unit = device_get_unit(dev);
981 com = device_get_softc(dev);
982 flags = device_get_flags(dev);
983
984 if (unit >= sio_numunits)
985 sio_numunits = unit + 1;
986 /*
987 * sioprobe() has initialized the device registers as follows:
988 * o cfcr = CFCR_8BITS.
989 * It is most important that CFCR_DLAB is off, so that the
990 * data port is not hidden when we enable interrupts.
991 * o ier = 0.
992 * Interrupts are only enabled when the line is open.
993 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
994 * interrupt control register or the config specifies no irq.
995 * Keeping MCR_DTR and MCR_RTS off might stop the external
996 * device from sending before we are ready.
997 */
998 bzero(com, sizeof *com);
999 com->unit = unit;
1000 com->ioportres = port;
1001 com->bst = rman_get_bustag(port);
1002 com->bsh = rman_get_bushandle(port);
1003 com->cfcr_image = CFCR_8BITS;
1004 com->dtr_wait = 3 * hz;
1005 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1006 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1007 com->tx_fifo_size = 1;
1008 com->obufs[0].l_head = com->obuf1;
1009 com->obufs[1].l_head = com->obuf2;
1010
1011 com->data_port = iobase + com_data;
1012 com->int_id_port = iobase + com_iir;
1013 com->modem_ctl_port = iobase + com_mcr;
1014 com->mcr_image = inb(com->modem_ctl_port);
1015 com->line_status_port = iobase + com_lsr;
1016 com->modem_status_port = iobase + com_msr;
1017 com->intr_ctl_port = iobase + com_ier;
1018
1019 if (rclk == 0)
1020 rclk = DEFAULT_RCLK;
1021 com->rclk = rclk;
1022
1023 /*
1024 * We don't use all the flags from <sys/ttydefaults.h> since they
1025 * are only relevant for logins. It's important to have echo off
1026 * initially so that the line doesn't start blathering before the
1027 * echo flag can be turned off.
1028 */
1029 com->it_in.c_iflag = 0;
1030 com->it_in.c_oflag = 0;
1031 com->it_in.c_cflag = TTYDEF_CFLAG;
1032 com->it_in.c_lflag = 0;
1033 if (unit == comconsole) {
1034 com->it_in.c_iflag = TTYDEF_IFLAG;
1035 com->it_in.c_oflag = TTYDEF_OFLAG;
1036 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1037 com->it_in.c_lflag = TTYDEF_LFLAG;
1038 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1039 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1040 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1041 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1042 } else
1043 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1044 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
8a8d5d85 1045 com_unlock();
984263bc
MD
1046 /*
1047 * Leave i/o resources allocated if this is a `cn'-level
1048 * console, so that other devices can't snarf them.
1049 */
1050 if (iobase != siocniobase)
1051 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1052 return (ENOMEM);
1053 }
8a8d5d85 1054 com_unlock();
984263bc
MD
1055 termioschars(&com->it_in);
1056 com->it_out = com->it_in;
1057
1058 /* attempt to determine UART type */
1059 printf("sio%d: type", unit);
1060
1061
1062#ifdef COM_MULTIPORT
1063 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1064#else
1065 if (!COM_IIR_TXRDYBUG(flags))
1066#endif
1067 {
1068 u_char scr;
1069 u_char scr1;
1070 u_char scr2;
1071
1072 scr = sio_getreg(com, com_scr);
1073 sio_setreg(com, com_scr, 0xa5);
1074 scr1 = sio_getreg(com, com_scr);
1075 sio_setreg(com, com_scr, 0x5a);
1076 scr2 = sio_getreg(com, com_scr);
1077 sio_setreg(com, com_scr, scr);
1078 if (scr1 != 0xa5 || scr2 != 0x5a) {
1079 printf(" 8250");
1080 goto determined_type;
1081 }
1082 }
1083 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1084 DELAY(100);
1085 com->st16650a = 0;
1086 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1087 case FIFO_RX_LOW:
1088 printf(" 16450");
1089 break;
1090 case FIFO_RX_MEDL:
1091 printf(" 16450?");
1092 break;
1093 case FIFO_RX_MEDH:
1094 printf(" 16550?");
1095 break;
1096 case FIFO_RX_HIGH:
1097 if (COM_NOFIFO(flags)) {
1098 printf(" 16550A fifo disabled");
1099 } else {
1100 com->hasfifo = TRUE;
1101 if (COM_ST16650A(flags)) {
1102 com->st16650a = 1;
1103 com->tx_fifo_size = 32;
1104 printf(" ST16650A");
1105 } else if (COM_TI16754(flags)) {
1106 com->tx_fifo_size = 64;
1107 printf(" TI16754");
1108 } else {
1109 com->tx_fifo_size = COM_FIFOSIZE(flags);
1110 printf(" 16550A");
1111 }
1112 }
1113#ifdef COM_ESP
1114 for (espp = likely_esp_ports; *espp != 0; espp++)
1115 if (espattach(com, *espp)) {
1116 com->tx_fifo_size = 1024;
1117 break;
1118 }
1119#endif
1120 if (!com->st16650a && !COM_TI16754(flags)) {
1121 if (!com->tx_fifo_size)
1122 com->tx_fifo_size = 16;
1123 else
1124 printf(" lookalike with %d bytes FIFO",
1125 com->tx_fifo_size);
1126 }
1127
1128 break;
1129 }
1130
1131#ifdef COM_ESP
1132 if (com->esp) {
1133 /*
1134 * Set 16550 compatibility mode.
1135 * We don't use the ESP_MODE_SCALE bit to increase the
1136 * fifo trigger levels because we can't handle large
1137 * bursts of input.
1138 * XXX flow control should be set in comparam(), not here.
1139 */
1140 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1141 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1142
1143 /* Set RTS/CTS flow control. */
1144 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1145 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1146 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1147
1148 /* Set flow-control levels. */
1149 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1150 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1151 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1152 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1153 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1154 }
1155#endif /* COM_ESP */
1156 sio_setreg(com, com_fifo, 0);
1157determined_type: ;
1158
1159#ifdef COM_MULTIPORT
1160 if (COM_ISMULTIPORT(flags)) {
1161 device_t masterdev;
1162
1163 com->multiport = TRUE;
1164 printf(" (multiport");
1165 if (unit == COM_MPMASTER(flags))
1166 printf(" master");
1167 printf(")");
1168 masterdev = devclass_get_device(sio_devclass,
1169 COM_MPMASTER(flags));
1170 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1171 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1172 }
1173#endif /* COM_MULTIPORT */
1174 if (unit == comconsole)
1175 printf(", console");
1176 if (COM_IIR_TXRDYBUG(flags))
1177 printf(" with a bogus IIR_TXRDY register");
1178 printf("\n");
1179
1180 if (!sio_registered) {
ef0fdad1 1181 register_swi(SWI_TTY, siopoll, NULL ,"swi_siopoll");
984263bc
MD
1182 sio_registered = TRUE;
1183 }
1184 minorbase = UNIT_TO_MINOR(unit);
1185 make_dev(&sio_cdevsw, minorbase,
1186 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1187 make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE,
1188 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1189 make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE,
1190 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1191 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK,
1192 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1193 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_INIT_STATE,
1194 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1195 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE,
1196 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1197 com->flags = flags;
1198 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1199 pps_init(&com->pps);
1200
1201 rid = 0;
1202 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1203 RF_ACTIVE);
1204 if (com->irqres) {
1205 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1206 INTR_TYPE_TTY | INTR_TYPE_FAST,
1207 siointr, com, &com->cookie);
1208 if (ret) {
1209 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1210 com->irqres, INTR_TYPE_TTY,
1211 siointr, com, &com->cookie);
1212 if (ret == 0)
1213 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1214 }
1215 if (ret)
1216 device_printf(dev, "could not activate interrupt\n");
1217#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1218 defined(ALT_BREAK_TO_DEBUGGER))
1219 /*
1220 * Enable interrupts for early break-to-debugger support
1221 * on the console.
1222 */
1223 if (ret == 0 && unit == comconsole)
1224 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1225 IER_EMSC);
1226#endif
1227 }
1228
1229 return (0);
1230}
1231
1232static int
41c20dac 1233sioopen(dev_t dev, int flag, int mode, struct thread *td)
984263bc
MD
1234{
1235 struct com_s *com;
1236 int error;
1237 int mynor;
1238 int s;
1239 struct tty *tp;
1240 int unit;
1241
1242 mynor = minor(dev);
1243 unit = MINOR_TO_UNIT(mynor);
1244 com = com_addr(unit);
1245 if (com == NULL)
1246 return (ENXIO);
1247 if (com->gone)
1248 return (ENXIO);
1249 if (mynor & CONTROL_MASK)
1250 return (0);
1251 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1252 s = spltty();
1253 /*
1254 * We jump to this label after all non-interrupted sleeps to pick
1255 * up any changes of the device state.
1256 */
1257open_top:
1258 while (com->state & CS_DTR_OFF) {
377d4740 1259 error = tsleep(&com->dtr_wait, PCATCH, "siodtr", 0);
984263bc
MD
1260 if (com_addr(unit) == NULL)
1261 return (ENXIO);
1262 if (error != 0 || com->gone)
1263 goto out;
1264 }
1265 if (tp->t_state & TS_ISOPEN) {
1266 /*
1267 * The device is open, so everything has been initialized.
1268 * Handle conflicts.
1269 */
1270 if (mynor & CALLOUT_MASK) {
1271 if (!com->active_out) {
1272 error = EBUSY;
1273 goto out;
1274 }
1275 } else {
1276 if (com->active_out) {
1277 if (flag & O_NONBLOCK) {
1278 error = EBUSY;
1279 goto out;
1280 }
1281 error = tsleep(&com->active_out,
377d4740 1282 PCATCH, "siobi", 0);
984263bc
MD
1283 if (com_addr(unit) == NULL)
1284 return (ENXIO);
1285 if (error != 0 || com->gone)
1286 goto out;
1287 goto open_top;
1288 }
1289 }
dadab5e9 1290 if (tp->t_state & TS_XCLUDE && suser(td)) {
984263bc
MD
1291 error = EBUSY;
1292 goto out;
1293 }
1294 } else {
1295 /*
1296 * The device isn't open, so there are no conflicts.
1297 * Initialize it. Initialization is done twice in many
1298 * cases: to preempt sleeping callin opens if we are
1299 * callout, and to complete a callin open after DCD rises.
1300 */
1301 tp->t_oproc = comstart;
1302 tp->t_param = comparam;
1303 tp->t_stop = comstop;
1304 tp->t_dev = dev;
1305 tp->t_termios = mynor & CALLOUT_MASK
1306 ? com->it_out : com->it_in;
1307 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1308 com->poll = com->no_irq;
1309 com->poll_output = com->loses_outints;
1310 ++com->wopeners;
1311 error = comparam(tp, &tp->t_termios);
1312 --com->wopeners;
1313 if (error != 0)
1314 goto out;
1315 /*
1316 * XXX we should goto open_top if comparam() slept.
1317 */
1318 if (com->hasfifo) {
1319 /*
1320 * (Re)enable and drain fifos.
1321 *
1322 * Certain SMC chips cause problems if the fifos
1323 * are enabled while input is ready. Turn off the
1324 * fifo if necessary to clear the input. We test
1325 * the input ready bit after enabling the fifos
1326 * since we've already enabled them in comparam()
1327 * and to handle races between enabling and fresh
1328 * input.
1329 */
1330 while (TRUE) {
1331 sio_setreg(com, com_fifo,
1332 FIFO_RCV_RST | FIFO_XMT_RST
1333 | com->fifo_image);
1334 /*
1335 * XXX the delays are for superstitious
1336 * historical reasons. It must be less than
1337 * the character time at the maximum
1338 * supported speed (87 usec at 115200 bps
1339 * 8N1). Otherwise we might loop endlessly
1340 * if data is streaming in. We used to use
1341 * delays of 100. That usually worked
1342 * because DELAY(100) used to usually delay
1343 * for about 85 usec instead of 100.
1344 */
1345 DELAY(50);
1346 if (!(inb(com->line_status_port) & LSR_RXRDY))
1347 break;
1348 sio_setreg(com, com_fifo, 0);
1349 DELAY(50);
1350 (void) inb(com->data_port);
1351 }
1352 }
1353
8a8d5d85 1354 com_lock();
984263bc
MD
1355 (void) inb(com->line_status_port);
1356 (void) inb(com->data_port);
1357 com->prev_modem_status = com->last_modem_status
1358 = inb(com->modem_status_port);
1359 if (COM_IIR_TXRDYBUG(com->flags)) {
1360 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1361 | IER_EMSC);
1362 } else {
1363 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1364 | IER_ERLS | IER_EMSC);
1365 }
8a8d5d85 1366 com_unlock();
984263bc
MD
1367 /*
1368 * Handle initial DCD. Callout devices get a fake initial
1369 * DCD (trapdoor DCD). If we are callout, then any sleeping
1370 * callin opens get woken up and resume sleeping on "siobi"
1371 * instead of "siodcd".
1372 */
1373 /*
1374 * XXX `mynor & CALLOUT_MASK' should be
1375 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1376 * TRAPDOOR_CARRIER is the default initial state for callout
1377 * devices and SOFT_CARRIER is like CLOCAL except it hides
1378 * the true carrier.
1379 */
1380 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1381 (*linesw[tp->t_line].l_modem)(tp, 1);
1382 }
1383 /*
1384 * Wait for DCD if necessary.
1385 */
1386 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1387 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1388 ++com->wopeners;
377d4740 1389 error = tsleep(TSA_CARR_ON(tp), PCATCH, "siodcd", 0);
984263bc
MD
1390 if (com_addr(unit) == NULL)
1391 return (ENXIO);
1392 --com->wopeners;
1393 if (error != 0 || com->gone)
1394 goto out;
1395 goto open_top;
1396 }
1397 error = (*linesw[tp->t_line].l_open)(dev, tp);
1398 disc_optim(tp, &tp->t_termios, com);
1399 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1400 com->active_out = TRUE;
1401 siosettimeout();
1402out:
1403 splx(s);
1404 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1405 comhardclose(com);
1406 return (error);
1407}
1408
1409static int
41c20dac 1410sioclose(dev_t dev, int flag, int mode, struct thread *td)
984263bc
MD
1411{
1412 struct com_s *com;
1413 int mynor;
1414 int s;
1415 struct tty *tp;
1416
1417 mynor = minor(dev);
1418 if (mynor & CONTROL_MASK)
1419 return (0);
1420 com = com_addr(MINOR_TO_UNIT(mynor));
1421 if (com == NULL)
1422 return (ENODEV);
1423 tp = com->tp;
1424 s = spltty();
1425 (*linesw[tp->t_line].l_close)(tp, flag);
1426 disc_optim(tp, &tp->t_termios, com);
1427 comstop(tp, FREAD | FWRITE);
1428 comhardclose(com);
1429 ttyclose(tp);
1430 siosettimeout();
1431 splx(s);
1432 if (com->gone) {
1433 printf("sio%d: gone\n", com->unit);
1434 s = spltty();
1435 if (com->ibuf != NULL)
1436 free(com->ibuf, M_DEVBUF);
1437 bzero(tp, sizeof *tp);
1438 splx(s);
1439 }
1440 return (0);
1441}
1442
1443static void
1444comhardclose(com)
1445 struct com_s *com;
1446{
1447 int s;
1448 struct tty *tp;
1449 int unit;
1450
1451 unit = com->unit;
1452 s = spltty();
1453 com->poll = FALSE;
1454 com->poll_output = FALSE;
1455 com->do_timestamp = FALSE;
1456 com->do_dcd_timestamp = FALSE;
1457 com->pps.ppsparam.mode = 0;
1458 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1459 tp = com->tp;
1460
1461#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1462 defined(ALT_BREAK_TO_DEBUGGER))
1463 /*
1464 * Leave interrupts enabled and don't clear DTR if this is the
1465 * console. This allows us to detect break-to-debugger events
1466 * while the console device is closed.
1467 */
1468 if (com->unit != comconsole)
1469#endif
1470 {
1471 sio_setreg(com, com_ier, 0);
1472 if (tp->t_cflag & HUPCL
1473 /*
1474 * XXX we will miss any carrier drop between here and the
1475 * next open. Perhaps we should watch DCD even when the
1476 * port is closed; it is not sufficient to check it at
1477 * the next open because it might go up and down while
1478 * we're not watching.
1479 */
1480 || (!com->active_out
1481 && !(com->prev_modem_status & MSR_DCD)
1482 && !(com->it_in.c_cflag & CLOCAL))
1483 || !(tp->t_state & TS_ISOPEN)) {
1484 (void)commctl(com, TIOCM_DTR, DMBIC);
1485 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1486 timeout(siodtrwakeup, com, com->dtr_wait);
1487 com->state |= CS_DTR_OFF;
1488 }
1489 }
1490 }
1491 if (com->hasfifo) {
1492 /*
1493 * Disable fifos so that they are off after controlled
1494 * reboots. Some BIOSes fail to detect 16550s when the
1495 * fifos are enabled.
1496 */
1497 sio_setreg(com, com_fifo, 0);
1498 }
1499 com->active_out = FALSE;
1500 wakeup(&com->active_out);
1501 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1502 splx(s);
1503}
1504
1505static int
1506sioread(dev, uio, flag)
1507 dev_t dev;
1508 struct uio *uio;
1509 int flag;
1510{
1511 int mynor;
1512 struct com_s *com;
1513
1514 mynor = minor(dev);
1515 if (mynor & CONTROL_MASK)
1516 return (ENODEV);
1517 com = com_addr(MINOR_TO_UNIT(mynor));
1518 if (com == NULL || com->gone)
1519 return (ENODEV);
1520 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1521}
1522
1523static int
1524siowrite(dev, uio, flag)
1525 dev_t dev;
1526 struct uio *uio;
1527 int flag;
1528{
1529 int mynor;
1530 struct com_s *com;
1531 int unit;
1532
1533 mynor = minor(dev);
1534 if (mynor & CONTROL_MASK)
1535 return (ENODEV);
1536
1537 unit = MINOR_TO_UNIT(mynor);
1538 com = com_addr(unit);
1539 if (com == NULL || com->gone)
1540 return (ENODEV);
1541 /*
1542 * (XXX) We disallow virtual consoles if the physical console is
1543 * a serial port. This is in case there is a display attached that
1544 * is not the console. In that situation we don't need/want the X
1545 * server taking over the console.
1546 */
1547 if (constty != NULL && unit == comconsole)
1548 constty = NULL;
1549 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1550}
1551
1552static void
1553siobusycheck(chan)
1554 void *chan;
1555{
1556 struct com_s *com;
1557 int s;
1558
1559 com = (struct com_s *)chan;
1560
1561 /*
1562 * Clear TS_BUSY if low-level output is complete.
1563 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1564 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1565 * called again. Reading the line status port outside of siointr1()
1566 * is safe because CS_BUSY is clear so there are no output interrupts
1567 * to lose.
1568 */
1569 s = spltty();
1570 if (com->state & CS_BUSY)
1571 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1572 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1573 == (LSR_TSRE | LSR_TXRDY)) {
1574 com->tp->t_state &= ~TS_BUSY;
1575 ttwwakeup(com->tp);
1576 com->extra_state &= ~CSE_BUSYCHECK;
1577 } else
1578 timeout(siobusycheck, com, hz / 100);
1579 splx(s);
1580}
1581
1582static u_int
1583siodivisor(rclk, speed)
1584 u_long rclk;
1585 speed_t speed;
1586{
1587 long actual_speed;
1588 u_int divisor;
1589 int error;
1590
1591 if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1592 return (0);
1593 divisor = (rclk / (8UL * speed) + 1) / 2;
1594 if (divisor == 0 || divisor >= 65536)
1595 return (0);
1596 actual_speed = rclk / (16UL * divisor);
1597
1598 /* 10 times error in percent: */
1599 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1600
1601 /* 3.0% maximum error tolerance: */
1602 if (error < -30 || error > 30)
1603 return (0);
1604
1605 return (divisor);
1606}
1607
1608static void
1609siodtrwakeup(chan)
1610 void *chan;
1611{
1612 struct com_s *com;
1613
1614 com = (struct com_s *)chan;
1615 com->state &= ~CS_DTR_OFF;
1616 wakeup(&com->dtr_wait);
1617}
1618
1619static void
1620sioinput(com)
1621 struct com_s *com;
1622{
1623 u_char *buf;
1624 int incc;
1625 u_char line_status;
1626 int recv_data;
1627 struct tty *tp;
1628
1629 buf = com->ibuf;
1630 tp = com->tp;
1631 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1632 com_events -= (com->iptr - com->ibuf);
1633 com->iptr = com->ibuf;
1634 return;
1635 }
1636 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1637 /*
1638 * Avoid the grotesquely inefficient lineswitch routine
1639 * (ttyinput) in "raw" mode. It usually takes about 450
1640 * instructions (that's without canonical processing or echo!).
1641 * slinput is reasonably fast (usually 40 instructions plus
1642 * call overhead).
1643 */
1644 do {
8a8d5d85 1645 com_unlock();
984263bc
MD
1646 incc = com->iptr - buf;
1647 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1648 && (com->state & CS_RTS_IFLOW
1649 || tp->t_iflag & IXOFF)
1650 && !(tp->t_state & TS_TBLOCK))
1651 ttyblock(tp);
1652 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1653 += b_to_q((char *)buf, incc, &tp->t_rawq);
1654 buf += incc;
1655 tk_nin += incc;
1656 tk_rawcc += incc;
1657 tp->t_rawcc += incc;
1658 ttwakeup(tp);
1659 if (tp->t_state & TS_TTSTOP
1660 && (tp->t_iflag & IXANY
1661 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1662 tp->t_state &= ~TS_TTSTOP;
1663 tp->t_lflag &= ~FLUSHO;
1664 comstart(tp);
1665 }
8a8d5d85 1666 com_lock();
984263bc
MD
1667 } while (buf < com->iptr);
1668 } else {
1669 do {
8a8d5d85 1670 com_unlock();
984263bc
MD
1671 line_status = buf[com->ierroff];
1672 recv_data = *buf++;
1673 if (line_status
1674 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1675 if (line_status & LSR_BI)
1676 recv_data |= TTY_BI;
1677 if (line_status & LSR_FE)
1678 recv_data |= TTY_FE;
1679 if (line_status & LSR_OE)
1680 recv_data |= TTY_OE;
1681 if (line_status & LSR_PE)
1682 recv_data |= TTY_PE;
1683 }
1684 (*linesw[tp->t_line].l_rint)(recv_data, tp);
8a8d5d85 1685 com_lock();
984263bc
MD
1686 } while (buf < com->iptr);
1687 }
1688 com_events -= (com->iptr - com->ibuf);
1689 com->iptr = com->ibuf;
1690
1691 /*
1692 * There is now room for another low-level buffer full of input,
1693 * so enable RTS if it is now disabled and there is room in the
1694 * high-level buffer.
1695 */
1696 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1697 !(tp->t_state & TS_TBLOCK))
1698 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1699}
1700
1701void
1702siointr(arg)
1703 void *arg;
1704{
1705#ifndef COM_MULTIPORT
8a8d5d85 1706 com_lock();
984263bc 1707 siointr1((struct com_s *) arg);
8a8d5d85 1708 com_unlock();
984263bc
MD
1709#else /* COM_MULTIPORT */
1710 bool_t possibly_more_intrs;
1711 int unit;
1712 struct com_s *com;
1713
1714 /*
1715 * Loop until there is no activity on any port. This is necessary
1716 * to get an interrupt edge more than to avoid another interrupt.
1717 * If the IRQ signal is just an OR of the IRQ signals from several
1718 * devices, then the edge from one may be lost because another is
1719 * on.
1720 */
8a8d5d85 1721 com_lock();
984263bc
MD
1722 do {
1723 possibly_more_intrs = FALSE;
1724 for (unit = 0; unit < sio_numunits; ++unit) {
1725 com = com_addr(unit);
1726 /*
8a8d5d85 1727 * XXX com_lock();
984263bc
MD
1728 * would it work here, or be counter-productive?
1729 */
1730 if (com != NULL
1731 && !com->gone
1732 && (inb(com->int_id_port) & IIR_IMASK)
1733 != IIR_NOPEND) {
1734 siointr1(com);
1735 possibly_more_intrs = TRUE;
1736 }
8a8d5d85 1737 /* XXX com_unlock(); */
984263bc
MD
1738 }
1739 } while (possibly_more_intrs);
8a8d5d85 1740 com_unlock();
984263bc
MD
1741#endif /* COM_MULTIPORT */
1742}
1743
1744static void
1745siointr1(com)
1746 struct com_s *com;
1747{
1748 u_char line_status;
1749 u_char modem_status;
1750 u_char *ioptr;
1751 u_char recv_data;
1752 u_char int_ctl;
1753 u_char int_ctl_new;
984263bc
MD
1754 u_int count;
1755
1756 int_ctl = inb(com->intr_ctl_port);
1757 int_ctl_new = int_ctl;
1758
1759 while (!com->gone) {
1760 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1761 modem_status = inb(com->modem_status_port);
1762 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
88c4d2f6
MD
1763 count = cputimer_count();
1764 pps_event(&com->pps, count,
984263bc
MD
1765 (modem_status & MSR_DCD) ?
1766 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
1767 }
1768 }
1769 line_status = inb(com->line_status_port);
1770
1771 /* input event? (check first to help avoid overruns) */
1772 while (line_status & LSR_RCV_MASK) {
1773 /* break/unnattached error bits or real input? */
1774 if (!(line_status & LSR_RXRDY))
1775 recv_data = 0;
1776 else
1777 recv_data = inb(com->data_port);
1778#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
1779 /*
1780 * Solaris implements a new BREAK which is initiated
1781 * by a character sequence CR ~ ^b which is similar
1782 * to a familiar pattern used on Sun servers by the
1783 * Remote Console.
1784 */
1785#define KEY_CRTLB 2 /* ^B */
1786#define KEY_CR 13 /* CR '\r' */
1787#define KEY_TILDE 126 /* ~ */
1788
1789 if (com->unit == comconsole) {
1790 static int brk_state1 = 0, brk_state2 = 0;
1791 if (recv_data == KEY_CR) {
1792 brk_state1 = recv_data;
1793 brk_state2 = 0;
1794 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) {
1795 if (recv_data == KEY_TILDE)
1796 brk_state2 = recv_data;
1797 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) {
1798 breakpoint();
1799 brk_state1 = brk_state2 = 0;
1800 goto cont;
1801 } else
1802 brk_state2 = 0;
1803 } else
1804 brk_state1 = 0;
1805 }
1806#endif
1807 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
1808 /*
1809 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
1810 * Otherwise, push the work to a higher level
1811 * (to handle PARMRK) if we're bypassing.
1812 * Otherwise, convert BI/FE and PE+INPCK to 0.
1813 *
1814 * This makes bypassing work right in the
1815 * usual "raw" case (IGNBRK set, and IGNPAR
1816 * and INPCK clear).
1817 *
1818 * Note: BI together with FE/PE means just BI.
1819 */
1820 if (line_status & LSR_BI) {
1821#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
1822 if (com->unit == comconsole) {
1823 breakpoint();
1824 goto cont;
1825 }
1826#endif
1827 if (com->tp == NULL
1828 || com->tp->t_iflag & IGNBRK)
1829 goto cont;
1830 } else {
1831 if (com->tp == NULL
1832 || com->tp->t_iflag & IGNPAR)
1833 goto cont;
1834 }
1835 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
1836 && (line_status & (LSR_BI | LSR_FE)
1837 || com->tp->t_iflag & INPCK))
1838 recv_data = 0;
1839 }
1840 ++com->bytes_in;
1841 if (com->hotchar != 0 && recv_data == com->hotchar)
1842 setsofttty();
1843 ioptr = com->iptr;
1844 if (ioptr >= com->ibufend)
1845 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
1846 else {
1847 if (com->do_timestamp)
1848 microtime(&com->timestamp);
1849 ++com_events;
1850 schedsofttty();
1851#if 0 /* for testing input latency vs efficiency */
1852if (com->iptr - com->ibuf == 8)
1853 setsofttty();
1854#endif
1855 ioptr[0] = recv_data;
1856 ioptr[com->ierroff] = line_status;
1857 com->iptr = ++ioptr;
1858 if (ioptr == com->ihighwater
1859 && com->state & CS_RTS_IFLOW)
1860 outb(com->modem_ctl_port,
1861 com->mcr_image &= ~MCR_RTS);
1862 if (line_status & LSR_OE)
1863 CE_RECORD(com, CE_OVERRUN);
1864 }
1865cont:
1866 /*
1867 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
1868 * jump from the top of the loop to here
1869 */
1870 line_status = inb(com->line_status_port) & 0x7F;
1871 }
1872
1873 /* modem status change? (always check before doing output) */
1874 modem_status = inb(com->modem_status_port);
1875 if (modem_status != com->last_modem_status) {
1876 if (com->do_dcd_timestamp
1877 && !(com->last_modem_status & MSR_DCD)
1878 && modem_status & MSR_DCD)
1879 microtime(&com->dcd_timestamp);
1880
1881 /*
1882 * Schedule high level to handle DCD changes. Note
1883 * that we don't use the delta bits anywhere. Some
1884 * UARTs mess them up, and it's easy to remember the
1885 * previous bits and calculate the delta.
1886 */
1887 com->last_modem_status = modem_status;
1888 if (!(com->state & CS_CHECKMSR)) {
1889 com_events += LOTS_OF_EVENTS;
1890 com->state |= CS_CHECKMSR;
1891 setsofttty();
1892 }
1893
1894 /* handle CTS change immediately for crisp flow ctl */
1895 if (com->state & CS_CTS_OFLOW) {
1896 if (modem_status & MSR_CTS)
1897 com->state |= CS_ODEVREADY;
1898 else
1899 com->state &= ~CS_ODEVREADY;
1900 }
1901 }
1902
1903 /* output queued and everything ready? */
1904 if (line_status & LSR_TXRDY
1905 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
1906 ioptr = com->obufq.l_head;
1907 if (com->tx_fifo_size > 1) {
1908 u_int ocount;
1909
1910 ocount = com->obufq.l_tail - ioptr;
1911 if (ocount > com->tx_fifo_size)
1912 ocount = com->tx_fifo_size;
1913 com->bytes_out += ocount;
1914 do
1915 outb(com->data_port, *ioptr++);
1916 while (--ocount != 0);
1917 } else {
1918 outb(com->data_port, *ioptr++);
1919 ++com->bytes_out;
1920 }
1921 com->obufq.l_head = ioptr;
1922 if (COM_IIR_TXRDYBUG(com->flags)) {
1923 int_ctl_new = int_ctl | IER_ETXRDY;
1924 }
1925 if (ioptr >= com->obufq.l_tail) {
1926 struct lbq *qp;
1927
1928 qp = com->obufq.l_next;
1929 qp->l_queued = FALSE;
1930 qp = qp->l_next;
1931 if (qp != NULL) {
1932 com->obufq.l_head = qp->l_head;
1933 com->obufq.l_tail = qp->l_tail;
1934 com->obufq.l_next = qp;
1935 } else {
1936 /* output just completed */
1937 if (COM_IIR_TXRDYBUG(com->flags)) {
1938 int_ctl_new = int_ctl & ~IER_ETXRDY;
1939 }
1940 com->state &= ~CS_BUSY;
1941 }
1942 if (!(com->state & CS_ODONE)) {
1943 com_events += LOTS_OF_EVENTS;
1944 com->state |= CS_ODONE;
1945 setsofttty(); /* handle at high level ASAP */
1946 }
1947 }
1948 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
1949 outb(com->intr_ctl_port, int_ctl_new);
1950 }
1951 }
1952
1953 /* finished? */
1954#ifndef COM_MULTIPORT
1955 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
1956#endif /* COM_MULTIPORT */
1957 return;
1958 }
1959}
1960
1961static int
41c20dac 1962sioioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc
MD
1963{
1964 struct com_s *com;
1965 int error;
1966 int mynor;
1967 int s;
1968 struct tty *tp;
1969#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1970 u_long oldcmd;
1971 struct termios term;
1972#endif
1973
1974 mynor = minor(dev);
1975 com = com_addr(MINOR_TO_UNIT(mynor));
1976 if (com == NULL || com->gone)
1977 return (ENODEV);
1978 if (mynor & CONTROL_MASK) {
1979 struct termios *ct;
1980
1981 switch (mynor & CONTROL_MASK) {
1982 case CONTROL_INIT_STATE:
1983 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
1984 break;
1985 case CONTROL_LOCK_STATE:
1986 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
1987 break;
1988 default:
1989 return (ENODEV); /* /dev/nodev */
1990 }
1991 switch (cmd) {
1992 case TIOCSETA:
dadab5e9 1993 error = suser(td);
984263bc
MD
1994 if (error != 0)
1995 return (error);
1996 *ct = *(struct termios *)data;
1997 return (0);
1998 case TIOCGETA:
1999 *(struct termios *)data = *ct;
2000 return (0);
2001 case TIOCGETD:
2002 *(int *)data = TTYDISC;
2003 return (0);
2004 case TIOCGWINSZ:
2005 bzero(data, sizeof(struct winsize));
2006 return (0);
2007 default:
2008 return (ENOTTY);
2009 }
2010 }
2011 tp = com->tp;
2012#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2013 term = tp->t_termios;
2014 oldcmd = cmd;
2015 error = ttsetcompat(tp, &cmd, data, &term);
2016 if (error != 0)
2017 return (error);
2018 if (cmd != oldcmd)
2019 data = (caddr_t)&term;
2020#endif
2021 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2022 int cc;
2023 struct termios *dt = (struct termios *)data;
2024 struct termios *lt = mynor & CALLOUT_MASK
2025 ? &com->lt_out : &com->lt_in;
2026
2027 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2028 | (dt->c_iflag & ~lt->c_iflag);
2029 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2030 | (dt->c_oflag & ~lt->c_oflag);
2031 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2032 | (dt->c_cflag & ~lt->c_cflag);
2033 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2034 | (dt->c_lflag & ~lt->c_lflag);
2035 for (cc = 0; cc < NCCS; ++cc)
2036 if (lt->c_cc[cc] != 0)
2037 dt->c_cc[cc] = tp->t_cc[cc];
2038 if (lt->c_ispeed != 0)
2039 dt->c_ispeed = tp->t_ispeed;
2040 if (lt->c_ospeed != 0)
2041 dt->c_ospeed = tp->t_ospeed;
2042 }
41c20dac 2043 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
984263bc
MD
2044 if (error != ENOIOCTL)
2045 return (error);
2046 s = spltty();
2047 error = ttioctl(tp, cmd, data, flag);
2048 disc_optim(tp, &tp->t_termios, com);
2049 if (error != ENOIOCTL) {
2050 splx(s);
2051 return (error);
2052 }
2053 switch (cmd) {
2054 case TIOCSBRK:
2055 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2056 break;
2057 case TIOCCBRK:
2058 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2059 break;
2060 case TIOCSDTR:
2061 (void)commctl(com, TIOCM_DTR, DMBIS);
2062 break;
2063 case TIOCCDTR:
2064 (void)commctl(com, TIOCM_DTR, DMBIC);
2065 break;
2066 /*
2067 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2068 * changes get undone on the next call to comparam().
2069 */
2070 case TIOCMSET:
2071 (void)commctl(com, *(int *)data, DMSET);
2072 break;
2073 case TIOCMBIS:
2074 (void)commctl(com, *(int *)data, DMBIS);
2075 break;
2076 case TIOCMBIC:
2077 (void)commctl(com, *(int *)data, DMBIC);
2078 break;
2079 case TIOCMGET:
2080 *(int *)data = commctl(com, 0, DMGET);
2081 break;
2082 case TIOCMSDTRWAIT:
2083 /* must be root since the wait applies to following logins */
dadab5e9 2084 error = suser(td);
984263bc
MD
2085 if (error != 0) {
2086 splx(s);
2087 return (error);
2088 }
2089 com->dtr_wait = *(int *)data * hz / 100;
2090 break;
2091 case TIOCMGDTRWAIT:
2092 *(int *)data = com->dtr_wait * 100 / hz;
2093 break;
2094 case TIOCTIMESTAMP:
2095 com->do_timestamp = TRUE;
2096 *(struct timeval *)data = com->timestamp;
2097 break;
2098 case TIOCDCDTIMESTAMP:
2099 com->do_dcd_timestamp = TRUE;
2100 *(struct timeval *)data = com->dcd_timestamp;
2101 break;
2102 default:
2103 splx(s);
2104 error = pps_ioctl(cmd, data, &com->pps);
2105 if (error == ENODEV)
2106 error = ENOTTY;
2107 return (error);
2108 }
2109 splx(s);
2110 return (0);
2111}
2112
2113static void
ef0fdad1 2114siopoll(void *dummy)
984263bc
MD
2115{
2116 int unit;
2117
2118 if (com_events == 0)
2119 return;
2120repeat:
2121 for (unit = 0; unit < sio_numunits; ++unit) {
2122 struct com_s *com;
2123 int incc;
2124 struct tty *tp;
2125
2126 com = com_addr(unit);
2127 if (com == NULL)
2128 continue;
2129 tp = com->tp;
2130 if (tp == NULL || com->gone) {
2131 /*
2132 * Discard any events related to never-opened or
2133 * going-away devices.
2134 */
8a8d5d85 2135 com_lock();
984263bc
MD
2136 incc = com->iptr - com->ibuf;
2137 com->iptr = com->ibuf;
2138 if (com->state & CS_CHECKMSR) {
2139 incc += LOTS_OF_EVENTS;
2140 com->state &= ~CS_CHECKMSR;
2141 }
2142 com_events -= incc;
8a8d5d85 2143 com_unlock();
984263bc
MD
2144 continue;
2145 }
2146 if (com->iptr != com->ibuf) {
8a8d5d85 2147 com_lock();
984263bc 2148 sioinput(com);
8a8d5d85 2149 com_unlock();
984263bc
MD
2150 }
2151 if (com->state & CS_CHECKMSR) {
2152 u_char delta_modem_status;
2153
8a8d5d85 2154 com_lock();
984263bc
MD
2155 delta_modem_status = com->last_modem_status
2156 ^ com->prev_modem_status;
2157 com->prev_modem_status = com->last_modem_status;
2158 com_events -= LOTS_OF_EVENTS;
2159 com->state &= ~CS_CHECKMSR;
8a8d5d85 2160 com_unlock();
984263bc
MD
2161 if (delta_modem_status & MSR_DCD)
2162 (*linesw[tp->t_line].l_modem)
2163 (tp, com->prev_modem_status & MSR_DCD);
2164 }
2165 if (com->state & CS_ODONE) {
8a8d5d85 2166 com_lock();
984263bc
MD
2167 com_events -= LOTS_OF_EVENTS;
2168 com->state &= ~CS_ODONE;
8a8d5d85 2169 com_unlock();
984263bc
MD
2170 if (!(com->state & CS_BUSY)
2171 && !(com->extra_state & CSE_BUSYCHECK)) {
2172 timeout(siobusycheck, com, hz / 100);
2173 com->extra_state |= CSE_BUSYCHECK;
2174 }
2175 (*linesw[tp->t_line].l_start)(tp);
2176 }
2177 if (com_events == 0)
2178 break;
2179 }
2180 if (com_events >= LOTS_OF_EVENTS)
2181 goto repeat;
2182}
2183
2184static int
2185comparam(tp, t)
2186 struct tty *tp;
2187 struct termios *t;
2188{
2189 u_int cfcr;
2190 int cflag;
2191 struct com_s *com;
2192 u_int divisor;
2193 u_char dlbh;
2194 u_char dlbl;
2195 int s;
2196 int unit;
2197
2198 unit = DEV_TO_UNIT(tp->t_dev);
2199 com = com_addr(unit);
2200 if (com == NULL)
2201 return (ENODEV);
2202
2203 /* do historical conversions */
2204 if (t->c_ispeed == 0)
2205 t->c_ispeed = t->c_ospeed;
2206
2207 /* check requested parameters */
2208 if (t->c_ospeed == 0)
2209 divisor = 0;
2210 else {
2211 if (t->c_ispeed != t->c_ospeed)
2212 return (EINVAL);
2213 divisor = siodivisor(com->rclk, t->c_ispeed);
2214 if (divisor == 0)
2215 return (EINVAL);
2216 }
2217
2218 /* parameters are OK, convert them to the com struct and the device */
2219 s = spltty();
2220 if (divisor == 0)
2221 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2222 else
2223 (void)commctl(com, TIOCM_DTR, DMBIS);
2224 cflag = t->c_cflag;
2225 switch (cflag & CSIZE) {
2226 case CS5:
2227 cfcr = CFCR_5BITS;
2228 break;
2229 case CS6:
2230 cfcr = CFCR_6BITS;
2231 break;
2232 case CS7:
2233 cfcr = CFCR_7BITS;
2234 break;
2235 default:
2236 cfcr = CFCR_8BITS;
2237 break;
2238 }
2239 if (cflag & PARENB) {
2240 cfcr |= CFCR_PENAB;
2241 if (!(cflag & PARODD))
2242 cfcr |= CFCR_PEVEN;
2243 }
2244 if (cflag & CSTOPB)
2245 cfcr |= CFCR_STOPB;
2246
2247 if (com->hasfifo && divisor != 0) {
2248 /*
2249 * Use a fifo trigger level low enough so that the input
2250 * latency from the fifo is less than about 16 msec and
2251 * the total latency is less than about 30 msec. These
2252 * latencies are reasonable for humans. Serial comms
2253 * protocols shouldn't expect anything better since modem
2254 * latencies are larger.
2255 *
2256 * Interrupts can be held up for long periods of time
2257 * due to inefficiencies in other parts of the kernel,
2258 * certain video cards, etc. Setting the FIFO trigger
2259 * point to MEDH instead of HIGH gives us 694uS of slop
2260 * (8 character times) instead of 173uS (2 character times)
2261 * @ 115200 bps.
2262 */
2263 com->fifo_image = t->c_ospeed <= 4800
2264 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2265#ifdef COM_ESP
2266 /*
2267 * The Hayes ESP card needs the fifo DMA mode bit set
2268 * in compatibility mode. If not, it will interrupt
2269 * for each character received.
2270 */
2271 if (com->esp)
2272 com->fifo_image |= FIFO_DMA_MODE;
2273#endif
2274 sio_setreg(com, com_fifo, com->fifo_image);
2275 }
2276
2277 /*
2278 * This returns with interrupts disabled so that we can complete
2279 * the speed change atomically. Keeping interrupts disabled is
2280 * especially important while com_data is hidden.
2281 */
2282 (void) siosetwater(com, t->c_ispeed);
2283
2284 if (divisor != 0) {
2285 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2286 /*
2287 * Only set the divisor registers if they would change,
2288 * since on some 16550 incompatibles (UMC8669F), setting
2289 * them while input is arriving them loses sync until
2290 * data stops arriving.
2291 */
2292 dlbl = divisor & 0xFF;
2293 if (sio_getreg(com, com_dlbl) != dlbl)
2294 sio_setreg(com, com_dlbl, dlbl);
2295 dlbh = divisor >> 8;
2296 if (sio_getreg(com, com_dlbh) != dlbh)
2297 sio_setreg(com, com_dlbh, dlbh);
2298 }
2299
2300 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2301
2302 if (!(tp->t_state & TS_TTSTOP))
2303 com->state |= CS_TTGO;
2304
2305 if (cflag & CRTS_IFLOW) {
2306 if (com->st16650a) {
2307 sio_setreg(com, com_cfcr, 0xbf);
2308 sio_setreg(com, com_fifo,
2309 sio_getreg(com, com_fifo) | 0x40);
2310 }
2311 com->state |= CS_RTS_IFLOW;
2312 /*
2313 * If CS_RTS_IFLOW just changed from off to on, the change
2314 * needs to be propagated to MCR_RTS. This isn't urgent,
2315 * so do it later by calling comstart() instead of repeating
2316 * a lot of code from comstart() here.
2317 */
2318 } else if (com->state & CS_RTS_IFLOW) {
2319 com->state &= ~CS_RTS_IFLOW;
2320 /*
2321 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2322 * on here, since comstart() won't do it later.
2323 */
2324 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2325 if (com->st16650a) {
2326 sio_setreg(com, com_cfcr, 0xbf);
2327 sio_setreg(com, com_fifo,
2328 sio_getreg(com, com_fifo) & ~0x40);
2329 }
2330 }
2331
2332
2333 /*
2334 * Set up state to handle output flow control.
2335 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2336 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2337 */
2338 com->state |= CS_ODEVREADY;
2339 com->state &= ~CS_CTS_OFLOW;
2340 if (cflag & CCTS_OFLOW) {
2341 com->state |= CS_CTS_OFLOW;
2342 if (!(com->last_modem_status & MSR_CTS))
2343 com->state &= ~CS_ODEVREADY;
2344 if (com->st16650a) {
2345 sio_setreg(com, com_cfcr, 0xbf);
2346 sio_setreg(com, com_fifo,
2347 sio_getreg(com, com_fifo) | 0x80);
2348 }
2349 } else {
2350 if (com->st16650a) {
2351 sio_setreg(com, com_cfcr, 0xbf);
2352 sio_setreg(com, com_fifo,
2353 sio_getreg(com, com_fifo) & ~0x80);
2354 }
2355 }
2356
2357 sio_setreg(com, com_cfcr, com->cfcr_image);
2358
2359 /* XXX shouldn't call functions while intrs are disabled. */
2360 disc_optim(tp, t, com);
2361 /*
2362 * Recover from fiddling with CS_TTGO. We used to call siointr1()
2363 * unconditionally, but that defeated the careful discarding of
2364 * stale input in sioopen().
2365 */
2366 if (com->state >= (CS_BUSY | CS_TTGO))
2367 siointr1(com);
2368
8a8d5d85 2369 com_unlock();
984263bc
MD
2370 splx(s);
2371 comstart(tp);
2372 if (com->ibufold != NULL) {
2373 free(com->ibufold, M_DEVBUF);
2374 com->ibufold = NULL;
2375 }
2376 return (0);
2377}
2378
2379static int
2380siosetwater(com, speed)
2381 struct com_s *com;
2382 speed_t speed;
2383{
2384 int cp4ticks;
2385 u_char *ibuf;
2386 int ibufsize;
2387 struct tty *tp;
2388
2389 /*
2390 * Make the buffer size large enough to handle a softtty interrupt
2391 * latency of about 2 ticks without loss of throughput or data
2392 * (about 3 ticks if input flow control is not used or not honoured,
2393 * but a bit less for CS5-CS7 modes).
2394 */
2395 cp4ticks = speed / 10 / hz * 4;
2396 for (ibufsize = 128; ibufsize < cp4ticks;)
2397 ibufsize <<= 1;
2398 if (ibufsize == com->ibufsize) {
8a8d5d85 2399 com_lock();
984263bc
MD
2400 return (0);
2401 }
2402
2403 /*
2404 * Allocate input buffer. The extra factor of 2 in the size is
2405 * to allow for an error byte for each input byte.
2406 */
2407 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2408 if (ibuf == NULL) {
8a8d5d85 2409 com_lock();
984263bc
MD
2410 return (ENOMEM);
2411 }
2412
2413 /* Initialize non-critical variables. */
2414 com->ibufold = com->ibuf;
2415 com->ibufsize = ibufsize;
2416 tp = com->tp;
2417 if (tp != NULL) {
2418 tp->t_ififosize = 2 * ibufsize;
2419 tp->t_ispeedwat = (speed_t)-1;
2420 tp->t_ospeedwat = (speed_t)-1;
2421 }
2422
2423 /*
2424 * Read current input buffer, if any. Continue with interrupts
2425 * disabled.
2426 */
8a8d5d85 2427 com_lock();
984263bc
MD
2428 if (com->iptr != com->ibuf)
2429 sioinput(com);
2430
2431 /*-
2432 * Initialize critical variables, including input buffer watermarks.
2433 * The external device is asked to stop sending when the buffer
2434 * exactly reaches high water, or when the high level requests it.
2435 * The high level is notified immediately (rather than at a later
2436 * clock tick) when this watermark is reached.
2437 * The buffer size is chosen so the watermark should almost never
2438 * be reached.
2439 * The low watermark is invisibly 0 since the buffer is always
2440 * emptied all at once.
2441 */
2442 com->iptr = com->ibuf = ibuf;
2443 com->ibufend = ibuf + ibufsize;
2444 com->ierroff = ibufsize;
2445 com->ihighwater = ibuf + 3 * ibufsize / 4;
2446 return (0);
2447}
2448
2449static void
2450comstart(tp)
2451 struct tty *tp;
2452{
2453 struct com_s *com;
2454 int s;
2455 int unit;
2456
2457 unit = DEV_TO_UNIT(tp->t_dev);
2458 com = com_addr(unit);
2459 if (com == NULL)
2460 return;
2461 s = spltty();
8a8d5d85 2462 com_lock();
984263bc
MD
2463 if (tp->t_state & TS_TTSTOP)
2464 com->state &= ~CS_TTGO;
2465 else
2466 com->state |= CS_TTGO;
2467 if (tp->t_state & TS_TBLOCK) {
2468 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2469 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2470 } else {
2471 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2472 && com->state & CS_RTS_IFLOW)
2473 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2474 }
8a8d5d85 2475 com_unlock();
984263bc
MD
2476 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2477 ttwwakeup(tp);
2478 splx(s);
2479 return;
2480 }
2481 if (tp->t_outq.c_cc != 0) {
2482 struct lbq *qp;
2483 struct lbq *next;
2484
2485 if (!com->obufs[0].l_queued) {
2486 com->obufs[0].l_tail
2487 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2488 sizeof com->obuf1);
2489 com->obufs[0].l_next = NULL;
2490 com->obufs[0].l_queued = TRUE;
8a8d5d85 2491 com_lock();
984263bc
MD
2492 if (com->state & CS_BUSY) {
2493 qp = com->obufq.l_next;
2494 while ((next = qp->l_next) != NULL)
2495 qp = next;
2496 qp->l_next = &com->obufs[0];
2497 } else {
2498 com->obufq.l_head = com->obufs[0].l_head;
2499 com->obufq.l_tail = com->obufs[0].l_tail;
2500 com->obufq.l_next = &com->obufs[0];
2501 com->state |= CS_BUSY;
2502 }
8a8d5d85 2503 com_unlock();
984263bc
MD
2504 }
2505 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2506 com->obufs[1].l_tail
2507 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2508 sizeof com->obuf2);
2509 com->obufs[1].l_next = NULL;
2510 com->obufs[1].l_queued = TRUE;
8a8d5d85 2511 com_lock();
984263bc
MD
2512 if (com->state & CS_BUSY) {
2513 qp = com->obufq.l_next;
2514 while ((next = qp->l_next) != NULL)
2515 qp = next;
2516 qp->l_next = &com->obufs[1];
2517 } else {
2518 com->obufq.l_head = com->obufs[1].l_head;
2519 com->obufq.l_tail = com->obufs[1].l_tail;
2520 com->obufq.l_next = &com->obufs[1];
2521 com->state |= CS_BUSY;
2522 }
8a8d5d85 2523 com_unlock();
984263bc
MD
2524 }
2525 tp->t_state |= TS_BUSY;
2526 }
8a8d5d85 2527 com_lock();
984263bc
MD
2528 if (com->state >= (CS_BUSY | CS_TTGO))
2529 siointr1(com); /* fake interrupt to start output */
8a8d5d85 2530 com_unlock();
984263bc
MD
2531 ttwwakeup(tp);
2532 splx(s);
2533}
2534
2535static void
2536comstop(tp, rw)
2537 struct tty *tp;
2538 int rw;
2539{
2540 struct com_s *com;
2541
2542 com = com_addr(DEV_TO_UNIT(tp->t_dev));
2543 if (com == NULL || com->gone)
2544 return;
8a8d5d85 2545 com_lock();
984263bc
MD
2546 if (rw & FWRITE) {
2547 if (com->hasfifo)
2548#ifdef COM_ESP
2549 /* XXX avoid h/w bug. */
2550 if (!com->esp)
2551#endif
2552 sio_setreg(com, com_fifo,
2553 FIFO_XMT_RST | com->fifo_image);
2554 com->obufs[0].l_queued = FALSE;
2555 com->obufs[1].l_queued = FALSE;
2556 if (com->state & CS_ODONE)
2557 com_events -= LOTS_OF_EVENTS;
2558 com->state &= ~(CS_ODONE | CS_BUSY);
2559 com->tp->t_state &= ~TS_BUSY;
2560 }
2561 if (rw & FREAD) {
2562 if (com->hasfifo)
2563#ifdef COM_ESP
2564 /* XXX avoid h/w bug. */
2565 if (!com->esp)
2566#endif
2567 sio_setreg(com, com_fifo,
2568 FIFO_RCV_RST | com->fifo_image);
2569 com_events -= (com->iptr - com->ibuf);
2570 com->iptr = com->ibuf;
2571 }
8a8d5d85 2572 com_unlock();
984263bc
MD
2573 comstart(tp);
2574}
2575
2576static int
2577commctl(com, bits, how)
2578 struct com_s *com;
2579 int bits;
2580 int how;
2581{
2582 int mcr;
2583 int msr;
2584
2585 if (how == DMGET) {
2586 bits = TIOCM_LE; /* XXX - always enabled while open */
2587 mcr = com->mcr_image;
2588 if (mcr & MCR_DTR)
2589 bits |= TIOCM_DTR;
2590 if (mcr & MCR_RTS)
2591 bits |= TIOCM_RTS;
2592 msr = com->prev_modem_status;
2593 if (msr & MSR_CTS)
2594 bits |= TIOCM_CTS;
2595 if (msr & MSR_DCD)
2596 bits |= TIOCM_CD;
2597 if (msr & MSR_DSR)
2598 bits |= TIOCM_DSR;
2599 /*
2600 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2601 * more volatile by reading the modem status a lot. Perhaps
2602 * we should latch both bits until the status is read here.
2603 */
2604 if (msr & (MSR_RI | MSR_TERI))
2605 bits |= TIOCM_RI;
2606 return (bits);
2607 }
2608 mcr = 0;
2609 if (bits & TIOCM_DTR)
2610 mcr |= MCR_DTR;
2611 if (bits & TIOCM_RTS)
2612 mcr |= MCR_RTS;
2613 if (com->gone)
2614 return(0);
8a8d5d85 2615 com_lock();
984263bc
MD
2616 switch (how) {
2617 case DMSET:
2618 outb(com->modem_ctl_port,
2619 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2620 break;
2621 case DMBIS:
2622 outb(com->modem_ctl_port, com->mcr_image |= mcr);
2623 break;
2624 case DMBIC:
2625 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2626 break;
2627 }
8a8d5d85 2628 com_unlock();
984263bc
MD
2629 return (0);
2630}
2631
2632static void
2633siosettimeout()
2634{
2635 struct com_s *com;
2636 bool_t someopen;
2637 int unit;
2638
2639 /*
2640 * Set our timeout period to 1 second if no polled devices are open.
2641 * Otherwise set it to max(1/200, 1/hz).
2642 * Enable timeouts iff some device is open.
2643 */
2644 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2645 sio_timeout = hz;
2646 someopen = FALSE;
2647 for (unit = 0; unit < sio_numunits; ++unit) {
2648 com = com_addr(unit);
2649 if (com != NULL && com->tp != NULL
2650 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2651 someopen = TRUE;
2652 if (com->poll || com->poll_output) {
2653 sio_timeout = hz > 200 ? hz / 200 : 1;
2654 break;
2655 }
2656 }
2657 }
2658 if (someopen) {
2659 sio_timeouts_until_log = hz / sio_timeout;
2660 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2661 sio_timeout);
2662 } else {
2663 /* Flush error messages, if any. */
2664 sio_timeouts_until_log = 1;
2665 comwakeup((void *)NULL);
2666 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2667 }
2668}
2669
2670static void
2671comwakeup(chan)
2672 void *chan;
2673{
2674 struct com_s *com;
2675 int unit;
2676
2677 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2678
2679 /*
2680 * Recover from lost output interrupts.
2681 * Poll any lines that don't use interrupts.
2682 */
2683 for (unit = 0; unit < sio_numunits; ++unit) {
2684 com = com_addr(unit);
2685 if (com != NULL && !com->gone
2686 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
8a8d5d85 2687 com_lock();
984263bc 2688 siointr1(com);
8a8d5d85 2689 com_unlock();
984263bc
MD
2690 }
2691 }
2692
2693 /*
2694 * Check for and log errors, but not too often.
2695 */
2696 if (--sio_timeouts_until_log > 0)
2697 return;
2698 sio_timeouts_until_log = hz / sio_timeout;
2699 for (unit = 0; unit < sio_numunits; ++unit) {
2700 int errnum;
2701
2702 com = com_addr(unit);
2703 if (com == NULL)
2704 continue;
2705 if (com->gone)
2706 continue;
2707 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2708 u_int delta;
2709 u_long total;
2710
8a8d5d85 2711 com_lock();
984263bc
MD
2712 delta = com->delta_error_counts[errnum];
2713 com->delta_error_counts[errnum] = 0;
8a8d5d85 2714 com_unlock();
984263bc
MD
2715 if (delta == 0)
2716 continue;
2717 total = com->error_counts[errnum] += delta;
2718 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2719 unit, delta, error_desc[errnum],
2720 delta == 1 ? "" : "s", total);
2721 }
2722 }
2723}
2724
2725static void
2726disc_optim(tp, t, com)
2727 struct tty *tp;
2728 struct termios *t;
2729 struct com_s *com;
2730{
2731 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2732 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2733 && (!(t->c_iflag & PARMRK)
2734 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2735 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2736 && linesw[tp->t_line].l_rint == ttyinput)
2737 tp->t_state |= TS_CAN_BYPASS_L_RINT;
2738 else
2739 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2740 com->hotchar = linesw[tp->t_line].l_hotchar;
2741}
2742
2743/*
2744 * Following are all routines needed for SIO to act as console
2745 */
2746#include <sys/cons.h>
2747
2748struct siocnstate {
2749 u_char dlbl;
2750 u_char dlbh;
2751 u_char ier;
2752 u_char cfcr;
2753 u_char mcr;
2754};
2755
5ca58d54
RG
2756static speed_t siocngetspeed (Port_t, u_long rclk);
2757static void siocnclose (struct siocnstate *sp, Port_t iobase);
2758static void siocnopen (struct siocnstate *sp, Port_t iobase, int speed);
2759static void siocntxwait (Port_t iobase);
984263bc
MD
2760
2761static cn_probe_t siocnprobe;
2762static cn_init_t siocninit;
2763static cn_checkc_t siocncheckc;
2764static cn_getc_t siocngetc;
2765static cn_putc_t siocnputc;
2766
2767#ifdef __i386__
2768CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc,
2769 siocnputc, NULL);
2770#endif
2771
2772/* To get the GDB related variables */
2773#if DDB > 0
2774#include <ddb/ddb.h>
2775#endif
2776
2777static void
2778siocntxwait(iobase)
2779 Port_t iobase;
2780{
2781 int timo;
2782
2783 /*
2784 * Wait for any pending transmission to finish. Required to avoid
2785 * the UART lockup bug when the speed is changed, and for normal
2786 * transmits.
2787 */
2788 timo = 100000;
2789 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
2790 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
2791 ;
2792}
2793
2794/*
2795 * Read the serial port specified and try to figure out what speed
2796 * it's currently running at. We're assuming the serial port has
2797 * been initialized and is basicly idle. This routine is only intended
2798 * to be run at system startup.
2799 *
2800 * If the value read from the serial port doesn't make sense, return 0.
2801 */
2802
2803static speed_t
2804siocngetspeed(iobase, rclk)
2805 Port_t iobase;
2806 u_long rclk;
2807{
2808 u_int divisor;
2809 u_char dlbh;
2810 u_char dlbl;
2811 u_char cfcr;
2812
2813 cfcr = inb(iobase + com_cfcr);
2814 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2815
2816 dlbl = inb(iobase + com_dlbl);
2817 dlbh = inb(iobase + com_dlbh);
2818
2819 outb(iobase + com_cfcr, cfcr);
2820
2821 divisor = dlbh << 8 | dlbl;
2822
2823 /* XXX there should be more sanity checking. */
2824 if (divisor == 0)
2825 return (CONSPEED);
2826 return (rclk / (16UL * divisor));
2827}
2828
2829static void
2830siocnopen(sp, iobase, speed)
2831 struct siocnstate *sp;
2832 Port_t iobase;
2833 int speed;
2834{
2835 u_int divisor;
2836 u_char dlbh;
2837 u_char dlbl;
2838
2839 /*
2840 * Save all the device control registers except the fifo register
2841 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2842 * We can't save the fifo register since it is read-only.
2843 */
2844 sp->ier = inb(iobase + com_ier);
2845 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
2846 siocntxwait(iobase);
2847 sp->cfcr = inb(iobase + com_cfcr);
2848 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2849 sp->dlbl = inb(iobase + com_dlbl);
2850 sp->dlbh = inb(iobase + com_dlbh);
2851 /*
2852 * Only set the divisor registers if they would change, since on
2853 * some 16550 incompatibles (Startech), setting them clears the
2854 * data input register. This also reduces the effects of the
2855 * UMC8669F bug.
2856 */
2857 divisor = siodivisor(comdefaultrclk, speed);
2858 dlbl = divisor & 0xFF;
2859 if (sp->dlbl != dlbl)
2860 outb(iobase + com_dlbl, dlbl);
2861 dlbh = divisor >> 8;
2862 if (sp->dlbh != dlbh)
2863 outb(iobase + com_dlbh, dlbh);
2864 outb(iobase + com_cfcr, CFCR_8BITS);
2865 sp->mcr = inb(iobase + com_mcr);
2866 /*
2867 * We don't want interrupts, but must be careful not to "disable"
2868 * them by clearing the MCR_IENABLE bit, since that might cause
2869 * an interrupt by floating the IRQ line.
2870 */
2871 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
2872}
2873
2874static void
2875siocnclose(sp, iobase)
2876 struct siocnstate *sp;
2877 Port_t iobase;
2878{
2879 /*
2880 * Restore the device control registers.
2881 */
2882 siocntxwait(iobase);
2883 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2884 if (sp->dlbl != inb(iobase + com_dlbl))
2885 outb(iobase + com_dlbl, sp->dlbl);
2886 if (sp->dlbh != inb(iobase + com_dlbh))
2887 outb(iobase + com_dlbh, sp->dlbh);
2888 outb(iobase + com_cfcr, sp->cfcr);
2889 /*
2890 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
2891 */
2892 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
2893 outb(iobase + com_ier, sp->ier);
2894}
2895
2896static void
2897siocnprobe(cp)
2898 struct consdev *cp;
2899{
2900 speed_t boot_speed;
2901 u_char cfcr;
2902 u_int divisor;
2903 int s, unit;
2904 struct siocnstate sp;
2905
2906 /*
2907 * Find our first enabled console, if any. If it is a high-level
2908 * console device, then initialize it and return successfully.
2909 * If it is a low-level console device, then initialize it and
2910 * return unsuccessfully. It must be initialized in both cases
2911 * for early use by console drivers and debuggers. Initializing
2912 * the hardware is not necessary in all cases, since the i/o
2913 * routines initialize it on the fly, but it is necessary if
2914 * input might arrive while the hardware is switched back to an
2915 * uninitialized state. We can't handle multiple console devices
2916 * yet because our low-level routines don't take a device arg.
2917 * We trust the user to set the console flags properly so that we
2918 * don't need to probe.
2919 */
2920 cp->cn_pri = CN_DEAD;
2921
2922 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
2923 int flags;
2924 int disabled;
2925 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
2926 if (disabled)
2927 continue;
2928 }
2929 if (resource_int_value("sio", unit, "flags", &flags))
2930 continue;
2931 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
2932 int port;
2933 Port_t iobase;
2934
2935 if (resource_int_value("sio", unit, "port", &port))
2936 continue;
2937 iobase = port;
2938 s = spltty();
2939 if (boothowto & RB_SERIAL) {
2940 boot_speed =
2941 siocngetspeed(iobase, comdefaultrclk);
2942 if (boot_speed)
2943 comdefaultrate = boot_speed;
2944 }
2945
2946 /*
2947 * Initialize the divisor latch. We can't rely on
2948 * siocnopen() to do this the first time, since it
2949 * avoids writing to the latch if the latch appears
2950 * to have the correct value. Also, if we didn't
2951 * just read the speed from the hardware, then we
2952 * need to set the speed in hardware so that
2953 * switching it later is null.
2954 */
2955 cfcr = inb(iobase + com_cfcr);
2956 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2957 divisor = siodivisor(comdefaultrclk, comdefaultrate);
2958 outb(iobase + com_dlbl, divisor & 0xff);
2959 outb(iobase + com_dlbh, divisor >> 8);
2960 outb(iobase + com_cfcr, cfcr);
2961
2962 siocnopen(&sp, iobase, comdefaultrate);
2963
2964 splx(s);
2965 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2966 cp->cn_dev = makedev(CDEV_MAJOR, unit);
2967 cp->cn_pri = COM_FORCECONSOLE(flags)
2968 || boothowto & RB_SERIAL
2969 ? CN_REMOTE : CN_NORMAL;
2970 siocniobase = iobase;
2971 siocnunit = unit;
2972 }
2973 if (COM_DEBUGGER(flags)) {
2974 printf("sio%d: gdb debugging port\n", unit);
2975 siogdbiobase = iobase;
2976 siogdbunit = unit;
2977#if DDB > 0
2978 gdbdev = makedev(CDEV_MAJOR, unit);
2979 gdb_getc = siocngetc;
2980 gdb_putc = siocnputc;
2981#endif
2982 }
2983 }
2984 }
2985#ifdef __i386__
2986#if DDB > 0
2987 /*
2988 * XXX Ugly Compatability.
2989 * If no gdb port has been specified, set it to be the console
2990 * as some configuration files don't specify the gdb port.
2991 */
2992 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
2993 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
2994 siocnunit);
2995 printf("Set flag 0x80 on desired GDB port in your\n");
2996 printf("configuration file (currently sio only).\n");
2997 siogdbiobase = siocniobase;
2998 siogdbunit = siocnunit;
2999 gdbdev = makedev(CDEV_MAJOR, siocnunit);
3000 gdb_getc = siocngetc;
3001 gdb_putc = siocnputc;
3002 }
3003#endif
3004#endif
3005}
3006
3007#ifdef __alpha__
3008
3009CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
3010
3011int
3012siocnattach(port, speed)
3013 int port;
3014 int speed;
3015{
3016 int s;
3017 u_char cfcr;
3018 u_int divisor;
3019 struct siocnstate sp;
3020
3021 siocniobase = port;
3022 comdefaultrate = speed;
3023 sio_consdev.cn_pri = CN_NORMAL;
3024 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
3025
3026 s = spltty();
3027
3028 /*
3029 * Initialize the divisor latch. We can't rely on
3030 * siocnopen() to do this the first time, since it
3031 * avoids writing to the latch if the latch appears
3032 * to have the correct value. Also, if we didn't
3033 * just read the speed from the hardware, then we
3034 * need to set the speed in hardware so that
3035 * switching it later is null.
3036 */
3037 cfcr = inb(siocniobase + com_cfcr);
3038 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
3039 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3040 outb(siocniobase + com_dlbl, divisor & 0xff);
3041 outb(siocniobase + com_dlbh, divisor >> 8);
3042 outb(siocniobase + com_cfcr, cfcr);
3043
3044 siocnopen(&sp, siocniobase, comdefaultrate);
3045 splx(s);
3046
3047 cn_tab = &sio_consdev;
3048 return (0);
3049}
3050
3051int
3052siogdbattach(port, speed)
3053 int port;
3054 int speed;
3055{
3056 int s;
3057 u_char cfcr;
3058 u_int divisor;
3059 struct siocnstate sp;
3060
3061 siogdbiobase = port;
3062 gdbdefaultrate = speed;
3063
3064 s = spltty();
3065
3066 /*
3067 * Initialize the divisor latch. We can't rely on
3068 * siocnopen() to do this the first time, since it
3069 * avoids writing to the latch if the latch appears
3070 * to have the correct value. Also, if we didn't
3071 * just read the speed from the hardware, then we
3072 * need to set the speed in hardware so that
3073 * switching it later is null.
3074 */
3075 cfcr = inb(siogdbiobase + com_cfcr);
3076 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3077 divisor = siodivisor(comdefaultrclk, gdbdefaultrate);
3078 outb(siogdbiobase + com_dlbl, divisor & 0xff);
3079 outb(siogdbiobase + com_dlbh, divisor >> 8);
3080 outb(siogdbiobase + com_cfcr, cfcr);
3081
3082 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3083 splx(s);
3084
3085 return (0);
3086}
3087
3088#endif
3089
3090static void
3091siocninit(cp)
3092 struct consdev *cp;
3093{
3094 comconsole = DEV_TO_UNIT(cp->cn_dev);
3095}
3096
3097static int
3098siocncheckc(dev)
3099 dev_t dev;
3100{
3101 int c;
3102 Port_t iobase;
3103 int s;
3104 struct siocnstate sp;
3105
3106 if (minor(dev) == siogdbunit)
3107 iobase = siogdbiobase;
3108 else
3109 iobase = siocniobase;
3110 s = spltty();
3111 siocnopen(&sp, iobase, comdefaultrate);
3112 if (inb(iobase + com_lsr) & LSR_RXRDY)
3113 c = inb(iobase + com_data);
3114 else
3115 c = -1;
3116 siocnclose(&sp, iobase);
3117 splx(s);
3118 return (c);
3119}
3120
3121
3122int
3123siocngetc(dev)
3124 dev_t dev;
3125{
3126 int c;
3127 Port_t iobase;
3128 int s;
3129 struct siocnstate sp;
3130
3131 if (minor(dev) == siogdbunit)
3132 iobase = siogdbiobase;
3133 else
3134 iobase = siocniobase;
3135 s = spltty();
3136 siocnopen(&sp, iobase, comdefaultrate);
3137 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3138 ;
3139 c = inb(iobase + com_data);
3140 siocnclose(&sp, iobase);
3141 splx(s);
3142 return (c);
3143}
3144
3145void
3146siocnputc(dev, c)
3147 dev_t dev;
3148 int c;
3149{
3150 int s;
3151 struct siocnstate sp;
3152 Port_t iobase;
3153
3154 if (minor(dev) == siogdbunit)
3155 iobase = siogdbiobase;
3156 else
3157 iobase = siocniobase;
3158 s = spltty();
3159 siocnopen(&sp, iobase, comdefaultrate);
3160 siocntxwait(iobase);
3161 outb(iobase + com_data, c);
3162 siocnclose(&sp, iobase);
3163 splx(s);
3164}
3165
3166#ifdef __alpha__
3167int
3168siogdbgetc()
3169{
3170 int c;
3171 Port_t iobase;
3172 int s;
3173 struct siocnstate sp;
3174
3175 iobase = siogdbiobase;
3176 s = spltty();
3177 siocnopen(&sp, iobase, gdbdefaultrate);
3178 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3179 ;
3180 c = inb(iobase + com_data);
3181 siocnclose(&sp, iobase);
3182 splx(s);
3183 return (c);
3184}
3185
3186void
3187siogdbputc(c)
3188 int c;
3189{
3190 int s;
3191 struct siocnstate sp;
3192
3193 s = spltty();
3194 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3195 siocntxwait(siogdbiobase);
3196 outb(siogdbiobase + com_data, c);
3197 siocnclose(&sp, siogdbiobase);
3198 splx(s);
3199}
3200#endif
3201
3202DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
984263bc
MD
3203#if NPCI > 0
3204DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
3205#endif
3206#if NPUC > 0
3207DRIVER_MODULE(sio, puc, sio_puc_driver, sio_devclass, 0, 0);
3208#endif