This commit represents a major revamping of the clock interrupt and timebase
[dragonfly.git] / sys / platform / pc32 / isa / clock.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
88c4d2f6 38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.11 2004/01/30 05:42:16 dillon Exp $
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39 */
40
41/*
42 * Routines to handle clock hardware.
43 */
44
45/*
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 *
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
50 */
51
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52#include "use_apm.h"
53#include "use_mca.h"
984263bc 54#include "opt_clock.h"
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55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/time.h>
59#include <sys/kernel.h>
60#ifndef SMP
61#include <sys/lock.h>
62#endif
63#include <sys/sysctl.h>
64#include <sys/cons.h>
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65#include <sys/systimer.h>
66#include <sys/globaldata.h>
67#include <sys/thread2.h>
68#include <sys/systimer.h>
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69
70#include <machine/clock.h>
71#ifdef CLK_CALIBRATION_LOOP
72#endif
73#include <machine/cputypes.h>
74#include <machine/frame.h>
75#include <machine/ipl.h>
76#include <machine/limits.h>
77#include <machine/md_var.h>
78#include <machine/psl.h>
79#ifdef APIC_IO
80#include <machine/segments.h>
81#endif
82#if defined(SMP) || defined(APIC_IO)
83#include <machine/smp.h>
84#endif /* SMP || APIC_IO */
85#include <machine/specialreg.h>
86
87#include <i386/isa/icu.h>
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88#include <bus/isa/i386/isa.h>
89#include <bus/isa/rtc.h>
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90#include <i386/isa/timerreg.h>
91
92#include <i386/isa/intr_machdep.h>
93
984263bc 94#if NMCA > 0
1f2de5d4 95#include <bus/mca/i386/mca_machdep.h>
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96#endif
97
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98#ifdef APIC_IO
99#include <i386/isa/intr_machdep.h>
100/* The interrupt triggered by the 8254 (timer) chip */
101int apic_8254_intr;
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102static u_long read_intr_count (int vec);
103static void setup_8254_mixed_mode (void);
984263bc 104#endif
88c4d2f6 105static void i8254_restore(void);
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106
107/*
108 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
109 * can use a simple formula for leap years.
110 */
111#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
112#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
113
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114#ifndef TIMER_FREQ
115#define TIMER_FREQ 1193182
116#endif
984263bc 117
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118#define TIMER_SELX TIMER_SEL2
119#define TIMER_CNTRX TIMER_CNTR2
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120
121int adjkerntz; /* local offset from GMT in seconds */
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122int disable_rtc_set; /* disable resettodr() if != 0 */
123volatile u_int idelayed;
88c4d2f6 124int statclock_disable = 1; /* we don't use the statclock right now */
984263bc 125u_int stat_imask = SWI_CLOCK_MASK;
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126u_int cputimer_freq = TIMER_FREQ;
127#if 0
128int64_t cputimer_freq64_usec = ((int64_t)TIMER_FREQ << 32) / 1000000;
129int64_t cputimer_freq64_nsec = ((int64_t)TIMER_FREQ << 32) / 1000000000LL;
984263bc 130#endif
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131int64_t cputimer_freq64_usec = (1000000LL << 32) / TIMER_FREQ;
132int64_t cputimer_freq64_nsec = (1000000000LL << 32) / TIMER_FREQ;
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133u_int tsc_freq;
134int tsc_is_broken;
135int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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136int timer0_running;
137enum tstate { RELEASED, ACQUIRED };
138enum tstate timer0_state;
139enum tstate timer1_state;
140enum tstate timer2_state;
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141
142static int beeping = 0;
143static u_int clk_imask = HWI_MASK | SWI_MASK;
144static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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145static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
146static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
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147static u_int tsc_present;
148
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149/*
150 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
151 * counting as of this interrupt. We use timer1 in free-running mode (not
152 * generating any interrupts) as our main counter. Each cpu has timeouts
153 * pending.
154 */
984263bc 155static void
88c4d2f6 156clkintr(struct intrframe frame)
984263bc 157{
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158 static sysclock_t timer1_count;
159 struct globaldata *gd = mycpu;
160 struct globaldata *gscan;
161 int n;
9a47427a 162
b505872f 163 /*
88c4d2f6 164 * SWSTROBE mode is a one-shot, the timer is no longer running
b505872f 165 */
88c4d2f6 166 timer0_running = 0;
b505872f 167
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168 /*
169 * XXX this could be done more efficiently by using a bitmask?
170 */
171 timer1_count = cputimer_count();
172 for (n = 0; n < ncpus; ++n) {
173 gscan = globaldata_find(n);
174 if (gscan->gd_nextclock == 0)
175 continue;
176 if (gscan != gd) {
177 lwkt_send_ipiq(gscan->gd_cpuid, (ipifunc_t)systimer_intr, &timer1_count);
178 } else {
179 systimer_intr(&timer1_count, &frame);
180 }
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181 }
182#if NMCA > 0
183 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
184 if (MCA_system)
185 outb(0x61, inb(0x61) | 0x80);
186#endif
187}
188
88c4d2f6 189
984263bc 190/*
88c4d2f6 191 * NOTE! not MP safe.
984263bc 192 */
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193int
194acquire_timer2(int mode)
195{
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196 /* Timer2 is being used for time count operation */
197 return(-1);
198#if 0
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199 if (timer2_state != RELEASED)
200 return (-1);
201 timer2_state = ACQUIRED;
202
203 /*
204 * This access to the timer registers is as atomic as possible
205 * because it is a single instruction. We could do better if we
88c4d2f6 206 * knew the rate.
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207 */
208 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
984263bc 209 return (0);
88c4d2f6 210#endif
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211}
212
213int
214release_timer2()
215{
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216 if (timer2_state != ACQUIRED)
217 return (-1);
984263bc 218 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
88c4d2f6 219 timer2_state = RELEASED;
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220 return (0);
221}
222
223/*
224 * This routine receives statistical clock interrupts from the RTC.
225 * As explained above, these occur at 128 interrupts per second.
226 * When profiling, we receive interrupts at a rate of 1024 Hz.
227 *
228 * This does not actually add as much overhead as it sounds, because
229 * when the statistical clock is active, the hardclock driver no longer
230 * needs to keep (inaccurate) statistics on its own. This decouples
231 * statistics gathering from scheduling interrupts.
232 *
233 * The RTC chip requires that we read status register C (RTC_INTR)
234 * to acknowledge an interrupt, before it will generate the next one.
235 * Under high interrupt load, rtcintr() can be indefinitely delayed and
236 * the clock can tick immediately after the read from RTC_INTR. In this
237 * case, the mc146818A interrupt signal will not drop for long enough
238 * to register with the 8259 PIC. If an interrupt is missed, the stat
239 * clock will halt, considerably degrading system performance. This is
240 * why we use 'while' rather than a more straightforward 'if' below.
241 * Stat clock ticks can still be lost, causing minor loss of accuracy
242 * in the statistics, but the stat clock will no longer stop.
243 */
244static void
88c4d2f6 245rtcintr(struct intrframe frame)
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246{
247 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
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248 ;
249 /* statclock(&frame); no longer used */
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250}
251
252#include "opt_ddb.h"
253#ifdef DDB
254#include <ddb/ddb.h>
255
256DB_SHOW_COMMAND(rtc, rtc)
257{
258 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
259 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
260 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
261 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
262}
263#endif /* DDB */
264
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265/*
266 * Convert a frequency to a cpu timer count.
267 */
268sysclock_t
269cputimer_fromhz(int freq)
984263bc 270{
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271 return(cputimer_freq / freq + 1);
272}
984263bc 273
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274sysclock_t
275cputimer_fromus(int us)
276{
277 return((int64_t)cputimer_freq * us / 1000000);
278}
984263bc 279
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280/*
281 * Return the current cpu timer count as a 32 bit integer.
282 */
283sysclock_t
284cputimer_count(void)
285{
286 static sysclock_t cputimer_base;
287 static __uint16_t cputimer_last;
288 __uint16_t count;
289 sysclock_t ret;
984263bc 290
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291 clock_lock();
292 outb(TIMER_MODE, TIMER_SELX | TIMER_LATCH);
293 count = (__uint8_t)inb(TIMER_CNTRX); /* get countdown */
294 count |= ((__uint8_t)inb(TIMER_CNTRX) << 8);
295 count = -count; /* -> countup */
296 if (count < cputimer_last) /* rollover */
297 cputimer_base += 0x00010000;
298 ret = cputimer_base | count;
299 cputimer_last = count;
8a8d5d85 300 clock_unlock();
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301 return(ret);
302}
303
304/*
305 * Reload for the next timeout. It is possible for the reload value
306 * to be 0 or negative, indicating that an immediate timer interrupt
307 * is desired. For now make the minimum 2 ticks.
308 */
309void
310cputimer_intr_reload(sysclock_t reload)
311{
312 __uint16_t count;
313
314 if ((int)reload < 2)
315 reload = 2;
316
317 clock_lock();
318 if (timer0_running) {
319 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
320 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
321 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
322 if (reload < count) {
323 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
324 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
325 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
326 }
327 } else {
328 timer0_running = 1;
329 if (reload > 0xFFFF)
330 reload = 0; /* full count */
331 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
332 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
333 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
334 }
335 clock_unlock();
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336}
337
338/*
339 * Wait "n" microseconds.
88c4d2f6 340 * Relies on timer 1 counting down from (cputimer_freq / hz)
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341 * Note: timer had better have been programmed before this is first used!
342 */
343void
344DELAY(int n)
345{
346 int delta, prev_tick, tick, ticks_left;
347
348#ifdef DELAYDEBUG
349 int getit_calls = 1;
350 int n1;
351 static int state = 0;
352
353 if (state == 0) {
354 state = 1;
355 for (n1 = 1; n1 <= 10000000; n1 *= 10)
356 DELAY(n1);
357 state = 2;
358 }
359 if (state == 1)
360 printf("DELAY(%d)...", n);
361#endif
362 /*
363 * Guard against the timer being uninitialized if we are called
364 * early for console i/o.
365 */
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366 if (timer0_state == RELEASED)
367 i8254_restore();
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368
369 /*
370 * Read the counter first, so that the rest of the setup overhead is
371 * counted. Guess the initial overhead is 20 usec (on most systems it
372 * takes about 1.5 usec for each of the i/o's in getit(). The loop
373 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
374 * multiplications and divisions to scale the count take a while).
375 */
88c4d2f6 376 prev_tick = cputimer_count();
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377 n -= 0; /* XXX actually guess no initial overhead */
378 /*
88c4d2f6 379 * Calculate (n * (cputimer_freq / 1e6)) without using floating point
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380 * and without any avoidable overflows.
381 */
88c4d2f6 382 if (n <= 0) {
984263bc 383 ticks_left = 0;
88c4d2f6 384 } else if (n < 256) {
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385 /*
386 * Use fixed point to avoid a slow division by 1000000.
387 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
388 * 2^15 is the first power of 2 that gives exact results
389 * for n between 0 and 256.
390 */
391 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
88c4d2f6 392 } else {
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393 /*
394 * Don't bother using fixed point, although gcc-2.7.2
395 * generates particularly poor code for the long long
396 * division, since even the slow way will complete long
397 * before the delay is up (unless we're interrupted).
398 */
88c4d2f6 399 ticks_left = ((u_int)n * (long long)cputimer_freq + 999999)
984263bc 400 / 1000000;
88c4d2f6 401 }
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402
403 while (ticks_left > 0) {
88c4d2f6 404 tick = cputimer_count();
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405#ifdef DELAYDEBUG
406 ++getit_calls;
407#endif
88c4d2f6 408 delta = tick - prev_tick;
984263bc 409 prev_tick = tick;
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410 if (delta < 0)
411 delta = 0;
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412 ticks_left -= delta;
413 }
414#ifdef DELAYDEBUG
415 if (state == 1)
416 printf(" %d calls to getit() at %d usec each\n",
417 getit_calls, (n + 5) / getit_calls);
418#endif
419}
420
421static void
422sysbeepstop(void *chan)
423{
424 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
984263bc 425 beeping = 0;
88c4d2f6 426 release_timer2();
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427}
428
429int
430sysbeep(int pitch, int period)
431{
984263bc 432 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
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433 return(-1);
434 /*
435 * Nobody else is using timer2, we do not need the clock lock
436 */
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437 outb(TIMER_CNTR2, pitch);
438 outb(TIMER_CNTR2, (pitch>>8));
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439 if (!beeping) {
440 /* enable counter2 output to speaker */
441 outb(IO_PPI, inb(IO_PPI) | 3);
442 beeping = period;
443 timeout(sysbeepstop, (void *)NULL, period);
444 }
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445 return (0);
446}
447
448/*
449 * RTC support routines
450 */
451
452int
453rtcin(reg)
454 int reg;
455{
456 int s;
457 u_char val;
458
459 s = splhigh();
460 outb(IO_RTC, reg);
461 inb(0x84);
462 val = inb(IO_RTC + 1);
463 inb(0x84);
464 splx(s);
465 return (val);
466}
467
468static __inline void
469writertc(u_char reg, u_char val)
470{
471 int s;
472
473 s = splhigh();
474 inb(0x84);
475 outb(IO_RTC, reg);
476 inb(0x84);
477 outb(IO_RTC + 1, val);
478 inb(0x84); /* XXX work around wrong order in rtcin() */
479 splx(s);
480}
481
482static __inline int
483readrtc(int port)
484{
485 return(bcd2bin(rtcin(port)));
486}
487
488static u_int
489calibrate_clocks(void)
490{
491 u_int64_t old_tsc;
492 u_int count, prev_count, tot_count;
493 int sec, start_sec, timeout;
494
495 if (bootverbose)
496 printf("Calibrating clock(s) ... ");
497 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
498 goto fail;
499 timeout = 100000000;
500
501 /* Read the mc146818A seconds counter. */
502 for (;;) {
503 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
504 sec = rtcin(RTC_SEC);
505 break;
506 }
507 if (--timeout == 0)
508 goto fail;
509 }
510
511 /* Wait for the mC146818A seconds counter to change. */
512 start_sec = sec;
513 for (;;) {
514 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
515 sec = rtcin(RTC_SEC);
516 if (sec != start_sec)
517 break;
518 }
519 if (--timeout == 0)
520 goto fail;
521 }
522
523 /* Start keeping track of the i8254 counter. */
88c4d2f6 524 prev_count = cputimer_count();
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525 tot_count = 0;
526
527 if (tsc_present)
528 old_tsc = rdtsc();
529 else
530 old_tsc = 0; /* shut up gcc */
531
532 /*
533 * Wait for the mc146818A seconds counter to change. Read the i8254
534 * counter for each iteration since this is convenient and only
535 * costs a few usec of inaccuracy. The timing of the final reads
536 * of the counters almost matches the timing of the initial reads,
537 * so the main cause of inaccuracy is the varying latency from
538 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
539 * rtcin(RTC_SEC) that returns a changed seconds count. The
540 * maximum inaccuracy from this cause is < 10 usec on 486's.
541 */
542 start_sec = sec;
543 for (;;) {
544 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
545 sec = rtcin(RTC_SEC);
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546 count = cputimer_count();
547 tot_count += (int)(count - prev_count);
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548 prev_count = count;
549 if (sec != start_sec)
550 break;
551 if (--timeout == 0)
552 goto fail;
553 }
554
555 /*
556 * Read the cpu cycle counter. The timing considerations are
557 * similar to those for the i8254 clock.
558 */
559 if (tsc_present)
560 tsc_freq = rdtsc() - old_tsc;
561
562 if (bootverbose) {
563 if (tsc_present)
564 printf("TSC clock: %u Hz, ", tsc_freq);
565 printf("i8254 clock: %u Hz\n", tot_count);
566 }
567 return (tot_count);
568
569fail:
570 if (bootverbose)
571 printf("failed, using default i8254 clock of %u Hz\n",
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572 cputimer_freq);
573 return (cputimer_freq);
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574}
575
576static void
577i8254_restore(void)
578{
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579 timer0_state = ACQUIRED;
580 timer1_state = ACQUIRED;
8a8d5d85 581 clock_lock();
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582 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
583 outb(TIMER_CNTR0, 2); /* lsb */
584 outb(TIMER_CNTR0, 0); /* msb */
585 outb(TIMER_MODE, TIMER_SELX | TIMER_RATEGEN | TIMER_16BIT);
586 outb(TIMER_CNTRX, 0); /* lsb */
587 outb(TIMER_CNTRX, 0); /* msb */
588 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
8a8d5d85 589 clock_unlock();
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590}
591
592static void
593rtc_restore(void)
594{
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595 /* Restore all of the RTC's "status" (actually, control) registers. */
596 writertc(RTC_STATUSB, RTCSB_24HR);
597 writertc(RTC_STATUSA, rtc_statusa);
598 writertc(RTC_STATUSB, rtc_statusb);
599}
600
601/*
602 * Restore all the timers non-atomically (XXX: should be atomically).
603 *
604 * This function is called from apm_default_resume() to restore all the timers.
605 * This should not be necessary, but there are broken laptops that do not
606 * restore all the timers on resume.
607 */
608void
609timer_restore(void)
610{
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611 i8254_restore(); /* restore timer_freq and hz */
612 rtc_restore(); /* reenable RTC interrupts */
613}
614
615/*
616 * Initialize 8254 timer 0 early so that it can be used in DELAY().
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617 */
618void
619startrtclock()
620{
621 u_int delta, freq;
622
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623 /*
624 * Can we use the TSC?
625 */
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626 if (cpu_feature & CPUID_TSC)
627 tsc_present = 1;
628 else
629 tsc_present = 0;
630
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631 /*
632 * Initial RTC state, don't do anything unexpected
633 */
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634 writertc(RTC_STATUSA, rtc_statusa);
635 writertc(RTC_STATUSB, RTCSB_24HR);
636
88c4d2f6
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637 /*
638 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
639 * generate an interrupt, which we will ignore for now.
640 *
641 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
642 * (so it counts a full 2^16 and repeats). We will use this timer
643 * for our counting.
644 */
645 i8254_restore();
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646 freq = calibrate_clocks();
647#ifdef CLK_CALIBRATION_LOOP
648 if (bootverbose) {
649 printf(
650 "Press a key on the console to abort clock calibration\n");
651 while (cncheckc() == -1)
652 calibrate_clocks();
653 }
654#endif
655
656 /*
657 * Use the calibrated i8254 frequency if it seems reasonable.
658 * Otherwise use the default, and don't use the calibrated i586
659 * frequency.
660 */
88c4d2f6
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661 delta = freq > cputimer_freq ?
662 freq - cputimer_freq : cputimer_freq - freq;
663 if (delta < cputimer_freq / 100) {
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664#ifndef CLK_USE_I8254_CALIBRATION
665 if (bootverbose)
666 printf(
667"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
88c4d2f6 668 freq = cputimer_freq;
984263bc 669#endif
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670 cputimer_freq = freq;
671 cputimer_freq64_usec = (1000000LL << 32) / freq;
672 cputimer_freq64_nsec = (1000000000LL << 32) / freq;
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673 } else {
674 if (bootverbose)
675 printf(
676 "%d Hz differs from default of %d Hz by more than 1%%\n",
88c4d2f6 677 freq, cputimer_freq);
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678 tsc_freq = 0;
679 }
680
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681#ifndef CLK_USE_TSC_CALIBRATION
682 if (tsc_freq != 0) {
683 if (bootverbose)
684 printf(
685"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
686 tsc_freq = 0;
687 }
688#endif
689 if (tsc_present && tsc_freq == 0) {
690 /*
691 * Calibration of the i586 clock relative to the mc146818A
692 * clock failed. Do a less accurate calibration relative
693 * to the i8254 clock.
694 */
695 u_int64_t old_tsc = rdtsc();
696
697 DELAY(1000000);
698 tsc_freq = rdtsc() - old_tsc;
699#ifdef CLK_USE_TSC_CALIBRATION
700 if (bootverbose)
701 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
702#endif
703 }
704
705#if !defined(SMP)
706 /*
707 * We can not use the TSC in SMP mode, until we figure out a
708 * cheap (impossible), reliable and precise (yeah right!) way
709 * to synchronize the TSCs of all the CPUs.
710 * Curse Intel for leaving the counter out of the I/O APIC.
711 */
712
713#if NAPM > 0
714 /*
715 * We can not use the TSC if we support APM. Precise timekeeping
716 * on an APM'ed machine is at best a fools pursuit, since
717 * any and all of the time spent in various SMM code can't
718 * be reliably accounted for. Reading the RTC is your only
719 * source of reliable time info. The i8254 looses too of course
720 * but we need to have some kind of time...
721 * We don't know at this point whether APM is going to be used
722 * or not, nor when it might be activated. Play it safe.
723 */
724 return;
725#endif /* NAPM > 0 */
726
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727#endif /* !defined(SMP) */
728}
729
730/*
731 * Initialize the time of day register, based on the time base which is, e.g.
732 * from a filesystem.
733 */
734void
735inittodr(time_t base)
736{
737 unsigned long sec, days;
738 int yd;
739 int year, month;
88c4d2f6 740 int y, m;
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741 struct timespec ts;
742
743 if (base) {
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744 ts.tv_sec = base;
745 ts.tv_nsec = 0;
88c4d2f6 746 set_timeofday(&ts);
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747 }
748
749 /* Look if we have a RTC present and the time is valid */
750 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
751 goto wrong_time;
752
753 /* wait for time update to complete */
754 /* If RTCSA_TUP is zero, we have at least 244us before next update */
88c4d2f6 755 crit_enter();
984263bc 756 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
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757 crit_exit();
758 crit_enter();
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759 }
760
761 days = 0;
762#ifdef USE_RTC_CENTURY
763 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
764#else
765 year = readrtc(RTC_YEAR) + 1900;
766 if (year < 1970)
767 year += 100;
768#endif
769 if (year < 1970) {
88c4d2f6 770 crit_exit();
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771 goto wrong_time;
772 }
773 month = readrtc(RTC_MONTH);
774 for (m = 1; m < month; m++)
775 days += daysinmonth[m-1];
776 if ((month > 2) && LEAPYEAR(year))
777 days ++;
778 days += readrtc(RTC_DAY) - 1;
779 yd = days;
780 for (y = 1970; y < year; y++)
781 days += DAYSPERYEAR + LEAPYEAR(y);
782 sec = ((( days * 24 +
783 readrtc(RTC_HRS)) * 60 +
784 readrtc(RTC_MIN)) * 60 +
785 readrtc(RTC_SEC));
786 /* sec now contains the number of seconds, since Jan 1 1970,
787 in the local time zone */
788
789 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
790
791 y = time_second - sec;
792 if (y <= -2 || y >= 2) {
793 /* badly off, adjust it */
794 ts.tv_sec = sec;
795 ts.tv_nsec = 0;
88c4d2f6 796 set_timeofday(&ts);
984263bc 797 }
88c4d2f6 798 crit_exit();
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799 return;
800
801wrong_time:
802 printf("Invalid time in real time clock.\n");
803 printf("Check and reset the date immediately!\n");
804}
805
806/*
807 * Write system time back to RTC
808 */
809void
810resettodr()
811{
812 unsigned long tm;
88c4d2f6 813 int y, m;
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814
815 if (disable_rtc_set)
816 return;
817
984263bc 818 tm = time_second;
984263bc 819
88c4d2f6 820 crit_enter();
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821 /* Disable RTC updates and interrupts. */
822 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
823
824 /* Calculate local time to put in RTC */
825
826 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
827
828 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
829 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
830 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
831
832 /* We have now the days since 01-01-1970 in tm */
833 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
834 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
835 tm >= m;
836 y++, m = DAYSPERYEAR + LEAPYEAR(y))
837 tm -= m;
838
839 /* Now we have the years in y and the day-of-the-year in tm */
840 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
841#ifdef USE_RTC_CENTURY
842 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
843#endif
844 for (m = 0; ; m++) {
845 int ml;
846
847 ml = daysinmonth[m];
848 if (m == 1 && LEAPYEAR(y))
849 ml++;
850 if (tm < ml)
851 break;
852 tm -= ml;
853 }
854
855 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
856 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
857
858 /* Reenable RTC updates and interrupts. */
859 writertc(RTC_STATUSB, rtc_statusb);
88c4d2f6 860 crit_exit();
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861}
862
863
864/*
88c4d2f6
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865 * Start both clocks running. DragonFly note: the stat clock is no longer
866 * used. Instead, 8254 based systimers are used for all major clock
867 * interrupts. statclock_disable is set by default.
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868 */
869void
870cpu_initclocks()
871{
872 int diag;
873#ifdef APIC_IO
874 int apic_8254_trial;
875 struct intrec *clkdesc;
876#endif /* APIC_IO */
877
878 if (statclock_disable) {
879 /*
880 * The stat interrupt mask is different without the
881 * statistics clock. Also, don't set the interrupt
882 * flag which would normally cause the RTC to generate
883 * interrupts.
884 */
885 stat_imask = HWI_MASK | SWI_MASK;
886 rtc_statusb = RTCSB_24HR;
887 } else {
888 /* Setting stathz to nonzero early helps avoid races. */
889 stathz = RTC_NOPROFRATE;
890 profhz = RTC_PROFRATE;
891 }
892
893 /* Finish initializing 8253 timer 0. */
894#ifdef APIC_IO
895
896 apic_8254_intr = isa_apic_irq(0);
897 apic_8254_trial = 0;
898 if (apic_8254_intr >= 0 ) {
899 if (apic_int_type(0, 0) == 3)
900 apic_8254_trial = 1;
901 } else {
902 /* look for ExtInt on pin 0 */
903 if (apic_int_type(0, 0) == 3) {
904 apic_8254_intr = apic_irq(0, 0);
905 setup_8254_mixed_mode();
906 } else
907 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
908 }
909
910 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
4b5f931b 911 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
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912 INTREN(1 << apic_8254_intr);
913
914#else /* APIC_IO */
915
916 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
4b5f931b 917 INTR_EXCL | INTR_FAST);
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918 INTREN(IRQ0);
919
920#endif /* APIC_IO */
921
922 /* Initialize RTC. */
923 writertc(RTC_STATUSA, rtc_statusa);
924 writertc(RTC_STATUSB, RTCSB_24HR);
925
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926 if (statclock_disable == 0) {
927 diag = rtcin(RTC_DIAG);
928 if (diag != 0)
929 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
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930
931#ifdef APIC_IO
88c4d2f6
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932 if (isa_apic_irq(8) != 8)
933 panic("APIC RTC != 8");
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934#endif /* APIC_IO */
935
88c4d2f6
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936 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
937 INTR_EXCL | INTR_FAST);
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938
939#ifdef APIC_IO
88c4d2f6 940 INTREN(APIC_IRQ8);
984263bc 941#else
88c4d2f6 942 INTREN(IRQ8);
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943#endif /* APIC_IO */
944
88c4d2f6
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945 writertc(RTC_STATUSB, rtc_statusb);
946 }
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947
948#ifdef APIC_IO
949 if (apic_8254_trial) {
88c4d2f6
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950 sysclock_t base;
951 int lastcnt = read_intr_count(apic_8254_intr);
952
953 /*
954 * XXX this assumes the 8254 is the cpu timer. Force an
955 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
956 * then see if we got it.
957 */
984263bc 958 printf("APIC_IO: Testing 8254 interrupt delivery\n");
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959 cputimer_intr_reload(2); /* XXX assumes 8254 */
960 base = cputimer_count();
961 while (cputimer_count() - base < cputimer_freq / 100)
984263bc 962 ; /* nothing */
88c4d2f6 963 if (read_intr_count(apic_8254_intr) - lastcnt == 0) {
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964 /*
965 * The MP table is broken.
966 * The 8254 was not connected to the specified pin
967 * on the IO APIC.
968 * Workaround: Limited variant of mixed mode.
969 */
970 INTRDIS(1 << apic_8254_intr);
971 inthand_remove(clkdesc);
972 printf("APIC_IO: Broken MP table detected: "
973 "8254 is not connected to "
974 "IOAPIC #%d intpin %d\n",
975 int_to_apicintpin[apic_8254_intr].ioapic,
976 int_to_apicintpin[apic_8254_intr].int_pin);
977 /*
978 * Revoke current ISA IRQ 0 assignment and
979 * configure a fallback interrupt routing from
980 * the 8254 Timer via the 8259 PIC to the
981 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
982 * We reuse the low level interrupt handler number.
983 */
984 if (apic_irq(0, 0) < 0) {
985 revoke_apic_irq(apic_8254_intr);
986 assign_apic_irq(0, 0, apic_8254_intr);
987 }
988 apic_8254_intr = apic_irq(0, 0);
989 setup_8254_mixed_mode();
990 inthand_add("clk", apic_8254_intr,
991 (inthand2_t *)clkintr,
4b5f931b 992 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
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993 INTREN(1 << apic_8254_intr);
994 }
995
996 }
997 if (apic_int_type(0, 0) != 3 ||
998 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
88c4d2f6 999 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
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1000 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1001 int_to_apicintpin[apic_8254_intr].ioapic,
1002 int_to_apicintpin[apic_8254_intr].int_pin);
88c4d2f6 1003 } else {
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1004 printf("APIC_IO: "
1005 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
88c4d2f6 1006 }
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1007#endif
1008
1009}
1010
1011#ifdef APIC_IO
1012static u_long
1013read_intr_count(int vec)
1014{
1015 u_long *up;
1016 up = intr_countp[vec];
1017 if (up)
1018 return *up;
1019 return 0UL;
1020}
1021
1022static void
1023setup_8254_mixed_mode()
1024{
1025 /*
1026 * Allow 8254 timer to INTerrupt 8259:
1027 * re-initialize master 8259:
1028 * reset; prog 4 bytes, single ICU, edge triggered
1029 */
1030 outb(IO_ICU1, 0x13);
1031 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1032 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1033 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1034 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1035
1036 /* program IO APIC for type 3 INT on INT0 */
1037 if (ext_int_setup(0, 0) < 0)
1038 panic("8254 redirect via APIC pin0 impossible!");
1039}
1040#endif
1041
1042void
1043setstatclockrate(int newhz)
1044{
1045 if (newhz == RTC_PROFRATE)
1046 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1047 else
1048 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1049 writertc(RTC_STATUSA, rtc_statusa);
1050}
1051
88c4d2f6 1052#if 0
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1053static unsigned
1054tsc_get_timecount(struct timecounter *tc)
1055{
1056 return (rdtsc());
1057}
88c4d2f6 1058#endif
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1059
1060#ifdef KERN_TIMESTAMP
1061#define KERN_TIMESTAMP_SIZE 16384
1062static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1063SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1064 sizeof(tsc), "LU", "Kernel timestamps");
1065void
1066_TSTMP(u_int32_t x)
1067{
1068 static int i;
1069
1070 tsc[i] = (u_int32_t)rdtsc();
1071 tsc[i+1] = x;
1072 i = i + 2;
1073 if (i >= KERN_TIMESTAMP_SIZE)
1074 i = 0;
1075 tsc[i] = 0; /* mark last entry */
1076}
6b08710e 1077#endif /* KERN_TIMESTAMP */
984263bc 1078