projects / dragonfly.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | history | HEAD
jme: Cache align software TX/RX descriptor data
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
CommitLineData
76fbb0b9
SZ		 1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
76fbb0b9
SZ		 28 */
29
8a0620e4 30#include "opt_ifpoll.h"
93bfe1b8 31#include "opt_jme.h"
9de40864 32
76fbb0b9
SZ		 33#include <sys/param.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/interrupt.h>
38#include <sys/malloc.h>
39#include <sys/proc.h>
40#include <sys/rman.h>
41#include <sys/serialize.h>
31f0d5a2 42#include <sys/serialize2.h>
76fbb0b9
SZ		 43#include <sys/socket.h>
44#include <sys/sockio.h>
45#include <sys/sysctl.h>
46
47#include <net/ethernet.h>
48#include <net/if.h>
49#include <net/bpf.h>
50#include <net/if_arp.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
8a0620e4 53#include <net/if_poll.h>
76fbb0b9 54#include <net/ifq_var.h>
24dd1705 55#include <net/toeplitz.h>
a6acc6e2 56#include <net/toeplitz2.h>
76fbb0b9
SZ		 57#include <net/vlan/if_vlan_var.h>
58#include <net/vlan/if_vlan_ether.h>
59
1bedd927
SZ		 60#include <netinet/ip.h>
61#include <netinet/tcp.h>
a6acc6e2 62
76fbb0b9 63#include <dev/netif/mii_layer/miivar.h>
dbe37f03 64#include <dev/netif/mii_layer/jmphyreg.h>
76fbb0b9
SZ		 65
66#include <bus/pci/pcireg.h>
67#include <bus/pci/pcivar.h>
68#include <bus/pci/pcidevs.h>
69
08c76ecf
SZ		 70#include <dev/netif/jme/if_jmereg.h>
71#include <dev/netif/jme/if_jmevar.h>
76fbb0b9
SZ		 72
73#include "miibus_if.h"
74
29890f78
SZ		 75#define JME_TX_SERIALIZE 1
76#define JME_RX_SERIALIZE 2
77
76fbb0b9
SZ		 78#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
79
760c056c
SZ		 80#ifdef JME_RSS_DEBUG
81#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
82do { \
66f75939 83 if ((sc)->jme_rss_debug >= (lvl)) \
760c056c
SZ		 84 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
85} while (0)
86#else /* !JME_RSS_DEBUG */
87#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
88#endif /* JME_RSS_DEBUG */
89
76fbb0b9
SZ		 90static int jme_probe(device_t);
91static int jme_attach(device_t);
92static int jme_detach(device_t);
93static int jme_shutdown(device_t);
94static int jme_suspend(device_t);
95static int jme_resume(device_t);
96
97static int jme_miibus_readreg(device_t, int, int);
98static int jme_miibus_writereg(device_t, int, int, int);
99static void jme_miibus_statchg(device_t);
100
101static void jme_init(void *);
102static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
103static void jme_start(struct ifnet *);
104static void jme_watchdog(struct ifnet *);
105static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
106static int jme_mediachange(struct ifnet *);
8a0620e4
SZ		 107#ifdef IFPOLL_ENABLE
108static void jme_npoll(struct ifnet *, struct ifpoll_info *);
9b99c84f
SZ		 109static void jme_npoll_status(struct ifnet *, int);
110static void jme_npoll_rx(struct ifnet *, void *, int);
111static void jme_npoll_tx(struct ifnet *, void *, int);
9de40864 112#endif
31f0d5a2
SZ		 113static void jme_serialize(struct ifnet *, enum ifnet_serialize);
114static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
115static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
116#ifdef INVARIANTS
117static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
118 boolean_t);
119#endif
76fbb0b9
SZ		 120
121static void jme_intr(void *);
58880b0d
SZ		 122static void jme_msix_tx(void *);
123static void jme_msix_rx(void *);
e0009afb 124static void jme_msix_status(void *);
9b99c84f 125static void jme_txeof(struct jme_txdata *);
dea2452a 126static void jme_rxeof(struct jme_rxdata *, int);
4447c752 127static void jme_rx_intr(struct jme_softc *, uint32_t);
8a0620e4
SZ		 128static void jme_enable_intr(struct jme_softc *);
129static void jme_disable_intr(struct jme_softc *);
de437f82 130static void jme_rx_restart(struct jme_softc *, uint32_t);
76fbb0b9 131
58880b0d
SZ		 132static int jme_msix_setup(device_t);
133static void jme_msix_teardown(device_t, int);
134static int jme_intr_setup(device_t);
135static void jme_intr_teardown(device_t);
136static void jme_msix_try_alloc(device_t);
137static void jme_msix_free(device_t);
138static int jme_intr_alloc(device_t);
139static void jme_intr_free(device_t);
76fbb0b9 140static int jme_dma_alloc(struct jme_softc *);
0b3414d9 141static void jme_dma_free(struct jme_softc *);
dea2452a 142static int jme_init_rx_ring(struct jme_rxdata *);
9b99c84f 143static void jme_init_tx_ring(struct jme_txdata *);
76fbb0b9 144static void jme_init_ssb(struct jme_softc *);
dea2452a 145static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
9b99c84f 146static int jme_encap(struct jme_txdata *, struct mbuf **);
dea2452a
SZ		 147static void jme_rxpkt(struct jme_rxdata *);
148static int jme_rxring_dma_alloc(struct jme_rxdata *);
149static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
064b75ed 150static int jme_rxbuf_dma_filter(void *, bus_addr_t);
76fbb0b9
SZ		 151
152static void jme_tick(void *);
153static void jme_stop(struct jme_softc *);
154static void jme_reset(struct jme_softc *);
58880b0d 155static void jme_set_msinum(struct jme_softc *);
76fbb0b9
SZ		 156static void jme_set_vlan(struct jme_softc *);
157static void jme_set_filter(struct jme_softc *);
158static void jme_stop_tx(struct jme_softc *);
159static void jme_stop_rx(struct jme_softc *);
160static void jme_mac_config(struct jme_softc *);
161static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
162static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
163static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
164#ifdef notyet
165static void jme_setwol(struct jme_softc *);
166static void jme_setlinkspeed(struct jme_softc *);
167#endif
2870abc4
SZ		 168static void jme_set_tx_coal(struct jme_softc *);
169static void jme_set_rx_coal(struct jme_softc *);
760c056c
SZ		 170static void jme_enable_rss(struct jme_softc *);
171static void jme_disable_rss(struct jme_softc *);
cccc3955
SZ		 172static void jme_serialize_skipmain(struct jme_softc *);
173static void jme_deserialize_skipmain(struct jme_softc *);
76fbb0b9
SZ		 174
175static void jme_sysctl_node(struct jme_softc *);
2870abc4
SZ		 176static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
177static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
178static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
179static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
8a0620e4
SZ		 180#ifdef IFPOLL_ENABLE
181static int jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
182static int jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
183#endif
76fbb0b9
SZ		 184
185/*
186 * Devices supported by this driver.
187 */
188static const struct jme_dev {
189 uint16_t jme_vendorid;
190 uint16_t jme_deviceid;
3a5f3f36 191 uint32_t jme_caps;
76fbb0b9
SZ		 192 const char *jme_name;
193} jme_devs[] = {
44e8c66c 194 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
3a5f3f36 195 JME_CAP_JUMBO,
76fbb0b9 196 "JMicron Inc, JMC250 Gigabit Ethernet" },
44e8c66c 197 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
3a5f3f36 198 JME_CAP_FASTETH,
76fbb0b9 199 "JMicron Inc, JMC260 Fast Ethernet" },
3a5f3f36 200 { 0, 0, 0, NULL }
76fbb0b9
SZ		 201};
202
203static device_method_t jme_methods[] = {
204 /* Device interface. */
205 DEVMETHOD(device_probe, jme_probe),
206 DEVMETHOD(device_attach, jme_attach),
207 DEVMETHOD(device_detach, jme_detach),
208 DEVMETHOD(device_shutdown, jme_shutdown),
209 DEVMETHOD(device_suspend, jme_suspend),
210 DEVMETHOD(device_resume, jme_resume),
211
212 /* Bus interface. */
213 DEVMETHOD(bus_print_child, bus_generic_print_child),
214 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215
216 /* MII interface. */
217 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
218 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
219 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
220
221 { NULL, NULL }
222};
223
224static driver_t jme_driver = {
225 "jme",
226 jme_methods,
227 sizeof(struct jme_softc)
228};
229
230static devclass_t jme_devclass;
231
232DECLARE_DUMMY_MODULE(if_jme);
233MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
aa2b9d05
SW		 234DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
235DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
76fbb0b9 236
4447c752
SZ		 237static const struct {
238 uint32_t jme_coal;
239 uint32_t jme_comp;
58880b0d 240 uint32_t jme_empty;
4447c752 241} jme_rx_status[JME_NRXRING_MAX] = {
58880b0d
SZ		 242 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
243 INTR_RXQ0_DESC_EMPTY },
244 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
245 INTR_RXQ1_DESC_EMPTY },
246 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
247 INTR_RXQ2_DESC_EMPTY },
248 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
249 INTR_RXQ3_DESC_EMPTY }
4447c752
SZ		 250};
251
69325526
SZ		 252static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
253static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
6afef6ab 254static int jme_rx_ring_count = 0;
3eba890a 255static int jme_msi_enable = 1;
58880b0d 256static int jme_msix_enable = 1;
83b03786
SZ		 257
258TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
259TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
413d06bb 260TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
3eba890a 261TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
58880b0d 262TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
83b03786 263
fd2a6d2c
SZ		 264static __inline void
265jme_setup_rxdesc(struct jme_rxdesc *rxd)
266{
267 struct jme_desc *desc;
268
269 desc = rxd->rx_desc;
270 desc->buflen = htole32(MCLBYTES);
271 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
272 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
273 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
274}
275
76fbb0b9
SZ		 276/*
277 * Read a PHY register on the MII of the JMC250.
278 */
279static int
280jme_miibus_readreg(device_t dev, int phy, int reg)
281{
282 struct jme_softc *sc = device_get_softc(dev);
283 uint32_t val;
284 int i;
285
286 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 287 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ		 288 if (phy == 0)
289 return (0);
290 } else {
291 if (sc->jme_phyaddr != phy)
292 return (0);
293 }
294
295 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
296 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
297
298 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
299 DELAY(1);
300 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
301 break;
302 }
303 if (i == 0) {
304 device_printf(sc->jme_dev, "phy read timeout: "
305 "phy %d, reg %d\n", phy, reg);
306 return (0);
307 }
308
309 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
310}
311
312/*
313 * Write a PHY register on the MII of the JMC250.
314 */
315static int
316jme_miibus_writereg(device_t dev, int phy, int reg, int val)
317{
318 struct jme_softc *sc = device_get_softc(dev);
319 int i;
320
321 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 322 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ		 323 if (phy == 0)
324 return (0);
325 } else {
326 if (sc->jme_phyaddr != phy)
327 return (0);
328 }
329
330 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
331 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
332 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
333
334 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
335 DELAY(1);
336 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
337 break;
338 }
339 if (i == 0) {
340 device_printf(sc->jme_dev, "phy write timeout: "
341 "phy %d, reg %d\n", phy, reg);
342 }
343
344 return (0);
345}
346
347/*
348 * Callback from MII layer when media changes.
349 */
350static void
351jme_miibus_statchg(device_t dev)
352{
353 struct jme_softc *sc = device_get_softc(dev);
354 struct ifnet *ifp = &sc->arpcom.ac_if;
9b99c84f 355 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ		 356 struct mii_data *mii;
357 struct jme_txdesc *txd;
358 bus_addr_t paddr;
4447c752 359 int i, r;
76fbb0b9 360
cccc3955
SZ		 361 if (sc->jme_in_tick)
362 jme_serialize_skipmain(sc);
31f0d5a2 363 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 364
365 if ((ifp->if_flags & IFF_RUNNING) == 0)
cccc3955 366 goto done;
76fbb0b9
SZ		 367
368 mii = device_get_softc(sc->jme_miibus);
369
cccc3955 370 sc->jme_has_link = FALSE;
76fbb0b9
SZ		 371 if ((mii->mii_media_status & IFM_AVALID) != 0) {
372 switch (IFM_SUBTYPE(mii->mii_media_active)) {
373 case IFM_10_T:
374 case IFM_100_TX:
cccc3955 375 sc->jme_has_link = TRUE;
76fbb0b9
SZ		 376 break;
377 case IFM_1000_T:
ec7e787b 378 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 379 break;
cccc3955 380 sc->jme_has_link = TRUE;
76fbb0b9
SZ		 381 break;
382 default:
383 break;
384 }
385 }
386
387 /*
388 * Disabling Rx/Tx MACs have a side-effect of resetting
389 * JME_TXNDA/JME_RXNDA register to the first address of
390 * Tx/Rx descriptor address. So driver should reset its
391 * internal procucer/consumer pointer and reclaim any
392 * allocated resources. Note, just saving the value of
393 * JME_TXNDA and JME_RXNDA registers before stopping MAC
394 * and restoring JME_TXNDA/JME_RXNDA register is not
395 * sufficient to make sure correct MAC state because
396 * stopping MAC operation can take a while and hardware
397 * might have updated JME_TXNDA/JME_RXNDA registers
398 * during the stop operation.
399 */
400
401 /* Disable interrupts */
402 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
403
404 /* Stop driver */
405 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
406 ifp->if_timer = 0;
407 callout_stop(&sc->jme_tick_ch);
408
409 /* Stop receiver/transmitter. */
410 jme_stop_rx(sc);
411 jme_stop_tx(sc);
412
7b040092 413 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 414 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
415
dea2452a 416 jme_rxeof(rdata, -1);
4447c752
SZ		 417 if (rdata->jme_rxhead != NULL)
418 m_freem(rdata->jme_rxhead);
dea2452a 419 JME_RXCHAIN_RESET(rdata);
4447c752
SZ		 420
421 /*
422 * Reuse configured Rx descriptors and reset
423 * procuder/consumer index.
424 */
425 rdata->jme_rx_cons = 0;
426 }
6afef6ab 427 if (JME_ENABLE_HWRSS(sc))
deaeb5a5
SZ		 428 jme_enable_rss(sc);
429 else
430 jme_disable_rss(sc);
76fbb0b9 431
9b99c84f
SZ		 432 jme_txeof(tdata);
433 if (tdata->jme_tx_cnt != 0) {
76fbb0b9 434 /* Remove queued packets for transmit. */
9b99c84f
SZ		 435 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
436 txd = &tdata->jme_txdesc[i];
76fbb0b9 437 if (txd->tx_m != NULL) {
9b99c84f 438 bus_dmamap_unload( tdata->jme_tx_tag,
76fbb0b9
SZ		 439 txd->tx_dmamap);
440 m_freem(txd->tx_m);
441 txd->tx_m = NULL;
442 txd->tx_ndesc = 0;
443 ifp->if_oerrors++;
444 }
445 }
446 }
9b99c84f 447 jme_init_tx_ring(tdata);
76fbb0b9
SZ		 448
449 /* Initialize shadow status block. */
450 jme_init_ssb(sc);
451
452 /* Program MAC with resolved speed/duplex/flow-control. */
cccc3955 453 if (sc->jme_has_link) {
76fbb0b9
SZ		 454 jme_mac_config(sc);
455
76fbb0b9
SZ		 456 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
457
458 /* Set Tx ring address to the hardware. */
9b99c84f 459 paddr = tdata->jme_tx_ring_paddr;
76fbb0b9
SZ		 460 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
461 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
462
7b040092 463 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 464 CSR_WRITE_4(sc, JME_RXCSR,
465 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
466
467 /* Set Rx ring address to the hardware. */
468 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
469 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
470 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
471 }
76fbb0b9
SZ		 472
473 /* Restart receiver/transmitter. */
474 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
475 RXCSR_RXQ_START);
476 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
477 }
478
479 ifp->if_flags |= IFF_RUNNING;
480 ifp->if_flags &= ~IFF_OACTIVE;
481 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
482
8a0620e4
SZ		 483#ifdef IFPOLL_ENABLE
484 if (!(ifp->if_flags & IFF_NPOLLING))
9de40864 485#endif
76fbb0b9
SZ		 486 /* Reenable interrupts. */
487 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
cccc3955
SZ		 488
489done:
490 if (sc->jme_in_tick)
491 jme_deserialize_skipmain(sc);
76fbb0b9
SZ		 492}
493
494/*
495 * Get the current interface media status.
496 */
497static void
498jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
499{
500 struct jme_softc *sc = ifp->if_softc;
501 struct mii_data *mii = device_get_softc(sc->jme_miibus);
502
31f0d5a2 503 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 504
505 mii_pollstat(mii);
506 ifmr->ifm_status = mii->mii_media_status;
507 ifmr->ifm_active = mii->mii_media_active;
508}
509
510/*
511 * Set hardware to newly-selected media.
512 */
513static int
514jme_mediachange(struct ifnet *ifp)
515{
516 struct jme_softc *sc = ifp->if_softc;
517 struct mii_data *mii = device_get_softc(sc->jme_miibus);
518 int error;
519
31f0d5a2 520 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 521
522 if (mii->mii_instance != 0) {
523 struct mii_softc *miisc;
524
525 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
526 mii_phy_reset(miisc);
527 }
528 error = mii_mediachg(mii);
529
530 return (error);
531}
532
533static int
534jme_probe(device_t dev)
535{
536 const struct jme_dev *sp;
537 uint16_t vid, did;
538
539 vid = pci_get_vendor(dev);
540 did = pci_get_device(dev);
541 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
542 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
3a5f3f36
SZ		 543 struct jme_softc *sc = device_get_softc(dev);
544
545 sc->jme_caps = sp->jme_caps;
76fbb0b9 546 device_set_desc(dev, sp->jme_name);
76fbb0b9
SZ		 547 return (0);
548 }
549 }
550 return (ENXIO);
551}
552
553static int
554jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
555{
556 uint32_t reg;
557 int i;
558
559 *val = 0;
560 for (i = JME_TIMEOUT; i > 0; i--) {
561 reg = CSR_READ_4(sc, JME_SMBCSR);
562 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
563 break;
564 DELAY(1);
565 }
566
567 if (i == 0) {
568 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
569 return (ETIMEDOUT);
570 }
571
572 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
573 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
574 for (i = JME_TIMEOUT; i > 0; i--) {
575 DELAY(1);
576 reg = CSR_READ_4(sc, JME_SMBINTF);
577 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
578 break;
579 }
580
581 if (i == 0) {
582 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
583 return (ETIMEDOUT);
584 }
585
586 reg = CSR_READ_4(sc, JME_SMBINTF);
587 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
588
589 return (0);
590}
591
592static int
593jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
594{
595 uint8_t fup, reg, val;
596 uint32_t offset;
597 int match;
598
599 offset = 0;
600 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
601 fup != JME_EEPROM_SIG0)
602 return (ENOENT);
603 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
604 fup != JME_EEPROM_SIG1)
605 return (ENOENT);
606 match = 0;
607 do {
608 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
609 break;
09927fe6
SZ		 610 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
611 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
76fbb0b9
SZ		 612 if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
613 break;
614 if (reg >= JME_PAR0 &&
615 reg < JME_PAR0 + ETHER_ADDR_LEN) {
616 if (jme_eeprom_read_byte(sc, offset + 2,
617 &val) != 0)
618 break;
619 eaddr[reg - JME_PAR0] = val;
620 match++;
621 }
622 }
09927fe6
SZ		 623 /* Check for the end of EEPROM descriptor. */
624 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
625 break;
76fbb0b9
SZ		 626 /* Try next eeprom descriptor. */
627 offset += JME_EEPROM_DESC_BYTES;
628 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
629
630 if (match == ETHER_ADDR_LEN)
631 return (0);
632
633 return (ENOENT);
634}
635
636static void
637jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
638{
639 uint32_t par0, par1;
640
641 /* Read station address. */
642 par0 = CSR_READ_4(sc, JME_PAR0);
643 par1 = CSR_READ_4(sc, JME_PAR1);
644 par1 &= 0xFFFF;
645 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
646 device_printf(sc->jme_dev,
647 "generating fake ethernet address.\n");
648 par0 = karc4random();
649 /* Set OUI to JMicron. */
650 eaddr[0] = 0x00;
651 eaddr[1] = 0x1B;
652 eaddr[2] = 0x8C;
653 eaddr[3] = (par0 >> 16) & 0xff;
654 eaddr[4] = (par0 >> 8) & 0xff;
655 eaddr[5] = par0 & 0xff;
656 } else {
657 eaddr[0] = (par0 >> 0) & 0xFF;
658 eaddr[1] = (par0 >> 8) & 0xFF;
659 eaddr[2] = (par0 >> 16) & 0xFF;
660 eaddr[3] = (par0 >> 24) & 0xFF;
661 eaddr[4] = (par1 >> 0) & 0xFF;
662 eaddr[5] = (par1 >> 8) & 0xFF;
663 }
664}
665
666static int
667jme_attach(device_t dev)
668{
669 struct jme_softc *sc = device_get_softc(dev);
670 struct ifnet *ifp = &sc->arpcom.ac_if;
671 uint32_t reg;
b249905b
SZ		 672 uint16_t did;
673 uint8_t pcie_ptr, rev;
a3fede62 674 int error = 0, i, j, rx_desc_cnt, coal_max;
76fbb0b9 675 uint8_t eaddr[ETHER_ADDR_LEN];
8a0620e4
SZ		 676#ifdef IFPOLL_ENABLE
677 int offset, offset_def;
678#endif
76fbb0b9 679
9b99c84f
SZ		 680 /*
681 * Initialize serializers
682 */
31f0d5a2 683 lwkt_serialize_init(&sc->jme_serialize);
9b99c84f 684 lwkt_serialize_init(&sc->jme_cdata.jme_tx_data.jme_tx_serialize);
31f0d5a2
SZ		 685 for (i = 0; i < JME_NRXRING_MAX; ++i) {
686 lwkt_serialize_init(
687 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
688 }
689
9b99c84f
SZ		 690 /*
691 * Get # of RX ring descriptors
692 */
7b040092 693 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
1cc217a9 694 jme_rx_desc_count);
7b040092
SZ		 695 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
696 if (rx_desc_cnt > JME_NDESC_MAX)
697 rx_desc_cnt = JME_NDESC_MAX;
69325526 698
9b99c84f
SZ		 699 /*
700 * Get # of TX ring descriptors
701 */
702 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt =
703 device_getenv_int(dev, "tx_desc_count", jme_tx_desc_count);
704 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt =
705 roundup(sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, JME_NDESC_ALIGN);
706 if (sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt > JME_NDESC_MAX)
707 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = JME_NDESC_MAX;
83b03786 708
9389fe19 709 /*
9b99c84f 710 * Get # of RX rings
9389fe19 711 */
7b040092 712 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
1cc217a9 713 jme_rx_ring_count);
7b040092
SZ		 714 sc->jme_cdata.jme_rx_ring_cnt =
715 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
4447c752 716
9b99c84f
SZ		 717 /*
718 * Initialize serializer array
719 */
31f0d5a2
SZ		 720 i = 0;
721 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
29890f78
SZ		 722
723 KKASSERT(i == JME_TX_SERIALIZE);
9b99c84f
SZ		 724 sc->jme_serialize_arr[i++] =
725 &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
29890f78
SZ		 726
727 KKASSERT(i == JME_RX_SERIALIZE);
7b040092 728 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
31f0d5a2
SZ		 729 sc->jme_serialize_arr[i++] =
730 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
731 }
732 KKASSERT(i <= JME_NSERIALIZE);
733 sc->jme_serialize_cnt = i;
734
9b99c84f
SZ		 735 /*
736 * Setup TX ring specific data
737 */
738 sc->jme_cdata.jme_tx_data.jme_sc = sc;
739
740 /*
741 * Setup RX rings specific data
742 */
7b040092 743 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
58880b0d
SZ		 744 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
745
746 rdata->jme_sc = sc;
747 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
748 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
749 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
750 rdata->jme_rx_idx = i;
7b040092 751 rdata->jme_rx_desc_cnt = rx_desc_cnt;
58880b0d
SZ		 752 }
753
76fbb0b9 754 sc->jme_dev = dev;
b249905b
SZ		 755 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
756
76fbb0b9
SZ		 757 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
758
759 callout_init(&sc->jme_tick_ch);
760
761#ifndef BURN_BRIDGES
762 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
763 uint32_t irq, mem;
764
765 irq = pci_read_config(dev, PCIR_INTLINE, 4);
766 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
767
768 device_printf(dev, "chip is in D%d power mode "
769 "-- setting to D0\n", pci_get_powerstate(dev));
770
771 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
772
773 pci_write_config(dev, PCIR_INTLINE, irq, 4);
774 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
775 }
776#endif /* !BURN_BRIDGE */
777
778 /* Enable bus mastering */
779 pci_enable_busmaster(dev);
780
781 /*
782 * Allocate IO memory
783 *
784 * JMC250 supports both memory mapped and I/O register space
785 * access. Because I/O register access should use different
786 * BARs to access registers it's waste of time to use I/O
787 * register spce access. JMC250 uses 16K to map entire memory
788 * space.
789 */
790 sc->jme_mem_rid = JME_PCIR_BAR;
791 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
792 &sc->jme_mem_rid, RF_ACTIVE);
793 if (sc->jme_mem_res == NULL) {
794 device_printf(dev, "can't allocate IO memory\n");
795 return ENXIO;
796 }
797 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
798 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
799
800 /*
801 * Allocate IRQ
802 */
58880b0d
SZ		 803 error = jme_intr_alloc(dev);
804 if (error)
76fbb0b9 805 goto fail;
76fbb0b9
SZ		 806
807 /*
b249905b 808 * Extract revisions
76fbb0b9
SZ		 809 */
810 reg = CSR_READ_4(sc, JME_CHIPMODE);
811 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
812 CHIPMODE_NOT_FPGA) {
ec7e787b 813 sc->jme_caps |= JME_CAP_FPGA;
76fbb0b9 814 if (bootverbose) {
b249905b 815 device_printf(dev, "FPGA revision: 0x%04x\n",
76fbb0b9
SZ		 816 (reg & CHIPMODE_FPGA_REV_MASK) >>
817 CHIPMODE_FPGA_REV_SHIFT);
818 }
819 }
820
b249905b
SZ		 821 /* NOTE: FM revision is put in the upper 4 bits */
822 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
823 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
824 if (bootverbose)
825 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
826
827 did = pci_get_device(dev);
828 switch (did) {
829 case PCI_PRODUCT_JMICRON_JMC250:
830 if (rev == JME_REV1_A2)
831 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
832 break;
833
834 case PCI_PRODUCT_JMICRON_JMC260:
835 if (rev == JME_REV2)
836 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
837 break;
838
839 default:
ed20d0e3 840 panic("unknown device id 0x%04x", did);
b249905b
SZ		 841 }
842 if (rev >= JME_REV2) {
843 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
844 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
845 GHC_TXMAC_CLKSRC_1000;
846 }
847
76fbb0b9
SZ		 848 /* Reset the ethernet controller. */
849 jme_reset(sc);
850
58880b0d
SZ		 851 /* Map MSI/MSI-X vectors */
852 jme_set_msinum(sc);
853
76fbb0b9
SZ		 854 /* Get station address. */
855 reg = CSR_READ_4(sc, JME_SMBCSR);
856 if (reg & SMBCSR_EEPROM_PRESENT)
857 error = jme_eeprom_macaddr(sc, eaddr);
858 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
859 if (error != 0 && (bootverbose)) {
860 device_printf(dev, "ethernet hardware address "
861 "not found in EEPROM.\n");
862 }
863 jme_reg_macaddr(sc, eaddr);
864 }
865
866 /*
867 * Save PHY address.
868 * Integrated JR0211 has fixed PHY address whereas FPGA version
869 * requires PHY probing to get correct PHY address.
870 */
ec7e787b 871 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
76fbb0b9
SZ		 872 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
873 GPREG0_PHY_ADDR_MASK;
874 if (bootverbose) {
875 device_printf(dev, "PHY is at address %d.\n",
876 sc->jme_phyaddr);
877 }
878 } else {
879 sc->jme_phyaddr = 0;
880 }
881
882 /* Set max allowable DMA size. */
883 pcie_ptr = pci_get_pciecap_ptr(dev);
884 if (pcie_ptr != 0) {
885 uint16_t ctrl;
886
ec7e787b 887 sc->jme_caps |= JME_CAP_PCIE;
76fbb0b9
SZ		 888 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
889 if (bootverbose) {
890 device_printf(dev, "Read request size : %d bytes.\n",
891 128 << ((ctrl >> 12) & 0x07));
892 device_printf(dev, "TLP payload size : %d bytes.\n",
893 128 << ((ctrl >> 5) & 0x07));
894 }
895 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
896 case PCIEM_DEVCTL_MAX_READRQ_128:
897 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
898 break;
899 case PCIEM_DEVCTL_MAX_READRQ_256:
900 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
901 break;
902 default:
903 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
904 break;
905 }
906 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
907 } else {
908 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
909 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
910 }
911
912#ifdef notyet
913 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
ec7e787b 914 sc->jme_caps |= JME_CAP_PMCAP;
76fbb0b9
SZ		 915#endif
916
8a0620e4
SZ		 917#ifdef IFPOLL_ENABLE
918 /*
919 * NPOLLING RX CPU offset
920 */
921 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
922 offset = 0;
923 } else {
924 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
925 device_get_unit(dev)) % ncpus2;
926 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
927 if (offset >= ncpus2 ||
928 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
929 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
930 offset, offset_def);
931 offset = offset_def;
932 }
933 }
934 sc->jme_npoll_rxoff = offset;
935
936 /*
937 * NPOLLING TX CPU offset
938 */
939 offset_def = sc->jme_npoll_rxoff;
940 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
941 if (offset >= ncpus2) {
942 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
943 offset, offset_def);
944 offset = offset_def;
945 }
946 sc->jme_npoll_txoff = offset;
947#endif
948
76fbb0b9 949 /*
a3fede62
SZ		 950 * Set default coalesce valves
951 */
952 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
953 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
954 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
955 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
956
957 /*
958 * Adjust coalesce valves, in case that the number of TX/RX
959 * descs are set to small values by users.
960 *
961 * NOTE: coal_max will not be zero, since number of descs
962 * must aligned by JME_NDESC_ALIGN (16 currently)
963 */
9b99c84f 964 coal_max = sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt / 2;
a3fede62
SZ		 965 if (coal_max < sc->jme_tx_coal_pkt)
966 sc->jme_tx_coal_pkt = coal_max;
967
968 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2;
969 if (coal_max < sc->jme_rx_coal_pkt)
970 sc->jme_rx_coal_pkt = coal_max;
971
972 /*
76fbb0b9
SZ		 973 * Create sysctl tree
974 */
975 jme_sysctl_node(sc);
976
977 /* Allocate DMA stuffs */
978 error = jme_dma_alloc(sc);
979 if (error)
980 goto fail;
981
982 ifp->if_softc = sc;
983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
984 ifp->if_init = jme_init;
985 ifp->if_ioctl = jme_ioctl;
986 ifp->if_start = jme_start;
8a0620e4
SZ		 987#ifdef IFPOLL_ENABLE
988 ifp->if_npoll = jme_npoll;
9de40864 989#endif
76fbb0b9 990 ifp->if_watchdog = jme_watchdog;
31f0d5a2
SZ		 991 ifp->if_serialize = jme_serialize;
992 ifp->if_deserialize = jme_deserialize;
993 ifp->if_tryserialize = jme_tryserialize;
994#ifdef INVARIANTS
995 ifp->if_serialize_assert = jme_serialize_assert;
996#endif
b020bb10 997 ifq_set_maxlen(&ifp->if_snd,
9b99c84f 998 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt - JME_TXD_RSVD);
76fbb0b9
SZ		 999 ifq_set_ready(&ifp->if_snd);
1000
1001 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
1002 ifp->if_capabilities = IFCAP_HWCSUM |
1bedd927 1003 IFCAP_TSO |
76fbb0b9
SZ		 1004 IFCAP_VLAN_MTU |
1005 IFCAP_VLAN_HWTAGGING;
7b040092 1006 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
d585233c 1007 ifp->if_capabilities |= IFCAP_RSS;
76fbb0b9
SZ		 1008 ifp->if_capenable = ifp->if_capabilities;
1009
3d2aeb15
SZ		 1010 /*
1011 * Disable TXCSUM by default to improve bulk data
1012 * transmit performance (+20Mbps improvement).
1013 */
1014 ifp->if_capenable &= ~IFCAP_TXCSUM;
1015
1016 if (ifp->if_capenable & IFCAP_TXCSUM)
1bedd927
SZ		 1017 ifp->if_hwassist |= JME_CSUM_FEATURES;
1018 ifp->if_hwassist |= CSUM_TSO;
3d2aeb15 1019
76fbb0b9
SZ		 1020 /* Set up MII bus. */
1021 error = mii_phy_probe(dev, &sc->jme_miibus,
1022 jme_mediachange, jme_mediastatus);
1023 if (error) {
1024 device_printf(dev, "no PHY found!\n");
1025 goto fail;
1026 }
1027
1028 /*
1029 * Save PHYADDR for FPGA mode PHY.
1030 */
ec7e787b 1031 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ		 1032 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1033
1034 if (mii->mii_instance != 0) {
1035 struct mii_softc *miisc;
1036
1037 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1038 if (miisc->mii_phy != 0) {
1039 sc->jme_phyaddr = miisc->mii_phy;
1040 break;
1041 }
1042 }
1043 if (sc->jme_phyaddr != 0) {
1044 device_printf(sc->jme_dev,
1045 "FPGA PHY is at %d\n", sc->jme_phyaddr);
1046 /* vendor magic. */
dbe37f03
SZ		 1047 jme_miibus_writereg(dev, sc->jme_phyaddr,
1048 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
1049
ad22907f 1050 /* XXX should we clear JME_WA_EXTFIFO */
76fbb0b9
SZ		 1051 }
1052 }
1053 }
1054
1055 ether_ifattach(ifp, eaddr, NULL);
1056
1057 /* Tell the upper layer(s) we support long frames. */
1058 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1059
58880b0d 1060 error = jme_intr_setup(dev);
76fbb0b9 1061 if (error) {
76fbb0b9
SZ		 1062 ether_ifdetach(ifp);
1063 goto fail;
1064 }
1065
76fbb0b9
SZ		 1066 return 0;
1067fail:
1068 jme_detach(dev);
1069 return (error);
1070}
1071
1072static int
1073jme_detach(device_t dev)
1074{
1075 struct jme_softc *sc = device_get_softc(dev);
1076
1077 if (device_is_attached(dev)) {
1078 struct ifnet *ifp = &sc->arpcom.ac_if;
1079
31f0d5a2 1080 ifnet_serialize_all(ifp);
76fbb0b9 1081 jme_stop(sc);
58880b0d 1082 jme_intr_teardown(dev);
31f0d5a2 1083 ifnet_deserialize_all(ifp);
76fbb0b9
SZ		 1084
1085 ether_ifdetach(ifp);
1086 }
1087
1088 if (sc->jme_sysctl_tree != NULL)
1089 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1090
1091 if (sc->jme_miibus != NULL)
1092 device_delete_child(dev, sc->jme_miibus);
1093 bus_generic_detach(dev);
1094
58880b0d 1095 jme_intr_free(dev);
76fbb0b9
SZ		 1096
1097 if (sc->jme_mem_res != NULL) {
1098 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1099 sc->jme_mem_res);
1100 }
1101
0b3414d9 1102 jme_dma_free(sc);
76fbb0b9
SZ		 1103
1104 return (0);
1105}
1106
1107static void
1108jme_sysctl_node(struct jme_softc *sc)
1109{
760c056c 1110#ifdef JME_RSS_DEBUG
760c056c
SZ		 1111 int r;
1112#endif
83b03786 1113
76fbb0b9
SZ		 1114 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1115 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1116 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1117 device_get_nameunit(sc->jme_dev),
1118 CTLFLAG_RD, 0, "");
1119 if (sc->jme_sysctl_tree == NULL) {
1120 device_printf(sc->jme_dev, "can't add sysctl node\n");
1121 return;
1122 }
1123
1124 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1125 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1126 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1127 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
76fbb0b9
SZ		 1128
1129 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1130 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1131 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1132 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
76fbb0b9
SZ		 1133
1134 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1135 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1136 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1137 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
76fbb0b9
SZ		 1138
1139 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1140 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ		 1141 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1142 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
76fbb0b9 1143
83b03786
SZ		 1144 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1145 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ		 1146 "rx_desc_count", CTLFLAG_RD,
1147 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
83b03786
SZ		 1148 0, "RX desc count");
1149 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1150 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
b020bb10 1151 "tx_desc_count", CTLFLAG_RD,
9b99c84f 1152 &sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt,
83b03786 1153 0, "TX desc count");
760c056c
SZ		 1154 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1155 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ		 1156 "rx_ring_count", CTLFLAG_RD,
1157 &sc->jme_cdata.jme_rx_ring_cnt,
760c056c 1158 0, "RX ring count");
8a0620e4 1159
760c056c
SZ		 1160#ifdef JME_RSS_DEBUG
1161 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1162 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
24dd1705 1163 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
760c056c 1164 0, "RSS debug level");
7b040092 1165 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
955f266e 1166 char rx_ring_desc[32];
7b040092 1167
955f266e
SZ		 1168 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1169 "rx_ring%d_pkt", r);
7b040092
SZ		 1170 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1171 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
955f266e 1172 rx_ring_desc, CTLFLAG_RW,
7b040092 1173 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
955f266e
SZ		 1174
1175 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1176 "rx_ring%d_emp", r);
1177 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1178 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1179 rx_ring_desc, CTLFLAG_RW,
1180 &sc->jme_cdata.jme_rx_data[r].jme_rx_emp,
1181 "# of time RX ring empty");
760c056c
SZ		 1182 }
1183#endif
83b03786 1184
8a0620e4
SZ		 1185#ifdef IFPOLL_ENABLE
1186 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1187 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1188 "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
1189 jme_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1190 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1191 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1192 "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
1193 jme_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1194#endif
76fbb0b9
SZ		 1195}
1196
76fbb0b9
SZ		 1197static int
1198jme_dma_alloc(struct jme_softc *sc)
1199{
9b99c84f 1200 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9 1201 struct jme_txdesc *txd;
1128a202 1202 bus_dmamem_t dmem;
ff7f3632 1203 int error, i, asize;
76fbb0b9 1204
89f41b28
SZ		 1205 asize = __VM_CACHELINE_ALIGN(
1206 tdata->jme_tx_desc_cnt * sizeof(struct jme_txdesc));
1207 tdata->jme_txdesc = kmalloc_cachealign(asize, M_DEVBUF,
1208 M_WAITOK | M_ZERO);
1209
7b040092
SZ		 1210 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1211 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1212
89f41b28
SZ		 1213 asize = __VM_CACHELINE_ALIGN(
1214 rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc));
1215 rdata->jme_rxdesc = kmalloc_cachealign(asize, M_DEVBUF,
1216 M_WAITOK | M_ZERO);
4447c752 1217 }
83b03786 1218
76fbb0b9
SZ		 1219 /* Create parent ring tag. */
1220 error = bus_dma_tag_create(NULL,/* parent */
a7547dad
SZ		 1221 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1222 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ		 1223 BUS_SPACE_MAXADDR, /* highaddr */
1224 NULL, NULL, /* filter, filterarg */
1225 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1226 0, /* nsegments */
1227 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1228 0, /* flags */
1229 &sc->jme_cdata.jme_ring_tag);
1230 if (error) {
1231 device_printf(sc->jme_dev,
1232 "could not create parent ring DMA tag.\n");
1233 return error;
1234 }
1235
1236 /*
1237 * Create DMA stuffs for TX ring
1238 */
9b99c84f 1239 asize = roundup2(JME_TX_RING_SIZE(tdata), JME_TX_RING_ALIGN);
1128a202
SZ		 1240 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1241 JME_TX_RING_ALIGN, 0,
0eb220ec 1242 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1243 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9 1244 if (error) {
1128a202 1245 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
76fbb0b9
SZ		 1246 return error;
1247 }
9b99c84f
SZ		 1248 tdata->jme_tx_ring_tag = dmem.dmem_tag;
1249 tdata->jme_tx_ring_map = dmem.dmem_map;
1250 tdata->jme_tx_ring = dmem.dmem_addr;
1251 tdata->jme_tx_ring_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ		 1252
1253 /*
1128a202 1254 * Create DMA stuffs for RX rings
76fbb0b9 1255 */
7b040092 1256 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1257 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752
SZ		 1258 if (error)
1259 return error;
76fbb0b9 1260 }
76fbb0b9 1261
76fbb0b9
SZ		 1262 /* Create parent buffer tag. */
1263 error = bus_dma_tag_create(NULL,/* parent */
1264 1, 0, /* algnmnt, boundary */
b249905b 1265 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ		 1266 BUS_SPACE_MAXADDR, /* highaddr */
1267 NULL, NULL, /* filter, filterarg */
1268 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1269 0, /* nsegments */
1270 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1271 0, /* flags */
1272 &sc->jme_cdata.jme_buffer_tag);
1273 if (error) {
1274 device_printf(sc->jme_dev,
1275 "could not create parent buffer DMA tag.\n");
1276 return error;
1277 }
1278
1279 /*
1280 * Create DMA stuffs for shadow status block
1281 */
ff7f3632 1282 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1128a202 1283 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
0eb220ec 1284 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1285 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9
SZ		 1286 if (error) {
1287 device_printf(sc->jme_dev,
1128a202 1288 "could not create shadow status block.\n");
76fbb0b9
SZ		 1289 return error;
1290 }
1128a202
SZ		 1291 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1292 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1293 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1294 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ		 1295
1296 /*
1297 * Create DMA stuffs for TX buffers
1298 */
1299
1300 /* Create tag for Tx buffers. */
1301 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1302 1, 0, /* algnmnt, boundary */
0eb220ec 1303 BUS_SPACE_MAXADDR, /* lowaddr */
76fbb0b9
SZ		 1304 BUS_SPACE_MAXADDR, /* highaddr */
1305 NULL, NULL, /* filter, filterarg */
1bedd927 1306 JME_TSO_MAXSIZE, /* maxsize */
76fbb0b9 1307 JME_MAXTXSEGS, /* nsegments */
9d424cee
SZ		 1308 JME_MAXSEGSIZE, /* maxsegsize */
1309 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
9b99c84f 1310 &tdata->jme_tx_tag);
76fbb0b9
SZ		 1311 if (error != 0) {
1312 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1313 return error;
1314 }
1315
1316 /* Create DMA maps for Tx buffers. */
9b99c84f
SZ		 1317 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
1318 txd = &tdata->jme_txdesc[i];
1319 error = bus_dmamap_create(tdata->jme_tx_tag,
9d424cee
SZ		 1320 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1321 &txd->tx_dmamap);
76fbb0b9
SZ		 1322 if (error) {
1323 int j;
1324
1325 device_printf(sc->jme_dev,
1326 "could not create %dth Tx dmamap.\n", i);
1327
1328 for (j = 0; j < i; ++j) {
9b99c84f
SZ		 1329 txd = &tdata->jme_txdesc[j];
1330 bus_dmamap_destroy(tdata->jme_tx_tag,
76fbb0b9
SZ		 1331 txd->tx_dmamap);
1332 }
9b99c84f
SZ		 1333 bus_dma_tag_destroy(tdata->jme_tx_tag);
1334 tdata->jme_tx_tag = NULL;
76fbb0b9
SZ		 1335 return error;
1336 }
1337 }
1338
1339 /*
1340 * Create DMA stuffs for RX buffers
1341 */
7b040092 1342 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1343 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752 1344 if (error)
76fbb0b9 1345 return error;
76fbb0b9
SZ		 1346 }
1347 return 0;
1348}
1349
1350static void
0b3414d9 1351jme_dma_free(struct jme_softc *sc)
76fbb0b9 1352{
9b99c84f 1353 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ		 1354 struct jme_txdesc *txd;
1355 struct jme_rxdesc *rxd;
4447c752
SZ		 1356 struct jme_rxdata *rdata;
1357 int i, r;
76fbb0b9
SZ		 1358
1359 /* Tx ring */
9b99c84f
SZ		 1360 if (tdata->jme_tx_ring_tag != NULL) {
1361 bus_dmamap_unload(tdata->jme_tx_ring_tag,
1362 tdata->jme_tx_ring_map);
1363 bus_dmamem_free(tdata->jme_tx_ring_tag,
1364 tdata->jme_tx_ring, tdata->jme_tx_ring_map);
1365 bus_dma_tag_destroy(tdata->jme_tx_ring_tag);
1366 tdata->jme_tx_ring_tag = NULL;
76fbb0b9
SZ		 1367 }
1368
1369 /* Rx ring */
7b040092 1370 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 1371 rdata = &sc->jme_cdata.jme_rx_data[r];
1372 if (rdata->jme_rx_ring_tag != NULL) {
1373 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1374 rdata->jme_rx_ring_map);
1375 bus_dmamem_free(rdata->jme_rx_ring_tag,
1376 rdata->jme_rx_ring,
1377 rdata->jme_rx_ring_map);
1378 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1379 rdata->jme_rx_ring_tag = NULL;
1380 }
76fbb0b9
SZ		 1381 }
1382
1383 /* Tx buffers */
9b99c84f
SZ		 1384 if (tdata->jme_tx_tag != NULL) {
1385 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
1386 txd = &tdata->jme_txdesc[i];
1387 bus_dmamap_destroy(tdata->jme_tx_tag, txd->tx_dmamap);
76fbb0b9 1388 }
9b99c84f
SZ		 1389 bus_dma_tag_destroy(tdata->jme_tx_tag);
1390 tdata->jme_tx_tag = NULL;
76fbb0b9
SZ		 1391 }
1392
1393 /* Rx buffers */
7b040092 1394 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 1395 rdata = &sc->jme_cdata.jme_rx_data[r];
1396 if (rdata->jme_rx_tag != NULL) {
7b040092 1397 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ		 1398 rxd = &rdata->jme_rxdesc[i];
1399 bus_dmamap_destroy(rdata->jme_rx_tag,
1400 rxd->rx_dmamap);
1401 }
1402 bus_dmamap_destroy(rdata->jme_rx_tag,
1403 rdata->jme_rx_sparemap);
1404 bus_dma_tag_destroy(rdata->jme_rx_tag);
1405 rdata->jme_rx_tag = NULL;
76fbb0b9 1406 }
76fbb0b9
SZ		 1407 }
1408
1409 /* Shadow status block. */
1410 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1411 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1412 sc->jme_cdata.jme_ssb_map);
1413 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
560616bf 1414 sc->jme_cdata.jme_ssb_block,
76fbb0b9
SZ		 1415 sc->jme_cdata.jme_ssb_map);
1416 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1417 sc->jme_cdata.jme_ssb_tag = NULL;
1418 }
1419
1420 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1421 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1422 sc->jme_cdata.jme_buffer_tag = NULL;
1423 }
1424 if (sc->jme_cdata.jme_ring_tag != NULL) {
1425 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1426 sc->jme_cdata.jme_ring_tag = NULL;
1427 }
83b03786 1428
9b99c84f
SZ		 1429 if (tdata->jme_txdesc != NULL) {
1430 kfree(tdata->jme_txdesc, M_DEVBUF);
1431 tdata->jme_txdesc = NULL;
0b3414d9 1432 }
7b040092 1433 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
0b3414d9
SZ		 1434 rdata = &sc->jme_cdata.jme_rx_data[r];
1435 if (rdata->jme_rxdesc != NULL) {
1436 kfree(rdata->jme_rxdesc, M_DEVBUF);
1437 rdata->jme_rxdesc = NULL;
83b03786
SZ		 1438 }
1439 }
76fbb0b9
SZ		 1440}
1441
1442/*
1443 * Make sure the interface is stopped at reboot time.
1444 */
1445static int
1446jme_shutdown(device_t dev)
1447{
1448 return jme_suspend(dev);
1449}
1450
1451#ifdef notyet
1452/*
1453 * Unlike other ethernet controllers, JMC250 requires
1454 * explicit resetting link speed to 10/100Mbps as gigabit
1455 * link will cunsume more power than 375mA.
1456 * Note, we reset the link speed to 10/100Mbps with
1457 * auto-negotiation but we don't know whether that operation
1458 * would succeed or not as we have no control after powering
1459 * off. If the renegotiation fail WOL may not work. Running
1460 * at 1Gbps draws more power than 375mA at 3.3V which is
1461 * specified in PCI specification and that would result in
1462 * complete shutdowning power to ethernet controller.
1463 *
1464 * TODO
1465 * Save current negotiated media speed/duplex/flow-control
1466 * to softc and restore the same link again after resuming.
1467 * PHY handling such as power down/resetting to 100Mbps
1468 * may be better handled in suspend method in phy driver.
1469 */
1470static void
1471jme_setlinkspeed(struct jme_softc *sc)
1472{
1473 struct mii_data *mii;
1474 int aneg, i;
1475
1476 JME_LOCK_ASSERT(sc);
1477
1478 mii = device_get_softc(sc->jme_miibus);
1479 mii_pollstat(mii);
1480 aneg = 0;
1481 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1482 switch IFM_SUBTYPE(mii->mii_media_active) {
1483 case IFM_10_T:
1484 case IFM_100_TX:
1485 return;
1486 case IFM_1000_T:
1487 aneg++;
1488 default:
1489 break;
1490 }
1491 }
1492 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1493 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1494 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1495 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1496 BMCR_AUTOEN | BMCR_STARTNEG);
1497 DELAY(1000);
1498 if (aneg != 0) {
1499 /* Poll link state until jme(4) get a 10/100 link. */
1500 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1501 mii_pollstat(mii);
1502 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1503 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1504 case IFM_10_T:
1505 case IFM_100_TX:
1506 jme_mac_config(sc);
1507 return;
1508 default:
1509 break;
1510 }
1511 }
1512 JME_UNLOCK(sc);
1513 pause("jmelnk", hz);
1514 JME_LOCK(sc);
1515 }
1516 if (i == MII_ANEGTICKS_GIGE)
1517 device_printf(sc->jme_dev, "establishing link failed, "
1518 "WOL may not work!");
1519 }
1520 /*
1521 * No link, force MAC to have 100Mbps, full-duplex link.
1522 * This is the last resort and may/may not work.
1523 */
1524 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1525 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1526 jme_mac_config(sc);
1527}
1528
1529static void
1530jme_setwol(struct jme_softc *sc)
1531{
1532 struct ifnet *ifp = &sc->arpcom.ac_if;
1533 uint32_t gpr, pmcs;
1534 uint16_t pmstat;
1535 int pmc;
1536
1537 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1538 /* No PME capability, PHY power down. */
1539 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1540 MII_BMCR, BMCR_PDOWN);
1541 return;
1542 }
1543
1544 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1545 pmcs = CSR_READ_4(sc, JME_PMCS);
1546 pmcs &= ~PMCS_WOL_ENB_MASK;
1547 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1548 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1549 /* Enable PME message. */
1550 gpr |= GPREG0_PME_ENB;
1551 /* For gigabit controllers, reset link speed to 10/100. */
ec7e787b 1552 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
76fbb0b9
SZ		 1553 jme_setlinkspeed(sc);
1554 }
1555
1556 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1557 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1558
1559 /* Request PME. */
1560 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1561 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1562 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1563 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1564 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1565 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1566 /* No WOL, PHY power down. */
1567 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1568 MII_BMCR, BMCR_PDOWN);
1569 }
1570}
1571#endif
1572
1573static int
1574jme_suspend(device_t dev)
1575{
1576 struct jme_softc *sc = device_get_softc(dev);
1577 struct ifnet *ifp = &sc->arpcom.ac_if;
1578
31f0d5a2 1579 ifnet_serialize_all(ifp);
76fbb0b9
SZ		 1580 jme_stop(sc);
1581#ifdef notyet
1582 jme_setwol(sc);
1583#endif
31f0d5a2 1584 ifnet_deserialize_all(ifp);
76fbb0b9
SZ		 1585
1586 return (0);
1587}
1588
1589static int
1590jme_resume(device_t dev)
1591{
1592 struct jme_softc *sc = device_get_softc(dev);
1593 struct ifnet *ifp = &sc->arpcom.ac_if;
1594#ifdef notyet
1595 int pmc;
1596#endif
1597
31f0d5a2 1598 ifnet_serialize_all(ifp);
76fbb0b9
SZ		 1599
1600#ifdef notyet
1601 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1602 uint16_t pmstat;
1603
1604 pmstat = pci_read_config(sc->jme_dev,
1605 pmc + PCIR_POWER_STATUS, 2);
1606 /* Disable PME clear PME status. */
1607 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1608 pci_write_config(sc->jme_dev,
1609 pmc + PCIR_POWER_STATUS, pmstat, 2);
1610 }
1611#endif
1612
1613 if (ifp->if_flags & IFF_UP)
1614 jme_init(sc);
1615
31f0d5a2 1616 ifnet_deserialize_all(ifp);
76fbb0b9
SZ		 1617
1618 return (0);
1619}
1620
1bedd927
SZ		 1621static __inline int
1622jme_tso_pullup(struct mbuf **mp)
1623{
1624 int hoff, iphlen, thoff;
1625 struct mbuf *m;
1626
1627 m = *mp;
1628 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1629
1630 iphlen = m->m_pkthdr.csum_iphlen;
1631 thoff = m->m_pkthdr.csum_thlen;
1632 hoff = m->m_pkthdr.csum_lhlen;
1633
1634 KASSERT(iphlen > 0, ("invalid ip hlen"));
1635 KASSERT(thoff > 0, ("invalid tcp hlen"));
1636 KASSERT(hoff > 0, ("invalid ether hlen"));
1637
1638 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1639 m = m_pullup(m, hoff + iphlen + thoff);
1640 if (m == NULL) {
1641 *mp = NULL;
1642 return ENOBUFS;
1643 }
1644 *mp = m;
1645 }
1646 return 0;
1647}
1648
76fbb0b9 1649static int
9b99c84f 1650jme_encap(struct jme_txdata *tdata, struct mbuf **m_head)
76fbb0b9
SZ		 1651{
1652 struct jme_txdesc *txd;
1653 struct jme_desc *desc;
1654 struct mbuf *m;
76fbb0b9 1655 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
b0ba1747 1656 int maxsegs, nsegs;
9b3ee148 1657 int error, i, prod, symbol_desc;
1bedd927 1658 uint32_t cflags, flag64, mss;
76fbb0b9
SZ		 1659
1660 M_ASSERTPKTHDR((*m_head));
1661
1bedd927
SZ		 1662 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) {
1663 /* XXX Is this necessary? */
1664 error = jme_tso_pullup(m_head);
1665 if (error)
1666 return error;
1667 }
1668
9b99c84f
SZ		 1669 prod = tdata->jme_tx_prod;
1670 txd = &tdata->jme_txdesc[prod];
76fbb0b9 1671
9b99c84f 1672 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
9b3ee148
SZ		 1673 symbol_desc = 1;
1674 else
1675 symbol_desc = 0;
1676
9b99c84f 1677 maxsegs = (tdata->jme_tx_desc_cnt - tdata->jme_tx_cnt) -
9b3ee148 1678 (JME_TXD_RSVD + symbol_desc);
76fbb0b9
SZ		 1679 if (maxsegs > JME_MAXTXSEGS)
1680 maxsegs = JME_MAXTXSEGS;
1bedd927 1681 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc),
ed20d0e3 1682 ("not enough segments %d", maxsegs));
76fbb0b9 1683
9b99c84f 1684 error = bus_dmamap_load_mbuf_defrag(tdata->jme_tx_tag,
b0ba1747
SZ		 1685 txd->tx_dmamap, m_head,
1686 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1687 if (error)
ecc6de9e 1688 goto fail;
76fbb0b9 1689
9b99c84f 1690 bus_dmamap_sync(tdata->jme_tx_tag, txd->tx_dmamap,
4458ee95
SZ		 1691 BUS_DMASYNC_PREWRITE);
1692
76fbb0b9
SZ		 1693 m = *m_head;
1694 cflags = 0;
1bedd927 1695 mss = 0;
76fbb0b9
SZ		 1696
1697 /* Configure checksum offload. */
1bedd927
SZ		 1698 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1699 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT;
1700 cflags |= JME_TD_TSO;
1701 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) {
1702 if (m->m_pkthdr.csum_flags & CSUM_IP)
1703 cflags |= JME_TD_IPCSUM;
1704 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1705 cflags |= JME_TD_TCPCSUM;
1706 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1707 cflags |= JME_TD_UDPCSUM;
1708 }
76fbb0b9
SZ		 1709
1710 /* Configure VLAN. */
1711 if (m->m_flags & M_VLANTAG) {
1712 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1713 cflags |= JME_TD_VLAN_TAG;
1714 }
1715
9b99c84f 1716 desc = &tdata->jme_tx_ring[prod];
76fbb0b9 1717 desc->flags = htole32(cflags);
76fbb0b9 1718 desc->addr_hi = htole32(m->m_pkthdr.len);
9b99c84f 1719 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
7228f061
SZ		 1720 /*
1721 * Use 64bits TX desc chain format.
1722 *
1723 * The first TX desc of the chain, which is setup here,
1724 * is just a symbol TX desc carrying no payload.
1725 */
1726 flag64 = JME_TD_64BIT;
1bedd927 1727 desc->buflen = htole32(mss);
7228f061
SZ		 1728 desc->addr_lo = 0;
1729
1730 /* No effective TX desc is consumed */
1731 i = 0;
1732 } else {
1733 /*
1734 * Use 32bits TX desc chain format.
1735 *
1736 * The first TX desc of the chain, which is setup here,
1737 * is an effective TX desc carrying the first segment of
1738 * the mbuf chain.
1739 */
1740 flag64 = 0;
1bedd927 1741 desc->buflen = htole32(mss | txsegs[0].ds_len);
7228f061
SZ		 1742 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1743
1744 /* One effective TX desc is consumed */
1745 i = 1;
1746 }
9b99c84f
SZ		 1747 tdata->jme_tx_cnt++;
1748 KKASSERT(tdata->jme_tx_cnt - i < tdata->jme_tx_desc_cnt - JME_TXD_RSVD);
1749 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt);
7228f061
SZ		 1750
1751 txd->tx_ndesc = 1 - i;
b0ba1747 1752 for (; i < nsegs; i++) {
9b99c84f 1753 desc = &tdata->jme_tx_ring[prod];
76fbb0b9
SZ		 1754 desc->buflen = htole32(txsegs[i].ds_len);
1755 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1756 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
a54bd021 1757 desc->flags = htole32(JME_TD_OWN | flag64);
76fbb0b9 1758
9b99c84f
SZ		 1759 tdata->jme_tx_cnt++;
1760 KKASSERT(tdata->jme_tx_cnt <=
1761 tdata->jme_tx_desc_cnt - JME_TXD_RSVD);
1762 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt);
76fbb0b9
SZ		 1763 }
1764
1765 /* Update producer index. */
9b99c84f 1766 tdata->jme_tx_prod = prod;
76fbb0b9
SZ		 1767 /*
1768 * Finally request interrupt and give the first descriptor
1769 * owenership to hardware.
1770 */
1771 desc = txd->tx_desc;
1772 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1773
1774 txd->tx_m = m;
b0ba1747 1775 txd->tx_ndesc += nsegs;
76fbb0b9 1776
ecc6de9e
SZ		 1777 return 0;
1778fail:
1779 m_freem(*m_head);
1780 *m_head = NULL;
1781 return error;
76fbb0b9
SZ		 1782}
1783
1784static void
1785jme_start(struct ifnet *ifp)
1786{
1787 struct jme_softc *sc = ifp->if_softc;
9b99c84f 1788 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ		 1789 struct mbuf *m_head;
1790 int enq = 0;
1791
9b99c84f 1792 ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
76fbb0b9 1793
cccc3955 1794 if (!sc->jme_has_link) {
76fbb0b9
SZ		 1795 ifq_purge(&ifp->if_snd);
1796 return;
1797 }
1798
1799 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1800 return;
1801
9b99c84f
SZ		 1802 if (tdata->jme_tx_cnt >= JME_TX_DESC_HIWAT(tdata))
1803 jme_txeof(tdata);
76fbb0b9
SZ		 1804
1805 while (!ifq_is_empty(&ifp->if_snd)) {
1806 /*
1807 * Check number of available TX descs, always
1808 * leave JME_TXD_RSVD free TX descs.
1809 */
9b99c84f
SZ		 1810 if (tdata->jme_tx_cnt + JME_TXD_SPARE >
1811 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) {
76fbb0b9
SZ		 1812 ifp->if_flags |= IFF_OACTIVE;
1813 break;
1814 }
1815
1816 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1817 if (m_head == NULL)
1818 break;
1819
1820 /*
1821 * Pack the data into the transmit ring. If we
1822 * don't have room, set the OACTIVE flag and wait
1823 * for the NIC to drain the ring.
1824 */
9b99c84f 1825 if (jme_encap(tdata, &m_head)) {
ecc6de9e
SZ		 1826 KKASSERT(m_head == NULL);
1827 ifp->if_oerrors++;
76fbb0b9
SZ		 1828 ifp->if_flags |= IFF_OACTIVE;
1829 break;
1830 }
1831 enq++;
1832
1833 /*
1834 * If there's a BPF listener, bounce a copy of this frame
1835 * to him.
1836 */
1837 ETHER_BPF_MTAP(ifp, m_head);
1838 }
1839
1840 if (enq > 0) {
1841 /*
1842 * Reading TXCSR takes very long time under heavy load
1843 * so cache TXCSR value and writes the ORed value with
1844 * the kick command to the TXCSR. This saves one register
1845 * access cycle.
1846 */
1847 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1848 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1849 /* Set a timeout in case the chip goes out to lunch. */
1850 ifp->if_timer = JME_TX_TIMEOUT;
1851 }
1852}
1853
1854static void
1855jme_watchdog(struct ifnet *ifp)
1856{
1857 struct jme_softc *sc = ifp->if_softc;
9b99c84f 1858 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9 1859
31f0d5a2 1860 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9 1861
cccc3955 1862 if (!sc->jme_has_link) {
76fbb0b9
SZ		 1863 if_printf(ifp, "watchdog timeout (missed link)\n");
1864 ifp->if_oerrors++;
1865 jme_init(sc);
1866 return;
1867 }
1868
9b99c84f
SZ		 1869 jme_txeof(tdata);
1870 if (tdata->jme_tx_cnt == 0) {
76fbb0b9
SZ		 1871 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1872 "-- recovering\n");
1873 if (!ifq_is_empty(&ifp->if_snd))
1874 if_devstart(ifp);
1875 return;
1876 }
1877
1878 if_printf(ifp, "watchdog timeout\n");
1879 ifp->if_oerrors++;
1880 jme_init(sc);
1881 if (!ifq_is_empty(&ifp->if_snd))
1882 if_devstart(ifp);
1883}
1884
1885static int
1886jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1887{
1888 struct jme_softc *sc = ifp->if_softc;
1889 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1890 struct ifreq *ifr = (struct ifreq *)data;
1891 int error = 0, mask;
1892
31f0d5a2 1893 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 1894
1895 switch (cmd) {
1896 case SIOCSIFMTU:
1897 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
3a5f3f36 1898 (!(sc->jme_caps & JME_CAP_JUMBO) &&
76fbb0b9
SZ		 1899 ifr->ifr_mtu > JME_MAX_MTU)) {
1900 error = EINVAL;
1901 break;
1902 }
1903
1904 if (ifp->if_mtu != ifr->ifr_mtu) {
1905 /*
1906 * No special configuration is required when interface
1907 * MTU is changed but availability of Tx checksum
1908 * offload should be chcked against new MTU size as
1909 * FIFO size is just 2K.
1910 */
1911 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1bedd927
SZ		 1912 ifp->if_capenable &=
1913 ~(IFCAP_TXCSUM | IFCAP_TSO);
1914 ifp->if_hwassist &=
1915 ~(JME_CSUM_FEATURES | CSUM_TSO);
76fbb0b9
SZ		 1916 }
1917 ifp->if_mtu = ifr->ifr_mtu;
1918 if (ifp->if_flags & IFF_RUNNING)
1919 jme_init(sc);
1920 }
1921 break;
1922
1923 case SIOCSIFFLAGS:
1924 if (ifp->if_flags & IFF_UP) {
1925 if (ifp->if_flags & IFF_RUNNING) {
1926 if ((ifp->if_flags ^ sc->jme_if_flags) &
1927 (IFF_PROMISC | IFF_ALLMULTI))
1928 jme_set_filter(sc);
1929 } else {
1930 jme_init(sc);
1931 }
1932 } else {
1933 if (ifp->if_flags & IFF_RUNNING)
1934 jme_stop(sc);
1935 }
1936 sc->jme_if_flags = ifp->if_flags;
1937 break;
1938
1939 case SIOCADDMULTI:
1940 case SIOCDELMULTI:
1941 if (ifp->if_flags & IFF_RUNNING)
1942 jme_set_filter(sc);
1943 break;
1944
1945 case SIOCSIFMEDIA:
1946 case SIOCGIFMEDIA:
1947 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1948 break;
1949
1950 case SIOCSIFCAP:
1951 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1952
1953 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
e4616e94 1954 ifp->if_capenable ^= IFCAP_TXCSUM;
1bedd927 1955 if (ifp->if_capenable & IFCAP_TXCSUM)
e4616e94
SZ		 1956 ifp->if_hwassist |= JME_CSUM_FEATURES;
1957 else
1958 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
76fbb0b9 1959 }
e4616e94 1960 if (mask & IFCAP_RXCSUM) {
76fbb0b9
SZ		 1961 uint32_t reg;
1962
1963 ifp->if_capenable ^= IFCAP_RXCSUM;
1964 reg = CSR_READ_4(sc, JME_RXMAC);
1965 reg &= ~RXMAC_CSUM_ENB;
1966 if (ifp->if_capenable & IFCAP_RXCSUM)
1967 reg |= RXMAC_CSUM_ENB;
1968 CSR_WRITE_4(sc, JME_RXMAC, reg);
1969 }
1970
e4616e94 1971 if (mask & IFCAP_VLAN_HWTAGGING) {
76fbb0b9
SZ		 1972 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1973 jme_set_vlan(sc);
1974 }
e4616e94 1975
1bedd927
SZ		 1976 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1977 ifp->if_capenable ^= IFCAP_TSO;
1978 if (ifp->if_capenable & IFCAP_TSO)
1979 ifp->if_hwassist |= CSUM_TSO;
1980 else
1981 ifp->if_hwassist &= ~CSUM_TSO;
1982 }
1983
9f20b7b3 1984 if (mask & IFCAP_RSS)
d585233c 1985 ifp->if_capenable ^= IFCAP_RSS;
76fbb0b9
SZ		 1986 break;
1987
1988 default:
1989 error = ether_ioctl(ifp, cmd, data);
1990 break;
1991 }
1992 return (error);
1993}
1994
1995static void
1996jme_mac_config(struct jme_softc *sc)
1997{
1998 struct mii_data *mii;
3b3da110
SZ		 1999 uint32_t ghc, rxmac, txmac, txpause, gp1;
2000 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
76fbb0b9
SZ		 2001
2002 mii = device_get_softc(sc->jme_miibus);
2003
2004 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2005 DELAY(10);
2006 CSR_WRITE_4(sc, JME_GHC, 0);
2007 ghc = 0;
2008 rxmac = CSR_READ_4(sc, JME_RXMAC);
2009 rxmac &= ~RXMAC_FC_ENB;
2010 txmac = CSR_READ_4(sc, JME_TXMAC);
2011 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2012 txpause = CSR_READ_4(sc, JME_TXPFC);
2013 txpause &= ~TXPFC_PAUSE_ENB;
2014 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2015 ghc |= GHC_FULL_DUPLEX;
2016 rxmac &= ~RXMAC_COLL_DET_ENB;
2017 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2018 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2019 TXMAC_FRAME_BURST);
2020#ifdef notyet
2021 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2022 txpause |= TXPFC_PAUSE_ENB;
2023 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2024 rxmac |= RXMAC_FC_ENB;
2025#endif
2026 /* Disable retry transmit timer/retry limit. */
2027 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2028 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2029 } else {
2030 rxmac |= RXMAC_COLL_DET_ENB;
2031 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2032 /* Enable retry transmit timer/retry limit. */
2033 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2034 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2035 }
2036
3b3da110
SZ		 2037 /*
2038 * Reprogram Tx/Rx MACs with resolved speed/duplex.
2039 */
2040 gp1 = CSR_READ_4(sc, JME_GPREG1);
2041 gp1 &= ~GPREG1_WA_HDX;
2042
2043 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2044 hdx = 1;
2045
76fbb0b9
SZ		 2046 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2047 case IFM_10_T:
b249905b 2048 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
3b3da110
SZ		 2049 if (hdx)
2050 gp1 |= GPREG1_WA_HDX;
76fbb0b9 2051 break;
dbe37f03 2052
76fbb0b9 2053 case IFM_100_TX:
b249905b 2054 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
3b3da110
SZ		 2055 if (hdx)
2056 gp1 |= GPREG1_WA_HDX;
dbe37f03
SZ		 2057
2058 /*
2059 * Use extended FIFO depth to workaround CRC errors
2060 * emitted by chips before JMC250B
2061 */
2062 phyconf = JMPHY_CONF_EXTFIFO;
76fbb0b9 2063 break;
dbe37f03 2064
76fbb0b9 2065 case IFM_1000_T:
ec7e787b 2066 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 2067 break;
dbe37f03 2068
b249905b 2069 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
3b3da110 2070 if (hdx)
76fbb0b9
SZ		 2071 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2072 break;
dbe37f03 2073
76fbb0b9
SZ		 2074 default:
2075 break;
2076 }
2077 CSR_WRITE_4(sc, JME_GHC, ghc);
2078 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2079 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2080 CSR_WRITE_4(sc, JME_TXPFC, txpause);
dbe37f03 2081
ad22907f 2082 if (sc->jme_workaround & JME_WA_EXTFIFO) {
dbe37f03
SZ		 2083 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2084 JMPHY_CONF, phyconf);
2085 }
3b3da110
SZ		 2086 if (sc->jme_workaround & JME_WA_HDX)
2087 CSR_WRITE_4(sc, JME_GPREG1, gp1);
76fbb0b9
SZ		 2088}
2089
2090static void
2091jme_intr(void *xsc)
2092{
2093 struct jme_softc *sc = xsc;
2094 struct ifnet *ifp = &sc->arpcom.ac_if;
2095 uint32_t status;
4447c752 2096 int r;
76fbb0b9 2097
31f0d5a2 2098 ASSERT_SERIALIZED(&sc->jme_serialize);
76fbb0b9
SZ		 2099
2100 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2101 if (status == 0 || status == 0xFFFFFFFF)
2102 return;
2103
2104 /* Disable interrupts. */
2105 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2106
2107 status = CSR_READ_4(sc, JME_INTR_STATUS);
2108 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2109 goto back;
2110
2111 /* Reset PCC counter/timer and Ack interrupts. */
2112 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
4447c752 2113
76fbb0b9
SZ		 2114 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2115 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
4447c752 2116
7b040092 2117 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 2118 if (status & jme_rx_status[r].jme_coal) {
2119 status |= jme_rx_status[r].jme_coal |
2120 jme_rx_status[r].jme_comp;
2121 }
2122 }
2123
76fbb0b9
SZ		 2124 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2125
2126 if (ifp->if_flags & IFF_RUNNING) {
9b99c84f
SZ		 2127 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
2128
76fbb0b9 2129 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
4447c752 2130 jme_rx_intr(sc, status);
76fbb0b9
SZ		 2131
2132 if (status & INTR_RXQ_DESC_EMPTY) {
2133 /*
2134 * Notify hardware availability of new Rx buffers.
2135 * Reading RXCSR takes very long time under heavy
2136 * load so cache RXCSR value and writes the ORed
2137 * value with the kick command to the RXCSR. This
2138 * saves one register access cycle.
2139 */
2140 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2141 RXCSR_RX_ENB | RXCSR_RXQ_START);
2142 }
2143
2144 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
9b99c84f
SZ		 2145 lwkt_serialize_enter(&tdata->jme_tx_serialize);
2146 jme_txeof(tdata);
76fbb0b9
SZ		 2147 if (!ifq_is_empty(&ifp->if_snd))
2148 if_devstart(ifp);
9b99c84f 2149 lwkt_serialize_exit(&tdata->jme_tx_serialize);
76fbb0b9
SZ		 2150 }
2151 }
2152back:
2153 /* Reenable interrupts. */
2154 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2155}
2156
2157static void
9b99c84f 2158jme_txeof(struct jme_txdata *tdata)
76fbb0b9 2159{
9b99c84f 2160 struct ifnet *ifp = &tdata->jme_sc->arpcom.ac_if;
6960d7d2 2161 int cons;
76fbb0b9 2162
9b99c84f
SZ		 2163 cons = tdata->jme_tx_cons;
2164 if (cons == tdata->jme_tx_prod)
76fbb0b9
SZ		 2165 return;
2166
76fbb0b9
SZ		 2167 /*
2168 * Go through our Tx list and free mbufs for those
2169 * frames which have been transmitted.
2170 */
9b99c84f 2171 while (cons != tdata->jme_tx_prod) {
6960d7d2
SZ		 2172 struct jme_txdesc *txd, *next_txd;
2173 uint32_t status, next_status;
2174 int next_cons, nsegs;
2175
9b99c84f 2176 txd = &tdata->jme_txdesc[cons];
76fbb0b9 2177 KASSERT(txd->tx_m != NULL,
ed20d0e3 2178 ("%s: freeing NULL mbuf!", __func__));
76fbb0b9
SZ		 2179
2180 status = le32toh(txd->tx_desc->flags);
2181 if ((status & JME_TD_OWN) == JME_TD_OWN)
2182 break;
2183
6960d7d2
SZ		 2184 /*
2185 * NOTE:
2186 * This chip will always update the TX descriptor's
2187 * buflen field and this updating always happens
2188 * after clearing the OWN bit, so even if the OWN
2189 * bit is cleared by the chip, we still don't sure
2190 * about whether the buflen field has been updated
2191 * by the chip or not. To avoid this race, we wait
2192 * for the next TX descriptor's OWN bit to be cleared
2193 * by the chip before reusing this TX descriptor.
2194 */
2195 next_cons = cons;
9b99c84f
SZ		 2196 JME_DESC_ADD(next_cons, txd->tx_ndesc, tdata->jme_tx_desc_cnt);
2197 next_txd = &tdata->jme_txdesc[next_cons];
6960d7d2
SZ		 2198 if (next_txd->tx_m == NULL)
2199 break;
2200 next_status = le32toh(next_txd->tx_desc->flags);
2201 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2202 break;
2203
76fbb0b9
SZ		 2204 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2205 ifp->if_oerrors++;
2206 } else {
2207 ifp->if_opackets++;
2208 if (status & JME_TD_COLLISION) {
2209 ifp->if_collisions +=
2210 le32toh(txd->tx_desc->buflen) &
2211 JME_TD_BUF_LEN_MASK;
2212 }
2213 }
2214
2215 /*
2216 * Only the first descriptor of multi-descriptor
2217 * transmission is updated so driver have to skip entire
2218 * chained buffers for the transmiited frame. In other
2219 * words, JME_TD_OWN bit is valid only at the first
2220 * descriptor of a multi-descriptor transmission.
2221 */
2222 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
9b99c84f
SZ		 2223 tdata->jme_tx_ring[cons].flags = 0;
2224 JME_DESC_INC(cons, tdata->jme_tx_desc_cnt);
76fbb0b9
SZ		 2225 }
2226
2227 /* Reclaim transferred mbufs. */
9b99c84f 2228 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap);
76fbb0b9
SZ		 2229 m_freem(txd->tx_m);
2230 txd->tx_m = NULL;
9b99c84f
SZ		 2231 tdata->jme_tx_cnt -= txd->tx_ndesc;
2232 KASSERT(tdata->jme_tx_cnt >= 0,
ed20d0e3 2233 ("%s: Active Tx desc counter was garbled", __func__));
76fbb0b9
SZ		 2234 txd->tx_ndesc = 0;
2235 }
9b99c84f 2236 tdata->jme_tx_cons = cons;
76fbb0b9 2237
1bedd927 2238 /* 1 for symbol TX descriptor */
9b99c84f 2239 if (tdata->jme_tx_cnt <= JME_MAXTXSEGS + 1)
76fbb0b9
SZ		 2240 ifp->if_timer = 0;
2241
9b99c84f
SZ		 2242 if (tdata->jme_tx_cnt + JME_TXD_SPARE <=
2243 tdata->jme_tx_desc_cnt - JME_TXD_RSVD)
76fbb0b9 2244 ifp->if_flags &= ~IFF_OACTIVE;
76fbb0b9
SZ		 2245}
2246
2247static __inline void
dea2452a 2248jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
76fbb0b9
SZ		 2249{
2250 int i;
2251
2252 for (i = 0; i < count; ++i) {
fd2a6d2c 2253 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
7b040092 2254 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
76fbb0b9
SZ		 2255 }
2256}
2257
a6acc6e2
SZ		 2258static __inline struct pktinfo *
2259jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2260{
2261 if (flags & JME_RD_IPV4)
2262 pi->pi_netisr = NETISR_IP;
2263 else if (flags & JME_RD_IPV6)
2264 pi->pi_netisr = NETISR_IPV6;
2265 else
2266 return NULL;
2267
2268 pi->pi_flags = 0;
2269 pi->pi_l3proto = IPPROTO_UNKNOWN;
2270
2271 if (flags & JME_RD_MORE_FRAG)
2272 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2273 else if (flags & JME_RD_TCP)
2274 pi->pi_l3proto = IPPROTO_TCP;
2275 else if (flags & JME_RD_UDP)
2276 pi->pi_l3proto = IPPROTO_UDP;
7345eb80
SZ		 2277 else
2278 pi = NULL;
a6acc6e2
SZ		 2279 return pi;
2280}
2281
76fbb0b9
SZ		 2282/* Receive a frame. */
2283static void
dea2452a 2284jme_rxpkt(struct jme_rxdata *rdata)
76fbb0b9 2285{
dea2452a 2286 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
76fbb0b9
SZ		 2287 struct jme_desc *desc;
2288 struct jme_rxdesc *rxd;
2289 struct mbuf *mp, *m;
a6acc6e2 2290 uint32_t flags, status, hash, hashinfo;
76fbb0b9
SZ		 2291 int cons, count, nsegs;
2292
4447c752
SZ		 2293 cons = rdata->jme_rx_cons;
2294 desc = &rdata->jme_rx_ring[cons];
9d4f763d 2295
76fbb0b9
SZ		 2296 flags = le32toh(desc->flags);
2297 status = le32toh(desc->buflen);
a6acc6e2
SZ		 2298 hash = le32toh(desc->addr_hi);
2299 hashinfo = le32toh(desc->addr_lo);
76fbb0b9
SZ		 2300 nsegs = JME_RX_NSEGS(status);
2301
9d4f763d
SZ		 2302 if (nsegs > 1) {
2303 /* Skip the first descriptor. */
2304 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2305
2306 /*
2307 * Clear the OWN bit of the following RX descriptors;
2308 * hardware will not clear the OWN bit except the first
2309 * RX descriptor.
2310 *
2311 * Since the first RX descriptor is setup, i.e. OWN bit
2312 * on, before its followins RX descriptors, leaving the
2313 * OWN bit on the following RX descriptors will trick
2314 * the hardware into thinking that the following RX
2315 * descriptors are ready to be used too.
2316 */
2317 for (count = 1; count < nsegs; count++,
2318 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2319 rdata->jme_rx_ring[cons].flags = 0;
2320
2321 cons = rdata->jme_rx_cons;
2322 }
2323
7b040092 2324 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
a6acc6e2 2325 "hash 0x%08x, hash info 0x%08x\n",
7b040092 2326 rdata->jme_rx_idx, flags, hash, hashinfo);
760c056c 2327
76fbb0b9
SZ		 2328 if (status & JME_RX_ERR_STAT) {
2329 ifp->if_ierrors++;
dea2452a 2330 jme_discard_rxbufs(rdata, cons, nsegs);
76fbb0b9 2331#ifdef JME_SHOW_ERRORS
7b040092 2332 if_printf(ifp, "%s : receive error = 0x%b\n",
76fbb0b9
SZ		 2333 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2334#endif
4447c752 2335 rdata->jme_rx_cons += nsegs;
7b040092 2336 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ		 2337 return;
2338 }
2339
4447c752 2340 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
76fbb0b9 2341 for (count = 0; count < nsegs; count++,
7b040092 2342 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
4447c752 2343 rxd = &rdata->jme_rxdesc[cons];
76fbb0b9
SZ		 2344 mp = rxd->rx_m;
2345
2346 /* Add a new receive buffer to the ring. */
dea2452a 2347 if (jme_newbuf(rdata, rxd, 0) != 0) {
76fbb0b9
SZ		 2348 ifp->if_iqdrops++;
2349 /* Reuse buffer. */
dea2452a 2350 jme_discard_rxbufs(rdata, cons, nsegs - count);
4447c752
SZ		 2351 if (rdata->jme_rxhead != NULL) {
2352 m_freem(rdata->jme_rxhead);
dea2452a 2353 JME_RXCHAIN_RESET(rdata);
76fbb0b9
SZ		 2354 }
2355 break;
2356 }
2357
2358 /*
2359 * Assume we've received a full sized frame.
2360 * Actual size is fixed when we encounter the end of
2361 * multi-segmented frame.
2362 */
2363 mp->m_len = MCLBYTES;
2364
2365 /* Chain received mbufs. */
4447c752
SZ		 2366 if (rdata->jme_rxhead == NULL) {
2367 rdata->jme_rxhead = mp;
2368 rdata->jme_rxtail = mp;
76fbb0b9
SZ		 2369 } else {
2370 /*
2371 * Receive processor can receive a maximum frame
2372 * size of 65535 bytes.
2373 */
4447c752
SZ		 2374 rdata->jme_rxtail->m_next = mp;
2375 rdata->jme_rxtail = mp;
76fbb0b9
SZ		 2376 }
2377
2378 if (count == nsegs - 1) {
a6acc6e2
SZ		 2379 struct pktinfo pi0, *pi;
2380
76fbb0b9 2381 /* Last desc. for this frame. */
4447c752 2382 m = rdata->jme_rxhead;
4447c752 2383 m->m_pkthdr.len = rdata->jme_rxlen;
76fbb0b9
SZ		 2384 if (nsegs > 1) {
2385 /* Set first mbuf size. */
2386 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2387 /* Set last mbuf size. */
4447c752 2388 mp->m_len = rdata->jme_rxlen -
76fbb0b9
SZ		 2389 ((MCLBYTES - JME_RX_PAD_BYTES) +
2390 (MCLBYTES * (nsegs - 2)));
2391 } else {
4447c752 2392 m->m_len = rdata->jme_rxlen;
76fbb0b9
SZ		 2393 }
2394 m->m_pkthdr.rcvif = ifp;
2395
2396 /*
2397 * Account for 10bytes auto padding which is used
2398 * to align IP header on 32bit boundary. Also note,
2399 * CRC bytes is automatically removed by the
2400 * hardware.
2401 */
2402 m->m_data += JME_RX_PAD_BYTES;
2403
2404 /* Set checksum information. */
2405 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2406 (flags & JME_RD_IPV4)) {
2407 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2408 if (flags & JME_RD_IPCSUM)
2409 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2410 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2411 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2412 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2413 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2414 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2415 m->m_pkthdr.csum_flags |=
2416 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2417 m->m_pkthdr.csum_data = 0xffff;
2418 }
2419 }
2420
2421 /* Check for VLAN tagged packets. */
2422 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2423 (flags & JME_RD_VLAN_TAG)) {
2424 m->m_pkthdr.ether_vlantag =
2425 flags & JME_RD_VLAN_MASK;
2426 m->m_flags |= M_VLANTAG;
2427 }
2428
2429 ifp->if_ipackets++;
a6acc6e2
SZ		 2430
2431 if (ifp->if_capenable & IFCAP_RSS)
2432 pi = jme_pktinfo(&pi0, flags);
2433 else
2434 pi = NULL;
2435
2436 if (pi != NULL &&
055b7997
SZ		 2437 (hashinfo & JME_RD_HASH_FN_MASK) ==
2438 JME_RD_HASH_FN_TOEPLITZ) {
2439 m->m_flags |= (M_HASH | M_CKHASH);
a6acc6e2
SZ		 2440 m->m_pkthdr.hash = toeplitz_hash(hash);
2441 }
2442
2443#ifdef JME_RSS_DEBUG
2444 if (pi != NULL) {
7b040092 2445 JME_RSS_DPRINTF(rdata->jme_sc, 10,
a6acc6e2
SZ		 2446 "isr %d flags %08x, l3 %d %s\n",
2447 pi->pi_netisr, pi->pi_flags,
2448 pi->pi_l3proto,
2449 (m->m_flags & M_HASH) ? "hash" : "");
2450 }
2451#endif
2452
76fbb0b9 2453 /* Pass it on. */
eda7db08 2454 ether_input_pkt(ifp, m, pi);
76fbb0b9
SZ		 2455
2456 /* Reset mbuf chains. */
dea2452a 2457 JME_RXCHAIN_RESET(rdata);
760c056c 2458#ifdef JME_RSS_DEBUG
7b040092 2459 rdata->jme_rx_pkt++;
760c056c 2460#endif
76fbb0b9
SZ		 2461 }
2462 }
2463
4447c752 2464 rdata->jme_rx_cons += nsegs;
7b040092 2465 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ		 2466}
2467
eda7db08 2468static void
dea2452a 2469jme_rxeof(struct jme_rxdata *rdata, int count)
76fbb0b9
SZ		 2470{
2471 struct jme_desc *desc;
eda7db08 2472 int nsegs, pktlen;
76fbb0b9 2473
76fbb0b9 2474 for (;;) {
8a0620e4 2475#ifdef IFPOLL_ENABLE
3fa06afc
SZ		 2476 if (count >= 0 && count-- == 0)
2477 break;
2478#endif
4447c752 2479 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
76fbb0b9
SZ		 2480 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2481 break;
2482 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2483 break;
2484
2485 /*
2486 * Check number of segments against received bytes.
2487 * Non-matching value would indicate that hardware
2488 * is still trying to update Rx descriptors. I'm not
2489 * sure whether this check is needed.
2490 */
2491 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2492 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2493 if (nsegs != howmany(pktlen, MCLBYTES)) {
dea2452a
SZ		 2494 if_printf(&rdata->jme_sc->arpcom.ac_if,
2495 "RX fragment count(%d) and "
2496 "packet size(%d) mismach\n", nsegs, pktlen);
76fbb0b9
SZ		 2497 break;
2498 }
2499
6afef6ab
SZ		 2500 /*
2501 * NOTE:
2502 * RSS hash and hash information may _not_ be set by the
2503 * hardware even if the OWN bit is cleared and VALID bit
2504 * is set.
2505 *
2506 * If the RSS information is not delivered by the hardware
2507 * yet, we MUST NOT accept this packet, let alone reusing
2508 * its RX descriptor. If this packet was accepted and its
2509 * RX descriptor was reused before hardware delivering the
2510 * RSS information, the RX buffer's address would be trashed
2511 * by the RSS information delivered by the hardware.
2512 */
2513 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2514 struct jme_rxdesc *rxd;
2515 uint32_t hashinfo;
2516
2517 hashinfo = le32toh(desc->addr_lo);
2518 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2519
2520 /*
2521 * This test should be enough to detect the pending
2522 * RSS information delivery, given:
2523 * - If RSS hash is not calculated, the hashinfo
064b75ed
SZ		 2524 * will be 0. Howvever, the lower 32bits of RX
2525 * buffers' physical address will never be 0.
2526 * (see jme_rxbuf_dma_filter)
6afef6ab
SZ		 2527 * - If RSS hash is calculated, the lowest 4 bits
2528 * of hashinfo will be set, while the RX buffers
2529 * are at least 2K aligned.
2530 */
2531 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2532#ifdef JME_SHOW_RSSWB
2533 if_printf(&rdata->jme_sc->arpcom.ac_if,
2534 "RSS is not written back yet\n");
2535#endif
2536 break;
2537 }
2538 }
2539
76fbb0b9 2540 /* Received a frame. */
dea2452a 2541 jme_rxpkt(rdata);
76fbb0b9 2542 }
76fbb0b9
SZ		 2543}
2544
2545static void
2546jme_tick(void *xsc)
2547{
2548 struct jme_softc *sc = xsc;
76fbb0b9
SZ		 2549 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2550
cccc3955 2551 lwkt_serialize_enter(&sc->jme_serialize);
76fbb0b9 2552
cccc3955 2553 sc->jme_in_tick = TRUE;
76fbb0b9 2554 mii_tick(mii);
cccc3955
SZ		 2555 sc->jme_in_tick = FALSE;
2556
76fbb0b9
SZ		 2557 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2558
cccc3955 2559 lwkt_serialize_exit(&sc->jme_serialize);
76fbb0b9
SZ		 2560}
2561
2562static void
2563jme_reset(struct jme_softc *sc)
2564{
409fe405
SZ		 2565 uint32_t val;
2566
2567 /* Make sure that TX and RX are stopped */
76fbb0b9 2568 jme_stop_tx(sc);
409fe405
SZ		 2569 jme_stop_rx(sc);
2570
2571 /* Start reset */
76fbb0b9 2572 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
409fe405
SZ		 2573 DELAY(20);
2574
2575 /*
2576 * Hold reset bit before stop reset
2577 */
2578
2579 /* Disable TXMAC and TXOFL clock sources */
2580 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2581 /* Disable RXMAC clock source */
2582 val = CSR_READ_4(sc, JME_GPREG1);
2583 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2584 /* Flush */
2585 CSR_READ_4(sc, JME_GHC);
2586
2587 /* Stop reset */
2588 CSR_WRITE_4(sc, JME_GHC, 0);
2589 /* Flush */
2590 CSR_READ_4(sc, JME_GHC);
2591
2592 /*
2593 * Clear reset bit after stop reset
2594 */
2595
2596 /* Enable TXMAC and TXOFL clock sources */
2597 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2598 /* Enable RXMAC clock source */
2599 val = CSR_READ_4(sc, JME_GPREG1);
2600 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2601 /* Flush */
2602 CSR_READ_4(sc, JME_GHC);
2603
2604 /* Disable TXMAC and TXOFL clock sources */
76fbb0b9 2605 CSR_WRITE_4(sc, JME_GHC, 0);
409fe405
SZ		 2606 /* Disable RXMAC clock source */
2607 val = CSR_READ_4(sc, JME_GPREG1);
2608 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2609 /* Flush */
2610 CSR_READ_4(sc, JME_GHC);
2611
2612 /* Enable TX and RX */
2613 val = CSR_READ_4(sc, JME_TXCSR);
2614 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2615 val = CSR_READ_4(sc, JME_RXCSR);
2616 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2617 /* Flush */
2618 CSR_READ_4(sc, JME_TXCSR);
2619 CSR_READ_4(sc, JME_RXCSR);
2620
2621 /* Enable TXMAC and TXOFL clock sources */
2622 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2623 /* Eisable RXMAC clock source */
2624 val = CSR_READ_4(sc, JME_GPREG1);
2625 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2626 /* Flush */
2627 CSR_READ_4(sc, JME_GHC);
2628
2629 /* Stop TX and RX */
2630 jme_stop_tx(sc);
2631 jme_stop_rx(sc);
76fbb0b9
SZ		 2632}
2633
2634static void
2635jme_init(void *xsc)
2636{
2637 struct jme_softc *sc = xsc;
2638 struct ifnet *ifp = &sc->arpcom.ac_if;
2639 struct mii_data *mii;
2640 uint8_t eaddr[ETHER_ADDR_LEN];
2641 bus_addr_t paddr;
2642 uint32_t reg;
4447c752 2643 int error, r;
76fbb0b9 2644
31f0d5a2 2645 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 2646
2647 /*
2648 * Cancel any pending I/O.
2649 */
2650 jme_stop(sc);
2651
2652 /*
2653 * Reset the chip to a known state.
2654 */
2655 jme_reset(sc);
2656
58880b0d
SZ		 2657 /*
2658 * Setup MSI/MSI-X vectors to interrupts mapping
2659 */
2660 jme_set_msinum(sc);
2661
6afef6ab 2662 if (JME_ENABLE_HWRSS(sc))
760c056c
SZ		 2663 jme_enable_rss(sc);
2664 else
2665 jme_disable_rss(sc);
4447c752
SZ		 2666
2667 /* Init RX descriptors */
7b040092 2668 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
dea2452a 2669 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
4447c752
SZ		 2670 if (error) {
2671 if_printf(ifp, "initialization failed: "
2672 "no memory for %dth RX ring.\n", r);
2673 jme_stop(sc);
2674 return;
2675 }
2676 }
2677
2678 /* Init TX descriptors */
9b99c84f 2679 jme_init_tx_ring(&sc->jme_cdata.jme_tx_data);
76fbb0b9
SZ		 2680
2681 /* Initialize shadow status block. */
2682 jme_init_ssb(sc);
2683
2684 /* Reprogram the station address. */
2685 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2686 CSR_WRITE_4(sc, JME_PAR0,
2687 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2688 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2689
2690 /*
2691 * Configure Tx queue.
2692 * Tx priority queue weight value : 0
2693 * Tx FIFO threshold for processing next packet : 16QW
2694 * Maximum Tx DMA length : 512
2695 * Allow Tx DMA burst.
2696 */
2697 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2698 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2699 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2700 sc->jme_txcsr |= sc->jme_tx_dma_size;
2701 sc->jme_txcsr |= TXCSR_DMA_BURST;
2702 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2703
2704 /* Set Tx descriptor counter. */
9b99c84f 2705 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt);
76fbb0b9
SZ		 2706
2707 /* Set Tx ring address to the hardware. */
9b99c84f 2708 paddr = sc->jme_cdata.jme_tx_data.jme_tx_ring_paddr;
76fbb0b9
SZ		 2709 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2710 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2711
2712 /* Configure TxMAC parameters. */
2713 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2714 reg |= TXMAC_THRESH_1_PKT;
2715 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2716 CSR_WRITE_4(sc, JME_TXMAC, reg);
2717
2718 /*
2719 * Configure Rx queue.
2720 * FIFO full threshold for transmitting Tx pause packet : 128T
2721 * FIFO threshold for processing next packet : 128QW
2722 * Rx queue 0 select
2723 * Max Rx DMA length : 128
2724 * Rx descriptor retry : 32
2725 * Rx descriptor retry time gap : 256ns
2726 * Don't receive runt/bad frame.
2727 */
2728 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
223cfc2f 2729#if 0
76fbb0b9
SZ		 2730 /*
2731 * Since Rx FIFO size is 4K bytes, receiving frames larger
2732 * than 4K bytes will suffer from Rx FIFO overruns. So
2733 * decrease FIFO threshold to reduce the FIFO overruns for
2734 * frames larger than 4000 bytes.
2735 * For best performance of standard MTU sized frames use
2736 * maximum allowable FIFO threshold, 128QW.
2737 */
2738 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2739 JME_RX_FIFO_SIZE)
2740 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2741 else
2742 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
223cfc2f
SZ		 2743#else
2744 /* Improve PCI Express compatibility */
2745 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2746#endif
2747 sc->jme_rxcsr |= sc->jme_rx_dma_size;
76fbb0b9
SZ		 2748 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2749 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2750 /* XXX TODO DROP_BAD */
76fbb0b9 2751
7b040092
SZ		 2752 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2753 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2754
4447c752
SZ		 2755 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2756
2757 /* Set Rx descriptor counter. */
7b040092 2758 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
76fbb0b9 2759
4447c752 2760 /* Set Rx ring address to the hardware. */
7b040092 2761 paddr = rdata->jme_rx_ring_paddr;
4447c752
SZ		 2762 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2763 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2764 }
76fbb0b9
SZ		 2765
2766 /* Clear receive filter. */
2767 CSR_WRITE_4(sc, JME_RXMAC, 0);
2768
2769 /* Set up the receive filter. */
2770 jme_set_filter(sc);
2771 jme_set_vlan(sc);
2772
2773 /*
2774 * Disable all WOL bits as WOL can interfere normal Rx
2775 * operation. Also clear WOL detection status bits.
2776 */
2777 reg = CSR_READ_4(sc, JME_PMCS);
2778 reg &= ~PMCS_WOL_ENB_MASK;
2779 CSR_WRITE_4(sc, JME_PMCS, reg);
2780
2781 /*
2782 * Pad 10bytes right before received frame. This will greatly
2783 * help Rx performance on strict-alignment architectures as
2784 * it does not need to copy the frame to align the payload.
2785 */
2786 reg = CSR_READ_4(sc, JME_RXMAC);
2787 reg |= RXMAC_PAD_10BYTES;
2788
2789 if (ifp->if_capenable & IFCAP_RXCSUM)
2790 reg |= RXMAC_CSUM_ENB;
2791 CSR_WRITE_4(sc, JME_RXMAC, reg);
2792
2793 /* Configure general purpose reg0 */
2794 reg = CSR_READ_4(sc, JME_GPREG0);
2795 reg &= ~GPREG0_PCC_UNIT_MASK;
2796 /* Set PCC timer resolution to micro-seconds unit. */
2797 reg |= GPREG0_PCC_UNIT_US;
2798 /*
2799 * Disable all shadow register posting as we have to read
2800 * JME_INTR_STATUS register in jme_intr. Also it seems
2801 * that it's hard to synchronize interrupt status between
2802 * hardware and software with shadow posting due to
2803 * requirements of bus_dmamap_sync(9).
2804 */
2805 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2806 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2807 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2808 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2809 /* Disable posting of DW0. */
2810 reg &= ~GPREG0_POST_DW0_ENB;
2811 /* Clear PME message. */
2812 reg &= ~GPREG0_PME_ENB;
2813 /* Set PHY address. */
2814 reg &= ~GPREG0_PHY_ADDR_MASK;
2815 reg |= sc->jme_phyaddr;
2816 CSR_WRITE_4(sc, JME_GPREG0, reg);
2817
2818 /* Configure Tx queue 0 packet completion coalescing. */
2870abc4 2819 jme_set_tx_coal(sc);
76fbb0b9 2820
dea2452a 2821 /* Configure Rx queues packet completion coalescing. */
2870abc4 2822 jme_set_rx_coal(sc);
76fbb0b9
SZ		 2823
2824 /* Configure shadow status block but don't enable posting. */
560616bf 2825 paddr = sc->jme_cdata.jme_ssb_block_paddr;
76fbb0b9
SZ		 2826 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2827 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2828
2829 /* Disable Timer 1 and Timer 2. */
2830 CSR_WRITE_4(sc, JME_TIMER1, 0);
2831 CSR_WRITE_4(sc, JME_TIMER2, 0);
2832
2833 /* Configure retry transmit period, retry limit value. */
2834 CSR_WRITE_4(sc, JME_TXTRHD,
2835 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2836 TXTRHD_RT_PERIOD_MASK) |
2837 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2838 TXTRHD_RT_LIMIT_SHIFT));
2839
8a0620e4
SZ		 2840#ifdef IFPOLL_ENABLE
2841 if (!(ifp->if_flags & IFF_NPOLLING))
9de40864 2842#endif
76fbb0b9 2843 /* Initialize the interrupt mask. */
8a0620e4 2844 jme_enable_intr(sc);
76fbb0b9
SZ		 2845 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2846
2847 /*
2848 * Enabling Tx/Rx DMA engines and Rx queue processing is
2849 * done after detection of valid link in jme_miibus_statchg.
2850 */
cccc3955 2851 sc->jme_has_link = FALSE;
76fbb0b9
SZ		 2852
2853 /* Set the current media. */
2854 mii = device_get_softc(sc->jme_miibus);
2855 mii_mediachg(mii);
2856
2857 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2858
2859 ifp->if_flags |= IFF_RUNNING;
2860 ifp->if_flags &= ~IFF_OACTIVE;
2861}
2862
2863static void
2864jme_stop(struct jme_softc *sc)
2865{
2866 struct ifnet *ifp = &sc->arpcom.ac_if;
9b99c84f 2867 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ		 2868 struct jme_txdesc *txd;
2869 struct jme_rxdesc *rxd;
4447c752
SZ		 2870 struct jme_rxdata *rdata;
2871 int i, r;
76fbb0b9 2872
31f0d5a2 2873 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 2874
2875 /*
2876 * Mark the interface down and cancel the watchdog timer.
2877 */
2878 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2879 ifp->if_timer = 0;
2880
2881 callout_stop(&sc->jme_tick_ch);
cccc3955 2882 sc->jme_has_link = FALSE;
76fbb0b9
SZ		 2883
2884 /*
2885 * Disable interrupts.
2886 */
8a0620e4 2887 jme_disable_intr(sc);
76fbb0b9
SZ		 2888 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2889
2890 /* Disable updating shadow status block. */
2891 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2892 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2893
2894 /* Stop receiver, transmitter. */
2895 jme_stop_rx(sc);
2896 jme_stop_tx(sc);
2897
76fbb0b9
SZ		 2898 /*
2899 * Free partial finished RX segments
2900 */
7b040092 2901 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ		 2902 rdata = &sc->jme_cdata.jme_rx_data[r];
2903 if (rdata->jme_rxhead != NULL)
2904 m_freem(rdata->jme_rxhead);
dea2452a 2905 JME_RXCHAIN_RESET(rdata);
4447c752 2906 }
76fbb0b9
SZ		 2907
2908 /*
2909 * Free RX and TX mbufs still in the queues.
2910 */
7b040092 2911 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752 2912 rdata = &sc->jme_cdata.jme_rx_data[r];
7b040092 2913 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ		 2914 rxd = &rdata->jme_rxdesc[i];
2915 if (rxd->rx_m != NULL) {
2916 bus_dmamap_unload(rdata->jme_rx_tag,
2917 rxd->rx_dmamap);
2918 m_freem(rxd->rx_m);
2919 rxd->rx_m = NULL;
2920 }
76fbb0b9 2921 }
4447c752 2922 }
9b99c84f
SZ		 2923 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
2924 txd = &tdata->jme_txdesc[i];
76fbb0b9 2925 if (txd->tx_m != NULL) {
9b99c84f 2926 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap);
76fbb0b9
SZ		 2927 m_freem(txd->tx_m);
2928 txd->tx_m = NULL;
2929 txd->tx_ndesc = 0;
2930 }
2931 }
2932}
2933
2934static void
2935jme_stop_tx(struct jme_softc *sc)
2936{
2937 uint32_t reg;
2938 int i;
2939
2940 reg = CSR_READ_4(sc, JME_TXCSR);
2941 if ((reg & TXCSR_TX_ENB) == 0)
2942 return;
2943 reg &= ~TXCSR_TX_ENB;
2944 CSR_WRITE_4(sc, JME_TXCSR, reg);
2945 for (i = JME_TIMEOUT; i > 0; i--) {
2946 DELAY(1);
2947 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2948 break;
2949 }
2950 if (i == 0)
2951 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2952}
2953
2954static void
2955jme_stop_rx(struct jme_softc *sc)
2956{
2957 uint32_t reg;
2958 int i;
2959
2960 reg = CSR_READ_4(sc, JME_RXCSR);
2961 if ((reg & RXCSR_RX_ENB) == 0)
2962 return;
2963 reg &= ~RXCSR_RX_ENB;
2964 CSR_WRITE_4(sc, JME_RXCSR, reg);
2965 for (i = JME_TIMEOUT; i > 0; i--) {
2966 DELAY(1);
2967 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2968 break;
2969 }
2970 if (i == 0)
2971 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2972}
2973
2974static void
9b99c84f 2975jme_init_tx_ring(struct jme_txdata *tdata)
76fbb0b9 2976{
76fbb0b9
SZ		 2977 struct jme_txdesc *txd;
2978 int i;
2979
9b99c84f
SZ		 2980 tdata->jme_tx_prod = 0;
2981 tdata->jme_tx_cons = 0;
2982 tdata->jme_tx_cnt = 0;
76fbb0b9 2983
9b99c84f
SZ		 2984 bzero(tdata->jme_tx_ring, JME_TX_RING_SIZE(tdata));
2985 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
2986 txd = &tdata->jme_txdesc[i];
76fbb0b9 2987 txd->tx_m = NULL;
9b99c84f 2988 txd->tx_desc = &tdata->jme_tx_ring[i];
76fbb0b9
SZ		 2989 txd->tx_ndesc = 0;
2990 }
76fbb0b9
SZ		 2991}
2992
2993static void
2994jme_init_ssb(struct jme_softc *sc)
2995{
560616bf 2996 struct jme_chain_data *cd;
76fbb0b9 2997
560616bf
SZ		 2998 cd = &sc->jme_cdata;
2999 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
76fbb0b9
SZ		 3000}
3001
3002static int
dea2452a 3003jme_init_rx_ring(struct jme_rxdata *rdata)
76fbb0b9 3004{
76fbb0b9
SZ		 3005 struct jme_rxdesc *rxd;
3006 int i;
3007
4447c752
SZ		 3008 KKASSERT(rdata->jme_rxhead == NULL &&
3009 rdata->jme_rxtail == NULL &&
3010 rdata->jme_rxlen == 0);
3011 rdata->jme_rx_cons = 0;
76fbb0b9 3012
7b040092
SZ		 3013 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
3014 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
76fbb0b9
SZ		 3015 int error;
3016
4447c752 3017 rxd = &rdata->jme_rxdesc[i];
76fbb0b9 3018 rxd->rx_m = NULL;
4447c752 3019 rxd->rx_desc = &rdata->jme_rx_ring[i];
dea2452a 3020 error = jme_newbuf(rdata, rxd, 1);
76fbb0b9 3021 if (error)
4447c752 3022 return error;
76fbb0b9 3023 }
4447c752 3024 return 0;
76fbb0b9
SZ		 3025}
3026
3027static int
dea2452a 3028jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
76fbb0b9 3029{
76fbb0b9 3030 struct mbuf *m;
76fbb0b9
SZ		 3031 bus_dma_segment_t segs;
3032 bus_dmamap_t map;
b0ba1747 3033 int error, nsegs;
76fbb0b9
SZ		 3034
3035 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3036 if (m == NULL)
4447c752 3037 return ENOBUFS;
76fbb0b9
SZ		 3038 /*
3039 * JMC250 has 64bit boundary alignment limitation so jme(4)
3040 * takes advantage of 10 bytes padding feature of hardware
3041 * in order not to copy entire frame to align IP header on
3042 * 32bit boundary.
3043 */
3044 m->m_len = m->m_pkthdr.len = MCLBYTES;
3045
b0ba1747
SZ		 3046 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
3047 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
3048 BUS_DMA_NOWAIT);
3049 if (error) {
76fbb0b9 3050 m_freem(m);
dea2452a
SZ		 3051 if (init) {
3052 if_printf(&rdata->jme_sc->arpcom.ac_if,
3053 "can't load RX mbuf\n");
3054 }
4447c752 3055 return error;
76fbb0b9
SZ		 3056 }
3057
3058 if (rxd->rx_m != NULL) {
4447c752 3059 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
76fbb0b9 3060 BUS_DMASYNC_POSTREAD);
4447c752 3061 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
76fbb0b9
SZ		 3062 }
3063 map = rxd->rx_dmamap;
4447c752
SZ		 3064 rxd->rx_dmamap = rdata->jme_rx_sparemap;
3065 rdata->jme_rx_sparemap = map;
76fbb0b9 3066 rxd->rx_m = m;
fd2a6d2c 3067 rxd->rx_paddr = segs.ds_addr;
76fbb0b9 3068
fd2a6d2c 3069 jme_setup_rxdesc(rxd);
4447c752 3070 return 0;
76fbb0b9
SZ		 3071}
3072
3073static void
3074jme_set_vlan(struct jme_softc *sc)
3075{
3076 struct ifnet *ifp = &sc->arpcom.ac_if;
3077 uint32_t reg;
3078
31f0d5a2 3079 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 3080
3081 reg = CSR_READ_4(sc, JME_RXMAC);
3082 reg &= ~RXMAC_VLAN_ENB;
3083 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
3084 reg |= RXMAC_VLAN_ENB;
3085 CSR_WRITE_4(sc, JME_RXMAC, reg);
3086}
3087
3088static void
3089jme_set_filter(struct jme_softc *sc)
3090{
3091 struct ifnet *ifp = &sc->arpcom.ac_if;
3092 struct ifmultiaddr *ifma;
3093 uint32_t crc;
3094 uint32_t mchash[2];
3095 uint32_t rxcfg;
3096
31f0d5a2 3097 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ		 3098
3099 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3100 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3101 RXMAC_ALLMULTI);
3102
3103 /*
3104 * Always accept frames destined to our station address.
3105 * Always accept broadcast frames.
3106 */
3107 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
3108
3109 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
3110 if (ifp->if_flags & IFF_PROMISC)
3111 rxcfg |= RXMAC_PROMISC;
3112 if (ifp->if_flags & IFF_ALLMULTI)
3113 rxcfg |= RXMAC_ALLMULTI;
3114 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3115 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3116 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3117 return;
3118 }
3119
3120 /*
3121 * Set up the multicast address filter by passing all multicast
3122 * addresses through a CRC generator, and then using the low-order
3123 * 6 bits as an index into the 64 bit multicast hash table. The
3124 * high order bits select the register, while the rest of the bits
3125 * select the bit within the register.
3126 */
3127 rxcfg |= RXMAC_MULTICAST;
3128 bzero(mchash, sizeof(mchash));
3129
441d34b2 3130 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
76fbb0b9
SZ		 3131 if (ifma->ifma_addr->sa_family != AF_LINK)
3132 continue;
3133 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3134 ifma->ifma_addr), ETHER_ADDR_LEN);
3135
3136 /* Just want the 6 least significant bits. */
3137 crc &= 0x3f;
3138
3139 /* Set the corresponding bit in the hash table. */
3140 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3141 }
3142
3143 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3144 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3145 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3146}
3147
3148static int
2870abc4 3149jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3150{
2870abc4
SZ		 3151 struct jme_softc *sc = arg1;
3152 struct ifnet *ifp = &sc->arpcom.ac_if;
3153 int error, v;
3154
31f0d5a2 3155 ifnet_serialize_all(ifp);
2870abc4
SZ		 3156
3157 v = sc->jme_tx_coal_to;
3158 error = sysctl_handle_int(oidp, &v, 0, req);
3159 if (error || req->newptr == NULL)
3160 goto back;
3161
3162 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3163 error = EINVAL;
3164 goto back;
3165 }
3166
3167 if (v != sc->jme_tx_coal_to) {
3168 sc->jme_tx_coal_to = v;
3169 if (ifp->if_flags & IFF_RUNNING)
3170 jme_set_tx_coal(sc);
3171 }
3172back:
31f0d5a2 3173 ifnet_deserialize_all(ifp);
2870abc4 3174 return error;
76fbb0b9
SZ		 3175}
3176
3177static int
2870abc4 3178jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
76fbb0b9 3179{
2870abc4
SZ		 3180 struct jme_softc *sc = arg1;
3181 struct ifnet *ifp = &sc->arpcom.ac_if;
3182 int error, v;
3183
31f0d5a2 3184 ifnet_serialize_all(ifp);
2870abc4
SZ		 3185
3186 v = sc->jme_tx_coal_pkt;
3187 error = sysctl_handle_int(oidp, &v, 0, req);
3188 if (error || req->newptr == NULL)
3189 goto back;
3190
3191 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3192 error = EINVAL;
3193 goto back;
3194 }
3195
3196 if (v != sc->jme_tx_coal_pkt) {
3197 sc->jme_tx_coal_pkt = v;
3198 if (ifp->if_flags & IFF_RUNNING)
3199 jme_set_tx_coal(sc);
3200 }
3201back:
31f0d5a2 3202 ifnet_deserialize_all(ifp);
2870abc4 3203 return error;
76fbb0b9
SZ		 3204}
3205
3206static int
2870abc4 3207jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3208{
2870abc4
SZ		 3209 struct jme_softc *sc = arg1;
3210 struct ifnet *ifp = &sc->arpcom.ac_if;
3211 int error, v;
3212
31f0d5a2 3213 ifnet_serialize_all(ifp);
2870abc4
SZ		 3214
3215 v = sc->jme_rx_coal_to;
3216 error = sysctl_handle_int(oidp, &v, 0, req);
3217 if (error || req->newptr == NULL)
3218 goto back;
3219
3220 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3221 error = EINVAL;
3222 goto back;
3223 }
3224
3225 if (v != sc->jme_rx_coal_to) {
3226 sc->jme_rx_coal_to = v;
3227 if (ifp->if_flags & IFF_RUNNING)
3228 jme_set_rx_coal(sc);
3229 }
3230back:
31f0d5a2 3231 ifnet_deserialize_all(ifp);
2870abc4 3232 return error;
76fbb0b9
SZ		 3233}
3234
3235static int
2870abc4
SZ		 3236jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3237{
3238 struct jme_softc *sc = arg1;
3239 struct ifnet *ifp = &sc->arpcom.ac_if;
3240 int error, v;
3241
31f0d5a2 3242 ifnet_serialize_all(ifp);
2870abc4
SZ		 3243
3244 v = sc->jme_rx_coal_pkt;
3245 error = sysctl_handle_int(oidp, &v, 0, req);
3246 if (error || req->newptr == NULL)
3247 goto back;
3248
3249 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3250 error = EINVAL;
3251 goto back;
3252 }
3253
3254 if (v != sc->jme_rx_coal_pkt) {
3255 sc->jme_rx_coal_pkt = v;
3256 if (ifp->if_flags & IFF_RUNNING)
3257 jme_set_rx_coal(sc);
3258 }
3259back:
31f0d5a2 3260 ifnet_deserialize_all(ifp);
2870abc4
SZ		 3261 return error;
3262}
3263
3264static void
3265jme_set_tx_coal(struct jme_softc *sc)
3266{
3267 uint32_t reg;
3268
3269 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3270 PCCTX_COAL_TO_MASK;
3271 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3272 PCCTX_COAL_PKT_MASK;
3273 reg |= PCCTX_COAL_TXQ0;
3274 CSR_WRITE_4(sc, JME_PCCTX, reg);
3275}
3276
3277static void
3278jme_set_rx_coal(struct jme_softc *sc)
76fbb0b9 3279{
2870abc4 3280 uint32_t reg;
4447c752 3281 int r;
2870abc4
SZ		 3282
3283 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3284 PCCRX_COAL_TO_MASK;
3285 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3286 PCCRX_COAL_PKT_MASK;
7b040092 3287 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
9f20b7b3 3288 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
76fbb0b9 3289}
9de40864 3290
8a0620e4 3291#ifdef IFPOLL_ENABLE
9de40864
SZ		 3292
3293static void
8a0620e4 3294jme_npoll_status(struct ifnet *ifp, int pollhz __unused)
9de40864
SZ		 3295{
3296 struct jme_softc *sc = ifp->if_softc;
3297 uint32_t status;
3298
31f0d5a2 3299 ASSERT_SERIALIZED(&sc->jme_serialize);
9de40864 3300
8a0620e4
SZ		 3301 status = CSR_READ_4(sc, JME_INTR_STATUS);
3302 if (status & INTR_RXQ_DESC_EMPTY) {
41d0e8e7 3303 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY);
de437f82 3304 jme_rx_restart(sc, status);
8a0620e4
SZ		 3305 }
3306}
0e7f1e6f 3307
8a0620e4
SZ		 3308static void
3309jme_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3310{
3311 struct jme_rxdata *rdata = arg;
3312
3313 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3314
3315 jme_rxeof(rdata, cycle);
3316}
3317
3318static void
9b99c84f 3319jme_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
8a0620e4 3320{
9b99c84f 3321 struct jme_txdata *tdata = arg;
8a0620e4 3322
9b99c84f 3323 ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
8a0620e4 3324
9b99c84f 3325 jme_txeof(tdata);
8a0620e4
SZ		 3326 if (!ifq_is_empty(&ifp->if_snd))
3327 if_devstart(ifp);
3328}
3329
3330static void
3331jme_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3332{
3333 struct jme_softc *sc = ifp->if_softc;
3334
3335 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3336
3337 if (info) {
3338 int i, off;
3339
3340 info->ifpi_status.status_func = jme_npoll_status;
3341 info->ifpi_status.serializer = &sc->jme_serialize;
3342
3343 off = sc->jme_npoll_txoff;
3344 KKASSERT(off <= ncpus2);
3345 info->ifpi_tx[off].poll_func = jme_npoll_tx;
9b99c84f
SZ		 3346 info->ifpi_tx[off].arg = &sc->jme_cdata.jme_tx_data;
3347 info->ifpi_tx[off].serializer =
3348 &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
8a0620e4
SZ		 3349
3350 off = sc->jme_npoll_rxoff;
3351 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
31f0d5a2 3352 struct jme_rxdata *rdata =
8a0620e4
SZ		 3353 &sc->jme_cdata.jme_rx_data[i];
3354 int idx = i + off;
31f0d5a2 3355
8a0620e4
SZ		 3356 info->ifpi_rx[idx].poll_func = jme_npoll_rx;
3357 info->ifpi_rx[idx].arg = rdata;
3358 info->ifpi_rx[idx].serializer =
3359 &rdata->jme_rx_serialize;
31f0d5a2 3360 }
9de40864 3361
8a0620e4
SZ		 3362 if (ifp->if_flags & IFF_RUNNING)
3363 jme_disable_intr(sc);
3364 ifp->if_npoll_cpuid = sc->jme_npoll_txoff;
3365 } else {
3366 if (ifp->if_flags & IFF_RUNNING)
3367 jme_enable_intr(sc);
3368 ifp->if_npoll_cpuid = -1;
3369 }
3370}
9de40864 3371
8a0620e4
SZ		 3372static int
3373jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3374{
3375 struct jme_softc *sc = (void *)arg1;
3376 struct ifnet *ifp = &sc->arpcom.ac_if;
3377 int error, off;
3378
3379 off = sc->jme_npoll_rxoff;
3380 error = sysctl_handle_int(oidp, &off, 0, req);
3381 if (error || req->newptr == NULL)
3382 return error;
3383 if (off < 0)
3384 return EINVAL;
3385
3386 ifnet_serialize_all(ifp);
3387 if (off >= ncpus2 || off % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3388 error = EINVAL;
3389 } else {
3390 error = 0;
3391 sc->jme_npoll_rxoff = off;
3392 }
3393 ifnet_deserialize_all(ifp);
3394
3395 return error;
3396}
3397
3398static int
3399jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3400{
3401 struct jme_softc *sc = (void *)arg1;
3402 struct ifnet *ifp = &sc->arpcom.ac_if;
3403 int error, off;
3404
3405 off = sc->jme_npoll_txoff;
3406 error = sysctl_handle_int(oidp, &off, 0, req);
3407 if (error || req->newptr == NULL)
3408 return error;
3409 if (off < 0)
3410 return EINVAL;
3411
3412 ifnet_serialize_all(ifp);
3413 if (off >= ncpus2) {
3414 error = EINVAL;
3415 } else {
3416 error = 0;
3417 sc->jme_npoll_txoff = off;
9de40864 3418 }
8a0620e4
SZ		 3419 ifnet_deserialize_all(ifp);
3420
3421 return error;
9de40864
SZ		 3422}
3423
8a0620e4 3424#endif /* IFPOLL_ENABLE */
4447c752
SZ		 3425
3426static int
dea2452a 3427jme_rxring_dma_alloc(struct jme_rxdata *rdata)
4447c752 3428{
1128a202 3429 bus_dmamem_t dmem;
ff7f3632 3430 int error, asize;
4447c752 3431
ff7f3632 3432 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
dea2452a 3433 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
1128a202 3434 JME_RX_RING_ALIGN, 0,
0eb220ec 3435 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 3436 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4447c752 3437 if (error) {
dea2452a
SZ		 3438 device_printf(rdata->jme_sc->jme_dev,
3439 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
4447c752
SZ		 3440 return error;
3441 }
1128a202
SZ		 3442 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3443 rdata->jme_rx_ring_map = dmem.dmem_map;
3444 rdata->jme_rx_ring = dmem.dmem_addr;
3445 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
4447c752
SZ		 3446
3447 return 0;
3448}
3449
3450static int
064b75ed
SZ		 3451jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3452{
3453 if ((paddr & 0xffffffff) == 0) {
3454 /*
3455 * Don't allow lower 32bits of the RX buffer's
3456 * physical address to be 0, else it will break
3457 * hardware pending RSS information delivery
3458 * detection on RX path.
3459 */
3460 return 1;
3461 }
3462 return 0;
3463}
3464
3465static int
dea2452a 3466jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
4447c752 3467{
064b75ed 3468 bus_addr_t lowaddr;
4447c752
SZ		 3469 int i, error;
3470
064b75ed
SZ		 3471 lowaddr = BUS_SPACE_MAXADDR;
3472 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3473 /* jme_rxbuf_dma_filter will be called */
3474 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3475 }
3476
4447c752 3477 /* Create tag for Rx buffers. */
dea2452a
SZ		 3478 error = bus_dma_tag_create(
3479 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
4447c752 3480 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
064b75ed 3481 lowaddr, /* lowaddr */
4447c752 3482 BUS_SPACE_MAXADDR, /* highaddr */
064b75ed 3483 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
4447c752
SZ		 3484 MCLBYTES, /* maxsize */
3485 1, /* nsegments */
3486 MCLBYTES, /* maxsegsize */
9d424cee 3487 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
4447c752
SZ		 3488 &rdata->jme_rx_tag);
3489 if (error) {
dea2452a
SZ		 3490 device_printf(rdata->jme_sc->jme_dev,
3491 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
4447c752
SZ		 3492 return error;
3493 }
3494
3495 /* Create DMA maps for Rx buffers. */
9d424cee 3496 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ		 3497 &rdata->jme_rx_sparemap);
3498 if (error) {
dea2452a
SZ		 3499 device_printf(rdata->jme_sc->jme_dev,
3500 "could not create %dth spare Rx dmamap.\n",
3501 rdata->jme_rx_idx);
4447c752
SZ		 3502 bus_dma_tag_destroy(rdata->jme_rx_tag);
3503 rdata->jme_rx_tag = NULL;
3504 return error;
3505 }
7b040092 3506 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ		 3507 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3508
9d424cee 3509 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ		 3510 &rxd->rx_dmamap);
3511 if (error) {
3512 int j;
3513
dea2452a 3514 device_printf(rdata->jme_sc->jme_dev,
4447c752 3515 "could not create %dth Rx dmamap "
dea2452a 3516 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
4447c752
SZ		 3517
3518 for (j = 0; j < i; ++j) {
3519 rxd = &rdata->jme_rxdesc[j];
3520 bus_dmamap_destroy(rdata->jme_rx_tag,
3521 rxd->rx_dmamap);
3522 }
3523 bus_dmamap_destroy(rdata->jme_rx_tag,
3524 rdata->jme_rx_sparemap);
3525 bus_dma_tag_destroy(rdata->jme_rx_tag);
3526 rdata->jme_rx_tag = NULL;
3527 return error;
3528 }
3529 }
3530 return 0;
3531}
3532
3533static void
3534jme_rx_intr(struct jme_softc *sc, uint32_t status)
3535{
eda7db08 3536 int r;
4447c752 3537
7b040092 3538 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31810fb8 3539 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
31f0d5a2 3540
31810fb8 3541 if (status & rdata->jme_rx_coal) {
31f0d5a2 3542 lwkt_s