x86_64: Add setidt(), which setup an IDT entry on the specified cpu
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
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41 */
42
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43//#include "use_npx.h"
44#include "use_isa.h"
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45#include "opt_compat.h"
46#include "opt_cpu.h"
47#include "opt_ddb.h"
48#include "opt_directio.h"
49#include "opt_inet.h"
50#include "opt_ipx.h"
51#include "opt_msgbuf.h"
52#include "opt_swap.h"
53
54#include <sys/param.h>
55#include <sys/systm.h>
56#include <sys/sysproto.h>
57#include <sys/signalvar.h>
58#include <sys/kernel.h>
59#include <sys/linker.h>
60#include <sys/malloc.h>
61#include <sys/proc.h>
895c1f85 62#include <sys/priv.h>
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63#include <sys/buf.h>
64#include <sys/reboot.h>
65#include <sys/mbuf.h>
66#include <sys/msgbuf.h>
67#include <sys/sysent.h>
68#include <sys/sysctl.h>
69#include <sys/vmmeter.h>
70#include <sys/bus.h>
71#include <sys/upcall.h>
72#include <sys/usched.h>
73#include <sys/reg.h>
74
75#include <vm/vm.h>
76#include <vm/vm_param.h>
77#include <sys/lock.h>
78#include <vm/vm_kern.h>
79#include <vm/vm_object.h>
80#include <vm/vm_page.h>
81#include <vm/vm_map.h>
82#include <vm/vm_pager.h>
83#include <vm/vm_extern.h>
84
85#include <sys/thread2.h>
684a93c4 86#include <sys/mplock2.h>
320c681e 87#include <sys/mutex2.h>
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88
89#include <sys/user.h>
90#include <sys/exec.h>
91#include <sys/cons.h>
92
93#include <ddb/ddb.h>
94
95#include <machine/cpu.h>
96#include <machine/clock.h>
97#include <machine/specialreg.h>
98#if JG
99#include <machine/bootinfo.h>
100#endif
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101#include <machine/md_var.h>
102#include <machine/metadata.h>
103#include <machine/pc/bios.h>
104#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
105#include <machine/globaldata.h> /* CPU_prvspace */
106#include <machine/smp.h>
107#ifdef PERFMON
108#include <machine/perfmon.h>
109#endif
110#include <machine/cputypes.h>
57a9c56b 111#include <machine/intr_machdep.h>
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112
113#ifdef OLD_BUS_ARCH
46d4e165 114#include <bus/isa/isa_device.h>
c8fe38ae 115#endif
57a9c56b 116#include <machine_base/isa/isa_intr.h>
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117#include <bus/isa/rtc.h>
118#include <sys/random.h>
119#include <sys/ptrace.h>
120#include <machine/sigframe.h>
121
faaf4131 122#include <sys/machintr.h>
9284cddf 123#include <machine_base/icu/icu_abi.h>
7265a4fe 124#include <machine_base/icu/elcr_var.h>
2e0ed166 125#include <machine_base/apic/lapic.h>
ed4d621d 126#include <machine_base/apic/ioapic.h>
a3dd9120 127#include <machine_base/apic/ioapic_abi.h>
8cc9a8d1 128#include <machine/mptable.h>
faaf4131 129
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130#define PHYSMAP_ENTRIES 10
131
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132extern u_int64_t hammer_time(u_int64_t, u_int64_t);
133
134extern void printcpuinfo(void); /* XXX header file */
135extern void identify_cpu(void);
136#if JG
137extern void finishidentcpu(void);
138#endif
139extern void panicifcpuunsupported(void);
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140
141static void cpu_startup(void *);
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142static void pic_finish(void *);
143static void cpu_finish(void *);
144
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145#ifndef CPU_DISABLE_SSE
146static void set_fpregs_xmm(struct save87 *, struct savexmm *);
147static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
148#endif /* CPU_DISABLE_SSE */
149#ifdef DIRECTIO
150extern void ffs_rawread_setup(void);
151#endif /* DIRECTIO */
152static void init_locks(void);
153
7c006a9e 154SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
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155SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
156SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
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157
158#ifdef DDB
159extern vm_offset_t ksym_start, ksym_end;
160#endif
161
da23a592 162struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
48ffc236 163
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164int _udatasel, _ucodesel, _ucode32sel;
165u_long atdevbase;
166#ifdef SMP
167int64_t tsc_offsets[MAXCPU];
168#else
169int64_t tsc_offsets[1];
170#endif
171
172#if defined(SWTCH_OPTIM_STATS)
173extern int swtch_optim_stats;
174SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
175 CTLFLAG_RD, &swtch_optim_stats, 0, "");
176SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
177 CTLFLAG_RD, &tlb_flush_count, 0, "");
178#endif
179
39d69dae 180long physmem = 0;
c8fe38ae 181
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182u_long ebda_addr = 0;
183
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184int imcr_present = 0;
185
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186int naps = 0; /* # of Applications processors */
187
8936cd9b 188u_int base_memory;
320c681e 189struct mtx dt_lock; /* lock for GDT and LDT */
8936cd9b 190
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191static int
192sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
193{
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194 u_long pmem = ctob(physmem);
195
196 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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197 return (error);
198}
199
39d69dae 200SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 201 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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202
203static int
204sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
205{
206 int error = sysctl_handle_int(oidp, 0,
207 ctob(physmem - vmstats.v_wire_count), req);
208 return (error);
209}
210
211SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
212 0, 0, sysctl_hw_usermem, "IU", "");
213
214static int
215sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
216{
c8fe38ae 217 int error = sysctl_handle_int(oidp, 0,
b2b3ffcd 218 x86_64_btop(avail_end - avail_start), req);
c8fe38ae 219 return (error);
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220}
221
222SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
223 0, 0, sysctl_hw_availpages, "I", "");
224
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225vm_paddr_t Maxmem;
226vm_paddr_t Realmem;
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227
228/*
229 * The number of PHYSMAP entries must be one less than the number of
230 * PHYSSEG entries because the PHYSMAP entry that spans the largest
231 * physical address that is accessible by ISA DMA is split into two
232 * PHYSSEG entries.
233 */
234#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
235
236vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
237vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
238
239/* must be 2 less so 0 0 can signal end of chunks */
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240#define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
241#define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
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242
243static vm_offset_t buffer_sva, buffer_eva;
244vm_offset_t clean_sva, clean_eva;
245static vm_offset_t pager_sva, pager_eva;
246static struct trapframe proc0_tf;
247
248static void
249cpu_startup(void *dummy)
250{
251 caddr_t v;
252 vm_size_t size = 0;
253 vm_offset_t firstaddr;
254
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255 /*
256 * Good {morning,afternoon,evening,night}.
257 */
258 kprintf("%s", version);
259 startrtclock();
260 printcpuinfo();
261 panicifcpuunsupported();
262#ifdef PERFMON
263 perfmon_init();
264#endif
15dc6550 265 kprintf("real memory = %ju (%ju MB)\n",
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266 (intmax_t)Realmem,
267 (intmax_t)Realmem / 1024 / 1024);
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268 /*
269 * Display any holes after the first chunk of extended memory.
270 */
271 if (bootverbose) {
272 int indx;
273
274 kprintf("Physical memory chunk(s):\n");
275 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
276 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
277
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278 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
279 (intmax_t)phys_avail[indx],
280 (intmax_t)phys_avail[indx + 1] - 1,
281 (intmax_t)size1,
282 (intmax_t)(size1 / PAGE_SIZE));
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283 }
284 }
285
286 /*
287 * Allocate space for system data structures.
288 * The first available kernel virtual address is in "v".
289 * As pages of kernel virtual memory are allocated, "v" is incremented.
290 * As pages of memory are allocated and cleared,
291 * "firstaddr" is incremented.
292 * An index into the kernel page table corresponding to the
293 * virtual memory address maintained in "v" is kept in "mapaddr".
294 */
295
296 /*
297 * Make two passes. The first pass calculates how much memory is
298 * needed and allocates it. The second pass assigns virtual
299 * addresses to the various data structures.
300 */
301 firstaddr = 0;
302again:
303 v = (caddr_t)firstaddr;
304
305#define valloc(name, type, num) \
306 (name) = (type *)v; v = (caddr_t)((name)+(num))
307#define valloclim(name, type, num, lim) \
308 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
309
310 /*
311 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
312 * For the first 64MB of ram nominally allocate sufficient buffers to
313 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
314 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
315 * the buffer cache we limit the eventual kva reservation to
316 * maxbcache bytes.
317 *
318 * factor represents the 1/4 x ram conversion.
319 */
320 if (nbuf == 0) {
321 int factor = 4 * BKVASIZE / 1024;
322 int kbytes = physmem * (PAGE_SIZE / 1024);
323
324 nbuf = 50;
325 if (kbytes > 4096)
326 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
327 if (kbytes > 65536)
328 nbuf += (kbytes - 65536) * 2 / (factor * 5);
329 if (maxbcache && nbuf > maxbcache / BKVASIZE)
330 nbuf = maxbcache / BKVASIZE;
331 }
332
333 /*
334 * Do not allow the buffer_map to be more then 1/2 the size of the
335 * kernel_map.
336 */
337 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
338 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
339 kprintf("Warning: nbufs capped at %d\n", nbuf);
340 }
341
342 nswbuf = max(min(nbuf/4, 256), 16);
343#ifdef NSWBUF_MIN
344 if (nswbuf < NSWBUF_MIN)
345 nswbuf = NSWBUF_MIN;
346#endif
347#ifdef DIRECTIO
348 ffs_rawread_setup();
349#endif
350
351 valloc(swbuf, struct buf, nswbuf);
352 valloc(buf, struct buf, nbuf);
353
354 /*
355 * End of first pass, size has been calculated so allocate memory
356 */
357 if (firstaddr == 0) {
358 size = (vm_size_t)(v - firstaddr);
359 firstaddr = kmem_alloc(&kernel_map, round_page(size));
360 if (firstaddr == 0)
361 panic("startup: no room for tables");
362 goto again;
363 }
364
365 /*
366 * End of second pass, addresses have been assigned
367 */
368 if ((vm_size_t)(v - firstaddr) != size)
369 panic("startup: table size inconsistency");
370
371 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
372 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
373 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
374 (nbuf*BKVASIZE));
375 buffer_map.system_map = 1;
376 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
377 (nswbuf*MAXPHYS) + pager_map_size);
378 pager_map.system_map = 1;
379
380#if defined(USERCONFIG)
381 userconfig();
382 cninit(); /* the preferred console may have changed */
383#endif
384
361c5f22 385 kprintf("avail memory = %ju (%ju MB)\n",
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386 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
387 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
388 1024 / 1024);
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389
390 /*
391 * Set up buffers, so they can be used to read disk labels.
392 */
393 bufinit();
394 vm_pager_bufferinit();
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395}
396
397static void
398cpu_finish(void *dummy __unused)
399{
400 cpu_setregs();
401}
402
403static void
404pic_finish(void *dummy __unused)
405{
406 /* Log ELCR information */
407 elcr_dump();
8dc88f05 408
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409 /* Log MPTABLE information */
410 mptable_pci_int_dump();
411
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412 /* Finalize PCI */
413 MachIntrABI.finalize();
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414}
415
416/*
417 * Send an interrupt to process.
418 *
419 * Stack is set up to allow sigcode stored
420 * at top to call routine, followed by kcall
421 * to sigreturn routine below. After sigreturn
422 * resets the signal mask, the stack, and the
423 * frame pointer, it returns to the user
424 * specified pc, psl.
425 */
426void
427sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
428{
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429 struct lwp *lp = curthread->td_lwp;
430 struct proc *p = lp->lwp_proc;
431 struct trapframe *regs;
432 struct sigacts *psp = p->p_sigacts;
433 struct sigframe sf, *sfp;
434 int oonstack;
a6a09809 435 char *sp;
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436
437 regs = lp->lwp_md.md_regs;
438 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
439
a6a09809 440 /* Save user context */
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441 bzero(&sf, sizeof(struct sigframe));
442 sf.sf_uc.uc_sigmask = *mask;
443 sf.sf_uc.uc_stack = lp->lwp_sigstk;
444 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
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445 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
446 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
c8fe38ae 447
a6a09809 448 /* Make the size of the saved context visible to userland */
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449 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
450
c8fe38ae 451 /* Allocate and validate space for the signal handler context. */
4643740a 452 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
c8fe38ae 453 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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454 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
455 sizeof(struct sigframe));
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456 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
457 } else {
89954408
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458 /* We take red zone into account */
459 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
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460 }
461
a6a09809 462 /* Align to 16 bytes */
4117f2fd 463 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
a6a09809 464
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465 /* Translate the signal is appropriate */
466 if (p->p_sysent->sv_sigtbl) {
467 if (sig <= p->p_sysent->sv_sigsize)
468 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
469 }
470
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471 /*
472 * Build the argument list for the signal handler.
473 *
474 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
475 */
476 regs->tf_rdi = sig; /* argument 1 */
477 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
478
c8fe38ae 479 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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480 /*
481 * Signal handler installed with SA_SIGINFO.
482 *
483 * action(signo, siginfo, ucontext)
484 */
485 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
630d9ab4 486 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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487 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
488
489 /* fill siginfo structure */
490 sf.sf_si.si_signo = sig;
491 sf.sf_si.si_code = code;
630d9ab4 492 sf.sf_si.si_addr = (void *)regs->tf_addr;
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493 } else {
494 /*
495 * Old FreeBSD-style arguments.
496 *
497 * handler (signo, code, [uc], addr)
498 */
499 regs->tf_rsi = (register_t)code; /* argument 2 */
630d9ab4 500 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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501 sf.sf_ahu.sf_handler = catcher;
502 }
503
504 /*
505 * If we're a vm86 process, we want to save the segment registers.
506 * We also change eflags to be our emulated eflags, not the actual
507 * eflags.
508 */
509#if JG
510 if (regs->tf_eflags & PSL_VM) {
511 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
512 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
513
514 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
515 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
516 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
517 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
518
519 if (vm86->vm86_has_vme == 0)
520 sf.sf_uc.uc_mcontext.mc_eflags =
521 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
522 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
523
524 /*
525 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
526 * syscalls made by the signal handler. This just avoids
527 * wasting time for our lazy fixup of such faults. PSL_NT
528 * does nothing in vm86 mode, but vm86 programs can set it
529 * almost legitimately in probes for old cpu types.
530 */
531 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
532 }
533#endif
534
535 /*
536 * Save the FPU state and reinit the FP unit
537 */
c8fe38ae 538 npxpush(&sf.sf_uc.uc_mcontext);
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539
540 /*
541 * Copy the sigframe out to the user's stack.
542 */
543 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
544 /*
545 * Something is wrong with the stack pointer.
546 * ...Kill the process.
547 */
548 sigexit(lp, SIGILL);
549 }
550
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551 regs->tf_rsp = (register_t)sfp;
552 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
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553
554 /*
555 * i386 abi specifies that the direction flag must be cleared
556 * on function entry
557 */
5b9f6cc4 558 regs->tf_rflags &= ~(PSL_T|PSL_D);
c8fe38ae 559
c8fe38ae 560 /*
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561 * 64 bit mode has a code and stack selector but
562 * no data or extra selector. %fs and %gs are not
563 * stored in-context.
c8fe38ae 564 */
a6a09809 565 regs->tf_cs = _ucodesel;
c8fe38ae 566 regs->tf_ss = _udatasel;
f2081646 567 clear_quickret();
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568}
569
570/*
571 * Sanitize the trapframe for a virtual kernel passing control to a custom
572 * VM context. Remove any items that would otherwise create a privilage
573 * issue.
574 *
575 * XXX at the moment we allow userland to set the resume flag. Is this a
576 * bad idea?
577 */
578int
579cpu_sanitize_frame(struct trapframe *frame)
580{
c8fe38ae 581 frame->tf_cs = _ucodesel;
c8fe38ae 582 frame->tf_ss = _udatasel;
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583 /* XXX VM (8086) mode not supported? */
584 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
585 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
586
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587 return(0);
588}
589
590/*
591 * Sanitize the tls so loading the descriptor does not blow up
b2b3ffcd 592 * on us. For x86_64 we don't have to do anything.
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593 */
594int
595cpu_sanitize_tls(struct savetls *tls)
596{
597 return(0);
598}
599
600/*
601 * sigreturn(ucontext_t *sigcntxp)
602 *
603 * System call to cleanup state after a signal
604 * has been taken. Reset signal mask and
605 * stack state from context left by sendsig (above).
606 * Return to previous pc and psl as specified by
607 * context left by sendsig. Check carefully to
608 * make sure that the user has not modified the
609 * state to gain improper privileges.
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610 *
611 * MPSAFE
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612 */
613#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
614#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
615
616int
617sys_sigreturn(struct sigreturn_args *uap)
618{
619 struct lwp *lp = curthread->td_lwp;
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620 struct trapframe *regs;
621 ucontext_t uc;
622 ucontext_t *ucp;
5b9f6cc4 623 register_t rflags;
c8fe38ae 624 int cs;
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625 int error;
626
627 /*
628 * We have to copy the information into kernel space so userland
629 * can't modify it while we are sniffing it.
630 */
631 regs = lp->lwp_md.md_regs;
632 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
633 if (error)
634 return (error);
635 ucp = &uc;
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636 rflags = ucp->uc_mcontext.mc_rflags;
637
638 /* VM (8086) mode not supported */
639 rflags &= ~PSL_VM_UNSUPP;
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640
641#if JG
642 if (eflags & PSL_VM) {
643 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
644 struct vm86_kernel *vm86;
645
646 /*
647 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
648 * set up the vm86 area, and we can't enter vm86 mode.
649 */
650 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
651 return (EINVAL);
652 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
653 if (vm86->vm86_inited == 0)
654 return (EINVAL);
655
656 /* go back to user mode if both flags are set */
657 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
658 trapsignal(lp, SIGBUS, 0);
659
660 if (vm86->vm86_has_vme) {
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661 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
662 (eflags & VME_USERCHANGE) | PSL_VM;
c8fe38ae 663 } else {
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664 vm86->vm86_eflags = eflags; /* save VIF, VIP */
665 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
666 (eflags & VM_USERCHANGE) | PSL_VM;
c8fe38ae 667 }
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668 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
669 tf->tf_eflags = eflags;
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670 tf->tf_vm86_ds = tf->tf_ds;
671 tf->tf_vm86_es = tf->tf_es;
672 tf->tf_vm86_fs = tf->tf_fs;
673 tf->tf_vm86_gs = tf->tf_gs;
674 tf->tf_ds = _udatasel;
675 tf->tf_es = _udatasel;
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676 tf->tf_fs = _udatasel;
677 tf->tf_gs = _udatasel;
5b9f6cc4 678 } else
c8fe38ae 679#endif
5b9f6cc4 680 {
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681 /*
682 * Don't allow users to change privileged or reserved flags.
683 */
684 /*
685 * XXX do allow users to change the privileged flag PSL_RF.
686 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
687 * should sometimes set it there too. tf_eflags is kept in
688 * the signal context during signal handling and there is no
689 * other place to remember it, so the PSL_RF bit may be
690 * corrupted by the signal handler without us knowing.
691 * Corruption of the PSL_RF bit at worst causes one more or
692 * one less debugger trap, so allowing it is fairly harmless.
693 */
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694 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
695 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
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696 return(EINVAL);
697 }
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698
699 /*
700 * Don't allow users to load a valid privileged %cs. Let the
701 * hardware check for invalid selectors, excess privilege in
702 * other selectors, invalid %eip's and invalid %esp's.
703 */
704 cs = ucp->uc_mcontext.mc_cs;
705 if (!CS_SECURE(cs)) {
706 kprintf("sigreturn: cs = 0x%x\n", cs);
707 trapsignal(lp, SIGBUS, T_PROTFLT);
708 return(EINVAL);
709 }
5b9f6cc4 710 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
c8fe38ae 711 }
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712
713 /*
714 * Restore the FPU state from the frame
715 */
3919ced0 716 crit_enter();
c8fe38ae 717 npxpop(&ucp->uc_mcontext);
c8fe38ae 718
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719 if (ucp->uc_mcontext.mc_onstack & 1)
720 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
721 else
722 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
723
724 lp->lwp_sigmask = ucp->uc_sigmask;
725 SIG_CANTMASK(lp->lwp_sigmask);
f2081646 726 clear_quickret();
3919ced0 727 crit_exit();
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728 return(EJUSTRETURN);
729}
730
731/*
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732 * Stack frame on entry to function. %rax will contain the function vector,
733 * %rcx will contain the function data. flags, rcx, and rax will have
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734 * already been pushed on the stack.
735 */
736struct upc_frame {
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737 register_t rax;
738 register_t rcx;
739 register_t rdx;
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740 register_t flags;
741 register_t oldip;
742};
743
744void
745sendupcall(struct vmupcall *vu, int morepending)
746{
747 struct lwp *lp = curthread->td_lwp;
748 struct trapframe *regs;
749 struct upcall upcall;
750 struct upc_frame upc_frame;
751 int crit_count = 0;
752
753 /*
754 * If we are a virtual kernel running an emulated user process
755 * context, switch back to the virtual kernel context before
756 * trying to post the signal.
757 */
758 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
759 lp->lwp_md.md_regs->tf_trapno = 0;
760 vkernel_trap(lp, lp->lwp_md.md_regs);
761 }
762
763 /*
764 * Get the upcall data structure
765 */
766 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
767 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
768 ) {
769 vu->vu_pending = 0;
770 kprintf("bad upcall address\n");
771 return;
772 }
773
774 /*
775 * If the data structure is already marked pending or has a critical
776 * section count, mark the data structure as pending and return
777 * without doing an upcall. vu_pending is left set.
778 */
779 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
780 if (upcall.upc_pending < vu->vu_pending) {
781 upcall.upc_pending = vu->vu_pending;
782 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
783 sizeof(upcall.upc_pending));
784 }
785 return;
786 }
787
788 /*
789 * We can run this upcall now, clear vu_pending.
790 *
791 * Bump our critical section count and set or clear the
792 * user pending flag depending on whether more upcalls are
793 * pending. The user will be responsible for calling
794 * upc_dispatch(-1) to process remaining upcalls.
795 */
796 vu->vu_pending = 0;
797 upcall.upc_pending = morepending;
f9235b6d 798 ++crit_count;
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799 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
800 sizeof(upcall.upc_pending));
801 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
802 sizeof(int));
803
804 /*
805 * Construct a stack frame and issue the upcall
806 */
807 regs = lp->lwp_md.md_regs;
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808 upc_frame.rax = regs->tf_rax;
809 upc_frame.rcx = regs->tf_rcx;
810 upc_frame.rdx = regs->tf_rdx;
811 upc_frame.flags = regs->tf_rflags;
812 upc_frame.oldip = regs->tf_rip;
2eddd927 813 if (copyout(&upc_frame, (void *)(regs->tf_rsp - sizeof(upc_frame) - 128),
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814 sizeof(upc_frame)) != 0) {
815 kprintf("bad stack on upcall\n");
816 } else {
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817 regs->tf_rax = (register_t)vu->vu_func;
818 regs->tf_rcx = (register_t)vu->vu_data;
819 regs->tf_rdx = (register_t)lp->lwp_upcall;
820 regs->tf_rip = (register_t)vu->vu_ctx;
2eddd927 821 regs->tf_rsp -= sizeof(upc_frame) + 128;
c8fe38ae 822 }
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823}
824
825/*
826 * fetchupcall occurs in the context of a system call, which means that
827 * we have to return EJUSTRETURN in order to prevent eax and edx from
828 * being overwritten by the syscall return value.
829 *
830 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
831 * and the function pointer in %eax.
832 */
833int
834fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
835{
836 struct upc_frame upc_frame;
837 struct lwp *lp = curthread->td_lwp;
838 struct trapframe *regs;
839 int error;
840 struct upcall upcall;
841 int crit_count;
842
843 regs = lp->lwp_md.md_regs;
844
845 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
846 if (error == 0) {
847 if (vu) {
848 /*
849 * This jumps us to the next ready context.
850 */
851 vu->vu_pending = 0;
852 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
853 crit_count = 0;
854 if (error == 0)
855 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 856 ++crit_count;
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857 if (error == 0)
858 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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859 regs->tf_rax = (register_t)vu->vu_func;
860 regs->tf_rcx = (register_t)vu->vu_data;
861 regs->tf_rdx = (register_t)lp->lwp_upcall;
862 regs->tf_rip = (register_t)vu->vu_ctx;
863 regs->tf_rsp = (register_t)rsp;
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864 } else {
865 /*
866 * This returns us to the originally interrupted code.
867 */
868 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
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869 regs->tf_rax = upc_frame.rax;
870 regs->tf_rcx = upc_frame.rcx;
871 regs->tf_rdx = upc_frame.rdx;
872 regs->tf_rflags = (regs->tf_rflags & ~PSL_USERCHANGE) |
c8fe38ae 873 (upc_frame.flags & PSL_USERCHANGE);
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874 regs->tf_rip = upc_frame.oldip;
875 regs->tf_rsp = (register_t)((char *)rsp + sizeof(upc_frame));
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876 }
877 }
878 if (error == 0)
879 error = EJUSTRETURN;
880 return(error);
881}
882
883/*
884 * Machine dependent boot() routine
885 *
886 * I haven't seen anything to put here yet
887 * Possibly some stuff might be grafted back here from boot()
888 */
889void
890cpu_boot(int howto)
891{
892}
893
894/*
895 * Shutdown the CPU as much as possible
896 */
897void
898cpu_halt(void)
899{
900 for (;;)
901 __asm__ __volatile("hlt");
902}
903
904/*
905 * cpu_idle() represents the idle LWKT. You cannot return from this function
906 * (unless you want to blow things up!). Instead we look for runnable threads
907 * and loop or halt as appropriate. Giant is not held on entry to the thread.
908 *
909 * The main loop is entered with a critical section held, we must release
910 * the critical section before doing anything else. lwkt_switch() will
911 * check for pending interrupts due to entering and exiting its own
912 * critical section.
913 *
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914 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
915 * However, there are cases where the idlethread will be entered with
916 * the possibility that no IPI will occur and in such cases
917 * lwkt_switch() sets TDF_IDLE_NOHLT.
918 *
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919 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
920 * 1 to just use hlt and for debugging purposes.
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921 *
922 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
923 * must occur before it starts using ACPI halt.
c8fe38ae 924 */
46e562ce 925static int cpu_idle_hlt = 2;
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926static int cpu_idle_hltcnt;
927static int cpu_idle_spincnt;
be71787b 928static u_int cpu_idle_repeat = 4;
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929SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
930 &cpu_idle_hlt, 0, "Idle loop HLT enable");
931SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
932 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
933SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
934 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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935SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
936 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
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937
938static void
939cpu_idle_default_hook(void)
940{
941 /*
942 * We must guarentee that hlt is exactly the instruction
943 * following the sti.
944 */
945 __asm __volatile("sti; hlt");
946}
947
948/* Other subsystems (e.g., ACPI) can hook this later. */
949void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
950
951void
952cpu_idle(void)
953{
0f0466c0 954 globaldata_t gd = mycpu;
86232a57 955 struct thread *td __debugvar = gd->gd_curthread;
0f0466c0 956 int reqflags;
be71787b 957 int quick;
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958
959 crit_exit();
f9235b6d 960 KKASSERT(td->td_critcount == 0);
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961 for (;;) {
962 /*
963 * See if there are any LWKTs ready to go.
964 */
965 lwkt_switch();
966
967 /*
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968 * When halting inside a cli we must check for reqflags
969 * races, particularly [re]schedule requests. Running
970 * splz() does the job.
971 *
972 * cpu_idle_hlt:
973 * 0 Never halt, just spin
974 *
975 * 1 Always use HLT (or MONITOR/MWAIT if avail).
976 * This typically eats more power than the
977 * ACPI halt.
978 *
979 * 2 Use HLT/MONITOR/MWAIT up to a point and then
980 * use the ACPI halt (default). This is a hybrid
981 * approach. See machdep.cpu_idle_repeat.
982 *
983 * 3 Always use the ACPI halt. This typically
984 * eats the least amount of power but the cpu
985 * will be slow waking up. Slows down e.g.
986 * compiles and other pipe/event oriented stuff.
987 *
988 * NOTE: Interrupts are enabled and we are not in a critical
989 * section.
990 *
991 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
992 * don't bother capping gd_idle_repeat, it is ok if
993 * it overflows.
c8fe38ae 994 */
be71787b 995 ++gd->gd_idle_repeat;
0f0466c0 996 reqflags = gd->gd_reqflags;
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997 quick = (cpu_idle_hlt == 1) ||
998 (cpu_idle_hlt < 3 &&
999 gd->gd_idle_repeat < cpu_idle_repeat);
1000
1001 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
0f0466c0 1002 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
701c977e 1003 splz(); /* XXX */
0f0466c0 1004 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
be71787b 1005 ++cpu_idle_hltcnt;
0f0466c0 1006 } else if (cpu_idle_hlt) {
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1007 __asm __volatile("cli");
1008 splz();
0f0466c0 1009 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
be71787b 1010 if (quick)
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1011 cpu_idle_default_hook();
1012 else
1013 cpu_idle_hook();
1014 }
7d4d6fdb 1015 __asm __volatile("sti");
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1016 ++cpu_idle_hltcnt;
1017 } else {
c8fe38ae 1018 splz();
c5724852 1019 __asm __volatile("sti");
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1020 ++cpu_idle_spincnt;
1021 }
1022 }
1023}
1024
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1025#ifdef SMP
1026
c8fe38ae 1027/*
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1028 * This routine is called if a spinlock has been held through the
1029 * exponential backoff period and is seriously contested. On a real cpu
1030 * we let it spin.
1031 */
1032void
1033cpu_spinlock_contested(void)
1034{
1035 cpu_pause();
1036}
1037
7ad8cc6c
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1038#endif
1039
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1040/*
1041 * Clear registers on exec
1042 */
1043void
1044exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1045{
1046 struct thread *td = curthread;
1047 struct lwp *lp = td->td_lwp;
1048 struct pcb *pcb = td->td_pcb;
1049 struct trapframe *regs = lp->lwp_md.md_regs;
1050
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1051 /* was i386_user_cleanup() in NetBSD */
1052 user_ldt_free(pcb);
1053
f2081646 1054 clear_quickret();
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1055 bzero((char *)regs, sizeof(struct trapframe));
1056 regs->tf_rip = entry;
1057 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1058 regs->tf_rdi = stack; /* argv */
1059 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1060 regs->tf_ss = _udatasel;
1061 regs->tf_cs = _ucodesel;
1062 regs->tf_rbx = ps_strings;
1063
1064 /*
1065 * Reset the hardware debug registers if they were in use.
1066 * They won't have any meaning for the newly exec'd process.
1067 */
1068 if (pcb->pcb_flags & PCB_DBREGS) {
1069 pcb->pcb_dr0 = 0;
1070 pcb->pcb_dr1 = 0;
1071 pcb->pcb_dr2 = 0;
1072 pcb->pcb_dr3 = 0;
1073 pcb->pcb_dr6 = 0;
0855a2af 1074 pcb->pcb_dr7 = 0; /* JG set bit 10? */
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1075 if (pcb == td->td_pcb) {
1076 /*
1077 * Clear the debug registers on the running
1078 * CPU, otherwise they will end up affecting
1079 * the next process we switch to.
1080 */
1081 reset_dbregs();
1082 }
1083 pcb->pcb_flags &= ~PCB_DBREGS;
1084 }
1085
1086 /*
1087 * Initialize the math emulator (if any) for the current process.
1088 * Actually, just clear the bit that says that the emulator has
1089 * been initialized. Initialization is delayed until the process
1090 * traps to the emulator (if it is done at all) mainly because
1091 * emulators don't provide an entry point for initialization.
1092 */
c8fe38ae 1093 pcb->pcb_flags &= ~FP_SOFTFP;
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1094
1095 /*
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1096 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1097 * gd_npxthread. Otherwise a preemptive interrupt thread
1098 * may panic in npxdna().
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1099 */
1100 crit_enter();
1101 load_cr0(rcr0() | CR0_MP);
1102
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1103 /*
1104 * NOTE: The MSR values must be correct so we can return to
1105 * userland. gd_user_fs/gs must be correct so the switch
1106 * code knows what the current MSR values are.
1107 */
1108 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
c8fe38ae 1109 pcb->pcb_gsbase = 0;
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1110 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1111 mdcpu->gd_user_gs = 0;
1112 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1113 wrmsr(MSR_KGSBASE, 0);
c8fe38ae 1114
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1115 /* Initialize the npx (if any) for the current process. */
1116 npxinit(__INITIAL_NPXCW__);
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1117 crit_exit();
1118
1119 pcb->pcb_ds = _udatasel;
1120 pcb->pcb_es = _udatasel;
1121 pcb->pcb_fs = _udatasel;
1122 pcb->pcb_gs = _udatasel;
1123}
1124
1125void
1126cpu_setregs(void)
1127{
1128 register_t cr0;
1129
1130 cr0 = rcr0();
1131 cr0 |= CR0_NE; /* Done by npxinit() */
1132 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1133 cr0 |= CR0_WP | CR0_AM;
1134 load_cr0(cr0);
1135 load_gs(_udatasel);
1136}
1137
1138static int
1139sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1140{
1141 int error;
1142 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1143 req);
1144 if (!error && req->newptr)
1145 resettodr();
1146 return (error);
1147}
1148
1149SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1150 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1151
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1152SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1153 CTLFLAG_RW, &disable_rtc_set, 0, "");
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1154
1155#if JG
1156SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1157 CTLFLAG_RD, &bootinfo, bootinfo, "");
1158#endif
1159
1160SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1161 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1162
1163extern u_long bootdev; /* not a cdev_t - encoding is different */
1164SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1165 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1166
1167/*
1168 * Initialize 386 and configure to run kernel
1169 */
1170
1171/*
1172 * Initialize segments & interrupt table
1173 */
1174
1175int _default_ldt;
1176struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
8a06c6ee 1177struct gate_descriptor idt_arr[MAXCPU][NIDT];
c8fe38ae
MD
1178#if JG
1179union descriptor ldt[NLDT]; /* local descriptor table */
1180#endif
1181
1182/* table descriptors - used to load tables by cpu */
8a06c6ee
SZ
1183struct region_descriptor r_gdt;
1184struct region_descriptor r_idt_arr[MAXCPU];
c8fe38ae 1185
c8fe38ae
MD
1186/* JG proc0paddr is a virtual address */
1187void *proc0paddr;
1188/* JG alignment? */
1189char proc0paddr_buff[LWKT_THREAD_STACK];
1190
1191
1192/* software prototypes -- in more palatable form */
1193struct soft_segment_descriptor gdt_segs[] = {
1194/* GNULL_SEL 0 Null Descriptor */
1195{ 0x0, /* segment base address */
1196 0x0, /* length */
1197 0, /* segment type */
1198 0, /* segment descriptor priority level */
1199 0, /* segment descriptor present */
1200 0, /* long */
1201 0, /* default 32 vs 16 bit size */
1202 0 /* limit granularity (byte/page units)*/ },
1203/* GCODE_SEL 1 Code Descriptor for kernel */
1204{ 0x0, /* segment base address */
1205 0xfffff, /* length - all address space */
1206 SDT_MEMERA, /* segment type */
1207 SEL_KPL, /* segment descriptor priority level */
1208 1, /* segment descriptor present */
1209 1, /* long */
1210 0, /* default 32 vs 16 bit size */
1211 1 /* limit granularity (byte/page units)*/ },
1212/* GDATA_SEL 2 Data Descriptor for kernel */
1213{ 0x0, /* segment base address */
1214 0xfffff, /* length - all address space */
1215 SDT_MEMRWA, /* segment type */
1216 SEL_KPL, /* segment descriptor priority level */
1217 1, /* segment descriptor present */
1218 1, /* long */
1219 0, /* default 32 vs 16 bit size */
1220 1 /* limit granularity (byte/page units)*/ },
1221/* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1222{ 0x0, /* segment base address */
1223 0xfffff, /* length - all address space */
1224 SDT_MEMERA, /* segment type */
1225 SEL_UPL, /* segment descriptor priority level */
1226 1, /* segment descriptor present */
1227 0, /* long */
1228 1, /* default 32 vs 16 bit size */
1229 1 /* limit granularity (byte/page units)*/ },
1230/* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1231{ 0x0, /* segment base address */
1232 0xfffff, /* length - all address space */
1233 SDT_MEMRWA, /* segment type */
1234 SEL_UPL, /* segment descriptor priority level */
1235 1, /* segment descriptor present */
1236 0, /* long */
1237 1, /* default 32 vs 16 bit size */
1238 1 /* limit granularity (byte/page units)*/ },
1239/* GUCODE_SEL 5 64 bit Code Descriptor for user */
1240{ 0x0, /* segment base address */
1241 0xfffff, /* length - all address space */
1242 SDT_MEMERA, /* segment type */
1243 SEL_UPL, /* segment descriptor priority level */
1244 1, /* segment descriptor present */
1245 1, /* long */
1246 0, /* default 32 vs 16 bit size */
1247 1 /* limit granularity (byte/page units)*/ },
1248/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1249{
1250 0x0, /* segment base address */
b2b3ffcd 1251 sizeof(struct x86_64tss)-1,/* length - all address space */
c8fe38ae
MD
1252 SDT_SYSTSS, /* segment type */
1253 SEL_KPL, /* segment descriptor priority level */
1254 1, /* segment descriptor present */
1255 0, /* long */
1256 0, /* unused - default 32 vs 16 bit size */
1257 0 /* limit granularity (byte/page units)*/ },
1258/* Actually, the TSS is a system descriptor which is double size */
1259{ 0x0, /* segment base address */
1260 0x0, /* length */
1261 0, /* segment type */
1262 0, /* segment descriptor priority level */
1263 0, /* segment descriptor present */
1264 0, /* long */
1265 0, /* default 32 vs 16 bit size */
1266 0 /* limit granularity (byte/page units)*/ },
1267/* GUGS32_SEL 8 32 bit GS Descriptor for user */
1268{ 0x0, /* segment base address */
1269 0xfffff, /* length - all address space */
1270 SDT_MEMRWA, /* segment type */
1271 SEL_UPL, /* segment descriptor priority level */
1272 1, /* segment descriptor present */
1273 0, /* long */
1274 1, /* default 32 vs 16 bit size */
1275 1 /* limit granularity (byte/page units)*/ },
1276};
1277
1278void
8a06c6ee 1279setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
c8fe38ae 1280{
8a06c6ee
SZ
1281 int cpu;
1282
1283 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1284 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1285
1286 ip->gd_looffset = (uintptr_t)func;
1287 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1288 ip->gd_ist = ist;
1289 ip->gd_xx = 0;
1290 ip->gd_type = typ;
1291 ip->gd_dpl = dpl;
1292 ip->gd_p = 1;
1293 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1294 }
c8fe38ae
MD
1295}
1296
8a782434
SZ
1297void
1298setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1299{
1300 struct gate_descriptor *ip;
1301
1302 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d\n", cpu));
1303
1304 ip = &idt_arr[cpu][idx];
1305 ip->gd_looffset = (uintptr_t)func;
1306 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1307 ip->gd_ist = ist;
1308 ip->gd_xx = 0;
1309 ip->gd_type = typ;
1310 ip->gd_dpl = dpl;
1311 ip->gd_p = 1;
1312 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1313}
1314
c8fe38ae
MD
1315#define IDTVEC(name) __CONCAT(X,name)
1316
1317extern inthand_t
1318 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1319 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1320 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1321 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1322 IDTVEC(xmm), IDTVEC(dblfault),
1323 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1324
1325#ifdef DEBUG_INTERRUPTS
1326extern inthand_t *Xrsvdary[256];
1327#endif
1328
1329void
1330sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1331{
1332 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1333 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1334 ssd->ssd_type = sd->sd_type;
1335 ssd->ssd_dpl = sd->sd_dpl;
1336 ssd->ssd_p = sd->sd_p;
1337 ssd->ssd_def32 = sd->sd_def32;
1338 ssd->ssd_gran = sd->sd_gran;
1339}
1340
1341void
1342ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1343{
1344
1345 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1346 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1347 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1348 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1349 sd->sd_type = ssd->ssd_type;
1350 sd->sd_dpl = ssd->ssd_dpl;
1351 sd->sd_p = ssd->ssd_p;
1352 sd->sd_long = ssd->ssd_long;
1353 sd->sd_def32 = ssd->ssd_def32;
1354 sd->sd_gran = ssd->ssd_gran;
1355}
1356
1357void
1358ssdtosyssd(struct soft_segment_descriptor *ssd,
1359 struct system_segment_descriptor *sd)
1360{
1361
1362 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1363 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1364 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1365 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1366 sd->sd_type = ssd->ssd_type;
1367 sd->sd_dpl = ssd->ssd_dpl;
1368 sd->sd_p = ssd->ssd_p;
1369 sd->sd_gran = ssd->ssd_gran;
1370}
1371
c8fe38ae
MD
1372/*
1373 * Populate the (physmap) array with base/bound pairs describing the
1374 * available physical memory in the system, then test this memory and
1375 * build the phys_avail array describing the actually-available memory.
1376 *
1377 * If we cannot accurately determine the physical memory map, then use
1378 * value from the 0xE801 call, and failing that, the RTC.
1379 *
1380 * Total memory size may be set by the kernel environment variable
1381 * hw.physmem or the compile-time define MAXMEM.
1382 *
b4d9abe2
MD
1383 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1384 * of PAGE_SIZE. This also greatly reduces the memory test time
1385 * which would otherwise be excessive on machines with > 8G of ram.
1386 *
c8fe38ae
MD
1387 * XXX first should be vm_paddr_t.
1388 */
b4d9abe2
MD
1389
1390#define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1391#define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1392
c8fe38ae
MD
1393static void
1394getmemsize(caddr_t kmdp, u_int64_t first)
1395{
b4d9abe2
MD
1396 int off, physmap_idx, pa_indx, da_indx;
1397 int i, j;
1398 vm_paddr_t physmap[PHYSMAP_SIZE];
1399 vm_paddr_t pa;
1400 vm_paddr_t msgbuf_size;
c8fe38ae
MD
1401 u_long physmem_tunable;
1402 pt_entry_t *pte;
1403 struct bios_smap *smapbase, *smap, *smapend;
1404 u_int32_t smapsize;
1405 quad_t dcons_addr, dcons_size;
1406
1407 bzero(physmap, sizeof(physmap));
c8fe38ae
MD
1408 physmap_idx = 0;
1409
1410 /*
1411 * get memory map from INT 15:E820, kindly supplied by the loader.
1412 *
1413 * subr_module.c says:
1414 * "Consumer may safely assume that size value precedes data."
1415 * ie: an int32_t immediately precedes smap.
1416 */
1417 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1418 MODINFO_METADATA | MODINFOMD_SMAP);
1419 if (smapbase == NULL)
1420 panic("No BIOS smap info from loader!");
1421
1422 smapsize = *((u_int32_t *)smapbase - 1);
1423 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1424
1425 for (smap = smapbase; smap < smapend; smap++) {
1426 if (boothowto & RB_VERBOSE)
1427 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1428 smap->type, smap->base, smap->length);
1429
1430 if (smap->type != SMAP_TYPE_MEMORY)
1431 continue;
1432
1433 if (smap->length == 0)
1434 continue;
1435
1436 for (i = 0; i <= physmap_idx; i += 2) {
1437 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1438 if (boothowto & RB_VERBOSE) {
1439 kprintf("Overlapping or non-monotonic "
1440 "memory region, ignoring "
1441 "second region\n");
1442 }
2eddd927 1443 break;
c8fe38ae
MD
1444 }
1445 }
2eddd927
MD
1446 if (i <= physmap_idx)
1447 continue;
1448
1bda0d3d 1449 Realmem += smap->length;
c8fe38ae
MD
1450
1451 if (smap->base == physmap[physmap_idx + 1]) {
1452 physmap[physmap_idx + 1] += smap->length;
1453 continue;
1454 }
1455
1456 physmap_idx += 2;
1457 if (physmap_idx == PHYSMAP_SIZE) {
1bda0d3d
MD
1458 kprintf("Too many segments in the physical "
1459 "address map, giving up\n");
c8fe38ae
MD
1460 break;
1461 }
1462 physmap[physmap_idx] = smap->base;
1463 physmap[physmap_idx + 1] = smap->base + smap->length;
1464 }
1465
8936cd9b 1466 base_memory = physmap[1] / 1024;
c8fe38ae
MD
1467#ifdef SMP
1468 /* make hole for AP bootstrap code */
8936cd9b 1469 physmap[1] = mp_bootaddress(base_memory);
2c36eb24 1470#endif
2331304b 1471
927c4c1f
MN
1472 /* Save EBDA address, if any */
1473 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1474 ebda_addr <<= 4;
c8fe38ae
MD
1475
1476 /*
1477 * Maxmem isn't the "maximum memory", it's one larger than the
1478 * highest page of the physical address space. It should be
1479 * called something like "Maxphyspage". We may adjust this
1480 * based on ``hw.physmem'' and the results of the memory test.
1481 */
1482 Maxmem = atop(physmap[physmap_idx + 1]);
1483
1484#ifdef MAXMEM
1485 Maxmem = MAXMEM / 4;
1486#endif
1487
1488 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1489 Maxmem = atop(physmem_tunable);
1490
1491 /*
1492 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1493 * in the system.
1494 */
1495 if (Maxmem > atop(physmap[physmap_idx + 1]))
1496 Maxmem = atop(physmap[physmap_idx + 1]);
1497
8e5ea5f7 1498 /*
b4d9abe2 1499 * Blowing out the DMAP will blow up the system.
8e5ea5f7
MD
1500 */
1501 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1502 kprintf("Limiting Maxmem due to DMAP size\n");
1503 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1504 }
1505
c8fe38ae 1506 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
b4d9abe2 1507 (boothowto & RB_VERBOSE)) {
c8fe38ae 1508 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
b4d9abe2 1509 }
c8fe38ae 1510
b4d9abe2
MD
1511 /*
1512 * Call pmap initialization to make new kernel address space
1513 *
1514 * Mask off page 0.
1515 */
48ffc236 1516 pmap_bootstrap(&first);
b4d9abe2
MD
1517 physmap[0] = PAGE_SIZE;
1518
1519 /*
1520 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1521 * exceeding Maxmem.
1522 */
1523 for (i = j = 0; i <= physmap_idx; i += 2) {
1524 if (physmap[i+1] > ptoa((vm_paddr_t)Maxmem))
1525 physmap[i+1] = ptoa((vm_paddr_t)Maxmem);
1526 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1527 ~PHYSMAP_ALIGN_MASK;
1528 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1529
1530 physmap[j] = physmap[i];
1531 physmap[j+1] = physmap[i+1];
1532
1533 if (physmap[i] < physmap[i+1])
1534 j += 2;
1535 }
1536 physmap_idx = j - 2;
1537
1538 /*
1539 * Align anything else used in the validation loop.
1540 */
1541 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
c8fe38ae
MD
1542
1543 /*
1544 * Size up each available chunk of physical memory.
1545 */
c8fe38ae
MD
1546 pa_indx = 0;
1547 da_indx = 1;
1548 phys_avail[pa_indx++] = physmap[0];
1549 phys_avail[pa_indx] = physmap[0];
1550 dump_avail[da_indx] = physmap[0];
1551 pte = CMAP1;
1552
1553 /*
1554 * Get dcons buffer address
1555 */
1556 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1557 kgetenv_quad("dcons.size", &dcons_size) == 0)
1558 dcons_addr = 0;
1559
1560 /*
b4d9abe2
MD
1561 * Validate the physical memory. The physical memory segments
1562 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1563 * of PAGE_SIZE.
c8fe38ae
MD
1564 */
1565 for (i = 0; i <= physmap_idx; i += 2) {
1566 vm_paddr_t end;
1567
b4d9abe2
MD
1568 end = physmap[i + 1];
1569
1570 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
c8fe38ae
MD
1571 int tmp, page_bad, full;
1572 int *ptr = (int *)CADDR1;
1573
1574 full = FALSE;
1575 /*
1576 * block out kernel memory as not available.
1577 */
1578 if (pa >= 0x100000 && pa < first)
1579 goto do_dump_avail;
1580
1581 /*
1582 * block out dcons buffer
1583 */
1584 if (dcons_addr > 0
1585 && pa >= trunc_page(dcons_addr)
b4d9abe2 1586 && pa < dcons_addr + dcons_size) {
c8fe38ae 1587 goto do_dump_avail;
b4d9abe2 1588 }
c8fe38ae
MD
1589
1590 page_bad = FALSE;
1591
1592 /*
1593 * map page into kernel: valid, read/write,non-cacheable
1594 */
1595 *pte = pa | PG_V | PG_RW | PG_N;
1596 cpu_invltlb();
1597
1598 tmp = *(int *)ptr;
1599 /*
1600 * Test for alternating 1's and 0's
1601 */
1602 *(volatile int *)ptr = 0xaaaaaaaa;
b4d9abe2 1603 cpu_mfence();
c8fe38ae
MD
1604 if (*(volatile int *)ptr != 0xaaaaaaaa)
1605 page_bad = TRUE;
1606 /*
1607 * Test for alternating 0's and 1's
1608 */
1609 *(volatile int *)ptr = 0x55555555;
b4d9abe2 1610 cpu_mfence();
c8fe38ae
MD
1611 if (*(volatile int *)ptr != 0x55555555)
1612 page_bad = TRUE;
1613 /*
1614 * Test for all 1's
1615 */
1616 *(volatile int *)ptr = 0xffffffff;
b4d9abe2 1617 cpu_mfence();
c8fe38ae
MD
1618 if (*(volatile int *)ptr != 0xffffffff)
1619 page_bad = TRUE;
1620 /*
1621 * Test for all 0's
1622 */
1623 *(volatile int *)ptr = 0x0;
b4d9abe2 1624 cpu_mfence();
c8fe38ae
MD
1625 if (*(volatile int *)ptr != 0x0)
1626 page_bad = TRUE;
1627 /*
1628 * Restore original value.
1629 */
1630 *(int *)ptr = tmp;
1631
1632 /*
1633 * Adjust array of valid/good pages.
1634 */
1635 if (page_bad == TRUE)
1636 continue;
1637 /*
1638 * If this good page is a continuation of the
1639 * previous set of good pages, then just increase
1640 * the end pointer. Otherwise start a new chunk.
1641 * Note that "end" points one higher than end,
1642 * making the range >= start and < end.
1643 * If we're also doing a speculative memory
1644 * test and we at or past the end, bump up Maxmem
1645 * so that we keep going. The first bad page
1646 * will terminate the loop.
1647 */
1648 if (phys_avail[pa_indx] == pa) {
b4d9abe2 1649 phys_avail[pa_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1650 } else {
1651 pa_indx++;
1652 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1653 kprintf(
1654 "Too many holes in the physical address space, giving up\n");
1655 pa_indx--;
1656 full = TRUE;
1657 goto do_dump_avail;
1658 }
b4d9abe2
MD
1659 phys_avail[pa_indx++] = pa;
1660 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae 1661 }
7a3eee88 1662 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
c8fe38ae
MD
1663do_dump_avail:
1664 if (dump_avail[da_indx] == pa) {
b4d9abe2 1665 dump_avail[da_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1666 } else {
1667 da_indx++;
1668 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1669 da_indx--;
1670 goto do_next;
1671 }
b4d9abe2
MD
1672 dump_avail[da_indx++] = pa;
1673 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1674 }
1675do_next:
1676 if (full)
1677 break;
1678 }
1679 }
1680 *pte = 0;
1681 cpu_invltlb();
1682
1683 /*
c8fe38ae
MD
1684 * The last chunk must contain at least one page plus the message
1685 * buffer to avoid complicating other code (message buffer address
1686 * calculation, etc.).
1687 */
b4d9abe2
MD
1688 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1689
1690 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1691 msgbuf_size >= phys_avail[pa_indx]) {
c8fe38ae
MD
1692 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1693 phys_avail[pa_indx--] = 0;
1694 phys_avail[pa_indx--] = 0;
1695 }
1696
1697 Maxmem = atop(phys_avail[pa_indx]);
1698
1699 /* Trim off space for the message buffer. */
b4d9abe2 1700 phys_avail[pa_indx] -= msgbuf_size;
c8fe38ae 1701
1185babf
JG
1702 avail_end = phys_avail[pa_indx];
1703
c8fe38ae 1704 /* Map the message buffer. */
b4d9abe2
MD
1705 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1706 pmap_kenter((vm_offset_t)msgbufp + off,
1707 phys_avail[pa_indx] + off);
1708 }
c8fe38ae
MD
1709}
1710
faaf4131
MN
1711struct machintr_abi MachIntrABI;
1712
c8fe38ae
MD
1713/*
1714 * IDT VECTORS:
1715 * 0 Divide by zero
1716 * 1 Debug
1717 * 2 NMI
1718 * 3 BreakPoint
1719 * 4 OverFlow
1720 * 5 Bound-Range
1721 * 6 Invalid OpCode
1722 * 7 Device Not Available (x87)
1723 * 8 Double-Fault
1724 * 9 Coprocessor Segment overrun (unsupported, reserved)
1725 * 10 Invalid-TSS
1726 * 11 Segment not present
1727 * 12 Stack
1728 * 13 General Protection
1729 * 14 Page Fault
1730 * 15 Reserved
1731 * 16 x87 FP Exception pending
1732 * 17 Alignment Check
1733 * 18 Machine Check
1734 * 19 SIMD floating point
1735 * 20-31 reserved
1736 * 32-255 INTn/external sources
1737 */
1738u_int64_t
1739hammer_time(u_int64_t modulep, u_int64_t physfree)
1740{
1741 caddr_t kmdp;
8a06c6ee 1742 int gsel_tss, x, cpu;
5b9f6cc4
MD
1743#if JG
1744 int metadata_missing, off;
1745#endif
c8fe38ae
MD
1746 struct mdglobaldata *gd;
1747 u_int64_t msr;
c8fe38ae 1748
c8fe38ae
MD
1749 /*
1750 * Prevent lowering of the ipl if we call tsleep() early.
1751 */
1752 gd = &CPU_prvspace[0].mdglobaldata;
1753 bzero(gd, sizeof(*gd));
1754
1755 /*
1756 * Note: on both UP and SMP curthread must be set non-NULL
1757 * early in the boot sequence because the system assumes
1758 * that 'curthread' is never NULL.
1759 */
1760
1761 gd->mi.gd_curthread = &thread0;
1762 thread0.td_gd = &gd->mi;
1763
1764 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1765
1766#if JG
1767 metadata_missing = 0;
1768 if (bootinfo.bi_modulep) {
1769 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1770 preload_bootstrap_relocate(KERNBASE);
1771 } else {
1772 metadata_missing = 1;
1773 }
1774 if (bootinfo.bi_envp)
1775 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1776#endif
1777
1778 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1779 preload_bootstrap_relocate(PTOV_OFFSET);
1780 kmdp = preload_search_by_type("elf kernel");
1781 if (kmdp == NULL)
1782 kmdp = preload_search_by_type("elf64 kernel");
1783 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1784 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1785#ifdef DDB
1786 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1787 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1788#endif
1789
27af435a
SZ
1790 if (boothowto & RB_VERBOSE)
1791 bootverbose++;
1792
c8fe38ae 1793 /*
10db3cc6 1794 * Default MachIntrABI to ICU
faaf4131
MN
1795 */
1796 MachIntrABI = MachIntrABI_ICU;
9a4bd8f3 1797
d745d2b8
SZ
1798 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1799 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2e0ed166 1800 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
faaf4131
MN
1801
1802 /*
c8fe38ae
MD
1803 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1804 * and ncpus_fit_mask remain 0.
1805 */
1806 ncpus = 1;
1807 ncpus2 = 1;
1808 ncpus_fit = 1;
1809 /* Init basic tunables, hz etc */
1810 init_param1();
1811
1812 /*
1813 * make gdt memory segments
1814 */
1815 gdt_segs[GPROC0_SEL].ssd_base =
1816 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1817
1818 gd->mi.gd_prvspace = &CPU_prvspace[0];
1819
1820 for (x = 0; x < NGDT; x++) {
1821 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1822 ssdtosd(&gdt_segs[x], &gdt[x]);
1823 }
1824 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1825 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
48ffc236 1826
c8fe38ae
MD
1827 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1828 r_gdt.rd_base = (long) gdt;
1829 lgdt(&r_gdt);
1830
1831 wrmsr(MSR_FSBASE, 0); /* User value */
1832 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1833 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1834
1835 mi_gdinit(&gd->mi, 0);
1836 cpu_gdinit(gd, 0);
1837 proc0paddr = proc0paddr_buff;
1838 mi_proc0init(&gd->mi, proc0paddr);
1839 safepri = TDPRI_MAX;
1840
1841 /* spinlocks and the BGL */
1842 init_locks();
1843
1844 /* exceptions */
1845 for (x = 0; x < NIDT; x++)
8a06c6ee
SZ
1846 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1847 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1848 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1849 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1850 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1851 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1852 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1853 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1854 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1855 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1856 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1857 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1858 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1859 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1860 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1861 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1862 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1863 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1864 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1865 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1866
1867 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1868 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
1869 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
1870 }
1871
1872 lidt(&r_idt_arr[0]);
c8fe38ae
MD
1873
1874 /*
1875 * Initialize the console before we print anything out.
1876 */
1877 cninit();
1878
1879#if JG
1880 if (metadata_missing)
1881 kprintf("WARNING: loader(8) metadata is missing!\n");
1882#endif
1883
1884#if NISA >0
e24dd6e0 1885 elcr_probe();
c8fe38ae
MD
1886 isa_defaultirq();
1887#endif
1888 rand_initialize();
1889
a3dd9120
SZ
1890 /*
1891 * Initialize IRQ mapping
1892 *
1893 * NOTE:
1894 * SHOULD be after elcr_probe()
1895 */
1896 MachIntrABI_ICU.initmap();
a3dd9120 1897 MachIntrABI_IOAPIC.initmap();
a3dd9120 1898
c8fe38ae
MD
1899#ifdef DDB
1900 kdb_init();
1901 if (boothowto & RB_KDB)
1902 Debugger("Boot flags requested debugger");
1903#endif
1904
1905#if JG
1906 finishidentcpu(); /* Final stage of CPU initialization */
2883d2d8
MD
1907 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1908 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
c8fe38ae
MD
1909#endif
1910 identify_cpu(); /* Final stage of CPU initialization */
1911 initializecpu(); /* Initialize CPU registers */
1912
1913 /* make an initial tss so cpu can get interrupt stack on syscall! */
5b9f6cc4
MD
1914 gd->gd_common_tss.tss_rsp0 =
1915 (register_t)(thread0.td_kstack +
1916 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
c8fe38ae 1917 /* Ensure the stack is aligned to 16 bytes */
2883d2d8 1918 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
c8fe38ae 1919
093565f2
MD
1920 /* double fault stack */
1921 gd->gd_common_tss.tss_ist1 =
1922 (long)&gd->mi.gd_prvspace->idlestack[
1923 sizeof(gd->mi.gd_prvspace->idlestack)];
c8fe38ae
MD
1924
1925 /* Set the IO permission bitmap (empty due to tss seg limit) */
b2b3ffcd 1926 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
c8fe38ae
MD
1927
1928 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1929 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1930 gd->gd_common_tssd = *gd->gd_tss_gdt;
1931 ltr(gsel_tss);
1932
1933 /* Set up the fast syscall stuff */
1934 msr = rdmsr(MSR_EFER) | EFER_SCE;
1935 wrmsr(MSR_EFER, msr);
1936 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1937 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1938 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1939 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1940 wrmsr(MSR_STAR, msr);
3338cc67 1941 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
c8fe38ae
MD
1942
1943 getmemsize(kmdp, physfree);
1944 init_param2(physmem);
1945
1946 /* now running on new page tables, configured,and u/iom is accessible */
1947
1948 /* Map the message buffer. */
1949#if JG
1950 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1951 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1952#endif
1953
1954 msgbufinit(msgbufp, MSGBUF_SIZE);
1955
1956
1957 /* transfer to user mode */
1958
1959 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1960 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1961 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1962
1963 load_ds(_udatasel);
1964 load_es(_udatasel);
1965 load_fs(_udatasel);
1966
1967 /* setup proc 0's pcb */
1968 thread0.td_pcb->pcb_flags = 0;
c8fe38ae 1969 thread0.td_pcb->pcb_cr3 = KPML4phys;
c8fe38ae 1970 thread0.td_pcb->pcb_ext = 0;
d1368d1a 1971 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
c8fe38ae
MD
1972
1973 /* Location of kernel stack for locore */
1974 return ((u_int64_t)thread0.td_pcb);
1975}
1976
1977/*
1978 * Initialize machine-dependant portions of the global data structure.
1979 * Note that the global data area and cpu0's idlestack in the private
1980 * data space were allocated in locore.
1981 *
1982 * Note: the idlethread's cpl is 0
1983 *
1984 * WARNING! Called from early boot, 'mycpu' may not work yet.
1985 */
1986void
1987cpu_gdinit(struct mdglobaldata *gd, int cpu)
1988{
1989 if (cpu)
1990 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
1991
1992 lwkt_init_thread(&gd->mi.gd_idlethread,
1993 gd->mi.gd_prvspace->idlestack,
1994 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 1995 0, &gd->mi);
c8fe38ae
MD
1996 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
1997 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
1998 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
1999 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2000}
2001
2002int
2003is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2004{
2005 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2006 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2007 return (TRUE);
2008 }
616516c8
MD
2009 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2010 return (TRUE);
c8fe38ae
MD
2011 return (FALSE);
2012}
2013
2014struct globaldata *
2015globaldata_find(int cpu)
2016{
2017 KKASSERT(cpu >= 0 && cpu < ncpus);
2018 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2019}
2020
c8fe38ae
MD
2021int
2022ptrace_set_pc(struct lwp *lp, unsigned long addr)
2023{
5b9f6cc4 2024 lp->lwp_md.md_regs->tf_rip = addr;
c8fe38ae
MD
2025 return (0);
2026}
2027
2028int
2029ptrace_single_step(struct lwp *lp)
2030{
5b9f6cc4 2031 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
c8fe38ae
MD
2032 return (0);
2033}
2034
2035int
2036fill_regs(struct lwp *lp, struct reg *regs)
2037{
c8fe38ae
MD
2038 struct trapframe *tp;
2039
d64d3805
MD
2040 if ((tp = lp->lwp_md.md_regs) == NULL)
2041 return EINVAL;
5b9f6cc4 2042 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
c8fe38ae
MD
2043 return (0);
2044}
2045
2046int
2047set_regs(struct lwp *lp, struct reg *regs)
2048{
c8fe38ae
MD
2049 struct trapframe *tp;
2050
2051 tp = lp->lwp_md.md_regs;
5b9f6cc4 2052 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
c8fe38ae
MD
2053 !CS_SECURE(regs->r_cs))
2054 return (EINVAL);
5b9f6cc4 2055 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
f2081646 2056 clear_quickret();
c8fe38ae
MD
2057 return (0);
2058}
2059
2060#ifndef CPU_DISABLE_SSE
2061static void
2062fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2063{
2064 struct env87 *penv_87 = &sv_87->sv_env;
2065 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2066 int i;
2067
2068 /* FPU control/status */
2069 penv_87->en_cw = penv_xmm->en_cw;
2070 penv_87->en_sw = penv_xmm->en_sw;
2071 penv_87->en_tw = penv_xmm->en_tw;
2072 penv_87->en_fip = penv_xmm->en_fip;
2073 penv_87->en_fcs = penv_xmm->en_fcs;
2074 penv_87->en_opcode = penv_xmm->en_opcode;
2075 penv_87->en_foo = penv_xmm->en_foo;
2076 penv_87->en_fos = penv_xmm->en_fos;
2077
2078 /* FPU registers */
2079 for (i = 0; i < 8; ++i)
2080 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
c8fe38ae
MD
2081}
2082
2083static void
2084set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2085{
2086 struct env87 *penv_87 = &sv_87->sv_env;
2087 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2088 int i;
2089
2090 /* FPU control/status */
2091 penv_xmm->en_cw = penv_87->en_cw;
2092 penv_xmm->en_sw = penv_87->en_sw;
2093 penv_xmm->en_tw = penv_87->en_tw;
2094 penv_xmm->en_fip = penv_87->en_fip;
2095 penv_xmm->en_fcs = penv_87->en_fcs;
2096 penv_xmm->en_opcode = penv_87->en_opcode;
2097 penv_xmm->en_foo = penv_87->en_foo;
2098 penv_xmm->en_fos = penv_87->en_fos;
2099
2100 /* FPU registers */
2101 for (i = 0; i < 8; ++i)
2102 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
c8fe38ae
MD
2103}
2104#endif /* CPU_DISABLE_SSE */
2105
2106int
2107fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2108{
d64d3805
MD
2109 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2110 return EINVAL;
c8fe38ae
MD
2111#ifndef CPU_DISABLE_SSE
2112 if (cpu_fxsr) {
2113 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2114 (struct save87 *)fpregs);
2115 return (0);
2116 }
2117#endif /* CPU_DISABLE_SSE */
2118 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2119 return (0);
2120}
2121
2122int
2123set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2124{
2125#ifndef CPU_DISABLE_SSE
2126 if (cpu_fxsr) {
2127 set_fpregs_xmm((struct save87 *)fpregs,
2128 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2129 return (0);
2130 }
2131#endif /* CPU_DISABLE_SSE */
2132 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2133 return (0);
2134}
2135
2136int
2137fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2138{
d64d3805
MD
2139 struct pcb *pcb;
2140
c8fe38ae 2141 if (lp == NULL) {
0855a2af
JG
2142 dbregs->dr[0] = rdr0();
2143 dbregs->dr[1] = rdr1();
2144 dbregs->dr[2] = rdr2();
2145 dbregs->dr[3] = rdr3();
2146 dbregs->dr[4] = rdr4();
2147 dbregs->dr[5] = rdr5();
2148 dbregs->dr[6] = rdr6();
2149 dbregs->dr[7] = rdr7();
d64d3805 2150 return (0);
c8fe38ae 2151 }
d64d3805
MD
2152 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2153 return EINVAL;
2154 dbregs->dr[0] = pcb->pcb_dr0;
2155 dbregs->dr[1] = pcb->pcb_dr1;
2156 dbregs->dr[2] = pcb->pcb_dr2;
2157 dbregs->dr[3] = pcb->pcb_dr3;
2158 dbregs->dr[4] = 0;
2159 dbregs->dr[5] = 0;
2160 dbregs->dr[6] = pcb->pcb_dr6;
2161 dbregs->dr[7] = pcb->pcb_dr7;
c8fe38ae
MD
2162 return (0);
2163}
2164
2165int
2166set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2167{
2168 if (lp == NULL) {
0855a2af
JG
2169 load_dr0(dbregs->dr[0]);
2170 load_dr1(dbregs->dr[1]);
2171 load_dr2(dbregs->dr[2]);
2172 load_dr3(dbregs->dr[3]);
2173 load_dr4(dbregs->dr[4]);
2174 load_dr5(dbregs->dr[5]);
2175 load_dr6(dbregs->dr[6]);
2176 load_dr7(dbregs->dr[7]);
c8fe38ae
MD
2177 } else {
2178 struct pcb *pcb;
2179 struct ucred *ucred;
2180 int i;
0855a2af 2181 uint64_t mask1, mask2;
c8fe38ae
MD
2182
2183 /*
2184 * Don't let an illegal value for dr7 get set. Specifically,
2185 * check for undefined settings. Setting these bit patterns
2186 * result in undefined behaviour and can lead to an unexpected
2187 * TRCTRAP.
2188 */
0855a2af
JG
2189 /* JG this loop looks unreadable */
2190 /* Check 4 2-bit fields for invalid patterns.
2191 * These fields are R/Wi, for i = 0..3
2192 */
2193 /* Is 10 in LENi allowed when running in compatibility mode? */
2194 /* Pattern 10 in R/Wi might be used to indicate
2195 * breakpoint on I/O. Further analysis should be
2196 * carried to decide if it is safe and useful to
2197 * provide access to that capability
2198 */
2199 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2200 i++, mask1 <<= 4, mask2 <<= 4)
2201 if ((dbregs->dr[7] & mask1) == mask2)
c8fe38ae 2202 return (EINVAL);
c8fe38ae
MD
2203
2204 pcb = lp->lwp_thread->td_pcb;
2205 ucred = lp->lwp_proc->p_ucred;
2206
2207 /*
2208 * Don't let a process set a breakpoint that is not within the
2209 * process's address space. If a process could do this, it
2210 * could halt the system by setting a breakpoint in the kernel
2211 * (if ddb was enabled). Thus, we need to check to make sure
2212 * that no breakpoints are being enabled for addresses outside
2213 * process's address space, unless, perhaps, we were called by
2214 * uid 0.
2215 *
2216 * XXX - what about when the watched area of the user's
2217 * address space is written into from within the kernel
2218 * ... wouldn't that still cause a breakpoint to be generated
2219 * from within kernel mode?
2220 */
2221
895c1f85 2222 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
0855a2af 2223 if (dbregs->dr[7] & 0x3) {
c8fe38ae 2224 /* dr0 is enabled */
0855a2af 2225 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2226 return (EINVAL);
2227 }
2228
0855a2af 2229 if (dbregs->dr[7] & (0x3<<2)) {
c8fe38ae 2230 /* dr1 is enabled */
0855a2af 2231 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2232 return (EINVAL);
2233 }
2234
0855a2af 2235 if (dbregs->dr[7] & (0x3<<4)) {
c8fe38ae 2236 /* dr2 is enabled */
0855a2af 2237 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2238 return (EINVAL);
2239 }
2240
0855a2af 2241 if (dbregs->dr[7] & (0x3<<6)) {
c8fe38ae 2242 /* dr3 is enabled */
0855a2af 2243 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2244 return (EINVAL);
2245 }
c8fe38ae
MD
2246 }
2247
0855a2af
JG
2248 pcb->pcb_dr0 = dbregs->dr[0];
2249 pcb->pcb_dr1 = dbregs->dr[1];
2250 pcb->pcb_dr2 = dbregs->dr[2];
2251 pcb->pcb_dr3 = dbregs->dr[3];
2252 pcb->pcb_dr6 = dbregs->dr[6];
2253 pcb->pcb_dr7 = dbregs->dr[7];
c8fe38ae
MD
2254
2255 pcb->pcb_flags |= PCB_DBREGS;
2256 }
2257
2258 return (0);
2259}
2260
2261/*
2262 * Return > 0 if a hardware breakpoint has been hit, and the
2263 * breakpoint was in user space. Return 0, otherwise.
2264 */
2265int
2266user_dbreg_trap(void)
2267{
0855a2af
JG
2268 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2269 u_int64_t bp; /* breakpoint bits extracted from dr6 */
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MD
2270 int nbp; /* number of breakpoints that triggered */
2271 caddr_t addr[4]; /* breakpoint addresses */
2272 int i;
2273
2274 dr7 = rdr7();
0855a2af 2275 if ((dr7 & 0xff) == 0) {
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MD
2276 /*
2277 * all GE and LE bits in the dr7 register are zero,
2278 * thus the trap couldn't have been caused by the
2279 * hardware debug registers
2280 */
2281 return 0;
2282 }
2283
2284 nbp = 0;
2285 dr6 = rdr6();
0855a2af 2286 bp = dr6 & 0xf;
c8fe38ae 2287
0855a2af 2288 if (bp == 0) {
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2289 /*
2290 * None of the breakpoint bits are set meaning this
2291 * trap was not caused by any of the debug registers
2292 */
2293 return 0;
2294 }
2295
2296 /*
2297 * at least one of the breakpoints were hit, check to see
2298 * which ones and if any of them are user space addresses
2299 */
2300
2301 if (bp & 0x01) {
2302 addr[nbp++] = (caddr_t)rdr0();
2303 }
2304 if (bp & 0x02) {
2305 addr[nbp++] = (caddr_t)rdr1();
2306 }
2307 if (bp & 0x04) {
2308 addr[nbp++] = (caddr_t)rdr2();
2309 }
2310 if (bp & 0x08) {
2311 addr[nbp++] = (caddr_t)rdr3();
2312 }
2313
2314 for (i=0; i<nbp; i++) {
2315 if (addr[i] <
2316 (caddr_t)VM_MAX_USER_ADDRESS) {
2317 /*
2318 * addr[i] is in user space
2319 */
2320 return nbp;
2321 }
2322 }
2323
2324 /*
2325 * None of the breakpoints are in user space.
2326 */
2327 return 0;
2328}
2329
2330
2331#ifndef DDB
2332void
2333Debugger(const char *msg)
2334{
2335 kprintf("Debugger(\"%s\") called.\n", msg);
2336}
2337#endif /* no DDB */
2338
2339#ifdef DDB
2340
2341/*
2342 * Provide inb() and outb() as functions. They are normally only
2343 * available as macros calling inlined functions, thus cannot be
2344 * called inside DDB.
2345 *
2346 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2347 */
2348
2349#undef inb
2350#undef outb
2351
2352/* silence compiler warnings */
2353u_char inb(u_int);
2354void outb(u_int, u_char);
2355
2356u_char
2357inb(u_int port)
2358{
2359 u_char data;
2360 /*
2361 * We use %%dx and not %1 here because i/o is done at %dx and not at
2362 * %edx, while gcc generates inferior code (movw instead of movl)
2363 * if we tell it to load (u_short) port.
2364 */
2365 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2366 return (data);
2367}
2368
2369void
2370outb(u_int port, u_char data)
2371{
2372 u_char al;
2373 /*
2374 * Use an unnecessary assignment to help gcc's register allocator.
2375 * This make a large difference for gcc-1.40 and a tiny difference
2376 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2377 * best results. gcc-2.6.0 can't handle this.
2378 */
2379 al = data;
2380 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2381}
2382
2383#endif /* DDB */
2384
2385
2386
2387#include "opt_cpu.h"
2388
2389
2390/*
2391 * initialize all the SMP locks
2392 */
2393
2394/* critical region when masking or unmasking interupts */
2395struct spinlock_deprecated imen_spinlock;
2396
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MD
2397/* critical region for old style disable_intr/enable_intr */
2398struct spinlock_deprecated mpintr_spinlock;
2399
2400/* critical region around INTR() routines */
2401struct spinlock_deprecated intr_spinlock;
2402
2403/* lock region used by kernel profiling */
2404struct spinlock_deprecated mcount_spinlock;
2405
2406/* locks com (tty) data/hardware accesses: a FASTINTR() */
2407struct spinlock_deprecated com_spinlock;
2408
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MD
2409/* lock regions around the clock hardware */
2410struct spinlock_deprecated clock_spinlock;
2411
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2412static void
2413init_locks(void)
2414{
b5d16701 2415#ifdef SMP
c8fe38ae 2416 /*
b5d16701 2417 * Get the initial mplock with a count of 1 for the BSP.
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MD
2418 * This uses a LOGICAL cpu ID, ie BSP == 0.
2419 */
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MD
2420 cpu_get_initial_mplock();
2421#endif
2422 /* DEPRECATED */
2423 spin_lock_init(&mcount_spinlock);
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MD
2424 spin_lock_init(&intr_spinlock);
2425 spin_lock_init(&mpintr_spinlock);
2426 spin_lock_init(&imen_spinlock);
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MD
2427 spin_lock_init(&com_spinlock);
2428 spin_lock_init(&clock_spinlock);
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MD
2429
2430 /* our token pool needs to work early */
2431 lwkt_token_pool_init();
2432}
2433