MP Implementation 1/2: Get the APIC code working again, sweetly integrate the
[dragonfly.git] / sys / i386 / include / smptests.h
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/include/smptests.h,v 1.33.2.1 2000/05/16 06:58:10 dillon Exp $
8a8d5d85 26 * $DragonFly: src/sys/i386/include/Attic/smptests.h,v 1.3 2003/07/06 21:23:49 dillon Exp $
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27 */
28
29#ifndef _MACHINE_SMPTESTS_H_
30#define _MACHINE_SMPTESTS_H_
31
32
33/*
34 * Various 'tests in progress' and configuration parameters.
35 */
36
37
38/*
39 * Tor's clock improvements.
40 *
41 * When the giant kernel lock disappears, a different strategy should
42 * probably be used, thus this patch can only be considered a temporary
43 * measure.
44 *
45 * This patch causes (NCPU-1)*(128+100) extra IPIs per second.
46 * During profiling, the number is (NCPU-1)*(1024+100) extra IPIs/s
47 * in addition to extra IPIs due to forwarding ASTs to other CPUs.
48 *
49 * Having a shared AST flag in an SMP configuration is wrong, and I've
50 * just kludged around it, based upon the kernel lock blocking other
51 * processors from entering the kernel while handling an AST for one
52 * processor. When the giant kernel lock disappers, this kludge breaks.
53 *
54 * -- Tor
55 */
56#define BETTER_CLOCK
57
58
59/*
60 * Control the "giant lock" pushdown by logical steps.
61 */
62#define PUSHDOWN_LEVEL_1
63#define PUSHDOWN_LEVEL_2
64#define PUSHDOWN_LEVEL_3_NOT
65#define PUSHDOWN_LEVEL_4_NOT
66
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67/*
68 * Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
69 * Allow the mp_lock() routines to handle FAST interrupts while spinning.
70 */
71#ifdef PUSHDOWN_LEVEL_1
72#define FAST_HI
73#endif
74
75
76/*
77 * These defines enable critical region locking of areas that were
78 * protected via cli/sti in the UP kernel.
79 *
80 * MPINTRLOCK protects all the generic areas.
81 * COMLOCK protects the sio/cy drivers.
82 * CLOCKLOCK protects clock hardware and data
83 * known to be incomplete:
84 * joystick lkm
85 * ?
86 */
87#ifdef PUSHDOWN_LEVEL_1
88#define USE_MPINTRLOCK
89#define USE_COMLOCK
90#define USE_CLOCKLOCK
91#endif
92
93
94/*
95 * INTR_SIMPLELOCK has been removed, as the interrupt mechanism will likely
96 * not use this sort of optimization if we move to interrupt threads.
97 */
98#ifdef PUSHDOWN_LEVEL_4
99#endif
100
101
102/*
103 * CPL_AND_CML has been removed. Interrupt threads will eventually not
104 * use either mechanism so there is no point trying to optimize it.
105 */
106#ifdef PUSHDOWN_LEVEL_3
107#endif
108
109
110/*
111 * SPL_DEBUG_POSTCODE/INTR_SPL/SPL_DEBUG - removed
112 *
113 * These functions were too expensive for the standard case but, more
114 * importantly, we should be able to come up with a much cleaner way
115 * to handle the cpl. Having to do any locking at all is a mistake
116 * for something that is modified as often as cpl is.
117 */
118
119/*
120 * FAST_WITHOUTCPL - now made the default (define removed). Text below
121 * contains the current discussion. I am confident we can find a solution
122 * that does not require us to process softints from a hard int, which can
123 * kill serial performance due to the lack of true hardware ipl's.
124 *
125 ****
126 *
127 * Ignore the ipending bits when exiting FAST_INTR() routines.
128 *
129 * according to Bruce:
130 *
131 * setsoft*() may set ipending. setsofttty() is actually used in the
132 * FAST_INTR handler in some serial drivers. This is necessary to get
133 * output completions and other urgent events handled as soon as possible.
134 * The flag(s) could be set in a variable other than ipending, but they
135 * needs to be checked against cpl to decide whether the software interrupt
136 * handler can/should run.
137 *
138 * (FAST_INTR used to just return
139 * in all cases until rev.1.7 of vector.s. This worked OK provided there
140 * were no user-mode CPU hogs. CPU hogs caused an average latency of 1/2
141 * clock tick for output completions...)
142 ***
143 *
144 * So I need to restore cpl handling someday, but AFTER
145 * I finish making spl/cpl MP-safe.
146 */
147#ifdef PUSHDOWN_LEVEL_1
148#endif
149
150
151/*
152 * FAST_SIMPLELOCK no longer exists, because it doesn't help us. The cpu
153 * is likely to already hold the MP lock and recursive MP locks are now
154 * very cheap, so we do not need this optimization. Eventually *ALL*
155 * interrupts will run in their own thread, so there is no sense complicating
156 * matters now.
157 */
158#ifdef PUSHDOWN_LEVEL_1
159#endif
160
161
162/*
163 * Portions of the old TEST_LOPRIO code, back from the grave!
164 */
165#define GRAB_LOPRIO
166
167
168/*
169 * Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
170 *
171#define VERBOSE_CPUSTOP_ON_DDBBREAK
172 */
173#define CPUSTOP_ON_DDBBREAK
174
175
176/*
177 * Bracket code/comments relevant to the current 'giant lock' model.
178 * Everything is now the 'giant lock' model, but we will use this as
179 * we start to "push down" the lock.
180 */
181#define GIANT_LOCK
182
183#ifdef APIC_IO
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184
185/*
186 * Don't assume that slow interrupt handler X is called from vector
187 * X + ICU_OFFSET.
188 */
189#define APIC_INTR_REORDER
190
191/*
192 * Redirect clock interrupts to a higher priority (fast intr) vector,
193 * while still using the slow interrupt handler. Only effective when
194 * APIC_INTR_REORDER is defined.
195 */
196#define APIC_INTR_HIGHPRI_CLOCK
197
198#endif /* APIC_IO */
199
200/*
201 * Misc. counters.
202 *
203#define COUNT_XINVLTLB_HITS
204 */
205
206
207/**
208 * Hack to "fake-out" kernel into thinking it is running on a 'default config'.
209 *
210 * value == default type
211#define TEST_DEFAULT_CONFIG 6
212 */
213
214
215/*
216 * Simple test code for IPI interaction, save for future...
217 *
218#define TEST_TEST1
219#define IPI_TARGET_TEST1 1
220 */
221
222
223/*
224 * Address of POST hardware port.
225 * Defining this enables POSTCODE macros.
226 *
227#define POST_ADDR 0x80
228 */
229
230
231/*
232 * POST hardware macros.
233 */
234#ifdef POST_ADDR
235#define ASMPOSTCODE_INC \
236 pushl %eax ; \
237 movl _current_postcode, %eax ; \
238 incl %eax ; \
239 andl $0xff, %eax ; \
240 movl %eax, _current_postcode ; \
241 outb %al, $POST_ADDR ; \
242 popl %eax
243
244/*
245 * Overwrite the current_postcode value.
246 */
247#define ASMPOSTCODE(X) \
248 pushl %eax ; \
249 movl $X, %eax ; \
250 movl %eax, _current_postcode ; \
251 outb %al, $POST_ADDR ; \
252 popl %eax
253
254/*
255 * Overwrite the current_postcode low nibble.
256 */
257#define ASMPOSTCODE_LO(X) \
258 pushl %eax ; \
259 movl _current_postcode, %eax ; \
260 andl $0xf0, %eax ; \
261 orl $X, %eax ; \
262 movl %eax, _current_postcode ; \
263 outb %al, $POST_ADDR ; \
264 popl %eax
265
266/*
267 * Overwrite the current_postcode high nibble.
268 */
269#define ASMPOSTCODE_HI(X) \
270 pushl %eax ; \
271 movl _current_postcode, %eax ; \
272 andl $0x0f, %eax ; \
273 orl $(X<<4), %eax ; \
274 movl %eax, _current_postcode ; \
275 outb %al, $POST_ADDR ; \
276 popl %eax
277#else
278#define ASMPOSTCODE_INC
279#define ASMPOSTCODE(X)
280#define ASMPOSTCODE_LO(X)
281#define ASMPOSTCODE_HI(X)
282#endif /* POST_ADDR */
283
284
285/*
286 * These are all temps for debugging...
287 *
288#define GUARD_INTS
289 */
290
291/*
292 * This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
293 */
294#ifdef GUARD_INTS
295#define GUARD_CPU 1
296#define MAYBE_PANIC(irq_num) \
297 cmpl $GUARD_CPU, _cpuid ; \
298 jne 9f ; \
299 cmpl $1, _ok_test1 ; \
300 jne 9f ; \
301 pushl lapic_isr3 ; \
302 pushl lapic_isr2 ; \
303 pushl lapic_isr1 ; \
304 pushl lapic_isr0 ; \
305 pushl lapic_irr3 ; \
306 pushl lapic_irr2 ; \
307 pushl lapic_irr1 ; \
308 pushl lapic_irr0 ; \
309 pushl $irq_num ; \
310 pushl _cpuid ; \
311 pushl $panic_msg ; \
312 call _printf ; \
313 addl $44, %esp ; \
3149:
315#else
316#define MAYBE_PANIC(irq_num)
317#endif /* GUARD_INTS */
318
319#endif /* _MACHINE_SMPTESTS_H_ */