MP Implementation 1/2: Get the APIC code working again, sweetly integrate the
[dragonfly.git] / sys / platform / pc32 / i386 / k6_mem.c
CommitLineData
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1/*-
2 * Copyright (c) 1999 Brian Fundakowski Feldman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/i386/i386/k6_mem.c,v 1.4.2.2 2002/09/16 21:58:41 dwmalone Exp $
8a8d5d85 27 * $DragonFly: src/sys/platform/pc32/i386/k6_mem.c,v 1.3 2003/07/06 21:23:48 dillon Exp $
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28 *
29 */
30
31#include <sys/param.h>
32#include <sys/kernel.h>
33#include <sys/systm.h>
34#include <sys/ioccom.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
37
38#include <machine/md_var.h>
39#include <machine/specialreg.h>
8a8d5d85 40#include <machine/lock.h>
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41
42/*
43 * A K6-2 MTRR is defined as the highest 15 bits having the address, the next
44 * 15 having the mask, the 1st bit being "write-combining" and the 0th bit
45 * being "uncacheable".
46 *
47 * Address Mask WC UC
48 * | XXXXXXXXXXXXXXX | XXXXXXXXXXXXXXX | X | X |
49 *
50 * There are two of these in the 64-bit UWCCR.
51 */
52
53/*
54 * NOTE: I do _not_ comment my code unless it's truly necessary. Don't
55 * expect anything frivolous here, and do NOT touch my bit-shifts
56 * unless you want to break this.
57 */
58
59#define UWCCR 0xc0000085
60
61#define k6_reg_get(reg, addr, mask, wc, uc) do { \
62 addr = (reg) & 0xfffe0000; \
63 mask = ((reg) & 0x1fffc) >> 2; \
64 wc = ((reg) & 0x2) >> 1; \
65 uc = (reg) & 0x1; \
66 } while (0)
67
68#define k6_reg_make(addr, mask, wc, uc) \
69 ((addr) | ((mask) << 2) | ((wc) << 1) | uc)
70
71static void k6_mrinit(struct mem_range_softc *sc);
72static int k6_mrset(struct mem_range_softc *, struct mem_range_desc *, int *);
73static __inline int k6_mrmake(struct mem_range_desc *, u_int32_t *);
74static void k6_mem_drvinit(void *);
75
76static struct mem_range_ops k6_mrops = {
77 k6_mrinit,
78 k6_mrset,
79 NULL
80};
81
82static __inline int
83k6_mrmake(struct mem_range_desc *desc, u_int32_t *mtrr) {
84 u_int32_t len = 0, wc, uc;
85 register int bit;
86
87 if (desc->mr_base &~ 0xfffe0000)
88 return EINVAL;
89 if (desc->mr_len < 131072 || !powerof2(desc->mr_len))
90 return EINVAL;
91 if (desc->mr_flags &~ (MDF_WRITECOMBINE|MDF_UNCACHEABLE|MDF_FORCE))
92 return EOPNOTSUPP;
93
94 for (bit = ffs(desc->mr_len >> 17) - 1; bit < 15; bit++)
95 len |= 1 << bit;
96 wc = (desc->mr_flags & MDF_WRITECOMBINE) ? 1 : 0;
97 uc = (desc->mr_flags & MDF_UNCACHEABLE) ? 1 : 0;
98
99 *mtrr = k6_reg_make(desc->mr_base, len, wc, uc);
100 return 0;
101}
102
103static void
104k6_mrinit(struct mem_range_softc *sc) {
105 u_int64_t reg;
106 u_int32_t addr, mask, wc, uc;
107 int d;
108
109 sc->mr_cap = 0;
110 sc->mr_ndesc = 2; /* XXX (BFF) For now, we only have one msr for this */
111 sc->mr_desc = malloc(sc->mr_ndesc * sizeof(struct mem_range_desc),
112 M_MEMDESC, M_NOWAIT);
113 if (sc->mr_desc == NULL)
114 panic("k6_mrinit: malloc returns NULL");
115 bzero(sc->mr_desc, sc->mr_ndesc * sizeof(struct mem_range_desc));
116
117 reg = rdmsr(UWCCR);
118 for (d = 0; d < sc->mr_ndesc; d++) {
119 u_int32_t one = (reg & (0xffffffff << (32 * d))) >> (32 * d);
120
121 k6_reg_get(one, addr, mask, wc, uc);
122 sc->mr_desc[d].mr_base = addr;
123 sc->mr_desc[d].mr_len = ffs(mask) << 17;
124 if (wc)
125 sc->mr_desc[d].mr_flags |= MDF_WRITECOMBINE;
126 if (uc)
127 sc->mr_desc[d].mr_flags |= MDF_UNCACHEABLE;
128 }
129
130 printf("K6-family MTRR support enabled (%d registers)\n", sc->mr_ndesc);
131}
132
133static int
134k6_mrset(struct mem_range_softc *sc, struct mem_range_desc *desc, int *arg) {
135 u_int64_t reg;
136 u_int32_t mtrr;
137 int error, d;
138
139 switch (*arg) {
140 case MEMRANGE_SET_UPDATE:
141 error = k6_mrmake(desc, &mtrr);
142 if (error)
143 return error;
144 for (d = 0; d < sc->mr_ndesc; d++) {
145 if (!sc->mr_desc[d].mr_len) {
146 sc->mr_desc[d] = *desc;
147 goto out;
148 }
149 if (sc->mr_desc[d].mr_base == desc->mr_base &&
150 sc->mr_desc[d].mr_len == desc->mr_len)
151 return EEXIST;
152 }
153
154 return ENOSPC;
155 case MEMRANGE_SET_REMOVE:
156 mtrr = 0;
157 for (d = 0; d < sc->mr_ndesc; d++)
158 if (sc->mr_desc[d].mr_base == desc->mr_base &&
159 sc->mr_desc[d].mr_len == desc->mr_len) {
160 bzero(&sc->mr_desc[d], sizeof(sc->mr_desc[d]));
161 goto out;
162 }
163
164 return ENOENT;
165 default:
166 return EOPNOTSUPP;
167 }
168
169out:
170
8a8d5d85 171 mpintr_lock();
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172 wbinvd();
173 reg = rdmsr(UWCCR);
174 reg &= ~(0xffffffff << (32 * d));
175 reg |= mtrr << (32 * d);
176 wrmsr(UWCCR, reg);
177 wbinvd();
8a8d5d85 178 mpintr_unlock();
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179
180 return 0;
181}
182
183static void
184k6_mem_drvinit(void *unused) {
185 if (!strcmp(cpu_vendor, "AuthenticAMD") &&
186 (cpu_id & 0xf00) == 0x500 &&
187 ((cpu_id & 0xf0) > 0x80 ||
188 ((cpu_id & 0xf0) == 0x80 &&
189 (cpu_id & 0xf) > 0x7))
190 )
191 mem_range_softc.mr_op = &k6_mrops;
192}
193
194SYSINIT(k6memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, k6_mem_drvinit, NULL)