AHCI - DHRS interrupt does not stop command processing.
[dragonfly.git] / sys / dev / disk / ahci / ahci.c
CommitLineData
258223a3
MD
1/*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 *
17 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
18 *
19 * This code is derived from software contributed to The DragonFly Project
20 * by Matthew Dillon <dillon@backplane.com>
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * 2. Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * 3. Neither the name of The DragonFly Project nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific, prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
39 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
40 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
41 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
46 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * SUCH DAMAGE.
48 *
49 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
50 */
51
52#include "ahci.h"
53
1980eff3 54int ahci_port_init(struct ahci_port *ap, struct ata_port *at);
17eab71e 55int ahci_port_start(struct ahci_port *);
258223a3
MD
56int ahci_port_stop(struct ahci_port *, int);
57int ahci_port_clo(struct ahci_port *);
258223a3
MD
58
59int ahci_load_prdt(struct ahci_ccb *);
60void ahci_unload_prdt(struct ahci_ccb *);
61static void ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs,
62 int nsegs, int error);
258223a3 63void ahci_start(struct ahci_ccb *);
17eab71e 64int ahci_port_softreset(struct ahci_port *ap);
1980eff3
MD
65int ahci_port_pmprobe(struct ahci_port *ap);
66int ahci_port_hardreset(struct ahci_port *ap, int hard);
cf5f3a81
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67void ahci_port_hardstop(struct ahci_port *ap);
68void ahci_flush_tfd(struct ahci_port *ap);
258223a3
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69
70static void ahci_ata_cmd_timeout_unserialized(void *arg);
258223a3
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71
72void ahci_issue_pending_ncq_commands(struct ahci_port *);
73void ahci_issue_pending_commands(struct ahci_port *, int);
74
258223a3
MD
75struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *);
76void ahci_put_err_ccb(struct ahci_ccb *);
77
78int ahci_port_read_ncq_error(struct ahci_port *, int *);
79
80struct ahci_dmamem *ahci_dmamem_alloc(struct ahci_softc *, bus_dma_tag_t tag);
81void ahci_dmamem_free(struct ahci_softc *, struct ahci_dmamem *);
82static void ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error);
83
84void ahci_empty_done(struct ahci_ccb *ccb);
85void ahci_ata_cmd_done(struct ahci_ccb *ccb);
86
87/* Wait for all bits in _b to be cleared */
cec85a37
MD
88#define ahci_pwait_clr(_ap, _r, _b) \
89 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0)
90#define ahci_pwait_clr_to(_ap, _to, _r, _b) \
91 ahci_pwait_eq((_ap), _to, (_r), (_b), 0)
258223a3
MD
92
93/* Wait for all bits in _b to be set */
cec85a37
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94#define ahci_pwait_set(_ap, _r, _b) \
95 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b))
96#define ahci_pwait_set_to(_ap, _to, _r, _b) \
97 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b))
98
99#define AHCI_PWAIT_TIMEOUT 1000
258223a3 100
fd8bd957
MD
101/*
102 * Initialize the global AHCI hardware. This code does not set up any of
103 * its ports.
104 */
258223a3
MD
105int
106ahci_init(struct ahci_softc *sc)
107{
108 u_int32_t cap, pi;
109
110 DPRINTF(AHCI_D_VERBOSE, " GHC 0x%b",
111 ahci_read(sc, AHCI_REG_GHC), AHCI_FMT_GHC);
112
113 /* save BIOS initialised parameters, enable staggered spin up */
114 cap = ahci_read(sc, AHCI_REG_CAP);
115 cap &= AHCI_REG_CAP_SMPS;
116 cap |= AHCI_REG_CAP_SSS;
117 pi = ahci_read(sc, AHCI_REG_PI);
118
17eab71e
MD
119 /*
120 * Unconditionally reset the controller, do not conditionalize on
121 * trying to figure it if it was previously active or not.
122 */
123 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_HR);
124 if (ahci_wait_ne(sc, AHCI_REG_GHC, AHCI_REG_GHC_HR,
125 AHCI_REG_GHC_HR) != 0) {
126 device_printf(sc->sc_dev,
127 "unable to reset controller\n");
128 return (1);
258223a3
MD
129 }
130
131 /* enable ahci (global interrupts disabled) */
132 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE);
133
134 /* restore parameters */
135 ahci_write(sc, AHCI_REG_CAP, cap);
136 ahci_write(sc, AHCI_REG_PI, pi);
137
138 return (0);
139}
140
fd8bd957
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141/*
142 * Allocate and initialize an AHCI port.
143 */
258223a3
MD
144int
145ahci_port_alloc(struct ahci_softc *sc, u_int port)
146{
1980eff3
MD
147 struct ahci_port *ap;
148 struct ata_port *at;
149 struct ahci_ccb *ccb;
150 u_int64_t dva;
151 u_int32_t cmd;
152 struct ahci_cmd_hdr *hdr;
153 struct ahci_cmd_table *table;
258223a3
MD
154 int rc = ENOMEM;
155 int error;
156 int i;
157
158 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO);
159 if (ap == NULL) {
160 device_printf(sc->sc_dev,
161 "unable to allocate memory for port %d\n",
162 port);
163 goto reterr;
164 }
165
166 ksnprintf(ap->ap_name, sizeof(ap->ap_name), "%s%d.%d",
167 device_get_name(sc->sc_dev),
168 device_get_unit(sc->sc_dev),
169 port);
170 sc->sc_ports[port] = ap;
171
1980eff3
MD
172 /*
173 * Allocate enough so we never have to reallocate, it makes
174 * it easier.
175 *
176 * ap_pmcount will be reduced by the scan if we encounter the
177 * port multiplier port prior to target 15.
178 */
179 if (ap->ap_ata == NULL) {
180 ap->ap_ata = kmalloc(sizeof(*ap->ap_ata) * AHCI_MAX_PMPORTS,
181 M_DEVBUF, M_INTWAIT | M_ZERO);
182 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) {
183 at = &ap->ap_ata[i];
184 at->at_ahci_port = ap;
185 at->at_target = i;
186 at->at_probe = ATA_PROBE_NEED_HARD_RESET;
187 ksnprintf(at->at_name, sizeof(at->at_name),
188 "%s.%d", ap->ap_name, i);
189 }
190 }
258223a3
MD
191 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
192 AHCI_PORT_REGION(port), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) {
193 device_printf(sc->sc_dev,
194 "unable to create register window for port %d\n",
195 port);
196 goto freeport;
197 }
198
199 ap->ap_sc = sc;
200 ap->ap_num = port;
1980eff3 201 ap->ap_probe = ATA_PROBE_NEED_HARD_RESET;
258223a3
MD
202 TAILQ_INIT(&ap->ap_ccb_free);
203 TAILQ_INIT(&ap->ap_ccb_pending);
204 lockinit(&ap->ap_ccb_lock, "ahcipo", 0, 0);
205
206 /* Disable port interrupts */
207 ahci_pwrite(ap, AHCI_PREG_IE, 0);
208
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MD
209 /*
210 * Sec 10.1.2 - deinitialise port if it is already running
211 */
258223a3
MD
212 cmd = ahci_pread(ap, AHCI_PREG_CMD);
213 if ((cmd & (AHCI_PREG_CMD_ST | AHCI_PREG_CMD_CR |
17eab71e 214 AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_FR)) ||
258223a3
MD
215 (ahci_pread(ap, AHCI_PREG_SCTL) & AHCI_PREG_SCTL_DET)) {
216 int r;
217
218 r = ahci_port_stop(ap, 1);
219 if (r) {
220 device_printf(sc->sc_dev,
221 "unable to disable %s, ignoring port %d\n",
222 ((r == 2) ? "CR" : "FR"), port);
223 rc = ENXIO;
224 goto freeport;
225 }
226
227 /* Write DET to zero */
cf5f3a81 228 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
258223a3
MD
229 }
230
231 /* Allocate RFIS */
232 ap->ap_dmamem_rfis = ahci_dmamem_alloc(sc, sc->sc_tag_rfis);
233 if (ap->ap_dmamem_rfis == NULL) {
cf5f3a81 234 kprintf("%s: NORFIS\n", PORTNAME(ap));
258223a3
MD
235 goto nomem;
236 }
237
238 /* Setup RFIS base address */
239 ap->ap_rfis = (struct ahci_rfis *) AHCI_DMA_KVA(ap->ap_dmamem_rfis);
240 dva = AHCI_DMA_DVA(ap->ap_dmamem_rfis);
241 ahci_pwrite(ap, AHCI_PREG_FBU, (u_int32_t)(dva >> 32));
242 ahci_pwrite(ap, AHCI_PREG_FB, (u_int32_t)dva);
243
244 /* Enable FIS reception and activate port. */
245 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1980eff3 246 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA);
258223a3
MD
247 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD | AHCI_PREG_CMD_SUD;
248 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE);
249
250 /* Check whether port activated. Skip it if not. */
251 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
252 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
cf5f3a81 253 kprintf("%s: NOT-ACTIVATED\n", PORTNAME(ap));
258223a3
MD
254 rc = ENXIO;
255 goto freeport;
256 }
257
258 /* Allocate a CCB for each command slot */
259 ap->ap_ccbs = kmalloc(sizeof(struct ahci_ccb) * sc->sc_ncmds, M_DEVBUF,
260 M_WAITOK | M_ZERO);
261 if (ap->ap_ccbs == NULL) {
262 device_printf(sc->sc_dev,
263 "unable to allocate command list for port %d\n",
264 port);
265 goto freeport;
266 }
267
268 /* Command List Structures and Command Tables */
269 ap->ap_dmamem_cmd_list = ahci_dmamem_alloc(sc, sc->sc_tag_cmdh);
270 ap->ap_dmamem_cmd_table = ahci_dmamem_alloc(sc, sc->sc_tag_cmdt);
271 if (ap->ap_dmamem_cmd_table == NULL ||
272 ap->ap_dmamem_cmd_list == NULL) {
273nomem:
274 device_printf(sc->sc_dev,
275 "unable to allocate DMA memory for port %d\n",
276 port);
277 goto freeport;
278 }
279
280 /* Setup command list base address */
281 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_list);
282 ahci_pwrite(ap, AHCI_PREG_CLBU, (u_int32_t)(dva >> 32));
283 ahci_pwrite(ap, AHCI_PREG_CLB, (u_int32_t)dva);
284
285 /* Split CCB allocation into CCBs and assign to command header/table */
286 hdr = AHCI_DMA_KVA(ap->ap_dmamem_cmd_list);
287 table = AHCI_DMA_KVA(ap->ap_dmamem_cmd_table);
288 for (i = 0; i < sc->sc_ncmds; i++) {
289 ccb = &ap->ap_ccbs[i];
290
291 error = bus_dmamap_create(sc->sc_tag_data, BUS_DMA_ALLOCNOW,
292 &ccb->ccb_dmamap);
293 if (error) {
294 device_printf(sc->sc_dev,
295 "unable to create dmamap for port %d "
296 "ccb %d\n", port, i);
297 goto freeport;
298 }
299
300 callout_init(&ccb->ccb_timeout);
301 ccb->ccb_slot = i;
302 ccb->ccb_port = ap;
303 ccb->ccb_cmd_hdr = &hdr[i];
304 ccb->ccb_cmd_table = &table[i];
305 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_table) +
306 ccb->ccb_slot * sizeof(struct ahci_cmd_table);
307 ccb->ccb_cmd_hdr->ctba_hi = htole32((u_int32_t)(dva >> 32));
308 ccb->ccb_cmd_hdr->ctba_lo = htole32((u_int32_t)dva);
309
310 ccb->ccb_xa.fis =
311 (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis;
312 ccb->ccb_xa.packetcmd = ccb->ccb_cmd_table->acmd;
313 ccb->ccb_xa.tag = i;
314
258223a3
MD
315 ccb->ccb_xa.state = ATA_S_COMPLETE;
316 ahci_put_ccb(ccb);
317 }
318
319 /* Wait for ICC change to complete */
320 ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_ICC);
321
fd8bd957
MD
322 /*
323 * Do device-related port initialization. A failure here does not
324 * cause the port to be deallocated as we want to receive future
325 * hot-plug events.
326 */
1980eff3 327 ahci_port_init(ap, NULL);
fd8bd957
MD
328 return(0);
329freeport:
330 ahci_port_free(sc, port);
331reterr:
332 return (rc);
333}
334
335/*
336 * [re]initialize an idle port. No CCBs should be active.
337 *
1980eff3
MD
338 * If at is NULL we are initializing a directly connected port, otherwise
339 * we are indirectly initializing a port multiplier port.
340 *
fd8bd957
MD
341 * This function is called during the initial port allocation sequence
342 * and is also called on hot-plug insertion. We take no chances and
343 * use a portreset instead of a softreset.
344 *
22181ab7
MD
345 * This function is the only way to move a failed port back to active
346 * status.
347 *
fd8bd957
MD
348 * Returns 0 if a device is successfully detected.
349 */
350int
1980eff3 351ahci_port_init(struct ahci_port *ap, struct ata_port *at)
fd8bd957 352{
1980eff3 353 u_int32_t data;
fd8bd957
MD
354 int rc;
355
356 /*
1980eff3 357 * Clear all notification bits
fd8bd957 358 */
1980eff3
MD
359 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
360 ahci_pwrite(ap, AHCI_PREG_SNTF, -1);
361
362 /*
363 * Hard-reset the port. If a device is detected but it is busy
364 * we try a second time, this time cycling the phy as well.
365 */
366 ap->ap_probe = ATA_PROBE_NEED_HARD_RESET;
367 rc = ahci_port_reset(ap, at, 1);
368 if (rc == EBUSY) {
369 rc = ahci_port_reset(ap, at, 2);
17eab71e 370 }
fd8bd957 371
258223a3
MD
372 switch (rc) {
373 case ENODEV:
fd8bd957
MD
374 /*
375 * We had problems talking to the device on the port.
376 */
258223a3
MD
377 switch (ahci_pread(ap, AHCI_PREG_SSTS) & AHCI_PREG_SSTS_DET) {
378 case AHCI_PREG_SSTS_DET_DEV_NE:
419cb1ab 379 kprintf("%s: Device not communicating\n", PORTNAME(ap));
258223a3
MD
380 break;
381 case AHCI_PREG_SSTS_DET_PHYOFFLINE:
419cb1ab 382 kprintf("%s: PHY offline\n", PORTNAME(ap));
258223a3
MD
383 break;
384 default:
419cb1ab 385 kprintf("%s: No device detected\n", PORTNAME(ap));
258223a3
MD
386 break;
387 }
388 break;
389
390 case EBUSY:
fd8bd957 391 /*
17eab71e
MD
392 * The device on the port is still telling us its busy,
393 * which means that it is not properly handling a SATA
394 * port COMRESET.
fd8bd957 395 *
17eab71e
MD
396 * It may be possible to softreset the device using CLO
397 * and a device reset command.
fd8bd957 398 */
17eab71e
MD
399 kprintf("%s: Device on port is bricked, trying softreset\n",
400 PORTNAME(ap));
258223a3 401
1980eff3 402 rc = ahci_port_reset(ap, at, 0);
258223a3 403 if (rc) {
17eab71e 404 kprintf("%s: Unable unbrick device\n",
fd8bd957
MD
405 PORTNAME(ap));
406 } else {
17eab71e 407 kprintf("%s: Successfully unbricked\n",
fd8bd957 408 PORTNAME(ap));
258223a3
MD
409 }
410 break;
411
412 default:
413 break;
414 }
415
416 /*
17eab71e
MD
417 * Command transfers can only be enabled if a device was successfully
418 * detected.
1980eff3
MD
419 *
420 * Allocate or deallocate the ap_ata array here too.
258223a3 421 */
1980eff3
MD
422 switch(ap->ap_type) {
423 case ATA_PORT_T_NONE:
424 ap->ap_pmcount = 0;
425 break;
426 case ATA_PORT_T_PM:
427 /* already set */
428 break;
429 default:
430 ap->ap_pmcount = 1;
431 break;
432 }
433
434 /*
435 * Start the port if we succeeded.
436 *
437 * There's nothing to start for devices behind a port multiplier.
438 */
439 if (rc == 0 && at == NULL) {
17eab71e 440 if (ahci_port_start(ap)) {
fd8bd957
MD
441 kprintf("%s: failed to start command DMA on port, "
442 "disabling\n", PORTNAME(ap));
258223a3
MD
443 rc = ENXIO; /* couldn't start port */
444 }
445 }
446
17eab71e 447 /*
1980eff3
MD
448 * Flush interupts on the port. XXX
449 *
450 * Enable interrupts on the port whether a device is sitting on
451 * it or not, to handle hot-plug events.
17eab71e 452 */
1980eff3
MD
453 if (at == NULL) {
454 ahci_pwrite(ap, AHCI_PREG_IS, ahci_pread(ap, AHCI_PREG_IS));
455 ahci_write(ap->ap_sc, AHCI_REG_IS, 1 << ap->ap_num);
456
457 data = AHCI_PREG_IE_TFEE | AHCI_PREG_IE_HBFE |
458 AHCI_PREG_IE_IFE | AHCI_PREG_IE_OFE |
459 AHCI_PREG_IE_DPE | AHCI_PREG_IE_UFE |
460 AHCI_PREG_IE_PCE | AHCI_PREG_IE_PRCE |
461 AHCI_PREG_IE_DHRE;
462 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
463 data |= AHCI_PREG_IE_SDBE;
258223a3 464#ifdef AHCI_COALESCE
1980eff3
MD
465 if (sc->sc_ccc_ports & (1 << port)
466 data &= ~(AHCI_PREG_IE_SDBE | AHCI_PREG_IE_DHRE);
258223a3 467#endif
1980eff3
MD
468 ahci_pwrite(ap, AHCI_PREG_IE, data);
469 }
fd8bd957 470 return(rc);
258223a3
MD
471}
472
fd8bd957
MD
473/*
474 * De-initialize and detach a port.
475 */
258223a3
MD
476void
477ahci_port_free(struct ahci_softc *sc, u_int port)
478{
479 struct ahci_port *ap = sc->sc_ports[port];
480 struct ahci_ccb *ccb;
481
17eab71e
MD
482 /*
483 * Ensure port is disabled and its interrupts are all flushed.
484 */
258223a3 485 if (ap->ap_sc) {
17eab71e 486 ahci_port_stop(ap, 1);
258223a3
MD
487 ahci_pwrite(ap, AHCI_PREG_CMD, 0);
488 ahci_pwrite(ap, AHCI_PREG_IE, 0);
489 ahci_pwrite(ap, AHCI_PREG_IS, ahci_pread(ap, AHCI_PREG_IS));
490 ahci_write(sc, AHCI_REG_IS, 1 << port);
491 }
492
493 if (ap->ap_ccbs) {
494 while ((ccb = ahci_get_ccb(ap)) != NULL) {
495 if (ccb->ccb_dmamap) {
496 bus_dmamap_destroy(sc->sc_tag_data,
497 ccb->ccb_dmamap);
498 ccb->ccb_dmamap = NULL;
499 }
500 }
501 kfree(ap->ap_ccbs, M_DEVBUF);
502 ap->ap_ccbs = NULL;
503 }
504
505 if (ap->ap_dmamem_cmd_list) {
506 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_list);
507 ap->ap_dmamem_cmd_list = NULL;
508 }
509 if (ap->ap_dmamem_rfis) {
510 ahci_dmamem_free(sc, ap->ap_dmamem_rfis);
511 ap->ap_dmamem_rfis = NULL;
512 }
513 if (ap->ap_dmamem_cmd_table) {
514 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_table);
515 ap->ap_dmamem_cmd_table = NULL;
516 }
1980eff3
MD
517 if (ap->ap_ata) {
518 kfree(ap->ap_ata, M_DEVBUF);
519 ap->ap_ata = NULL;
520 }
258223a3
MD
521
522 /* bus_space(9) says we dont free the subregions handle */
523
524 kfree(ap, M_DEVBUF);
525 sc->sc_ports[port] = NULL;
526}
527
fd8bd957
MD
528/*
529 * Start high-level command processing on the port
530 */
258223a3 531int
17eab71e 532ahci_port_start(struct ahci_port *ap)
258223a3 533{
8bf6a3ff 534 u_int32_t r, oldr, s, olds, is, oldis, tfd, oldtfd;
258223a3 535
17eab71e
MD
536 /*
537 * FRE must be turned on before ST. Wait for FR to go active
538 * before turning on ST. The spec doesn't seem to think this
539 * is necessary but waiting here avoids an on-off race in the
540 * ahci_port_stop() code.
541 */
1980eff3
MD
542 olds = ahci_pread(ap, AHCI_PREG_SERR);
543 oldis= ahci_pread(ap, AHCI_PREG_IS);
8bf6a3ff 544 oldtfd = ahci_pread(ap, AHCI_PREG_TFD);
1980eff3 545 oldr = r = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
17eab71e
MD
546 if ((r & AHCI_PREG_CMD_FRE) == 0) {
547 r |= AHCI_PREG_CMD_FRE;
548 ahci_pwrite(ap, AHCI_PREG_CMD, r);
549 }
550 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) {
551 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) {
552 kprintf("%s: Cannot start FIS reception\n",
553 PORTNAME(ap));
554 return (2);
555 }
556 }
557
558 /*
559 * Turn on ST, wait for CR to come up.
560 */
561 r |= AHCI_PREG_CMD_ST;
258223a3 562 ahci_pwrite(ap, AHCI_PREG_CMD, r);
17eab71e 563 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) {
8bf6a3ff
MD
564 s = ahci_pread(ap, AHCI_PREG_SERR);
565 is = ahci_pread(ap, AHCI_PREG_IS);
566 tfd = ahci_pread(ap, AHCI_PREG_TFD);
1980eff3
MD
567 kprintf("%s: Cannot start command DMA\n"
568 "OCMD=%b OSERR=%b\n"
569 "NCMP=%b NSERR=%b\n"
8bf6a3ff
MD
570 "OLDIS=%b\nNEWIS=%b\n"
571 "OLDTFD=%b\nNEWTFD=%b\n",
1980eff3
MD
572 PORTNAME(ap),
573 oldr, AHCI_PFMT_CMD, olds, AHCI_PFMT_SERR,
574 r, AHCI_PFMT_CMD, s, AHCI_PFMT_SERR,
8bf6a3ff
MD
575 oldis, AHCI_PFMT_IS, is, AHCI_PFMT_IS,
576 oldtfd, AHCI_PFMT_TFD_STS, tfd, AHCI_PFMT_TFD_STS);
17eab71e
MD
577 return (1);
578 }
258223a3
MD
579
580#ifdef AHCI_COALESCE
17eab71e
MD
581 /*
582 * (Re-)enable coalescing on the port.
583 */
258223a3
MD
584 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) {
585 ap->ap_sc->sc_ccc_ports_cur |= (1 << ap->ap_num);
586 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS,
587 ap->ap_sc->sc_ccc_ports_cur);
588 }
589#endif
590
258223a3
MD
591 return (0);
592}
593
fd8bd957
MD
594/*
595 * Stop high-level command processing on a port
596 */
258223a3
MD
597int
598ahci_port_stop(struct ahci_port *ap, int stop_fis_rx)
599{
600 u_int32_t r;
601
602#ifdef AHCI_COALESCE
17eab71e
MD
603 /*
604 * Disable coalescing on the port while it is stopped.
605 */
258223a3
MD
606 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) {
607 ap->ap_sc->sc_ccc_ports_cur &= ~(1 << ap->ap_num);
608 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS,
609 ap->ap_sc->sc_ccc_ports_cur);
610 }
611#endif
612
17eab71e
MD
613 /*
614 * Turn off ST, then wait for CR to go off.
615 */
258223a3
MD
616 r = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
617 r &= ~AHCI_PREG_CMD_ST;
258223a3
MD
618 ahci_pwrite(ap, AHCI_PREG_CMD, r);
619
17eab71e
MD
620 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) {
621 kprintf("%s: Port bricked, unable to stop (ST)\n",
622 PORTNAME(ap));
258223a3 623 return (1);
17eab71e 624 }
258223a3 625
1980eff3 626#if 0
17eab71e
MD
627 /*
628 * Turn off FRE, then wait for FR to go off. FRE cannot
629 * be turned off until CR transitions to 0.
630 */
1980eff3
MD
631 if ((r & AHCI_PREG_CMD_FR) == 0) {
632 kprintf("%s: FR stopped, clear FRE for next start\n",
633 PORTNAME(ap));
634 stop_fis_rx = 2;
635 }
636#endif
17eab71e
MD
637 if (stop_fis_rx) {
638 r &= ~AHCI_PREG_CMD_FRE;
639 ahci_pwrite(ap, AHCI_PREG_CMD, r);
640 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) {
641 kprintf("%s: Port bricked, unable to stop (FRE)\n",
642 PORTNAME(ap));
643 return (2);
644 }
645 }
258223a3
MD
646
647 return (0);
648}
649
fd8bd957
MD
650/*
651 * AHCI command list override -> forcibly clear TFD.STS.{BSY,DRQ}
652 */
258223a3
MD
653int
654ahci_port_clo(struct ahci_port *ap)
655{
656 struct ahci_softc *sc = ap->ap_sc;
657 u_int32_t cmd;
658
659 /* Only attempt CLO if supported by controller */
660 if ((ahci_read(sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) == 0)
661 return (1);
662
663 /* Issue CLO */
664 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
665#ifdef DIAGNOSTIC
666 if (cmd & AHCI_PREG_CMD_ST) {
667 kprintf("%s: CLO requested while port running\n",
668 PORTNAME(ap));
669 }
670#endif
671 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_CLO);
672
673 /* Wait for completion */
674 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CLO)) {
675 kprintf("%s: CLO did not complete\n", PORTNAME(ap));
676 return (1);
677 }
678
679 return (0);
680}
681
fd8bd957 682/*
1980eff3
MD
683 * Reset a port.
684 *
685 * If hard is 0 perform a softreset of the port.
686 * If hard is 1 perform a hard reset of the port.
687 * If hard is 2 perform a hard reset of the port and cycle the phy.
688 *
689 * If at is non-NULL an indirect port via a port-multiplier is being
690 * reset, otherwise a direct port is being reset.
17eab71e 691 *
1980eff3 692 * NOTE: Indirect ports can only be soft-reset.
17eab71e
MD
693 */
694int
1980eff3 695ahci_port_reset(struct ahci_port *ap, struct ata_port *at, int hard)
17eab71e
MD
696{
697 int rc;
698
699 if (hard) {
1980eff3
MD
700 if (at)
701 rc = ahci_pm_hardreset(ap, at->at_target, hard);
702 else
703 rc = ahci_port_hardreset(ap, hard);
17eab71e 704 } else {
1980eff3
MD
705 if (at)
706 rc = ahci_pm_softreset(ap, at->at_target);
707 else
708 rc = ahci_port_softreset(ap);
709#if 0
710 if (rc && at == NULL)
711 rc = ahci_port_hardreset(ap, hard);
712#endif
17eab71e
MD
713 }
714 return(rc);
715}
716
717/*
fd8bd957
MD
718 * AHCI soft reset, Section 10.4.1
719 *
1980eff3
MD
720 * (at) will be NULL when soft-resetting a directly-attached device, and
721 * non-NULL when soft-resetting a device through a port multiplier.
722 *
fd8bd957 723 * This function keeps port communications intact and attempts to generate
1980eff3 724 * a reset to the connected device using device commands.
fd8bd957 725 */
258223a3
MD
726int
727ahci_port_softreset(struct ahci_port *ap)
728{
1980eff3
MD
729 struct ahci_ccb *ccb = NULL;
730 struct ahci_cmd_hdr *cmd_slot;
731 u_int8_t *fis;
732 int rc, count;
733 u_int32_t cmd;
734
735 rc = EIO;
736 count = 10; /* device reset delay x 100ms */
737
738 kprintf("%s: START SOFTRESET %b\n", PORTNAME(ap),
739 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD);
258223a3
MD
740
741 DPRINTF(AHCI_D_VERBOSE, "%s: soft reset\n", PORTNAME(ap));
742
743 crit_enter();
1980eff3
MD
744 ap->ap_flags |= AP_F_IN_RESET;
745 ap->ap_state = AP_S_NORMAL;
258223a3 746
1980eff3
MD
747 /*
748 * Remember port state in cmd (main to restore start/stop)
749 *
750 * Idle port.
751 */
752 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
258223a3
MD
753 if (ahci_port_stop(ap, 0)) {
754 kprintf("%s: failed to stop port, cannot softreset\n",
755 PORTNAME(ap));
756 goto err;
757 }
cf5f3a81
MD
758
759 /*
1980eff3 760 * Request CLO if device appears hung.
cf5f3a81 761 */
258223a3 762 if (ahci_pread(ap, AHCI_PREG_TFD) &
1980eff3 763 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
258223a3
MD
764 ahci_port_clo(ap);
765 }
766
1980eff3
MD
767 /*
768 * This is an attempt to clear errors so a new signature will
769 * be latched. It isn't working properly. XXX
770 */
cf5f3a81 771 ahci_flush_tfd(ap);
1980eff3 772 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
258223a3
MD
773
774 /* Restart port */
17eab71e 775 if (ahci_port_start(ap)) {
258223a3
MD
776 kprintf("%s: failed to start port, cannot softreset\n",
777 PORTNAME(ap));
778 goto err;
779 }
780
781 /* Check whether CLO worked */
782 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1980eff3 783 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
258223a3
MD
784 kprintf("%s: CLO %s, need port reset\n",
785 PORTNAME(ap),
786 (ahci_read(ap->ap_sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO)
787 ? "failed" : "unsupported");
788 rc = EBUSY;
789 goto err;
790 }
791
cec85a37
MD
792 /*
793 * Prep first D2H command with SRST feature & clear busy/reset flags
794 *
795 * It is unclear which other fields in the FIS are used. Just zero
796 * everything.
797 */
258223a3 798 ccb = ahci_get_err_ccb(ap);
1980eff3 799 ccb->ccb_xa.at = NULL;
258223a3 800 cmd_slot = ccb->ccb_cmd_hdr;
258223a3
MD
801
802 fis = ccb->ccb_cmd_table->cfis;
cec85a37 803 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1980eff3
MD
804 fis[0] = ATA_FIS_TYPE_H2D;
805 fis[15] = ATA_FIS_CONTROL_SRST|ATA_FIS_CONTROL_4BIT;
258223a3
MD
806
807 cmd_slot->prdtl = 0;
808 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
809 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_C); /* Clear busy on OK */
810 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_R); /* Reset */
258223a3
MD
811
812 ccb->ccb_xa.state = ATA_S_PENDING;
5f8c1efd 813 ccb->ccb_xa.flags = 0;
1980eff3
MD
814 if (ahci_poll(ccb, hz, NULL) != 0 ||
815 ccb->ccb_xa.state != ATA_S_COMPLETE) {
5f8c1efd 816 kprintf("%s: First FIS failed\n", PORTNAME(ap));
258223a3 817 goto err;
cec85a37 818 }
258223a3 819
cec85a37 820 /*
1980eff3
MD
821 * The device may muff the PHY up.
822 */
823 DELAY(10000); /* XXX 3000 */
824
825 /*
cec85a37
MD
826 * Prep second D2H command to read status and complete reset sequence
827 * AHCI 10.4.1 and "Serial ATA Revision 2.6". I can't find the ATA
828 * Rev 2.6 and it is unclear how the second FIS should be set up
829 * from the AHCI document.
830 *
b089d0bf 831 * Give the device 3ms before sending the second FIS.
cec85a37
MD
832 *
833 * It is unclear which other fields in the FIS are used. Just zero
834 * everything.
835 */
836 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1980eff3
MD
837 fis[0] = ATA_FIS_TYPE_H2D;
838 fis[15] = ATA_FIS_CONTROL_4BIT;
258223a3
MD
839
840 cmd_slot->prdtl = 0;
841 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
258223a3
MD
842
843 ccb->ccb_xa.state = ATA_S_PENDING;
5f8c1efd 844 ccb->ccb_xa.flags = 0;
1980eff3
MD
845 if (ahci_poll(ccb, hz, NULL) != 0 ||
846 ccb->ccb_xa.state != ATA_S_COMPLETE) {
5f8c1efd 847 kprintf("%s: Second FIS failed\n", PORTNAME(ap));
258223a3 848 goto err;
cec85a37 849 }
258223a3 850
1980eff3
MD
851 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
852 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
258223a3
MD
853 kprintf("%s: device didn't come ready after reset, TFD: 0x%b\n",
854 PORTNAME(ap),
855 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS);
856 rc = EBUSY;
857 goto err;
858 }
1980eff3 859 DELAY(10000);
258223a3 860
fd8bd957
MD
861 /*
862 * If the softreset is trying to clear a BSY condition after a
863 * normal portreset we assign the port type.
864 *
865 * If the softreset is being run first as part of the ccb error
866 * processing code then report if the device signature changed
867 * unexpectedly.
868 */
1980eff3
MD
869 if (ap->ap_type == ATA_PORT_T_NONE) {
870 ap->ap_type = ahci_port_signature_detect(ap, NULL);
fd8bd957 871 } else {
1980eff3
MD
872 if (ahci_port_signature_detect(ap, NULL) != ap->ap_type) {
873 kprintf("%s: device signature unexpectedly "
874 "changed\n", PORTNAME(ap));
875 rc = EBUSY; /* XXX */
fd8bd957
MD
876 }
877 }
258223a3 878 rc = 0;
1980eff3 879
b089d0bf 880 DELAY(3000);
258223a3
MD
881err:
882 if (ccb != NULL) {
1980eff3
MD
883 /*
884 * Abort our command, if it failed, by stopping command DMA.
885 */
cf5f3a81 886 if (rc && (ap->ap_active & (1 << ccb->ccb_slot))) {
258223a3
MD
887 kprintf("%s: stopping the port, softreset slot "
888 "%d was still active.\n",
889 PORTNAME(ap),
890 ccb->ccb_slot);
891 ahci_port_stop(ap, 0);
892 }
893 ccb->ccb_xa.state = ATA_S_ERROR;
1980eff3 894 fis[15] = 0;
258223a3 895 ahci_put_err_ccb(ccb);
1980eff3
MD
896
897 /*
898 * If the target is busy use CLO to clear the busy
899 * condition. The BSY should be cleared on the next
900 * start.
901 */
902 if (ahci_pread(ap, AHCI_PREG_TFD) &
903 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
904 ahci_port_clo(ap);
905 }
258223a3
MD
906 }
907
cf5f3a81
MD
908 /*
909 * If we failed to softreset make the port quiescent, otherwise
910 * make sure the port's start/stop state matches what it was on
911 * entry.
1980eff3
MD
912 *
913 * Don't kill the port if the softreset is on a port multiplier
914 * target, that would kill all the targets!
cf5f3a81 915 */
1980eff3 916 if (rc) {
cf5f3a81
MD
917 ahci_port_hardstop(ap);
918 } else if (cmd & AHCI_PREG_CMD_ST) {
1980eff3 919 kprintf("%s: STARTING PORT\n", PORTNAME(ap));
cf5f3a81
MD
920 ahci_port_start(ap);
921 } else {
1980eff3 922 kprintf("%s: STOPPING PORT\n", PORTNAME(ap));
cf5f3a81
MD
923 ahci_port_stop(ap, !(cmd & AHCI_PREG_CMD_FRE));
924 }
1980eff3
MD
925 if (rc)
926 ap->ap_probe = ATA_PROBE_FAILED;
927 else
928 ap->ap_probe = ATA_PROBE_NEED_IDENT;
258223a3
MD
929
930 crit_exit();
931
1980eff3
MD
932 kprintf("%s: END SOFTRESET\n", PORTNAME(ap));
933 ap->ap_flags &= ~AP_F_IN_RESET;
934
258223a3
MD
935 return (rc);
936}
937
fd8bd957
MD
938/*
939 * AHCI port reset, Section 10.4.2
940 *
941 * This function does a hard reset of the port. Note that the device
942 * connected to the port could still end-up hung.
943 */
258223a3 944int
1980eff3 945ahci_port_hardreset(struct ahci_port *ap, int hard)
258223a3 946{
1980eff3
MD
947 u_int32_t cmd, r;
948 int rc;
949 int loop;
950 int type;
258223a3
MD
951
952 DPRINTF(AHCI_D_VERBOSE, "%s: port reset\n", PORTNAME(ap));
953
1980eff3
MD
954 ap->ap_flags |= AP_F_IN_RESET;
955
956 /*
957 * Idle the port,
958 */
258223a3 959 ahci_port_stop(ap, 0);
cf5f3a81 960 ap->ap_state = AP_S_NORMAL;
1980eff3
MD
961 ap->ap_probe = ATA_PROBE_FAILED;
962 rc = 0;
cf5f3a81
MD
963
964 /*
1980eff3
MD
965 * The port may have been quiescent with its SUD bit cleared, so
966 * set the SUD (spin up device).
cf5f3a81
MD
967 */
968 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
969 cmd |= AHCI_PREG_CMD_SUD;
970 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
258223a3 971
1980eff3
MD
972 /*
973 * Perform device detection. Cycle the PHY off, wait 10ms.
974 * This simulates the SATA cable being physically unplugged.
975 */
976 ap->ap_type = ATA_PORT_T_NONE;
977
978 r = AHCI_PREG_SCTL_IPM_DISABLED;
979 if (hard == 2)
980 r |= AHCI_PREG_SCTL_DET_DISABLE;
981 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
258223a3 982 DELAY(10000);
258223a3 983
1980eff3
MD
984 /*
985 * Start transmitting COMRESET. COMRESET must be sent for at
986 * least 1ms.
987 */
988 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT;
258223a3
MD
989 if (AhciForceGen1 & (1 << ap->ap_num)) {
990 kprintf("%s: Force 1.5Gbits\n", PORTNAME(ap));
991 r |= AHCI_PREG_SCTL_SPD_GEN1;
992 } else {
993 r |= AHCI_PREG_SCTL_SPD_ANY;
994 }
995 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
1980eff3 996 DELAY(1000);
cf5f3a81
MD
997
998 /*
999 * Only SERR_DIAG_X needs to be cleared for TFD updates, but
1000 * since we are hard-resetting the port we might as well clear
1001 * the whole enchillada
1002 */
1003 ahci_flush_tfd(ap);
1004 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
258223a3
MD
1005 r &= ~AHCI_PREG_SCTL_DET_INIT;
1006 r |= AHCI_PREG_SCTL_DET_NONE;
1007 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
258223a3 1008
1980eff3
MD
1009 /*
1010 * Try to determine if there is a device on the port.
1011 *
1012 * Give the device 3/10 second to at least be detected.
1013 * If we fail clear PRCS (phy detect) since we may cycled
1014 * the phy and probably caused another PRCS interrupt.
1015 */
1016 for (loop = 30; loop; --loop) {
1017 r = ahci_pread(ap, AHCI_PREG_SSTS);
1018 if (r & AHCI_PREG_SSTS_DET)
1019 break;
1020 DELAY(10000);
1021 }
1022 if (loop == 0) {
1023 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS);
1024 kprintf("%s: Port appears to be unplugged\n",
1025 PORTNAME(ap));
1026 rc = ENODEV;
1027 }
1028
1029 /*
1030 * There is something on the port. Give the device 3 seconds
1031 * to fully negotiate.
1032 */
1033 if (rc == 0 &&
1034 ahci_pwait_eq(ap, 3000, AHCI_PREG_SSTS,
1035 AHCI_PREG_SSTS_DET, AHCI_PREG_SSTS_DET_DEV)) {
1036 kprintf("%s: Device may be powered down\n",
1037 PORTNAME(ap));
258223a3 1038 rc = ENODEV;
258223a3
MD
1039 }
1040
cec85a37 1041 /*
1980eff3 1042 * Wait for the device to become ready.
cec85a37 1043 *
b089d0bf
MD
1044 * This can take more then a second, give it 3 seconds. If we
1045 * succeed give the device another 3ms after that.
1980eff3
MD
1046 *
1047 * NOTE: Port Multipliers can do two things here. First they can
1048 * return device-ready if a device is on target 0 and also
1049 * return the signature for that device. If there is no
1050 * device on target 0 then BSY/DRQ is never cleared and
1051 * it never comes ready.
cec85a37 1052 */
1980eff3
MD
1053 if (rc == 0 &&
1054 ahci_pwait_clr_to(ap, 3000, AHCI_PREG_TFD,
1055 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1056 /*
1057 * The device is bricked or its a port multiplier and will
1058 * not unbusy until we do the pmprobe CLO softreset sequence.
1059 */
1060 rc = ahci_port_pmprobe(ap);
1061 if (rc) {
1062 kprintf("%s: Device will not come ready 0x%b\n",
1063 PORTNAME(ap),
1064 ahci_pread(ap, AHCI_PREG_TFD),
1065 AHCI_PFMT_TFD_STS);
1066 } else {
1067 ap->ap_type = ATA_PORT_T_PM;
1068 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET;
1069 kprintf("%s: Port Multiplier detected\n",
1070 PORTNAME(ap));
1071 }
1072 } else if (rc == 0) {
1073 /*
1074 * We generally will not get a port multiplier signature in
1075 * this case even if this is a port multiplier, because of
1076 * Intel's stupidity. We almost certainly got target 0
1077 * behind the PM, if there is a PM.
1078 *
1079 * Save the signature and probe for a PM. If we do not
1080 * find a PM then use the saved signature and return
1081 * success.
1082 */
1083 type = ahci_port_signature_detect(ap, NULL);
1084 rc = ahci_port_pmprobe(ap);
1085 if (rc) {
1086 ap->ap_type = type;
1087 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET;
1088 rc = 0;
1089 } else {
1090 ap->ap_type = ATA_PORT_T_PM;
1091 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET;
1092 kprintf("%s: Port Multiplier detected\n",
1093 PORTNAME(ap));
1094 }
1095 }
1096
1097 /*
1098 * hard-stop the port if we failed. This will set ap_probe
1099 * to FAILED.
1100 */
1101 if (rc)
1102 ahci_port_hardstop(ap);
1103 ap->ap_flags &= ~AP_F_IN_RESET;
1104 return (rc);
1105}
1106
1107/*
1108 * AHCI port multiplier probe. This routine is run by the hardreset code
1109 * if it gets past the device detect, whether or not BSY is found to be
1110 * stuck.
1111 *
1112 * We MUST use CLO to properly probe whether the port multiplier exists
1113 * or not.
1114 *
1115 * Return 0 on success, non-zero on failure.
1116 */
1117int
1118ahci_port_pmprobe(struct ahci_port *ap)
1119{
1120 struct ahci_cmd_hdr *cmd_slot;
1121 struct ahci_ccb *ccb = NULL;
1122 u_int8_t *fis = NULL;
1123 int rc = EIO;
1124 u_int32_t cmd;
1125 int count;
1126
1127 /*
1128 * If we don't support port multipliers don't try to detect one.
1129 */
1130 if ((ap->ap_sc->sc_cap & AHCI_REG_CAP_SPM) == 0)
1131 return (ENODEV);
1132
1133 count = 2;
1134#if 0
1135 kprintf("%s: START PMPROBE\n", PORTNAME(ap));
1136#endif
1137retry:
1138 /*
1139 * This code is only called from hardreset, which does not
1140 * high level command processing. The port should be stopped.
1141 *
1142 * Set PMA mode while the port is stopped.
1143 *
1144 * NOTE: On retry the port might be running, stopped, or failed.
1145 */
1146 ahci_port_stop(ap, 0);
1147 ap->ap_state = AP_S_NORMAL;
1148 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1149 cmd |= AHCI_PREG_CMD_PMA;
1150 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1151
1152 /*
1153 * Flush any errors and request CLO unconditionally, then start
1154 * the port.
1155 */
1156 ahci_flush_tfd(ap);
1157 ahci_port_clo(ap);
1158 if (ahci_port_start(ap)) {
1159 kprintf("%s: PMPROBE failed to start port, cannot softreset\n",
1160 PORTNAME(ap));
1161 goto err;
1162 }
1163
1164 /*
1165 * Check whether CLO worked
1166 */
1167 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1168 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1169 kprintf("%s: PMPROBE CLO %s, need port reset\n",
258223a3 1170 PORTNAME(ap),
1980eff3
MD
1171 (ahci_read(ap->ap_sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO)
1172 ? "failed" : "unsupported");
1173 rc = EBUSY;
258223a3
MD
1174 goto err;
1175 }
1176
1980eff3
MD
1177 /*
1178 * Prep the first H2D command with SRST feature & clear busy/reset
1179 * flags.
1180 */
1181 ccb = ahci_get_err_ccb(ap);
1182 cmd_slot = ccb->ccb_cmd_hdr;
1183
1184 fis = ccb->ccb_cmd_table->cfis;
1185 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1186 fis[0] = ATA_FIS_TYPE_H2D;
1187 fis[1] = 0x0F; /* Target 15 */
1188 fis[15] = ATA_FIS_CONTROL_SRST | ATA_FIS_CONTROL_4BIT;
1189
1190 cmd_slot->prdtl = 0;
1191 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
1192 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_C); /* Clear busy on OK */
1193 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_R); /* Reset */
1194 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_PMP); /* port 0xF */
1195
1196 ccb->ccb_xa.state = ATA_S_PENDING;
1197 ccb->ccb_xa.flags = 0;
1198
1199 if (ahci_poll(ccb, hz, NULL) != 0 ||
1200 ccb->ccb_xa.state != ATA_S_COMPLETE) {
1201 kprintf("%s: PMPROBE First FIS failed\n", PORTNAME(ap));
1202 if (--count) {
1203 fis[15] = 0;
1204 ahci_put_err_ccb(ccb);
1205 goto retry;
1206 }
1207 goto err;
1208 }
1209 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1210 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1211 kprintf("%s: PMPROBE Busy after first FIS\n", PORTNAME(ap));
1212 }
1213
1214 /*
1215 * The device may have muffed up the PHY when it reset.
1216 */
1217 DELAY(10000);
1218 ahci_flush_tfd(ap);
1219 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
1220 /* ahci_pm_phy_status(ap, 15, &cmd); */
1221
1222 /*
1223 * Prep second D2H command to read status and complete reset sequence
1224 * AHCI 10.4.1 and "Serial ATA Revision 2.6". I can't find the ATA
1225 * Rev 2.6 and it is unclear how the second FIS should be set up
1226 * from the AHCI document.
1227 *
1228 * Give the device 3ms before sending the second FIS.
1229 *
1230 * It is unclear which other fields in the FIS are used. Just zero
1231 * everything.
1232 */
1233 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1234 fis[0] = ATA_FIS_TYPE_H2D;
1235 fis[1] = 0x0F;
1236 fis[15] = ATA_FIS_CONTROL_4BIT;
1237
1238 cmd_slot->prdtl = 0;
1239 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
1240 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_PMP); /* port 0xF */
1241
1242 ccb->ccb_xa.state = ATA_S_PENDING;
1243 ccb->ccb_xa.flags = 0;
1244
1245 if (ahci_poll(ccb, hz, NULL) != 0 ||
1246 ccb->ccb_xa.state != ATA_S_COMPLETE) {
1247 kprintf("%s: PMPROBE Second FIS failed\n", PORTNAME(ap));
1248 if (--count) {
1249 fis[15] = 0;
1250 ahci_put_err_ccb(ccb);
1251 goto retry;
1252 }
1253 goto err;
1254 }
1255
1256 /*
1257 * What? We succeeded? Yup, but for some reason the signature
1258 * is still latched from the original detect (that saw target 0
1259 * behind the PM), and I don't know how to clear the condition
1260 * other then by retrying the whole reset sequence.
1261 */
1262 if (--count) {
1263 fis[15] = 0;
1264 ahci_put_err_ccb(ccb);
1265 goto retry;
1266 }
1267
1268 /*
1269 * Get the signature. The caller sets the ap fields.
1270 */
1271 if (ahci_port_signature_detect(ap, NULL) == ATA_PORT_T_PM) {
1272 ap->ap_ata[15].at_probe = ATA_PROBE_GOOD;
1273 rc = 0;
1274 } else {
1275 rc = EBUSY;
1276 }
cf5f3a81
MD
1277
1278 /*
1980eff3 1279 * Fall through / clean up the CCB and perform error processing.
cf5f3a81 1280 */
258223a3 1281err:
1980eff3
MD
1282 if (ccb != NULL) {
1283 /*
1284 * Abort our command, if it failed, by stopping command DMA.
1285 */
1286#if 0
1287 kprintf("rc=%d active=%08x sactive=%08x slot=%d\n",
1288 rc, ap->ap_active, ap->ap_sactive, ccb->ccb_slot);
1289#endif
1290 if (rc && (ap->ap_active & (1 << ccb->ccb_slot))) {
1291 kprintf("%s: PMP stopping the port, softreset slot "
1292 "%d was still active.\n",
1293 PORTNAME(ap),
1294 ccb->ccb_slot);
1295 ahci_port_stop(ap, 0);
1296 }
1297 ccb->ccb_xa.state = ATA_S_ERROR;
1298 fis[15] = 0;
1299 ahci_put_err_ccb(ccb);
1300 }
1301
1302 /*
1303 * If we failed turn off PMA, otherwise identify the port multiplier.
1304 * CAM will iterate the devices.
1305 */
1306 if (rc) {
1307 ahci_port_stop(ap, 0);
1308 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1309 cmd &= ~AHCI_PREG_CMD_PMA;
1310 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1311 } else {
1312 ahci_pm_identify(ap);
1313#if 0
1314 ahci_pm_hardreset(ap, 0);
1315 ahci_pm_hardreset(ap, 1);
1316 ahci_pm_hardreset(ap, 2);
1317 ahci_pm_hardreset(ap, 3);
1318 ahci_pm_hardreset(ap, 4);
1319#endif
1320 }
1321 ahci_port_stop(ap, 0);
1322
1323#if 0
1324 kprintf("%s: END PMPROBE\n", PORTNAME(ap));
1325#endif
1326
1327 return(rc);
cf5f3a81
MD
1328}
1329
1980eff3 1330
cf5f3a81
MD
1331/*
1332 * Hard-stop on hot-swap device removal. See 10.10.1
1333 *
1334 * Place the port in a mode that will allow it to detect hot-swap insertions.
1335 * This is a bit imprecise because just setting-up SCTL to DET_INIT doesn't
1336 * seem to do the job.
1337 */
1338void
1339ahci_port_hardstop(struct ahci_port *ap)
1340{
1980eff3 1341 struct ata_port *at;
cf5f3a81
MD
1342 u_int32_t r;
1343 u_int32_t cmd;
1980eff3 1344 int i;
cf5f3a81
MD
1345
1346 /*
1347 * Stop the port. We can't modify things like SUD if the port
1348 * is running.
1349 */
1350 ap->ap_state = AP_S_FATAL_ERROR;
1980eff3
MD
1351 ap->ap_probe = ATA_PROBE_FAILED;
1352 ap->ap_type = ATA_PORT_T_NONE;
cf5f3a81
MD
1353 ahci_port_stop(ap, 0);
1354 cmd = ahci_pread(ap, AHCI_PREG_CMD);
1355
1356 /*
1980eff3
MD
1357 * Clean up AT sub-ports on SATA port.
1358 */
1359 for (i = 0; ap->ap_ata && i < AHCI_MAX_PMPORTS; ++i) {
1360 at = &ap->ap_ata[i];
1361 at->at_type = ATA_PORT_T_NONE;
1362 at->at_probe = ATA_PORT_T_NONE;
1363 }
1364
1365 /*
1366 * Turn off port-multiplier control bit
1367 */
1368 if (cmd & AHCI_PREG_CMD_PMA) {
1369 cmd &= ~AHCI_PREG_CMD_PMA;
1370 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1371 }
1372
1373 /*
cf5f3a81
MD
1374 * Make sure FRE is active. There isn't anything we can do if it
1375 * fails so just ignore errors.
1376 */
1377 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
1378 cmd |= AHCI_PREG_CMD_FRE;
1379 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1380 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0)
1381 ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR);
1382 }
1383
1384 /*
1385 * 10.10.3 DET must be set to 0 before setting SUD to 0.
1386 * 10.10.1 place us in the Listen state.
1387 *
1388 * Deactivating SUD only applies if the controller supports SUD.
1389 */
1390 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
1391 DELAY(1000);
1392 if (cmd & AHCI_PREG_CMD_SUD) {
1393 cmd &= ~AHCI_PREG_CMD_SUD;
1394 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1395 }
1396 DELAY(1000);
1397
1398 /*
1399 * Transition su to the spin-up state. HVA shall send COMRESET and
1400 * begin initialization sequence (whatever that means).
1401 *
1402 * This only applies if the controller supports SUD.
1403 */
1404 cmd |= AHCI_PREG_CMD_SUD;
258223a3 1405 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
cf5f3a81 1406 DELAY(1000);
258223a3 1407
cf5f3a81
MD
1408 /*
1409 * Transition us to the Reset state. Theoretically we send a
1410 * continuous stream of COMRESETs in this state.
1411 */
1412 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT;
1413 if (AhciForceGen1 & (1 << ap->ap_num)) {
1414 kprintf("%s: Force 1.5Gbits\n", PORTNAME(ap));
1415 r |= AHCI_PREG_SCTL_SPD_GEN1;
1416 } else {
1417 r |= AHCI_PREG_SCTL_SPD_ANY;
1418 }
1419 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
1420 DELAY(1000);
1421
1422 /*
1423 * Flush SERR_DIAG_X so the TFD can update.
1424 */
1425 ahci_flush_tfd(ap);
1426
1427 /*
1428 * Leave us in COMRESET (both SUD and INIT active), the HBA should
1429 * hopefully send us a DIAG_X-related interrupt if it receives
1430 * a COMINIT, and if not that then at least a Phy transition
1431 * interrupt.
1432 *
1433 * If we transition INIT from 1->0 to begin the initalization
1434 * sequence it is unclear if that sequence will remain active
1435 * until the next device insertion.
1436 *
1437 * If we go back to the listen state it is unclear if the
1438 * device will actually send us a COMINIT, since we aren't
1439 * sending any COMRESET's
1440 */
1441 /* NOP */
1442}
1443
1444/*
1445 * Multiple events may have built up in the TFD. The spec is not very
1446 * clear on this but it does seem to serialize events so clearing DIAG_X
1447 * just once might not do the job during a reset sequence.
1448 */
1449void
1450ahci_flush_tfd(struct ahci_port *ap)
1451{
1452 u_int32_t r;
1453
1454 r = ahci_pread(ap, AHCI_PREG_SERR);
1980eff3
MD
1455 while (r & AHCI_PREG_SERR_DIAG_X) {
1456 ahci_pwrite(ap, AHCI_PREG_SERR, AHCI_PREG_SERR_DIAG_X);
cf5f3a81
MD
1457 DELAY(1000);
1458 r = ahci_pread(ap, AHCI_PREG_SERR);
1459 }
258223a3
MD
1460}
1461
fd8bd957
MD
1462/*
1463 * Figure out what type of device is connected to the port, ATAPI or
1464 * DISK.
1465 */
1466int
1980eff3 1467ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at)
fd8bd957
MD
1468{
1469 u_int32_t sig;
1470
1471 sig = ahci_pread(ap, AHCI_PREG_SIG);
1980eff3 1472 kprintf("%s: sig %08x\n", ATANAME(ap, at), sig);
fd8bd957
MD
1473 if ((sig & 0xffff0000) == (SATA_SIGNATURE_ATAPI & 0xffff0000)) {
1474 return(ATA_PORT_T_ATAPI);
1980eff3
MD
1475 } else if ((sig & 0xffff0000) ==
1476 (SATA_SIGNATURE_PORT_MULTIPLIER & 0xffff0000)) {
1477 kprintf("found PM\n");
1478 return(ATA_PORT_T_PM);
fd8bd957
MD
1479 } else {
1480 return(ATA_PORT_T_DISK);
1481 }
1482}
1483
1484/*
1485 * Load the DMA descriptor table for a CCB's buffer.
1486 */
258223a3
MD
1487int
1488ahci_load_prdt(struct ahci_ccb *ccb)
1489{
1490 struct ahci_port *ap = ccb->ccb_port;
1491 struct ahci_softc *sc = ap->ap_sc;
1492 struct ata_xfer *xa = &ccb->ccb_xa;
1493 struct ahci_prdt *prdt = ccb->ccb_cmd_table->prdt;
1494 bus_dmamap_t dmap = ccb->ccb_dmamap;
1495 struct ahci_cmd_hdr *cmd_slot = ccb->ccb_cmd_hdr;
1496 int error;
1497
1498 if (xa->datalen == 0) {
1499 ccb->ccb_cmd_hdr->prdtl = 0;
1500 return (0);
1501 }
1502
1503 error = bus_dmamap_load(sc->sc_tag_data, dmap,
1504 xa->data, xa->datalen,
1505 ahci_load_prdt_callback,
1506 &prdt,
1507 ((xa->flags & ATA_F_NOWAIT) ?
1508 BUS_DMA_NOWAIT : BUS_DMA_WAITOK));
1509 if (error != 0) {
1510 kprintf("%s: error %d loading dmamap\n", PORTNAME(ap), error);
1511 return (1);
1512 }
1513 if (xa->flags & ATA_F_PIO)
1514 prdt->flags |= htole32(AHCI_PRDT_FLAG_INTR);
1515
1516 cmd_slot->prdtl = htole16(prdt - ccb->ccb_cmd_table->prdt + 1);
1517
1518 bus_dmamap_sync(sc->sc_tag_data, dmap,
1519 (xa->flags & ATA_F_READ) ?
1520 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1521
1522 return (0);
1523
1524#ifdef DIAGNOSTIC
1525diagerr:
1526 bus_dmamap_unload(sc->sc_tag_data, dmap);
1527 return (1);
1528#endif
1529}
1530
1531/*
1532 * Callback from BUSDMA system to load the segment list. The passed segment
1533 * list is a temporary structure.
1534 */
1535static
1536void
1537ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, int nsegs,
1538 int error)
1539{
1540 struct ahci_prdt *prd = *(void **)info;
1541 u_int64_t addr;
1542
1543 KKASSERT(nsegs <= AHCI_MAX_PRDT);
1544
1545 while (nsegs) {
1546 addr = segs->ds_addr;
1547 prd->dba_hi = htole32((u_int32_t)(addr >> 32));
1548 prd->dba_lo = htole32((u_int32_t)addr);
1549#ifdef DIAGNOSTIC
1550 KKASSERT((addr & 1) == 0);
1551 KKASSERT((segs->ds_len & 1) == 0);
1552#endif
1553 prd->flags = htole32(segs->ds_len - 1);
1554 --nsegs;
1555 if (nsegs)
1556 ++prd;
1557 ++segs;
1558 }
1559 *(void **)info = prd; /* return last valid segment */
1560}
1561
1562void
1563ahci_unload_prdt(struct ahci_ccb *ccb)
1564{
1565 struct ahci_port *ap = ccb->ccb_port;
1566 struct ahci_softc *sc = ap->ap_sc;
1567 struct ata_xfer *xa = &ccb->ccb_xa;
1568 bus_dmamap_t dmap = ccb->ccb_dmamap;
1569
1570 if (xa->datalen != 0) {
1571 bus_dmamap_sync(sc->sc_tag_data, dmap,
1572 (xa->flags & ATA_F_READ) ?
1573 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1574
1575 bus_dmamap_unload(sc->sc_tag_data, dmap);
1576
1577 if (ccb->ccb_xa.flags & ATA_F_NCQ)
1578 xa->resid = 0;
1579 else
1580 xa->resid = xa->datalen -
1581 le32toh(ccb->ccb_cmd_hdr->prdbc);
1582 }
1583}
1584
5f8c1efd
MD
1585/*
1586 * Start a command and poll for completion.
1587 *
1588 * NOTE: If the caller specifies a NULL timeout function the caller is
1589 * responsible for clearing hardware state on failure, but we will
1590 * deal with removing the ccb from any pending queue.
1591 *
1592 * NOTE: NCQ should never be used with this function.
cf5f3a81
MD
1593 *
1594 * NOTE: If the port is in a failed state and stopped we do not try
1595 * to activate the ccb.
5f8c1efd 1596 */
258223a3
MD
1597int
1598ahci_poll(struct ahci_ccb *ccb, int timeout, void (*timeout_fn)(void *))
1599{
5f8c1efd
MD
1600 struct ahci_port *ap = ccb->ccb_port;
1601 u_int32_t slot_mask = 1 << ccb->ccb_slot;
258223a3 1602
cf5f3a81
MD
1603 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) {
1604 ccb->ccb_xa.state = ATA_S_ERROR;
1605 return(1);
1606 }
258223a3
MD
1607 crit_enter();
1608 ahci_start(ccb);
1980eff3 1609
258223a3 1610 do {
5f8c1efd 1611 if (ahci_port_intr(ap, AHCI_PREG_CI_ALL_SLOTS) & slot_mask) {
258223a3
MD
1612 crit_exit();
1613 return (0);
1614 }
5f8c1efd
MD
1615 if (ccb->ccb_xa.state != ATA_S_ONCHIP &&
1616 ccb->ccb_xa.state != ATA_S_PENDING) {
1617 break;
1618 }
258223a3
MD
1619 DELAY(1000000 / hz);
1620 } while (--timeout > 0);
258223a3 1621
5f8c1efd
MD
1622 if (ccb->ccb_xa.state != ATA_S_ONCHIP &&
1623 ccb->ccb_xa.state != ATA_S_PENDING) {
1624 kprintf("%s: Warning poll completed unexpectedly for slot %d\n",
1625 PORTNAME(ap), ccb->ccb_slot);
1626 crit_exit();
1627 return (0);
1628 }
1629
1630 kprintf("%s: Poll timed-out for slot %d state %d\n",
1980eff3 1631 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_slot, ccb->ccb_xa.state);
5f8c1efd
MD
1632
1633 if (timeout_fn != NULL) {
258223a3 1634 timeout_fn(ccb);
5f8c1efd
MD
1635 } else {
1636 if (ccb->ccb_xa.state == ATA_S_PENDING)
1637 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
1638 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1639 }
258223a3
MD
1640 crit_exit();
1641
1642 return (1);
1643}
1644
1645void
1646ahci_start(struct ahci_ccb *ccb)
1647{
1648 struct ahci_port *ap = ccb->ccb_port;
1649 struct ahci_softc *sc = ap->ap_sc;
1650
1651 KKASSERT(ccb->ccb_xa.state == ATA_S_PENDING);
1652
1653 /* Zero transferred byte count before transfer */
1654 ccb->ccb_cmd_hdr->prdbc = 0;
1655
1656 /* Sync command list entry and corresponding command table entry */
1657 bus_dmamap_sync(sc->sc_tag_cmdh,
1658 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list),
1659 BUS_DMASYNC_PREWRITE);
1660 bus_dmamap_sync(sc->sc_tag_cmdt,
1661 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table),
1662 BUS_DMASYNC_PREWRITE);
1663
1664 /* Prepare RFIS area for write by controller */
1665 bus_dmamap_sync(sc->sc_tag_rfis,
1666 AHCI_DMA_MAP(ap->ap_dmamem_rfis),
1667 BUS_DMASYNC_PREREAD);
1668
1669 if (ccb->ccb_xa.flags & ATA_F_NCQ) {
1980eff3
MD
1670 /*
1671 * Issue NCQ commands only when there are no outstanding
1672 * standard commands.
1673 */
1674 if (ap->ap_active || TAILQ_FIRST(&ap->ap_ccb_pending)) {
258223a3 1675 TAILQ_INSERT_TAIL(&ap->ap_ccb_pending, ccb, ccb_entry);
1980eff3 1676 } else {
258223a3
MD
1677 KKASSERT(ap->ap_active_cnt == 0);
1678 ap->ap_sactive |= (1 << ccb->ccb_slot);
1679 ccb->ccb_xa.state = ATA_S_ONCHIP;
1680 ahci_pwrite(ap, AHCI_PREG_SACT, 1 << ccb->ccb_slot);
1681 ahci_pwrite(ap, AHCI_PREG_CI, 1 << ccb->ccb_slot);
1682 }
1683 } else {
5f8c1efd
MD
1684 /*
1685 * Wait for all NCQ commands to finish before issuing standard
1980eff3
MD
1686 * command. Allow up to <limit> non-NCQ commands to be active.
1687 *
1688 * XXX If ap is a port multiplier only allow 1. At least the
1689 * NVidia-MCP77 part seems to barf if more then one
1690 * command is activated, even though it isn't NCQ.
1691 *
1692 * If I set up more then one I get phy errors and the
1693 * port fails.
5f8c1efd 1694 */
1980eff3
MD
1695 int limit = (ap->ap_type == ATA_PORT_T_PM) ? 1 : 2;
1696 if (ap->ap_sactive || ap->ap_active_cnt >= limit) {
258223a3 1697 TAILQ_INSERT_TAIL(&ap->ap_ccb_pending, ccb, ccb_entry);
1980eff3 1698 } else {
258223a3
MD
1699 ap->ap_active |= 1 << ccb->ccb_slot;
1700 ccb->ccb_xa.state = ATA_S_ONCHIP;
1701 ahci_pwrite(ap, AHCI_PREG_CI, 1 << ccb->ccb_slot);
1702 ap->ap_active_cnt++;
1703 }
1704 }
1705}
1706
1707void
1708ahci_issue_pending_ncq_commands(struct ahci_port *ap)
1709{
1710 struct ahci_ccb *nextccb;
1711 u_int32_t sact_change = 0;
1712
1713 KKASSERT(ap->ap_active_cnt == 0);
1714
1715 nextccb = TAILQ_FIRST(&ap->ap_ccb_pending);
1716 if (nextccb == NULL || !(nextccb->ccb_xa.flags & ATA_F_NCQ))
1717 return;
1718
1719 /* Start all the NCQ commands at the head of the pending list. */
1720 do {
1721 TAILQ_REMOVE(&ap->ap_ccb_pending, nextccb, ccb_entry);
1722 sact_change |= 1 << nextccb->ccb_slot;
1723 nextccb->ccb_xa.state = ATA_S_ONCHIP;
1724 nextccb = TAILQ_FIRST(&ap->ap_ccb_pending);
1725 } while (nextccb && (nextccb->ccb_xa.flags & ATA_F_NCQ));
1726
1727 ap->ap_sactive |= sact_change;
1728 ahci_pwrite(ap, AHCI_PREG_SACT, sact_change);
1729 ahci_pwrite(ap, AHCI_PREG_CI, sact_change);
1730
1731 return;
1732}
1733
1734void
1735ahci_issue_pending_commands(struct ahci_port *ap, int last_was_ncq)
1736{
1737 struct ahci_ccb *nextccb;
1738
1739 nextccb = TAILQ_FIRST(&ap->ap_ccb_pending);
1740 if (nextccb && (nextccb->ccb_xa.flags & ATA_F_NCQ)) {
1741 KKASSERT(last_was_ncq == 0); /* otherwise it should have
1742 * been started already. */
1743
1980eff3
MD
1744 /*
1745 * Issue NCQ commands only when there are no outstanding
1746 * standard commands.
1747 */
258223a3
MD
1748 if (ap->ap_active == 0)
1749 ahci_issue_pending_ncq_commands(ap);
1750 else
1980eff3 1751 KKASSERT(ap->ap_active_cnt > 0);
258223a3 1752 } else if (nextccb) {
1980eff3 1753 if (ap->ap_sactive || last_was_ncq)
258223a3
MD
1754 KKASSERT(ap->ap_active_cnt == 0);
1755
1980eff3
MD
1756 /*
1757 * Wait for all NCQ commands to finish before issuing standard
1758 * command. Then keep up to 2 standard commands on-chip at
1759 * a time.
1760 */
1761 if (ap->ap_sactive)
258223a3
MD
1762 return;
1763
1980eff3
MD
1764 while (ap->ap_active_cnt < 2 &&
1765 nextccb && (nextccb->ccb_xa.flags & ATA_F_NCQ) == 0) {
258223a3
MD
1766 TAILQ_REMOVE(&ap->ap_ccb_pending, nextccb, ccb_entry);
1767 ap->ap_active |= 1 << nextccb->ccb_slot;
1768 nextccb->ccb_xa.state = ATA_S_ONCHIP;
1769 ahci_pwrite(ap, AHCI_PREG_CI, 1 << nextccb->ccb_slot);
1980eff3 1770 ap->ap_active_cnt++;
258223a3 1771 nextccb = TAILQ_FIRST(&ap->ap_ccb_pending);
1980eff3 1772 }
258223a3
MD
1773 }
1774}
1775
1776void
1777ahci_intr(void *arg)
1778{
1779 struct ahci_softc *sc = arg;
1780 u_int32_t is, ack = 0;
1781 int port;
1782
1783 /* Read global interrupt status */
1784 is = ahci_read(sc, AHCI_REG_IS);
1785 if (is == 0 || is == 0xffffffff)
1786 return;
1787 ack = is;
1788
1789#ifdef AHCI_COALESCE
1790 /* Check coalescing interrupt first */
1791 if (is & sc->sc_ccc_mask) {
1792 DPRINTF(AHCI_D_INTR, "%s: command coalescing interrupt\n",
1793 DEVNAME(sc));
1794 is &= ~sc->sc_ccc_mask;
1795 is |= sc->sc_ccc_ports_cur;
1796 }
1797#endif
1798
1799 /* Process interrupts for each port */
1800 while (is) {
1801 port = ffs(is) - 1;
1802 if (sc->sc_ports[port]) {
1803 ahci_port_intr(sc->sc_ports[port],
1804 AHCI_PREG_CI_ALL_SLOTS);
1805 }
1806 is &= ~(1 << port);
1807 }
1808
1809 /* Finally, acknowledge global interrupt */
1810 ahci_write(sc, AHCI_REG_IS, ack);
1811}
1812
1813u_int32_t
1814ahci_port_intr(struct ahci_port *ap, u_int32_t ci_mask)
1815{
1816 struct ahci_softc *sc = ap->ap_sc;
1817 u_int32_t is, ci_saved, ci_masked, processed = 0;
22181ab7 1818 int slot;
258223a3 1819 struct ahci_ccb *ccb = NULL;
1980eff3 1820 struct ata_port *ccb_at = NULL;
258223a3
MD
1821 volatile u_int32_t *active;
1822#ifdef DIAGNOSTIC
1823 u_int32_t tmp;
1824#endif
22181ab7
MD
1825 enum { NEED_NOTHING, NEED_RESTART, NEED_HOTPLUG_INSERT,
1826 NEED_HOTPLUG_REMOVE } need = NEED_NOTHING;
258223a3
MD
1827
1828 is = ahci_pread(ap, AHCI_PREG_IS);
1829
1980eff3
MD
1830#if 0
1831 kprintf("%s: INTERRUPT %b\n", PORTNAME(ap),
1832 is, AHCI_PFMT_IS);
1833#endif
1834
258223a3
MD
1835 /* Ack port interrupt only if checking all command slots. */
1836 if (ci_mask == AHCI_PREG_CI_ALL_SLOTS)
1837 ahci_pwrite(ap, AHCI_PREG_IS, is);
1838
1839 if (is)
1840 DPRINTF(AHCI_D_INTR, "%s: interrupt: %b\n", PORTNAME(ap),
1841 is, AHCI_PFMT_IS);
1842
1843 if (ap->ap_sactive) {
1844 /* Active NCQ commands - use SActive instead of CI */
1845 KKASSERT(ap->ap_active == 0);
1846 KKASSERT(ap->ap_active_cnt == 0);
1847 ci_saved = ahci_pread(ap, AHCI_PREG_SACT);
1848 active = &ap->ap_sactive;
1849 } else {
1850 /* Save CI */
1851 ci_saved = ahci_pread(ap, AHCI_PREG_CI);
1852 active = &ap->ap_active;
1853 }
1854
258223a3 1855 if (is & AHCI_PREG_IS_TFES) {
1980eff3
MD
1856 /*
1857 * Command failed. See AHCI 1.1 spec 6.2.2.1 and 6.2.2.2.
1858 *
1859 * This stops command processing.
1860 */
1861 u_int32_t tfd, serr;
1862 int err_slot;
258223a3
MD
1863
1864 tfd = ahci_pread(ap, AHCI_PREG_TFD);
1865 serr = ahci_pread(ap, AHCI_PREG_SERR);
1866
cf5f3a81
MD
1867 /*
1868 * If no NCQ commands are active the error slot is easily
1869 * determined, otherwise we have to extract the error
1870 * from the log page.
1871 */
258223a3 1872 if (ap->ap_sactive == 0) {
cf5f3a81
MD
1873 err_slot = AHCI_PREG_CMD_CCS(
1874 ahci_pread(ap, AHCI_PREG_CMD));
258223a3 1875 ccb = &ap->ap_ccbs[err_slot];
1980eff3 1876 ccb_at = ccb->ccb_xa.at; /* can be NULL */
258223a3
MD
1877
1878 /* Preserve received taskfile data from the RFIS. */
1879 memcpy(&ccb->ccb_xa.rfis, ap->ap_rfis->rfis,
cf5f3a81
MD
1880 sizeof(struct ata_fis_d2h));
1881 } else {
1882 err_slot = -1;
1883 }
258223a3 1884
1980eff3
MD
1885 DPRINTF(AHCI_D_VERBOSE, "%s: errd slot %d, TFD: %b, SERR: %b\n",
1886 PORTNAME(ap), err_slot,
1887 tfd, AHCI_PFMT_TFD_STS,
1888 serr, AHCI_PFMT_SERR);
258223a3 1889
cf5f3a81 1890 /* Stopping the port clears CI and SACT */
258223a3 1891 ahci_port_stop(ap, 0);
22181ab7 1892 need = NEED_RESTART;
258223a3 1893
cf5f3a81
MD
1894 /*
1895 * Clear SERR (primarily DIAG_X) to enable capturing of the
1896 * next error.
1897 */
258223a3
MD
1898 ahci_pwrite(ap, AHCI_PREG_SERR, serr);
1899
1900 /* Acknowledge the interrupts we can recover from. */
cf5f3a81
MD
1901 ahci_pwrite(ap, AHCI_PREG_IS,
1902 AHCI_PREG_IS_TFES | AHCI_PREG_IS_IFS);
1980eff3 1903 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_IFS);
258223a3
MD
1904
1905 /* If device hasn't cleared its busy status, try to idle it. */
1906 if (tfd & (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1980eff3
MD
1907 kprintf("%s: Attempting to idle device ccb=%p\n",
1908 PORTNAME(ap), ccb_at);
1909 if (ap->ap_flags & AP_F_IN_RESET)
1910 goto fatal;
1911 /*
1912 * XXX how do we unbrick a PM target (ccb_at != NULL).
1913 *
1914 * For now fail the target and use CLO to clear the
1915 * busy condition and make the ahci port usable for
1916 * the remaining devices.
1917 */
1918 if (ccb_at) {
1919 ccb_at->at_probe = ATA_PROBE_FAILED;
1920 ahci_port_clo(ap);
1921 } else if (ahci_port_reset(ap, ccb_at, 0)) {
17eab71e
MD
1922 kprintf("%s: Unable to idle device, port "
1923 "bricked on us\n",
258223a3 1924 PORTNAME(ap));
17eab71e 1925 goto fatal;
258223a3
MD
1926 }
1927
1928 /* Had to reset device, can't gather extended info. */
1929 } else if (ap->ap_sactive) {
1980eff3
MD
1930 /*
1931 * Recover the NCQ error from log page 10h.
1932 *
1933 * XXX NCQ currently not supported with port
1934 * multiplier.
1935 */
258223a3 1936 ahci_port_read_ncq_error(ap, &err_slot);
cf5f3a81 1937 kprintf("recover from NCQ error err_slot %d\n", err_slot);
258223a3
MD
1938 if (err_slot < 0)
1939 goto failall;
1940
1941 DPRINTF(AHCI_D_VERBOSE, "%s: NCQ errored slot %d\n",
1942 PORTNAME(ap), err_slot);
1943
1944 ccb = &ap->ap_ccbs[err_slot];
1945 } else {
1946 /* Didn't reset, could gather extended info from log. */
1980eff3
MD
1947 kprintf("%s: didn't reset err_slot %d "
1948 "sact=%08x act=%08x\n",
1949 PORTNAME(ap),
cf5f3a81 1950 err_slot, ap->ap_sactive, ap->ap_active);
258223a3
MD
1951 }
1952
1953 /*
1954 * If we couldn't determine the errored slot, reset the port
1955 * and fail all the active slots.
1956 */
1957 if (err_slot == -1) {
1980eff3
MD
1958 if (ap->ap_flags & AP_F_IN_RESET)
1959 goto fatal;
1960 /*
1961 * XXX how do we unbrick a PM target (ccb_at != NULL).
1962 *
1963 * For now fail the target and use CLO to clear the
1964 * busy condition and make the ahci port usable for
1965 * the remaining devices.
1966 */
1967 if (ccb_at) {
1968 ccb_at->at_probe = ATA_PROBE_FAILED;
1969 ahci_port_clo(ap);
1970 } else if (ahci_port_reset(ap, ccb_at, 0)) {
17eab71e
MD
1971 kprintf("%s: Unable to idle device after "
1972 "NCQ error, port bricked on us\n",
258223a3
MD
1973 PORTNAME(ap));
1974 goto fatal;
1975 }
1976 kprintf("%s: couldn't recover NCQ error, failing "
1977 "all outstanding commands.\n",
1978 PORTNAME(ap));
1979 goto failall;
1980 }
1981
1982 /* Clear the failed command in saved CI so completion runs. */
1983 ci_saved &= ~(1 << err_slot);
1984
1985 /* Note the error in the ata_xfer. */
1986 KKASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP);
1987 ccb->ccb_xa.state = ATA_S_ERROR;
1988
1989#ifdef DIAGNOSTIC
1990 /* There may only be one outstanding standard command now. */
1991 if (ap->ap_sactive == 0) {
1992 tmp = ci_saved;
1993 if (tmp) {
1994 slot = ffs(tmp) - 1;
1995 tmp &= ~(1 << slot);
1996 KKASSERT(tmp == 0);
1997 }
1998 }
1999#endif
1980eff3
MD
2000 } else if (is & AHCI_PREG_IS_DHRS) {
2001 /*
2002 * Command posted D2H register FIS to the rfis. This
8bf6a3ff
MD
2003 * does NOT stop command processing and it is unclear
2004 * how we are supposed to deal with it other then using
2005 * only a queue of 1.
2006 *
2007 * We must copy the port rfis to the ccb and restart
2008 * command processing. ahci_pm_read() does not function
2009 * without this support.
1980eff3
MD
2010 */
2011 int err_slot;
2012
2013 if (ap->ap_sactive == 0) {
2014 err_slot = AHCI_PREG_CMD_CCS(
2015 ahci_pread(ap, AHCI_PREG_CMD));
2016 ccb = &ap->ap_ccbs[err_slot];
2017 ccb_at = ccb->ccb_xa.at; /* can be NULL */
2018
2019 memcpy(&ccb->ccb_xa.rfis, ap->ap_rfis->rfis,
2020 sizeof(struct ata_fis_d2h));
2021 } else {
2022 kprintf("%s: Unexpected DHRS posted while "
2023 "NCQ running\n", PORTNAME(ap));
2024 err_slot = -1;
2025 }
1980eff3
MD
2026 }
2027
2028 /*
2029 * Device notification to us.
2030 *
2031 * For some reason this interrupt can occur without any notification
2032 * bits actually being set.
2033 */
2034 if ((is & AHCI_PREG_IS_SDBS) && (sc->sc_cap & AHCI_REG_CAP_SSNTF)) {
2035 u_int32_t data;
2036
2037 data = ahci_pread(ap, AHCI_PREG_SNTF);
2038 if (data) {
2039 kprintf("%s: NOTIFY %08x\n", PORTNAME(ap), data);
2040 ahci_pwrite(ap, AHCI_PREG_SNTF, data);
2041 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_SDBS);
2042 }
2043 }
2044#if 0
2045 /* XXX future IFS recovery code? or just scrap it */
2046 if (is & AHCI_PREG_IS_IFS) {
2047 u_int32_t serr = ahci_pread(ap, AHCI_PREG_SERR);
2048 kprintf("%s: Ignoring IFS (XXX) (IS: %b, SERR: %b)\n",
2049 PORTNAME(ap),
2050 is, AHCI_PFMT_IS,
2051 serr, AHCI_PFMT_SERR);
2052 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
2053 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_IFS);
2054 is &= ~AHCI_PREG_IS_IFS;
2055 ahci_port_stop(ap, 0);
2056 ahci_port_start(ap);
2057 need = NEED_RESTART;
258223a3 2058 }
1980eff3 2059#endif
258223a3
MD
2060
2061 /*
2062 * Port change (hot-plug).
2063 *
2064 * A PCS interrupt will occur on hot-plug once communication is
2065 * established.
2066 *
2067 * A PRCS interrupt will occur on hot-unplug (and possibly also
2068 * on hot-plug).
2069 *
22181ab7
MD
2070 * XXX We can then check the CPS (Cold Presence State) bit, if
2071 * supported, to determine if a device is plugged in or not and do
2072 * the right thing.
2073 *
2074 * WARNING: A PCS interrupt is cleared by clearing DIAG_X, and
2075 * can also occur if an unsolicited COMINIT is received.
2076 * If this occurs command processing is automatically
2077 * stopped (CR goes inactive) and the port must be stopped
2078 * and restarted.
258223a3
MD
2079 */
2080 if (is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)) {
2081 ahci_pwrite(ap, AHCI_PREG_SERR,
1980eff3 2082 (AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_X));
22181ab7 2083 ahci_port_stop(ap, 0);
258223a3
MD
2084 switch (ahci_pread(ap, AHCI_PREG_SSTS) & AHCI_PREG_SSTS_DET) {
2085 case AHCI_PREG_SSTS_DET_DEV:
1980eff3 2086 if (ap->ap_type == ATA_PORT_T_NONE) {
22181ab7
MD
2087 need = NEED_HOTPLUG_INSERT;
2088 goto fatal;
258223a3 2089 }
22181ab7 2090 need = NEED_RESTART;
258223a3
MD
2091 break;
2092 default:
1980eff3 2093 if (ap->ap_type != ATA_PORT_T_NONE) {
22181ab7
MD
2094 need = NEED_HOTPLUG_REMOVE;
2095 goto fatal;
258223a3 2096 }
22181ab7 2097 need = NEED_RESTART;
258223a3
MD
2098 break;
2099 }
2100 }
2101
22181ab7
MD
2102 /*
2103 * Check for remaining errors - they are fatal.
2104 */
258223a3
MD
2105 if (is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | AHCI_PREG_IS_IFS |
2106 AHCI_PREG_IS_OFS | AHCI_PREG_IS_UFS)) {
4444122d 2107 u_int32_t serr = ahci_pread(ap, AHCI_PREG_SERR);
1980eff3 2108 kprintf("%s: unrecoverable errors (IS: %b, SERR: %b), "
4444122d
MD
2109 "disabling port.\n",
2110 PORTNAME(ap),
2111 is, AHCI_PFMT_IS,
1980eff3 2112 serr, AHCI_PFMT_SERR
4444122d 2113 );
258223a3
MD
2114 /* XXX try recovery first */
2115 goto fatal;
2116 }
2117
22181ab7
MD
2118 /*
2119 * Fail all outstanding commands if we know the port won't recover.
1980eff3
MD
2120 *
2121 * We may have a ccb_at if the failed command is known and was
2122 * being sent to a device over a port multiplier (PM). In this
2123 * case if the port itself has not completely failed we fail just
2124 * the commands related to that target.
22181ab7 2125 */
258223a3
MD
2126 if (ap->ap_state == AP_S_FATAL_ERROR) {
2127fatal:
2128 ap->ap_state = AP_S_FATAL_ERROR;
2129failall:
2130
cf5f3a81
MD
2131 /* Stopping the port clears CI/SACT */
2132 ahci_port_stop(ap, 0);
258223a3 2133
1980eff3
MD
2134 /*
2135 * Error all the active slots. If running across a PM
2136 * try to error out just the slots related to the target.
2137 */
258223a3
MD
2138 ci_masked = ci_saved & *active;
2139 while (ci_masked) {
2140 slot = ffs(ci_masked) - 1;
2141 ccb = &ap->ap_ccbs[slot];
1980eff3
MD
2142 if (ccb_at == ccb->ccb_xa.at ||
2143 ap->ap_state == AP_S_FATAL_ERROR) {
2144 ci_masked &= ~(1 << slot);
2145 ccb->ccb_xa.state = ATA_S_ERROR;
2146 }
258223a3
MD
2147 }
2148
2149 /* Run completion for all active slots. */
2150 ci_saved &= ~*active;
2151
2152 /*
2153 * Don't restart the port if our problems were deemed fatal.
2154 *
2155 * Also acknowlege all fatal interrupt sources to prevent
2156 * a livelock.
2157 */
2158 if (ap->ap_state == AP_S_FATAL_ERROR) {
22181ab7
MD
2159 if (need == NEED_RESTART)
2160 need = NEED_NOTHING;
258223a3
MD
2161 ahci_pwrite(ap, AHCI_PREG_IS,
2162 AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2163 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2164 AHCI_PREG_IS_UFS);
2165 }
2166 }
2167
2168 /*
2169 * CCB completion is detected by noticing its slot's bit in CI has
2170 * changed to zero some time after we activated it.
2171 * If we are polling, we may only be interested in particular slot(s).
cf5f3a81
MD
2172 *
2173 * Any active bits not saved are completed within the restrictions
2174 * imposed by the caller.
258223a3
MD
2175 */
2176 ci_masked = ~ci_saved & *active & ci_mask;
2177 while (ci_masked) {
2178 slot = ffs(ci_masked) - 1;
2179 ccb = &ap->ap_ccbs[slot];
2180 ci_masked &= ~(1 << slot);
2181
2182 DPRINTF(AHCI_D_INTR, "%s: slot %d is complete%s\n",
2183 PORTNAME(ap), slot, ccb->ccb_xa.state == ATA_S_ERROR ?
2184 " (error)" : "");
2185
2186 bus_dmamap_sync(sc->sc_tag_cmdh,
2187 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list),
2188 BUS_DMASYNC_POSTWRITE);
2189
2190 bus_dmamap_sync(sc->sc_tag_cmdt,
2191 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table),
2192 BUS_DMASYNC_POSTWRITE);
2193
2194 bus_dmamap_sync(sc->sc_tag_rfis,
2195 AHCI_DMA_MAP(ap->ap_dmamem_rfis),
2196 BUS_DMASYNC_POSTREAD);
2197
2198 *active &= ~(1 << ccb->ccb_slot);
1980eff3
MD
2199 if (active == &ap->ap_active) {
2200 KKASSERT(ap->ap_active_cnt > 0);
2201 --ap->ap_active_cnt;
2202 }
258223a3
MD
2203 ccb->ccb_done(ccb);
2204
2205 processed |= 1 << ccb->ccb_slot;
2206 }
2207
22181ab7
MD
2208 switch(need) {
2209 case NEED_RESTART:
2210 /*
2211 * A recoverable error occured and we can restart outstanding
2212 * commands on the port.
2213 */
17eab71e 2214 ahci_port_start(ap);
258223a3 2215
258223a3
MD
2216 if (ci_saved) {
2217#ifdef DIAGNOSTIC
2218 tmp = ci_saved;
2219 while (tmp) {
2220 slot = ffs(tmp) - 1;
2221 tmp &= ~(1 << slot);
2222 ccb = &ap->ap_ccbs[slot];
2223 KKASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP);
2224 KKASSERT((!!(ccb->ccb_xa.flags & ATA_F_NCQ)) ==
2225 (!!ap->ap_sactive));
2226 }
2227#endif
2228 DPRINTF(AHCI_D_VERBOSE, "%s: ahci_port_intr "
2229 "re-enabling%s slots %08x\n", PORTNAME(ap),
2230 ap->ap_sactive ? " NCQ" : "", ci_saved);
2231
2232 if (ap->ap_sactive)
2233 ahci_pwrite(ap, AHCI_PREG_SACT, ci_saved);
2234 ahci_pwrite(ap, AHCI_PREG_CI, ci_saved);
2235 }
22181ab7
MD
2236 break;
2237 case NEED_HOTPLUG_INSERT:
2238 /*
cf5f3a81
MD
2239 * A hot-plug insertion event has occured and all
2240 * outstanding commands have already been revoked.
1980eff3
MD
2241 *
2242 * Don't recurse if this occurs while we are
2243 * resetting the port.
22181ab7 2244 */
1980eff3
MD
2245 if ((ap->ap_flags & AP_F_IN_RESET) == 0) {
2246 kprintf("%s: HOTPLUG - Device inserted\n",
2247 PORTNAME(ap));
2248 if (ahci_port_init(ap, NULL) == 0)
2249 ahci_cam_changed(ap, 1);
2250 }
22181ab7
MD
2251 break;
2252 case NEED_HOTPLUG_REMOVE:
cf5f3a81
MD
2253 /*
2254 * A hot-plug removal event has occured and all
2255 * outstanding commands have already been revoked.
1980eff3
MD
2256 *
2257 * Don't recurse if this occurs while we are
2258 * resetting the port.
cf5f3a81 2259 */
1980eff3
MD
2260 if ((ap->ap_flags & AP_F_IN_RESET) == 0) {
2261 kprintf("%s: HOTPLUG - Device removed\n",
2262 PORTNAME(ap));
2263 ahci_port_hardstop(ap);
2264 ahci_cam_changed(ap, 0);
2265 }
22181ab7
MD
2266 break;
2267 default:
2268 break;
258223a3 2269 }
258223a3
MD
2270 return (processed);
2271}
2272
2273struct ahci_ccb *
2274ahci_get_ccb(struct ahci_port *ap)
2275{
2276 struct ahci_ccb *ccb;
2277
2278 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE);
2279 ccb = TAILQ_FIRST(&ap->ap_ccb_free);
2280 if (ccb != NULL) {
2281 KKASSERT(ccb->ccb_xa.state == ATA_S_PUT);
2282 TAILQ_REMOVE(&ap->ap_ccb_free, ccb, ccb_entry);
2283 ccb->ccb_xa.state = ATA_S_SETUP;
1980eff3 2284 ccb->ccb_xa.at = NULL;
258223a3
MD
2285 }
2286 lockmgr(&ap->ap_ccb_lock, LK_RELEASE);
2287
2288 return (ccb);
2289}
2290
2291void
2292ahci_put_ccb(struct ahci_ccb *ccb)
2293{
2294 struct ahci_port *ap = ccb->ccb_port;
2295
2296#ifdef DIAGNOSTIC
2297 if (ccb->ccb_xa.state != ATA_S_COMPLETE &&
2298 ccb->ccb_xa.state != ATA_S_TIMEOUT &&
2299 ccb->ccb_xa.state != ATA_S_ERROR) {
2300 kprintf("%s: invalid ata_xfer state %02x in ahci_put_ccb, "
2301 "slot %d\n",
2302 PORTNAME(ccb->ccb_port), ccb->ccb_xa.state,
2303 ccb->ccb_slot);
2304 }
2305#endif
2306
2307 ccb->ccb_xa.state = ATA_S_PUT;
2308 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE);
2309 TAILQ_INSERT_TAIL(&ap->ap_ccb_free, ccb, ccb_entry);
2310 lockmgr(&ap->ap_ccb_lock, LK_RELEASE);
2311}
2312
2313struct ahci_ccb *
2314ahci_get_err_ccb(struct ahci_port *ap)
2315{
2316 struct ahci_ccb *err_ccb;
2317 u_int32_t sact;
2318
2319 /* No commands may be active on the chip. */
2320 sact = ahci_pread(ap, AHCI_PREG_SACT);
2321 if (sact != 0)
2322 kprintf("ahci_get_err_ccb but SACT %08x != 0?\n", sact);
2323 KKASSERT(ahci_pread(ap, AHCI_PREG_CI) == 0);
2324
2325#ifdef DIAGNOSTIC
2326 KKASSERT(ap->ap_err_busy == 0);
2327 ap->ap_err_busy = 1;
2328#endif
2329 /* Save outstanding command state. */
2330 ap->ap_err_saved_active = ap->ap_active;
2331 ap->ap_err_saved_active_cnt = ap->ap_active_cnt;
2332 ap->ap_err_saved_sactive = ap->ap_sactive;
2333
2334 /*
2335 * Pretend we have no commands outstanding, so that completions won't
2336 * run prematurely.
2337 */
2338 ap->ap_active = ap->ap_active_cnt = ap->ap_sactive = 0;
2339
2340 /*
2341 * Grab a CCB to use for error recovery. This should never fail, as
2342 * we ask atascsi to reserve one for us at init time.
2343 */
2344 err_ccb = ahci_get_ccb(ap);
2345 KKASSERT(err_ccb != NULL);
2346 err_ccb->ccb_xa.flags = 0;
2347 err_ccb->ccb_done = ahci_empty_done;
2348
2349 return err_ccb;
2350}
2351
2352void
2353ahci_put_err_ccb(struct ahci_ccb *ccb)
2354{
2355 struct ahci_port *ap = ccb->ccb_port;
2356 u_int32_t sact;
5f8c1efd 2357 u_int32_t ci;
258223a3
MD
2358
2359#ifdef DIAGNOSTIC
2360 KKASSERT(ap->ap_err_busy);
2361#endif
5f8c1efd
MD
2362 /*
2363 * No commands may be active on the chip
2364 */
258223a3 2365 sact = ahci_pread(ap, AHCI_PREG_SACT);
5f8c1efd
MD
2366 if (sact) {
2367 panic("ahci_port_err_ccb(%d) but SACT %08x != 0\n",
2368 ccb->ccb_slot, sact);
2369 }
2370 ci = ahci_pread(ap, AHCI_PREG_CI);
2371 if (ci) {
cf5f3a81
MD
2372 panic("ahci_put_err_ccb(%d) but CI %08x != 0 "
2373 "(act=%08x sact=%08x)\n",
2374 ccb->ccb_slot, ci,
2375 ap->ap_active, ap->ap_sactive);
258223a3 2376 }
258223a3
MD
2377
2378 /* Done with the CCB */
2379 ahci_put_ccb(ccb);
2380
2381 /* Restore outstanding command state */
2382 ap->ap_sactive = ap->ap_err_saved_sactive;
2383 ap->ap_active_cnt = ap->ap_err_saved_active_cnt;
2384 ap->ap_active = ap->ap_err_saved_active;
2385
2386#ifdef DIAGNOSTIC
2387 ap->ap_err_busy = 0;
2388#endif
2389}
2390
1980eff3
MD
2391/*
2392 * Read log page to get NCQ error.
2393 *
2394 * NOTE: NCQ not currently supported on port multipliers. XXX
2395 */
258223a3
MD
2396int
2397ahci_port_read_ncq_error(struct ahci_port *ap, int *err_slotp)
2398{
2399 struct ahci_ccb *ccb;
2400 struct ahci_cmd_hdr *cmd_slot;
2401 u_int32_t cmd;
2402 struct ata_fis_h2d *fis;
2403 int rc = EIO;
2404
2405 DPRINTF(AHCI_D_VERBOSE, "%s: read log page\n", PORTNAME(ap));
2406
2407 /* Save command register state. */
2408 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
2409
2410 /* Port should have been idled already. Start it. */
2411 KKASSERT((cmd & AHCI_PREG_CMD_CR) == 0);
17eab71e 2412 ahci_port_start(ap);
258223a3
MD
2413
2414 /* Prep error CCB for READ LOG EXT, page 10h, 1 sector. */
2415 ccb = ahci_get_err_ccb(ap);
2416 ccb->ccb_xa.flags = ATA_F_NOWAIT | ATA_F_READ | ATA_F_POLL;
2417 ccb->ccb_xa.data = ap->ap_err_scratch;
2418 ccb->ccb_xa.datalen = 512;
2419 cmd_slot = ccb->ccb_cmd_hdr;
2420 bzero(ccb->ccb_cmd_table, sizeof(struct ahci_cmd_table));
2421
2422 fis = (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis;
2423 fis->type = ATA_FIS_TYPE_H2D;
2424 fis->flags = ATA_H2D_FLAGS_CMD;
2425 fis->command = ATA_C_READ_LOG_EXT;
2426 fis->lba_low = 0x10; /* queued error log page (10h) */
2427 fis->sector_count = 1; /* number of sectors (1) */
2428 fis->sector_count_exp = 0;
2429 fis->lba_mid = 0; /* starting offset */
2430 fis->lba_mid_exp = 0;
2431 fis->device = 0;
2432
2433 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
2434
2435 if (ahci_load_prdt(ccb) != 0) {
2436 rc = ENOMEM; /* XXX caller must abort all commands */
2437 goto err;
2438 }
2439
2440 ccb->ccb_xa.state = ATA_S_PENDING;
2441 if (ahci_poll(ccb, hz, NULL) != 0)
2442 goto err;
2443
2444 rc = 0;
2445err:
2446 /* Abort our command, if it failed, by stopping command DMA. */
1980eff3 2447 if (rc && (ap->ap_active & (1 << ccb->ccb_slot))) {
258223a3
MD
2448 kprintf("%s: log page read failed, slot %d was still active.\n",
2449 PORTNAME(ap), ccb->ccb_slot);
2450 ahci_port_stop(ap, 0);
2451 }
2452
2453 /* Done with the error CCB now. */
2454 ahci_unload_prdt(ccb);
2455 ahci_put_err_ccb(ccb);
2456
2457 /* Extract failed register set and tags from the scratch space. */
2458 if (rc == 0) {
2459 struct ata_log_page_10h *log;
2460 int err_slot;
2461
2462 log = (struct ata_log_page_10h *)ap->ap_err_scratch;
2463 if (log->err_regs.type & ATA_LOG_10H_TYPE_NOTQUEUED) {
2464 /* Not queued bit was set - wasn't an NCQ error? */
2465 kprintf("%s: read NCQ error page, but not an NCQ "
2466 "error?\n",
2467 PORTNAME(ap));
2468 rc = ESRCH;
2469 } else {
2470 /* Copy back the log record as a D2H register FIS. */
2471 *err_slotp = err_slot = log->err_regs.type &
2472 ATA_LOG_10H_TYPE_TAG_MASK;
2473
2474 ccb = &ap->ap_ccbs[err_slot];
2475 memcpy(&ccb->ccb_xa.rfis, &log->err_regs,
2476 sizeof(struct ata_fis_d2h));
2477 ccb->ccb_xa.rfis.type = ATA_FIS_TYPE_D2H;
2478 ccb->ccb_xa.rfis.flags = 0;
2479 }
2480 }
2481
2482 /* Restore saved CMD register state */
2483 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
2484
2485 return (rc);
2486}
2487
2488/*
2489 * Allocate memory for various structures DMAd by hardware. The maximum
2490 * number of segments for these tags is 1 so the DMA memory will have a
2491 * single physical base address.
2492 */
2493struct ahci_dmamem *
2494ahci_dmamem_alloc(struct ahci_softc *sc, bus_dma_tag_t tag)
2495{
2496 struct ahci_dmamem *adm;
2497 int error;
2498
2499 adm = kmalloc(sizeof(*adm), M_DEVBUF, M_INTWAIT | M_ZERO);
2500
2501 error = bus_dmamem_alloc(tag, (void **)&adm->adm_kva,
2502 BUS_DMA_ZERO, &adm->adm_map);
2503 if (error == 0) {
2504 adm->adm_tag = tag;
2505 error = bus_dmamap_load(tag, adm->adm_map,
2506 adm->adm_kva,
2507 bus_dma_tag_getmaxsize(tag),
2508 ahci_dmamem_saveseg, &adm->adm_busaddr,
2509 0);
2510 }
2511 if (error) {
2512 if (adm->adm_map) {
2513 bus_dmamap_destroy(tag, adm->adm_map);
2514 adm->adm_map = NULL;
2515 adm->adm_tag = NULL;
2516 adm->adm_kva = NULL;
2517 }
2518 kfree(adm, M_DEVBUF);
2519 adm = NULL;
2520 }
2521 return (adm);
2522}
2523
2524static
2525void
2526ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error)
2527{
2528 KKASSERT(error == 0);
2529 KKASSERT(nsegs == 1);
2530 *(bus_addr_t *)info = segs->ds_addr;
2531}
2532
2533
2534void
2535ahci_dmamem_free(struct ahci_softc *sc, struct ahci_dmamem *adm)
2536{
2537 if (adm->adm_map) {
2538 bus_dmamap_unload(adm->adm_tag, adm->adm_map);
2539 bus_dmamap_destroy(adm->adm_tag, adm->adm_map);
2540 adm->adm_map = NULL;
2541 adm->adm_tag = NULL;
2542 adm->adm_kva = NULL;
2543 }
2544 kfree(adm, M_DEVBUF);
2545}
2546
2547u_int32_t
2548ahci_read(struct ahci_softc *sc, bus_size_t r)
2549{
2550 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4,
2551 BUS_SPACE_BARRIER_READ);
2552 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r));
2553}
2554
2555void
2556ahci_write(struct ahci_softc *sc, bus_size_t r, u_int32_t v)
2557{
2558 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v);
2559 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4,
2560 BUS_SPACE_BARRIER_WRITE);
2561}
2562
2563int
2564ahci_wait_ne(struct ahci_softc *sc, bus_size_t r, u_int32_t mask,
2565 u_int32_t target)
2566{
2567 int i;
2568
2569 for (i = 0; i < 1000; i++) {
2570 if ((ahci_read(sc, r) & mask) != target)
2571 return (0);
2572 DELAY(1000);
2573 }
2574
2575 return (1);
2576}
2577
2578u_int32_t
2579ahci_pread(struct ahci_port *ap, bus_size_t r)
2580{
2581 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4,
2582 BUS_SPACE_BARRIER_READ);
2583 return (bus_space_read_4(ap->ap_sc->sc_iot, ap->ap_ioh, r));
2584}
2585
2586void
2587ahci_pwrite(struct ahci_port *ap, bus_size_t r, u_int32_t v)
2588{
2589 bus_space_write_4(ap->ap_sc->sc_iot, ap->ap_ioh, r, v);
2590 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4,
2591 BUS_SPACE_BARRIER_WRITE);
2592}
2593
2594int
cec85a37
MD
2595ahci_pwait_eq(struct ahci_port *ap, int timeout,
2596 bus_size_t r, u_int32_t mask, u_int32_t target)
258223a3
MD
2597{
2598 int i;
2599
cec85a37 2600 for (i = 0; i < timeout; i++) {
258223a3
MD
2601 if ((ahci_pread(ap, r) & mask) == target)
2602 return (0);
2603 DELAY(1000);
2604 }
2605
2606 return (1);
2607}
2608
1980eff3
MD
2609/*
2610 * Acquire an ata transfer.
2611 *
2612 * Pass a NULL at for direct-attached transfers, and a non-NULL at for
2613 * targets that go through the port multiplier.
2614 */
258223a3 2615struct ata_xfer *
1980eff3 2616ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at)
258223a3 2617{
258223a3
MD
2618 struct ahci_ccb *ccb;
2619
2620 ccb = ahci_get_ccb(ap);
2621 if (ccb == NULL) {
2622 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer: NULL ccb\n",
2623 PORTNAME(ap));
2624 return (NULL);
2625 }
2626
2627 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer got slot %d\n",
2628 PORTNAME(ap), ccb->ccb_slot);
2629
1980eff3 2630 ccb->ccb_xa.at = at;
258223a3
MD
2631 ccb->ccb_xa.fis->type = ATA_FIS_TYPE_H2D;
2632
2633 return (&ccb->ccb_xa);
2634}
2635
2636void
2637ahci_ata_put_xfer(struct ata_xfer *xa)
2638{
2639 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
2640
2641 DPRINTF(AHCI_D_XFER, "ahci_ata_put_xfer slot %d\n", ccb->ccb_slot);
2642
2643 ahci_put_ccb(ccb);
2644}
2645
2646int
2647ahci_ata_cmd(struct ata_xfer *xa)
2648{
2649 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
2650 struct ahci_cmd_hdr *cmd_slot;
2651
2652 KKASSERT(xa->state == ATA_S_SETUP);
2653
2654 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR)
2655 goto failcmd;
1980eff3
MD
2656#if 0
2657 kprintf("%s: started std command %b ccb %d ccb_at %p %d\n",
2658 ATANAME(ccb->ccb_port, ccb->ccb_xa.at),
2659 ahci_pread(ccb->ccb_port, AHCI_PREG_CMD), AHCI_PFMT_CMD,
2660 ccb->ccb_slot,
2661 ccb->ccb_xa.at,
2662 ccb->ccb_xa.at ? ccb->ccb_xa.at->at_target : -1);
2663#endif
258223a3
MD
2664
2665 ccb->ccb_done = ahci_ata_cmd_done;
2666
2667 cmd_slot = ccb->ccb_cmd_hdr;
2668 cmd_slot->flags = htole16(5); /* FIS length (in DWORDs) */
1980eff3
MD
2669 if (ccb->ccb_xa.at) {
2670 cmd_slot->flags |= htole16(ccb->ccb_xa.at->at_target <<
2671 AHCI_CMD_LIST_FLAG_PMP_SHIFT);
2672 }
258223a3
MD
2673
2674 if (xa->flags & ATA_F_WRITE)
2675 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_W);
2676
2677 if (xa->flags & ATA_F_PACKET)
2678 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_A);
2679
2680 if (ahci_load_prdt(ccb) != 0)
2681 goto failcmd;
2682
2683 xa->state = ATA_S_PENDING;
2684
2685 if (xa->flags & ATA_F_POLL) {
2686 ahci_poll(ccb, xa->timeout, ahci_ata_cmd_timeout);
2687 return (ATA_COMPLETE);
2688 }
2689
2690 crit_enter();
2691 xa->flags |= ATA_F_TIMEOUT_RUNNING;
2692 callout_reset(&ccb->ccb_timeout, xa->timeout,
2693 ahci_ata_cmd_timeout_unserialized, ccb);
2694 ahci_start(ccb);
2695 crit_exit();
2696 return (ATA_QUEUED);
2697
2698failcmd:
2699 crit_enter();
2700 xa->state = ATA_S_ERROR;
2701 xa->complete(xa);
2702 crit_exit();
2703 return (ATA_ERROR);
2704}
2705
2706void
2707ahci_ata_cmd_done(struct ahci_ccb *ccb)
2708{
2709 struct ata_xfer *xa = &ccb->ccb_xa;
2710
2711 if (xa->flags & ATA_F_TIMEOUT_RUNNING) {
2712 xa->flags &= ~ATA_F_TIMEOUT_RUNNING;
2713 callout_stop(&ccb->ccb_timeout);
2714 }
2715
2716 if (xa->state == ATA_S_ONCHIP || xa->state == ATA_S_ERROR)
2717 ahci_issue_pending_commands(ccb->ccb_port,
2718 xa->flags & ATA_F_NCQ);
2719
2720 ahci_unload_prdt(ccb);
2721
2722 if (xa->state == ATA_S_ONCHIP)
2723 xa->state = ATA_S_COMPLETE;
2724#ifdef DIAGNOSTIC
2725 else if (xa->state != ATA_S_ERROR && xa->state != ATA_S_TIMEOUT)
2726 kprintf("%s: invalid ata_xfer state %02x in ahci_ata_cmd_done, "
2727 "slot %d\n",
2728 PORTNAME(ccb->ccb_port), xa->state, ccb->ccb_slot);
2729#endif
2730 if (xa->state != ATA_S_TIMEOUT)
2731 xa->complete(xa);
2732}
2733
2734static void
2735ahci_ata_cmd_timeout_unserialized(void *arg)
2736{
2737 struct ahci_ccb *ccb = arg;
2738 struct ahci_port *ap = ccb->ccb_port;
2739
2740 lwkt_serialize_enter(&ap->ap_sc->sc_serializer);
2741 ahci_ata_cmd_timeout(arg);
2742 lwkt_serialize_exit(&ap->ap_sc->sc_serializer);
2743}
2744
1980eff3 2745void
258223a3
MD
2746ahci_ata_cmd_timeout(void *arg)
2747{
2748 struct ahci_ccb *ccb = arg;
2749 struct ata_xfer *xa = &ccb->ccb_xa;
2750 struct ahci_port *ap = ccb->ccb_port;
2751 volatile u_int32_t *active;
2752 int ccb_was_started, ncq_cmd;
2753
2754 crit_enter();
cf5f3a81
MD
2755 kprintf("%s: CMD TIMEOUT cmd-reg 0x%b\n"
2756 "\tsactive=%08x active=%08x\n"
2757 "\t sact=%08x ci=%08x\n",
1980eff3 2758 ATANAME(ap, ccb->ccb_xa.at),
258223a3 2759 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD,
cf5f3a81 2760 ap->ap_sactive, ap->ap_active,
258223a3
MD
2761 ahci_pread(ap, AHCI_PREG_SACT),
2762 ahci_pread(ap, AHCI_PREG_CI));
2763
9e145b23
MD
2764 /*
2765 * NOTE: Timeout will not be running if the command was polled.
2766 */
2767 KKASSERT(xa->flags & (ATA_F_POLL|ATA_F_TIMEOUT_RUNNING));
258223a3
MD
2768 xa->flags &= ~ATA_F_TIMEOUT_RUNNING;
2769 ncq_cmd = (xa->flags & ATA_F_NCQ);
2770 active = ncq_cmd ? &ap->ap_sactive : &ap->ap_active;
2771
2772 if (ccb->ccb_xa.state == ATA_S_PENDING) {
2773 DPRINTF(AHCI_D_TIMEOUT, "%s: command for slot %d timed out "
2774 "before it got on chip\n", PORTNAME(ap), ccb->ccb_slot);
2775 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
2776 ccb_was_started = 0;
cf5f3a81
MD
2777 } else if (ccb->ccb_xa.state == ATA_S_ONCHIP &&
2778 ahci_port_intr(ap, 1 << ccb->ccb_slot)) {
258223a3
MD
2779 DPRINTF(AHCI_D_TIMEOUT, "%s: final poll of port completed "
2780 "command in slot %d\n", PORTNAME(ap), ccb->ccb_slot);
2781 goto ret;
2782 } else if (ccb->ccb_xa.state != ATA_S_ONCHIP) {
2783 DPRINTF(AHCI_D_TIMEOUT, "%s: command slot %d already "
2784 "handled%s\n", PORTNAME(ap), ccb->ccb_slot,
2785 (*active & (1 << ccb->ccb_slot)) ?
2786 " but slot is still active?" : ".");
2787 goto ret;
2788 } else if ((ahci_pread(ap, ncq_cmd ? AHCI_PREG_SACT : AHCI_PREG_CI) &
2789 (1 << ccb->ccb_slot)) == 0 &&
2790 (*active & (1 << ccb->ccb_slot))) {
2791 DPRINTF(AHCI_D_TIMEOUT, "%s: command slot %d completed but "
2792 "IRQ handler didn't detect it. Why?\n", PORTNAME(ap),
2793 ccb->ccb_slot);
2794 *active &= ~(1 << ccb->ccb_slot);
1980eff3
MD
2795 if (ncq_cmd == 0) {
2796 KKASSERT(ap->ap_active_cnt > 0);
2797 --ap->ap_active_cnt;
2798 }
258223a3
MD
2799 ccb->ccb_done(ccb);
2800 goto ret;
2801 } else {
258223a3
MD
2802 ccb_was_started = 1;
2803 }
2804
2805 /* Complete the slot with a timeout error. */
2806 ccb->ccb_xa.state = ATA_S_TIMEOUT;
2807 *active &= ~(1 << ccb->ccb_slot);
1980eff3
MD
2808 if (ncq_cmd == 0) {
2809 KKASSERT(ap->ap_active_cnt > 0);
2810 --ap->ap_active_cnt;
2811 }
258223a3
MD
2812 DPRINTF(AHCI_D_TIMEOUT, "%s: run completion (1)\n", PORTNAME(ap));
2813 ccb->ccb_done(ccb); /* This won't issue pending commands or run the
2814 atascsi completion. */
2815
2816 /* Reset port to abort running command. */
2817 if (ccb_was_started) {
2818 DPRINTF(AHCI_D_TIMEOUT, "%s: resetting port to abort%s command "
2819 "in slot %d, active %08x\n", PORTNAME(ap), ncq_cmd ? " NCQ"
2820 : "", ccb->ccb_slot, *active);
1980eff3
MD
2821 /* XXX */
2822 if (ccb->ccb_xa.at) {
2823 /* XXX how do we unbrick a PM target? */
2824 kprintf("%s: Unable to reset PM target during timeout"
2825 ", port bricked on us\n",
2826 PORTNAME(ap));
2827 ap->ap_state = AP_S_FATAL_ERROR;
2828 ahci_port_intr(ap, AHCI_PREG_CI_ALL_SLOTS);
2829 } else if (ahci_port_reset(ap, ccb->ccb_xa.at, 0)) {
cf5f3a81
MD
2830 /*
2831 * If the softreset failed place the port in a
2832 * failed state and use ahci_port_intr() to cancel
2833 * any remaining commands.
2834 */
17eab71e
MD
2835 kprintf("%s: Unable to reset during timeout, port "
2836 "bricked on us\n",
258223a3
MD
2837 PORTNAME(ap));
2838 ap->ap_state = AP_S_FATAL_ERROR;
cf5f3a81
MD
2839 ahci_port_intr(ap, AHCI_PREG_CI_ALL_SLOTS);
2840 } else {
2841 /*
2842 * Restart any other commands that were aborted
2843 * by the reset.
2844 */
2845 if (*active) {
2846 DPRINTF(AHCI_D_TIMEOUT, "%s: re-enabling%s slots "
2847 "%08x\n", PORTNAME(ap), ncq_cmd ? " NCQ" : "",
2848 *active);
2849 if (ncq_cmd)
2850 ahci_pwrite(ap, AHCI_PREG_SACT, *active);
2851 ahci_pwrite(ap, AHCI_PREG_CI, *active);
2852 }
258223a3
MD
2853 }
2854 }
2855
2856 /* Issue any pending commands now. */
2857 DPRINTF(AHCI_D_TIMEOUT, "%s: issue pending\n", PORTNAME(ap));
2858 if (ccb_was_started)
2859 ahci_issue_pending_commands(ap, ncq_cmd);
2860 else if (ap->ap_active == 0)
2861 ahci_issue_pending_ncq_commands(ap);
2862
2863 /* Complete the timed out ata_xfer I/O (may generate new I/O). */
2864 DPRINTF(AHCI_D_TIMEOUT, "%s: run completion (2)\n", PORTNAME(ap));
2865 xa->complete(xa);
2866
2867 DPRINTF(AHCI_D_TIMEOUT, "%s: splx\n", PORTNAME(ap));
2868ret:
2869 crit_exit();
2870}
2871
2872void
2873ahci_empty_done(struct ahci_ccb *ccb)
2874{
2875 ccb->ccb_xa.state = ATA_S_COMPLETE;
2876}