Remove unnecessary initialisations. Return ENXIO instead of 1 in
[dragonfly.git] / sys / dev / netif / an / if_an.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/dev/an/if_an.c,v 1.2.2.13 2003/02/11 03:32:48 ambrisko Exp $
902f6373 33 * $DragonFly: src/sys/dev/netif/an/if_an.c,v 1.28 2005/07/28 16:33:25 joerg Exp $
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34 */
35
36/*
37 * Aironet 4500/4800 802.11 PCMCIA/ISA/PCI driver for FreeBSD.
38 *
39 * Written by Bill Paul <wpaul@ctr.columbia.edu>
40 * Electrical Engineering Department
41 * Columbia University, New York City
42 */
43
44/*
45 * The Aironet 4500/4800 series cards come in PCMCIA, ISA and PCI form.
46 * This driver supports all three device types (PCI devices are supported
47 * through an extra PCI shim: /sys/dev/an/if_an_pci.c). ISA devices can be
48 * supported either using hard-coded IO port/IRQ settings or via Plug
49 * and Play. The 4500 series devices support 1Mbps and 2Mbps data rates.
50 * The 4800 devices support 1, 2, 5.5 and 11Mbps rates.
51 *
52 * Like the WaveLAN/IEEE cards, the Aironet NICs are all essentially
53 * PCMCIA devices. The ISA and PCI cards are a combination of a PCMCIA
54 * device and a PCMCIA to ISA or PCMCIA to PCI adapter card. There are
55 * a couple of important differences though:
56 *
57 * - Lucent ISA card looks to the host like a PCMCIA controller with
58 * a PCMCIA WaveLAN card inserted. This means that even desktop
59 * machines need to be configured with PCMCIA support in order to
60 * use WaveLAN/IEEE ISA cards. The Aironet cards on the other hand
61 * actually look like normal ISA and PCI devices to the host, so
62 * no PCMCIA controller support is needed
63 *
64 * The latter point results in a small gotcha. The Aironet PCMCIA
65 * cards can be configured for one of two operating modes depending
66 * on how the Vpp1 and Vpp2 programming voltages are set when the
67 * card is activated. In order to put the card in proper PCMCIA
68 * operation (where the CIS table is visible and the interface is
69 * programmed for PCMCIA operation), both Vpp1 and Vpp2 have to be
70 * set to 5 volts. FreeBSD by default doesn't set the Vpp voltages,
71 * which leaves the card in ISA/PCI mode, which prevents it from
72 * being activated as an PCMCIA device.
73 *
74 * Note that some PCMCIA controller software packages for Windows NT
75 * fail to set the voltages as well.
76 *
77 * The Aironet devices can operate in both station mode and access point
78 * mode. Typically, when programmed for station mode, the card can be set
79 * to automatically perform encapsulation/decapsulation of Ethernet II
80 * and 802.3 frames within 802.11 frames so that the host doesn't have
81 * to do it itself. This driver doesn't program the card that way: the
82 * driver handles all of the encapsulation/decapsulation itself.
83 */
84
85#include "opt_inet.h"
86
87#ifdef INET
88#define ANCACHE /* enable signal strength cache */
89#endif
90
91#include <sys/param.h>
92#include <sys/systm.h>
93#include <sys/sockio.h>
94#include <sys/mbuf.h>
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95#include <sys/kernel.h>
96#include <sys/proc.h>
97#include <sys/ucred.h>
98#include <sys/socket.h>
99#ifdef ANCACHE
100#include <sys/syslog.h>
101#endif
102#include <sys/sysctl.h>
41d6c56f 103#include <sys/thread2.h>
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104
105#include <sys/module.h>
106#include <sys/sysctl.h>
107#include <sys/bus.h>
108#include <machine/bus.h>
109#include <sys/rman.h>
110#include <machine/resource.h>
111#include <sys/malloc.h>
112
113#include <net/if.h>
38de8487 114#include <net/ifq_var.h>
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115#include <net/if_arp.h>
116#include <net/ethernet.h>
117#include <net/if_dl.h>
118#include <net/if_types.h>
984263bc 119#include <net/if_media.h>
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120#include <netproto/802_11/ieee80211.h>
121#include <netproto/802_11/ieee80211_ioctl.h>
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122
123#ifdef INET
124#include <netinet/in.h>
125#include <netinet/in_systm.h>
126#include <netinet/in_var.h>
127#include <netinet/ip.h>
128#endif
129
130#include <net/bpf.h>
131
132#include <machine/md_var.h>
133
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134#include "if_aironet_ieee.h"
135#include "if_anreg.h"
984263bc 136
984263bc 137/* These are global because we need them in sys/pci/if_an_p.c. */
b5101a88 138static void an_reset (struct an_softc *);
1c70eebf 139static int an_init_mpi350_desc (struct an_softc *);
bd4539cc
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140static int an_ioctl (struct ifnet *, u_long, caddr_t,
141 struct ucred *);
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142static void an_init (void *);
143static int an_init_tx_ring (struct an_softc *);
144static void an_start (struct ifnet *);
145static void an_watchdog (struct ifnet *);
146static void an_rxeof (struct an_softc *);
147static void an_txeof (struct an_softc *, int);
148
149static void an_promisc (struct an_softc *, int);
150static int an_cmd (struct an_softc *, int, int);
151static int an_cmd_struct (struct an_softc *, struct an_command *,
152 struct an_reply *);
153static int an_read_record (struct an_softc *, struct an_ltv_gen *);
154static int an_write_record (struct an_softc *, struct an_ltv_gen *);
155static int an_read_data (struct an_softc *, int,
156 int, caddr_t, int);
157static int an_write_data (struct an_softc *, int,
158 int, caddr_t, int);
159static int an_seek (struct an_softc *, int, int, int);
160static int an_alloc_nicmem (struct an_softc *, int, int *);
161static int an_dma_malloc (struct an_softc *, bus_size_t,
162 struct an_dma_alloc *, int);
163static void an_dma_free (struct an_softc *,
164 struct an_dma_alloc *);
165static void an_dma_malloc_cb (void *, bus_dma_segment_t *, int, int);
166static void an_stats_update (void *);
167static void an_setdef (struct an_softc *, struct an_req *);
984263bc 168#ifdef ANCACHE
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169static void an_cache_store (struct an_softc *, struct mbuf *,
170 uint8_t, uint8_t);
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171#endif
172
173/* function definitions for use with the Cisco's Linux configuration
174 utilities
175*/
176
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177static int readrids (struct ifnet*, struct aironet_ioctl*);
178static int writerids (struct ifnet*, struct aironet_ioctl*);
179static int flashcard (struct ifnet*, struct aironet_ioctl*);
984263bc 180
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181static int cmdreset (struct ifnet *);
182static int setflashmode (struct ifnet *);
183static int flashgchar (struct ifnet *,int,int);
184static int flashpchar (struct ifnet *,int,int);
185static int flashputbuf (struct ifnet *);
186static int flashrestart (struct ifnet *);
187static int WaitBusy (struct ifnet *, int);
188static int unstickbusy (struct ifnet *);
984263bc 189
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190static void an_dump_record (struct an_softc *,struct an_ltv_gen *,
191 char *);
984263bc 192
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193static int an_media_change (struct ifnet *);
194static void an_media_status (struct ifnet *, struct ifmediareq *);
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195
196static int an_dump = 0;
197static int an_cache_mode = 0;
198
199#define DBM 0
200#define PERCENT 1
201#define RAW 2
202
203static char an_conf[256];
204static char an_conf_cache[256];
205
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206DECLARE_DUMMY_MODULE(if_an);
207
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208/* sysctl vars */
209
210SYSCTL_NODE(_hw, OID_AUTO, an, CTLFLAG_RD, 0, "Wireless driver parameters");
211
212static int
213sysctl_an_dump(SYSCTL_HANDLER_ARGS)
214{
215 int error, r, last;
216 char *s = an_conf;
217
218 last = an_dump;
219
220 switch (an_dump) {
221 case 0:
222 strcpy(an_conf, "off");
223 break;
224 case 1:
225 strcpy(an_conf, "type");
226 break;
227 case 2:
228 strcpy(an_conf, "dump");
229 break;
230 default:
231 snprintf(an_conf, 5, "%x", an_dump);
232 break;
233 }
234
235 error = sysctl_handle_string(oidp, an_conf, sizeof(an_conf), req);
236
237 if (strncmp(an_conf,"off", 3) == 0) {
238 an_dump = 0;
239 }
240 if (strncmp(an_conf,"dump", 4) == 0) {
241 an_dump = 1;
242 }
243 if (strncmp(an_conf,"type", 4) == 0) {
244 an_dump = 2;
245 }
246 if (*s == 'f') {
247 r = 0;
248 for (;;s++) {
249 if ((*s >= '0') && (*s <= '9')) {
250 r = r * 16 + (*s - '0');
251 } else if ((*s >= 'a') && (*s <= 'f')) {
252 r = r * 16 + (*s - 'a' + 10);
253 } else {
254 break;
255 }
256 }
257 an_dump = r;
258 }
259 if (an_dump != last)
260 printf("Sysctl changed for Aironet driver\n");
261
262 return error;
263}
264
265SYSCTL_PROC(_hw_an, OID_AUTO, an_dump, CTLTYPE_STRING | CTLFLAG_RW,
266 0, sizeof(an_conf), sysctl_an_dump, "A", "");
267
268static int
269sysctl_an_cache_mode(SYSCTL_HANDLER_ARGS)
270{
271 int error, last;
272
273 last = an_cache_mode;
274
275 switch (an_cache_mode) {
276 case 1:
277 strcpy(an_conf_cache, "per");
278 break;
279 case 2:
280 strcpy(an_conf_cache, "raw");
281 break;
282 default:
283 strcpy(an_conf_cache, "dbm");
284 break;
285 }
286
287 error = sysctl_handle_string(oidp, an_conf_cache,
288 sizeof(an_conf_cache), req);
289
290 if (strncmp(an_conf_cache,"dbm", 3) == 0) {
291 an_cache_mode = 0;
292 }
293 if (strncmp(an_conf_cache,"per", 3) == 0) {
294 an_cache_mode = 1;
295 }
296 if (strncmp(an_conf_cache,"raw", 3) == 0) {
297 an_cache_mode = 2;
298 }
299
300 return error;
301}
302
303SYSCTL_PROC(_hw_an, OID_AUTO, an_cache_mode, CTLTYPE_STRING | CTLFLAG_RW,
304 0, sizeof(an_conf_cache), sysctl_an_cache_mode, "A", "");
305
306/*
307 * We probe for an Aironet 4500/4800 card by attempting to
308 * read the default SSID list. On reset, the first entry in
309 * the SSID list will contain the name "tsunami." If we don't
310 * find this, then there's no card present.
311 */
312int
313an_probe(dev)
314 device_t dev;
315{
316 struct an_softc *sc = device_get_softc(dev);
317 struct an_ltv_ssidlist ssid;
318 int error;
319
320 bzero((char *)&ssid, sizeof(ssid));
321
322 error = an_alloc_port(dev, 0, AN_IOSIZ);
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323 if (error)
324 return (error);
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325
326 /* can't do autoprobing */
327 if (rman_get_start(sc->port_res) == -1)
902f6373 328 return(ENXIO);
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329
330 /*
331 * We need to fake up a softc structure long enough
332 * to be able to issue commands and call some of the
333 * other routines.
334 */
335 sc->an_bhandle = rman_get_bushandle(sc->port_res);
336 sc->an_btag = rman_get_bustag(sc->port_res);
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337
338 ssid.an_len = sizeof(ssid);
339 ssid.an_type = AN_RID_SSIDLIST;
340
341 /* Make sure interrupts are disabled. */
342 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
343 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
344
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345 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
346 device_get_unit(dev));
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347 an_reset(sc);
348 /* No need for an_init_mpi350_desc since it will be done in attach */
349
350 if (an_cmd(sc, AN_CMD_READCFG, 0))
902f6373 351 return(ENXIO);
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352
353 if (an_read_record(sc, (struct an_ltv_gen *)&ssid))
902f6373 354 return(ENXIO);
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355
356 /* See if the ssid matches what we expect ... but doesn't have to */
357 if (strcmp(ssid.an_ssid1, AN_DEF_SSID))
902f6373 358 return(ENXIO);
984263bc 359
902f6373 360 return(0);
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361}
362
363/*
364 * Allocate a port resource with the given resource id.
365 */
366int
367an_alloc_port(dev, rid, size)
368 device_t dev;
369 int rid;
370 int size;
371{
372 struct an_softc *sc = device_get_softc(dev);
373 struct resource *res;
374
375 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
376 0ul, ~0ul, size, RF_ACTIVE);
377 if (res) {
378 sc->port_rid = rid;
379 sc->port_res = res;
380 return (0);
381 } else {
382 return (ENOENT);
383 }
384}
385
386/*
387 * Allocate a memory resource with the given resource id.
388 */
389int an_alloc_memory(device_t dev, int rid, int size)
390{
391 struct an_softc *sc = device_get_softc(dev);
392 struct resource *res;
393
394 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
395 0ul, ~0ul, size, RF_ACTIVE);
396 if (res) {
397 sc->mem_rid = rid;
398 sc->mem_res = res;
399 sc->mem_used = size;
400 return (0);
401 } else {
402 return (ENOENT);
403 }
404}
405
406/*
407 * Allocate a auxilary memory resource with the given resource id.
408 */
409int an_alloc_aux_memory(device_t dev, int rid, int size)
410{
411 struct an_softc *sc = device_get_softc(dev);
412 struct resource *res;
413
414 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
415 0ul, ~0ul, size, RF_ACTIVE);
416 if (res) {
417 sc->mem_aux_rid = rid;
418 sc->mem_aux_res = res;
419 sc->mem_aux_used = size;
420 return (0);
421 } else {
422 return (ENOENT);
423 }
424}
425
426/*
427 * Allocate an irq resource with the given resource id.
428 */
429int
430an_alloc_irq(dev, rid, flags)
431 device_t dev;
432 int rid;
433 int flags;
434{
435 struct an_softc *sc = device_get_softc(dev);
436 struct resource *res;
437
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438 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
439 (RF_ACTIVE | flags));
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440 if (res) {
441 sc->irq_rid = rid;
442 sc->irq_res = res;
443 return (0);
444 } else {
445 return (ENOENT);
446 }
447}
448
449static void
450an_dma_malloc_cb(arg, segs, nseg, error)
451 void *arg;
452 bus_dma_segment_t *segs;
453 int nseg;
454 int error;
455{
456 bus_addr_t *paddr = (bus_addr_t*) arg;
457 *paddr = segs->ds_addr;
458}
459
460/*
461 * Alloc DMA memory and set the pointer to it
462 */
463static int
464an_dma_malloc(sc, size, dma, mapflags)
465 struct an_softc *sc;
466 bus_size_t size;
467 struct an_dma_alloc *dma;
468 int mapflags;
469{
470 int r;
471
c45c9d6a 472 r = bus_dmamap_create(sc->an_dtag, 0, &dma->an_dma_map);
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473 if (r != 0)
474 goto fail_0;
475
476 r = bus_dmamem_alloc(sc->an_dtag, (void**) &dma->an_dma_vaddr,
c45c9d6a 477 BUS_DMA_WAITOK, &dma->an_dma_map);
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478 if (r != 0)
479 goto fail_1;
480
481 r = bus_dmamap_load(sc->an_dtag, dma->an_dma_map, dma->an_dma_vaddr,
482 size,
483 an_dma_malloc_cb,
484 &dma->an_dma_paddr,
c45c9d6a 485 mapflags);
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486 if (r != 0)
487 goto fail_2;
488
489 dma->an_dma_size = size;
490 return (0);
491
492fail_2:
493 bus_dmamap_unload(sc->an_dtag, dma->an_dma_map);
494fail_1:
495 bus_dmamem_free(sc->an_dtag, dma->an_dma_vaddr, dma->an_dma_map);
496fail_0:
497 bus_dmamap_destroy(sc->an_dtag, dma->an_dma_map);
498 dma->an_dma_map = NULL;
499 return (r);
500}
501
502static void
503an_dma_free(sc, dma)
504 struct an_softc *sc;
505 struct an_dma_alloc *dma;
506{
507 bus_dmamap_unload(sc->an_dtag, dma->an_dma_map);
508 bus_dmamem_free(sc->an_dtag, dma->an_dma_vaddr, dma->an_dma_map);
509 bus_dmamap_destroy(sc->an_dtag, dma->an_dma_map);
510}
511
512/*
513 * Release all resources
514 */
515void
516an_release_resources(dev)
517 device_t dev;
518{
519 struct an_softc *sc = device_get_softc(dev);
520 int i;
521
522 if (sc->port_res) {
523 bus_release_resource(dev, SYS_RES_IOPORT,
524 sc->port_rid, sc->port_res);
525 sc->port_res = 0;
526 }
527 if (sc->mem_res) {
528 bus_release_resource(dev, SYS_RES_MEMORY,
529 sc->mem_rid, sc->mem_res);
530 sc->mem_res = 0;
531 }
532 if (sc->mem_aux_res) {
533 bus_release_resource(dev, SYS_RES_MEMORY,
534 sc->mem_aux_rid, sc->mem_aux_res);
535 sc->mem_aux_res = 0;
536 }
537 if (sc->irq_res) {
538 bus_release_resource(dev, SYS_RES_IRQ,
539 sc->irq_rid, sc->irq_res);
540 sc->irq_res = 0;
541 }
542 if (sc->an_rid_buffer.an_dma_paddr) {
543 an_dma_free(sc, &sc->an_rid_buffer);
544 }
545 for (i = 0; i < AN_MAX_RX_DESC; i++)
546 if (sc->an_rx_buffer[i].an_dma_paddr) {
547 an_dma_free(sc, &sc->an_rx_buffer[i]);
548 }
549 for (i = 0; i < AN_MAX_TX_DESC; i++)
550 if (sc->an_tx_buffer[i].an_dma_paddr) {
551 an_dma_free(sc, &sc->an_tx_buffer[i]);
552 }
553 if (sc->an_dtag) {
554 bus_dma_tag_destroy(sc->an_dtag);
555 }
556
557}
558
559int
560an_init_mpi350_desc(sc)
561 struct an_softc *sc;
562{
563 struct an_command cmd_struct;
564 struct an_reply reply;
565 struct an_card_rid_desc an_rid_desc;
566 struct an_card_rx_desc an_rx_desc;
567 struct an_card_tx_desc an_tx_desc;
568 int i, desc;
569
570 if(!sc->an_rid_buffer.an_dma_paddr)
571 an_dma_malloc(sc, AN_RID_BUFFER_SIZE,
572 &sc->an_rid_buffer, 0);
573 for (i = 0; i < AN_MAX_RX_DESC; i++)
574 if(!sc->an_rx_buffer[i].an_dma_paddr)
575 an_dma_malloc(sc, AN_RX_BUFFER_SIZE,
576 &sc->an_rx_buffer[i], 0);
577 for (i = 0; i < AN_MAX_TX_DESC; i++)
578 if(!sc->an_tx_buffer[i].an_dma_paddr)
579 an_dma_malloc(sc, AN_TX_BUFFER_SIZE,
580 &sc->an_tx_buffer[i], 0);
581
582 /*
583 * Allocate RX descriptor
584 */
585 bzero(&reply,sizeof(reply));
586 cmd_struct.an_cmd = AN_CMD_ALLOC_DESC;
587 cmd_struct.an_parm0 = AN_DESCRIPTOR_RX;
588 cmd_struct.an_parm1 = AN_RX_DESC_OFFSET;
589 cmd_struct.an_parm2 = AN_MAX_RX_DESC;
590 if (an_cmd_struct(sc, &cmd_struct, &reply)) {
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591 if_printf(&sc->arpcom.ac_if,
592 "failed to allocate RX descriptor\n");
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593 return(EIO);
594 }
595
596 for (desc = 0; desc < AN_MAX_RX_DESC; desc++) {
597 bzero(&an_rx_desc, sizeof(an_rx_desc));
598 an_rx_desc.an_valid = 1;
599 an_rx_desc.an_len = AN_RX_BUFFER_SIZE;
600 an_rx_desc.an_done = 0;
601 an_rx_desc.an_phys = sc->an_rx_buffer[desc].an_dma_paddr;
602
603 for (i = 0; i < sizeof(an_rx_desc) / 4; i++)
604 CSR_MEM_AUX_WRITE_4(sc, AN_RX_DESC_OFFSET
605 + (desc * sizeof(an_rx_desc))
606 + (i * 4),
607 ((u_int32_t*)&an_rx_desc)[i]);
608 }
609
610 /*
611 * Allocate TX descriptor
612 */
613
614 bzero(&reply,sizeof(reply));
615 cmd_struct.an_cmd = AN_CMD_ALLOC_DESC;
616 cmd_struct.an_parm0 = AN_DESCRIPTOR_TX;
617 cmd_struct.an_parm1 = AN_TX_DESC_OFFSET;
618 cmd_struct.an_parm2 = AN_MAX_TX_DESC;
619 if (an_cmd_struct(sc, &cmd_struct, &reply)) {
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620 if_printf(&sc->arpcom.ac_if,
621 "failed to allocate TX descriptor\n");
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622 return(EIO);
623 }
624
625 for (desc = 0; desc < AN_MAX_TX_DESC; desc++) {
626 bzero(&an_tx_desc, sizeof(an_tx_desc));
627 an_tx_desc.an_offset = 0;
628 an_tx_desc.an_eoc = 0;
629 an_tx_desc.an_valid = 0;
630 an_tx_desc.an_len = 0;
631 an_tx_desc.an_phys = sc->an_tx_buffer[desc].an_dma_paddr;
632
633 for (i = 0; i < sizeof(an_tx_desc) / 4; i++)
634 CSR_MEM_AUX_WRITE_4(sc, AN_TX_DESC_OFFSET
635 + (desc * sizeof(an_tx_desc))
636 + (i * 4),
637 ((u_int32_t*)&an_tx_desc)[i]);
638 }
639
640 /*
641 * Allocate RID descriptor
642 */
643
644 bzero(&reply,sizeof(reply));
645 cmd_struct.an_cmd = AN_CMD_ALLOC_DESC;
646 cmd_struct.an_parm0 = AN_DESCRIPTOR_HOSTRW;
647 cmd_struct.an_parm1 = AN_HOST_DESC_OFFSET;
648 cmd_struct.an_parm2 = 1;
649 if (an_cmd_struct(sc, &cmd_struct, &reply)) {
1c70eebf
JS
650 if_printf(&sc->arpcom.ac_if,
651 "failed to allocate host descriptor\n");
984263bc
MD
652 return(EIO);
653 }
654
655 bzero(&an_rid_desc, sizeof(an_rid_desc));
656 an_rid_desc.an_valid = 1;
657 an_rid_desc.an_len = AN_RID_BUFFER_SIZE;
658 an_rid_desc.an_rid = 0;
659 an_rid_desc.an_phys = sc->an_rid_buffer.an_dma_paddr;
660
661 for (i = 0; i < sizeof(an_rid_desc) / 4; i++)
662 CSR_MEM_AUX_WRITE_4(sc, AN_HOST_DESC_OFFSET + i * 4,
663 ((u_int32_t*)&an_rid_desc)[i]);
664
665 return(0);
666}
667
668int
1c70eebf 669an_attach(sc, dev, flags)
984263bc 670 struct an_softc *sc;
1c70eebf 671 device_t dev;
984263bc
MD
672 int flags;
673{
674 struct ifnet *ifp = &sc->arpcom.ac_if;
675 int error;
676
89c0f216 677 callout_init(&sc->an_stat_timer);
984263bc
MD
678 sc->an_associated = 0;
679 sc->an_monitor = 0;
680 sc->an_was_monitor = 0;
681 sc->an_flash_buffer = NULL;
682
1c70eebf
JS
683 ifp->if_softc = sc;
684 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
685
984263bc
MD
686 /* Reset the NIC. */
687 an_reset(sc);
688 if (sc->mpi350) {
689 error = an_init_mpi350_desc(sc);
690 if (error)
691 return(error);
692 }
693
694 /* Load factory config */
695 if (an_cmd(sc, AN_CMD_READCFG, 0)) {
1c70eebf 696 device_printf(dev, "failed to load config data\n");
984263bc
MD
697 return(EIO);
698 }
699
700 /* Read the current configuration */
701 sc->an_config.an_type = AN_RID_GENCONFIG;
702 sc->an_config.an_len = sizeof(struct an_ltv_genconfig);
703 if (an_read_record(sc, (struct an_ltv_gen *)&sc->an_config)) {
1c70eebf 704 device_printf(dev, "read record failed\n");
984263bc
MD
705 return(EIO);
706 }
707
708 /* Read the card capabilities */
709 sc->an_caps.an_type = AN_RID_CAPABILITIES;
710 sc->an_caps.an_len = sizeof(struct an_ltv_caps);
711 if (an_read_record(sc, (struct an_ltv_gen *)&sc->an_caps)) {
1c70eebf 712 device_printf(dev, "read record failed\n");
984263bc
MD
713 return(EIO);
714 }
715
716 /* Read ssid list */
717 sc->an_ssidlist.an_type = AN_RID_SSIDLIST;
718 sc->an_ssidlist.an_len = sizeof(struct an_ltv_ssidlist);
719 if (an_read_record(sc, (struct an_ltv_gen *)&sc->an_ssidlist)) {
1c70eebf 720 device_printf(dev, "read record failed\n");
984263bc
MD
721 return(EIO);
722 }
723
724 /* Read AP list */
725 sc->an_aplist.an_type = AN_RID_APLIST;
726 sc->an_aplist.an_len = sizeof(struct an_ltv_aplist);
727 if (an_read_record(sc, (struct an_ltv_gen *)&sc->an_aplist)) {
1c70eebf 728 device_printf(dev, "read record failed\n");
984263bc
MD
729 return(EIO);
730 }
731
732#ifdef ANCACHE
733 /* Read the RSSI <-> dBm map */
734 sc->an_have_rssimap = 0;
735 if (sc->an_caps.an_softcaps & 8) {
736 sc->an_rssimap.an_type = AN_RID_RSSI_MAP;
737 sc->an_rssimap.an_len = sizeof(struct an_ltv_rssi_map);
738 if (an_read_record(sc, (struct an_ltv_gen *)&sc->an_rssimap)) {
1c70eebf 739 device_printf(dev, "unable to get RSSI <-> dBM map\n");
984263bc 740 } else {
1c70eebf 741 device_printf(dev, "got RSSI <-> dBM map\n");
984263bc
MD
742 sc->an_have_rssimap = 1;
743 }
744 } else {
1c70eebf 745 device_printf(dev, "no RSSI <-> dBM map\n");
984263bc
MD
746 }
747#endif
748
984263bc
MD
749 ifp->if_mtu = ETHERMTU;
750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
751 ifp->if_ioctl = an_ioctl;
984263bc
MD
752 ifp->if_start = an_start;
753 ifp->if_watchdog = an_watchdog;
754 ifp->if_init = an_init;
755 ifp->if_baudrate = 10000000;
38de8487
JS
756 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
757 ifq_set_ready(&ifp->if_snd);
984263bc
MD
758
759 bzero(sc->an_config.an_nodename, sizeof(sc->an_config.an_nodename));
760 bcopy(AN_DEFAULT_NODENAME, sc->an_config.an_nodename,
761 sizeof(AN_DEFAULT_NODENAME) - 1);
762
763 bzero(sc->an_ssidlist.an_ssid1, sizeof(sc->an_ssidlist.an_ssid1));
764 bcopy(AN_DEFAULT_NETNAME, sc->an_ssidlist.an_ssid1,
765 sizeof(AN_DEFAULT_NETNAME) - 1);
766 sc->an_ssidlist.an_ssid1_len = strlen(AN_DEFAULT_NETNAME);
767
768 sc->an_config.an_opmode =
769 AN_OPMODE_INFRASTRUCTURE_STATION;
770
771 sc->an_tx_rate = 0;
772 bzero((char *)&sc->an_stats, sizeof(sc->an_stats));
773
774 ifmedia_init(&sc->an_ifmedia, 0, an_media_change, an_media_status);
775#define ADD(m, c) ifmedia_add(&sc->an_ifmedia, (m), (c), NULL)
776 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS1,
777 IFM_IEEE80211_ADHOC, 0), 0);
778 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS1, 0, 0), 0);
779 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS2,
780 IFM_IEEE80211_ADHOC, 0), 0);
781 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS2, 0, 0), 0);
782 if (sc->an_caps.an_rates[2] == AN_RATE_5_5MBPS) {
783 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS5,
784 IFM_IEEE80211_ADHOC, 0), 0);
785 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS5, 0, 0), 0);
786 }
787 if (sc->an_caps.an_rates[3] == AN_RATE_11MBPS) {
788 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS11,
789 IFM_IEEE80211_ADHOC, 0), 0);
790 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_IEEE80211_DS11, 0, 0), 0);
791 }
792 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_AUTO,
793 IFM_IEEE80211_ADHOC, 0), 0);
794 ADD(IFM_MAKEWORD(IFM_IEEE80211, IFM_AUTO, 0, 0), 0);
795#undef ADD
796 ifmedia_set(&sc->an_ifmedia, IFM_MAKEWORD(IFM_IEEE80211, IFM_AUTO,
797 0, 0));
798
799 /*
800 * Call MI attach routine.
801 */
0a8b5977 802 ether_ifattach(ifp, sc->an_caps.an_oemaddr);
984263bc
MD
803
804 return(0);
805}
806
fcb0f42c
JS
807int
808an_detach(device_t dev)
809{
810 struct an_softc *sc = device_get_softc(dev);
811 struct ifnet *ifp = &sc->arpcom.ac_if;
812
813 crit_enter();
814 an_stop(sc);
815 ifmedia_removeall(&sc->an_ifmedia);
816 ether_ifdetach(ifp);
817 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
818 crit_exit();
819
820 an_release_resources(dev);
821 return 0;
822}
823
984263bc
MD
824static void
825an_rxeof(sc)
826 struct an_softc *sc;
827{
828 struct ifnet *ifp;
829 struct ether_header *eh;
830 struct ieee80211_frame *ih;
831 struct an_rxframe rx_frame;
832 struct an_rxframe_802_3 rx_frame_802_3;
833 struct mbuf *m;
834 int len, id, error = 0, i, count = 0;
835 int ieee80211_header_len;
836 u_char *bpf_buf;
837 u_short fc1;
838 struct an_card_rx_desc an_rx_desc;
839 u_int8_t *buf;
840
841 ifp = &sc->arpcom.ac_if;
842
843 if (!sc->mpi350) {
844 id = CSR_READ_2(sc, AN_RX_FID);
845
846 if (sc->an_monitor && (ifp->if_flags & IFF_PROMISC)) {
847 /* read raw 802.11 packet */
848 bpf_buf = sc->buf_802_11;
849
850 /* read header */
851 if (an_read_data(sc, id, 0x0, (caddr_t)&rx_frame,
852 sizeof(rx_frame))) {
853 ifp->if_ierrors++;
854 return;
855 }
856
857 /*
858 * skip beacon by default since this increases the
859 * system load a lot
860 */
861
862 if (!(sc->an_monitor & AN_MONITOR_INCLUDE_BEACON) &&
863 (rx_frame.an_frame_ctl &
864 IEEE80211_FC0_SUBTYPE_BEACON)) {
865 return;
866 }
867
868 if (sc->an_monitor & AN_MONITOR_AIRONET_HEADER) {
869 len = rx_frame.an_rx_payload_len
870 + sizeof(rx_frame);
871 /* Check for insane frame length */
872 if (len > sizeof(sc->buf_802_11)) {
1c70eebf
JS
873 if_printf(ifp,
874 "oversized packet received "
875 "(%d, %d)\n", len, MCLBYTES);
984263bc
MD
876 ifp->if_ierrors++;
877 return;
878 }
879
880 bcopy((char *)&rx_frame,
881 bpf_buf, sizeof(rx_frame));
882
883 error = an_read_data(sc, id, sizeof(rx_frame),
884 (caddr_t)bpf_buf+sizeof(rx_frame),
885 rx_frame.an_rx_payload_len);
886 } else {
887 fc1=rx_frame.an_frame_ctl >> 8;
888 ieee80211_header_len =
889 sizeof(struct ieee80211_frame);
890 if ((fc1 & IEEE80211_FC1_DIR_TODS) &&
891 (fc1 & IEEE80211_FC1_DIR_FROMDS)) {
892 ieee80211_header_len += ETHER_ADDR_LEN;
893 }
894
895 len = rx_frame.an_rx_payload_len
896 + ieee80211_header_len;
897 /* Check for insane frame length */
898 if (len > sizeof(sc->buf_802_11)) {
1c70eebf
JS
899 if_printf(ifp,
900 "oversized packet received "
901 "(%d, %d)\n", len, MCLBYTES);
984263bc
MD
902 ifp->if_ierrors++;
903 return;
904 }
905
906 ih = (struct ieee80211_frame *)bpf_buf;
907
908 bcopy((char *)&rx_frame.an_frame_ctl,
909 (char *)ih, ieee80211_header_len);
910
911 error = an_read_data(sc, id, sizeof(rx_frame) +
912 rx_frame.an_gaplen,
913 (caddr_t)ih +ieee80211_header_len,
914 rx_frame.an_rx_payload_len);
915 }
7600679e 916 BPF_TAP(ifp, bpf_buf, len);
984263bc 917 } else {
17b71a59 918 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
919 if (m == NULL) {
920 ifp->if_ierrors++;
921 return;
922 }
984263bc
MD
923 m->m_pkthdr.rcvif = ifp;
924 /* Read Ethernet encapsulated packet */
925
926#ifdef ANCACHE
927 /* Read NIC frame header */
928 if (an_read_data(sc, id, 0, (caddr_t)&rx_frame,
929 sizeof(rx_frame))) {
930 ifp->if_ierrors++;
931 return;
932 }
933#endif
934 /* Read in the 802_3 frame header */
935 if (an_read_data(sc, id, 0x34,
936 (caddr_t)&rx_frame_802_3,
937 sizeof(rx_frame_802_3))) {
938 ifp->if_ierrors++;
939 return;
940 }
941 if (rx_frame_802_3.an_rx_802_3_status != 0) {
942 ifp->if_ierrors++;
943 return;
944 }
945 /* Check for insane frame length */
946 len = rx_frame_802_3.an_rx_802_3_payload_len;
947 if (len > sizeof(sc->buf_802_11)) {
1c70eebf
JS
948 if_printf(ifp,
949 "oversized packet received (%d, %d)\n",
950 len, MCLBYTES);
984263bc
MD
951 ifp->if_ierrors++;
952 return;
953 }
954 m->m_pkthdr.len = m->m_len =
955 rx_frame_802_3.an_rx_802_3_payload_len + 12;
956
957 eh = mtod(m, struct ether_header *);
958
959 bcopy((char *)&rx_frame_802_3.an_rx_dst_addr,
960 (char *)&eh->ether_dhost, ETHER_ADDR_LEN);
961 bcopy((char *)&rx_frame_802_3.an_rx_src_addr,
962 (char *)&eh->ether_shost, ETHER_ADDR_LEN);
963
964 /* in mbuf header type is just before payload */
965 error = an_read_data(sc, id, 0x44,
966 (caddr_t)&(eh->ether_type),
967 rx_frame_802_3.an_rx_802_3_payload_len);
968
969 if (error) {
970 m_freem(m);
971 ifp->if_ierrors++;
972 return;
973 }
974 ifp->if_ipackets++;
975
984263bc 976#ifdef ANCACHE
3013ac0e 977 an_cache_store(sc, m,
984263bc
MD
978 rx_frame.an_rx_signal_strength,
979 rx_frame.an_rsvd0);
980#endif
3013ac0e 981 (*ifp->if_input)(ifp, m);
984263bc
MD
982 }
983
984 } else { /* MPI-350 */
985 for (count = 0; count < AN_MAX_RX_DESC; count++){
986 for (i = 0; i < sizeof(an_rx_desc) / 4; i++)
987 ((u_int32_t*)&an_rx_desc)[i]
988 = CSR_MEM_AUX_READ_4(sc,
989 AN_RX_DESC_OFFSET
990 + (count * sizeof(an_rx_desc))
991 + (i * 4));
992
993 if (an_rx_desc.an_done && !an_rx_desc.an_valid) {
994 buf = sc->an_rx_buffer[count].an_dma_vaddr;
995
17b71a59 996 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
997 if (m == NULL) {
998 ifp->if_ierrors++;
999 return;
1000 }
984263bc
MD
1001 m->m_pkthdr.rcvif = ifp;
1002 /* Read Ethernet encapsulated packet */
1003
1004 /*
1005 * No ANCACHE support since we just get back
1006 * an Ethernet packet no 802.11 info
1007 */
1008#if 0
1009#ifdef ANCACHE
1010 /* Read NIC frame header */
1011 bcopy(buf, (caddr_t)&rx_frame,
1012 sizeof(rx_frame));
1013#endif
1014#endif
1015 /* Check for insane frame length */
1016 len = an_rx_desc.an_len + 12;
1017 if (len > MCLBYTES) {
1c70eebf
JS
1018 if_printf(ifp,
1019 "oversized packet received "
1020 "(%d, %d)\n", len, MCLBYTES);
984263bc
MD
1021 ifp->if_ierrors++;
1022 return;
1023 }
1024
1025 m->m_pkthdr.len = m->m_len =
1026 an_rx_desc.an_len + 12;
1027
1028 eh = mtod(m, struct ether_header *);
1029
1030 bcopy(buf, (char *)eh,
1031 m->m_pkthdr.len);
1032
1033 ifp->if_ipackets++;
1034
984263bc
MD
1035#if 0
1036#ifdef ANCACHE
3013ac0e 1037 an_cache_store(sc, m,
984263bc
MD
1038 rx_frame.an_rx_signal_strength,
1039 rx_frame.an_rsvd0);
1040#endif
1041#endif
3013ac0e 1042 (*ifp->if_input)(ifp, m);
984263bc
MD
1043
1044 an_rx_desc.an_valid = 1;
1045 an_rx_desc.an_len = AN_RX_BUFFER_SIZE;
1046 an_rx_desc.an_done = 0;
1047 an_rx_desc.an_phys =
1048 sc->an_rx_buffer[count].an_dma_paddr;
1049
1050 for (i = 0; i < sizeof(an_rx_desc) / 4; i++)
1051 CSR_MEM_AUX_WRITE_4(sc,
1052 AN_RX_DESC_OFFSET
1053 + (count * sizeof(an_rx_desc))
1054 + (i * 4),
1055 ((u_int32_t*)&an_rx_desc)[i]);
1056
1057 } else {
1c70eebf
JS
1058 if_printf(ifp, "Didn't get valid RX packet "
1059 "%x %x %d\n",
1060 an_rx_desc.an_done,
1061 an_rx_desc.an_valid,
1062 an_rx_desc.an_len);
984263bc
MD
1063 }
1064 }
1065 }
1066}
1067
1068static void
1069an_txeof(sc, status)
1070 struct an_softc *sc;
1071 int status;
1072{
1073 struct ifnet *ifp;
1074 int id, i;
1075
1076 ifp = &sc->arpcom.ac_if;
1077
1078 ifp->if_timer = 0;
1079 ifp->if_flags &= ~IFF_OACTIVE;
1080
1081 if (!sc->mpi350) {
1082 id = CSR_READ_2(sc, AN_TX_CMP_FID);
1083
1084 if (status & AN_EV_TX_EXC) {
1085 ifp->if_oerrors++;
1086 } else
1087 ifp->if_opackets++;
1088
1089 for (i = 0; i < AN_TX_RING_CNT; i++) {
1090 if (id == sc->an_rdata.an_tx_ring[i]) {
1091 sc->an_rdata.an_tx_ring[i] = 0;
1092 break;
1093 }
1094 }
1095
1096 AN_INC(sc->an_rdata.an_tx_cons, AN_TX_RING_CNT);
1097 } else { /* MPI 350 */
1098 AN_INC(sc->an_rdata.an_tx_cons, AN_MAX_TX_DESC);
1099 if (sc->an_rdata.an_tx_prod ==
1100 sc->an_rdata.an_tx_cons)
1101 sc->an_rdata.an_tx_empty = 1;
1102 }
1103
1104 return;
1105}
1106
1107/*
1108 * We abuse the stats updater to check the current NIC status. This
1109 * is important because we don't want to allow transmissions until
1110 * the NIC has synchronized to the current cell (either as the master
1111 * in an ad-hoc group, or as a station connected to an access point).
1112 */
1113static void
1114an_stats_update(xsc)
1115 void *xsc;
1116{
1117 struct an_softc *sc;
1118 struct ifnet *ifp;
984263bc
MD
1119
1120 sc = xsc;
1121 ifp = &sc->arpcom.ac_if;
1122
41d6c56f
JS
1123 crit_enter();
1124
984263bc
MD
1125 sc->an_status.an_type = AN_RID_STATUS;
1126 sc->an_status.an_len = sizeof(struct an_ltv_status);
1127 an_read_record(sc, (struct an_ltv_gen *)&sc->an_status);
1128
1129 if (sc->an_status.an_opmode & AN_STATUS_OPMODE_IN_SYNC)
1130 sc->an_associated = 1;
1131 else
1132 sc->an_associated = 0;
1133
41d6c56f
JS
1134 /* Don't do this while we're not transmitting */
1135 if ((ifp->if_flags & IFF_OACTIVE) == 0) {
1136 sc->an_stats.an_len = sizeof(struct an_ltv_stats);
1137 sc->an_stats.an_type = AN_RID_32BITS_CUM;
1138 an_read_record(sc, (struct an_ltv_gen *)&sc->an_stats.an_len);
984263bc
MD
1139 }
1140
89c0f216 1141 callout_reset(&sc->an_stat_timer, hz, an_stats_update, sc);
984263bc 1142
41d6c56f 1143 crit_exit();
984263bc
MD
1144}
1145
1146void
1147an_intr(xsc)
1148 void *xsc;
1149{
1150 struct an_softc *sc;
1151 struct ifnet *ifp;
1152 u_int16_t status;
1153
1154 sc = (struct an_softc*)xsc;
1155
984263bc
MD
1156 ifp = &sc->arpcom.ac_if;
1157
1158 /* Disable interrupts. */
1159 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
1160
1161 status = CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350));
1162 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS);
1163
1164 if (status & AN_EV_AWAKE) {
1165 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_AWAKE);
1166 }
1167
1168 if (status & AN_EV_LINKSTAT) {
1169 if (CSR_READ_2(sc, AN_LINKSTAT(sc->mpi350))
1170 == AN_LINKSTAT_ASSOCIATED)
1171 sc->an_associated = 1;
1172 else
1173 sc->an_associated = 0;
1174 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT);
1175 }
1176
1177 if (status & AN_EV_RX) {
1178 an_rxeof(sc);
1179 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX);
1180 }
1181
1182 if (status & AN_EV_TX) {
1183 an_txeof(sc, status);
1184 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX);
1185 }
1186
1187 if (status & AN_EV_TX_EXC) {
1188 an_txeof(sc, status);
1189 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_EXC);
1190 }
1191
1192 if (status & AN_EV_ALLOC)
1193 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_ALLOC);
1194
1195 /* Re-enable interrupts. */
1196 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), AN_INTRS);
1197
38de8487 1198 if ((ifp->if_flags & IFF_UP) && !ifq_is_empty(&ifp->if_snd))
984263bc
MD
1199 an_start(ifp);
1200
1201 return;
1202}
1203
1204static int
1205an_cmd_struct(sc, cmd, reply)
1206 struct an_softc *sc;
1207 struct an_command *cmd;
1208 struct an_reply *reply;
1209{
1210 int i;
1211
1212 for (i = 0; i != AN_TIMEOUT; i++) {
1213 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY) {
1214 DELAY(1000);
1215 } else
1216 break;
1217 }
1218 if( i == AN_TIMEOUT) {
1219 printf("BUSY\n");
1220 return(ETIMEDOUT);
1221 }
1222
1223 CSR_WRITE_2(sc, AN_PARAM0(sc->mpi350), cmd->an_parm0);
1224 CSR_WRITE_2(sc, AN_PARAM1(sc->mpi350), cmd->an_parm1);
1225 CSR_WRITE_2(sc, AN_PARAM2(sc->mpi350), cmd->an_parm2);
1226 CSR_WRITE_2(sc, AN_COMMAND(sc->mpi350), cmd->an_cmd);
1227
1228 for (i = 0; i < AN_TIMEOUT; i++) {
1229 if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_CMD)
1230 break;
1231 DELAY(1000);
1232 }
1233
1234 reply->an_resp0 = CSR_READ_2(sc, AN_RESP0(sc->mpi350));
1235 reply->an_resp1 = CSR_READ_2(sc, AN_RESP1(sc->mpi350));
1236 reply->an_resp2 = CSR_READ_2(sc, AN_RESP2(sc->mpi350));
1237 reply->an_status = CSR_READ_2(sc, AN_STATUS(sc->mpi350));
1238
1239 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY)
1240 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_CLR_STUCK_BUSY);
1241
1242 /* Ack the command */
1243 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_CMD);
1244
1245 if (i == AN_TIMEOUT)
1246 return(ETIMEDOUT);
1247
1248 return(0);
1249}
1250
1251static int
1252an_cmd(sc, cmd, val)
1253 struct an_softc *sc;
1254 int cmd;
1255 int val;
1256{
1257 int i, s = 0;
1258
1259 CSR_WRITE_2(sc, AN_PARAM0(sc->mpi350), val);
1260 CSR_WRITE_2(sc, AN_PARAM1(sc->mpi350), 0);
1261 CSR_WRITE_2(sc, AN_PARAM2(sc->mpi350), 0);
1262 CSR_WRITE_2(sc, AN_COMMAND(sc->mpi350), cmd);
1263
1264 for (i = 0; i < AN_TIMEOUT; i++) {
1265 if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_CMD)
1266 break;
1267 else {
1268 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) == cmd)
1269 CSR_WRITE_2(sc, AN_COMMAND(sc->mpi350), cmd);
1270 }
1271 }
1272
1273 for (i = 0; i < AN_TIMEOUT; i++) {
1274 CSR_READ_2(sc, AN_RESP0(sc->mpi350));
1275 CSR_READ_2(sc, AN_RESP1(sc->mpi350));
1276 CSR_READ_2(sc, AN_RESP2(sc->mpi350));
1277 s = CSR_READ_2(sc, AN_STATUS(sc->mpi350));
1278 if ((s & AN_STAT_CMD_CODE) == (cmd & AN_STAT_CMD_CODE))
1279 break;
1280 }
1281
1282 /* Ack the command */
1283 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_CMD);
1284
1285 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY)
1286 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_CLR_STUCK_BUSY);
1287
1288 if (i == AN_TIMEOUT)
1289 return(ETIMEDOUT);
1290
1291 return(0);
1292}
1293
1294/*
1295 * This reset sequence may look a little strange, but this is the
1296 * most reliable method I've found to really kick the NIC in the
1297 * head and force it to reboot correctly.
1298 */
1299static void
1300an_reset(sc)
1301 struct an_softc *sc;
1302{
984263bc
MD
1303 an_cmd(sc, AN_CMD_ENABLE, 0);
1304 an_cmd(sc, AN_CMD_FW_RESTART, 0);
1305 an_cmd(sc, AN_CMD_NOOP2, 0);
1306
1307 if (an_cmd(sc, AN_CMD_FORCE_SYNCLOSS, 0) == ETIMEDOUT)
1c70eebf 1308 if_printf(&sc->arpcom.ac_if, "reset failed\n");
984263bc
MD
1309
1310 an_cmd(sc, AN_CMD_DISABLE, 0);
1311
1312 return;
1313}
1314
1315/*
1316 * Read an LTV record from the NIC.
1317 */
1318static int
1319an_read_record(sc, ltv)
1320 struct an_softc *sc;
1321 struct an_ltv_gen *ltv;
1322{
1323 struct an_ltv_gen *an_ltv;
1324 struct an_card_rid_desc an_rid_desc;
1325 struct an_command cmd;
1326 struct an_reply reply;
1327 u_int16_t *ptr;
1328 u_int8_t *ptr2;
1329 int i, len;
1330
1331 if (ltv->an_len < 4 || ltv->an_type == 0)
1332 return(EINVAL);
1333
1334 if (!sc->mpi350){
1335 /* Tell the NIC to enter record read mode. */
1336 if (an_cmd(sc, AN_CMD_ACCESS|AN_ACCESS_READ, ltv->an_type)) {
1c70eebf 1337 if_printf(&sc->arpcom.ac_if, "RID access failed\n");
984263bc
MD
1338 return(EIO);
1339 }
1340
1341 /* Seek to the record. */
1342 if (an_seek(sc, ltv->an_type, 0, AN_BAP1)) {
1c70eebf 1343 if_printf(&sc->arpcom.ac_if, "seek to record failed\n");
984263bc
MD
1344 return(EIO);
1345 }
1346
1347 /*
1348 * Read the length and record type and make sure they
1349 * match what we expect (this verifies that we have enough
1350 * room to hold all of the returned data).
1351 * Length includes type but not length.
1352 */
1353 len = CSR_READ_2(sc, AN_DATA1);
1354 if (len > (ltv->an_len - 2)) {
1c70eebf
JS
1355 if_printf(&sc->arpcom.ac_if,
1356 "record length mismatch -- expected %d, "
1357 "got %d for Rid %x\n",
1358 ltv->an_len - 2, len, ltv->an_type);
984263bc
MD
1359 len = ltv->an_len - 2;
1360 } else {
1361 ltv->an_len = len + 2;
1362 }
1363
1364 /* Now read the data. */
1365 len -= 2; /* skip the type */
1366 ptr = &ltv->an_val;
1367 for (i = len; i > 1; i -= 2)
1368 *ptr++ = CSR_READ_2(sc, AN_DATA1);
1369 if (i) {
1370 ptr2 = (u_int8_t *)ptr;
1371 *ptr2 = CSR_READ_1(sc, AN_DATA1);
1372 }
1373 } else { /* MPI-350 */
1374 an_rid_desc.an_valid = 1;
1375 an_rid_desc.an_len = AN_RID_BUFFER_SIZE;
1376 an_rid_desc.an_rid = 0;
1377 an_rid_desc.an_phys = sc->an_rid_buffer.an_dma_paddr;
1378 bzero(sc->an_rid_buffer.an_dma_vaddr, AN_RID_BUFFER_SIZE);
1379
1380 bzero(&cmd, sizeof(cmd));
1381 bzero(&reply, sizeof(reply));
1382 cmd.an_cmd = AN_CMD_ACCESS|AN_ACCESS_READ;
1383 cmd.an_parm0 = ltv->an_type;
1384
1385 for (i = 0; i < sizeof(an_rid_desc) / 4; i++)
1386 CSR_MEM_AUX_WRITE_4(sc, AN_HOST_DESC_OFFSET + i * 4,
1387 ((u_int32_t*)&an_rid_desc)[i]);
1388
1389 if (an_cmd_struct(sc, &cmd, &reply)
1390 || reply.an_status & AN_CMD_QUAL_MASK) {
1c70eebf
JS
1391 if_printf(&sc->arpcom.ac_if,
1392 "failed to read RID %x %x %x %x %x, %d\n",
1393 ltv->an_type,
1394 reply.an_status,
1395 reply.an_resp0,
1396 reply.an_resp1,
1397 reply.an_resp2,
1398 i);
984263bc
MD
1399 return(EIO);
1400 }
1401
1402 an_ltv = (struct an_ltv_gen *)sc->an_rid_buffer.an_dma_vaddr;
1403 if (an_ltv->an_len + 2 < an_rid_desc.an_len) {
1404 an_rid_desc.an_len = an_ltv->an_len;
1405 }
1406
1407 if (an_rid_desc.an_len > 2)
1408 bcopy(&an_ltv->an_type,
1409 &ltv->an_val,
1410 an_rid_desc.an_len - 2);
1411 ltv->an_len = an_rid_desc.an_len + 2;
1412 }
1413
1414 if (an_dump)
1415 an_dump_record(sc, ltv, "Read");
1416
1417 return(0);
1418}
1419
1420/*
1421 * Same as read, except we inject data instead of reading it.
1422 */
1423static int
1424an_write_record(sc, ltv)
1425 struct an_softc *sc;
1426 struct an_ltv_gen *ltv;
1427{
1428 struct an_card_rid_desc an_rid_desc;
1429 struct an_command cmd;
1430 struct an_reply reply;
1431 char *buf;
1432 u_int16_t *ptr;
1433 u_int8_t *ptr2;
1434 int i, len;
1435
1436 if (an_dump)
1437 an_dump_record(sc, ltv, "Write");
1438
1439 if (!sc->mpi350){
1440 if (an_cmd(sc, AN_CMD_ACCESS|AN_ACCESS_READ, ltv->an_type))
1441 return(EIO);
1442
1443 if (an_seek(sc, ltv->an_type, 0, AN_BAP1))
1444 return(EIO);
1445
1446 /*
1447 * Length includes type but not length.
1448 */
1449 len = ltv->an_len - 2;
1450 CSR_WRITE_2(sc, AN_DATA1, len);
1451
1452 len -= 2; /* skip the type */
1453 ptr = &ltv->an_val;
1454 for (i = len; i > 1; i -= 2)
1455 CSR_WRITE_2(sc, AN_DATA1, *ptr++);
1456 if (i) {
1457 ptr2 = (u_int8_t *)ptr;
1458 CSR_WRITE_1(sc, AN_DATA0, *ptr2);
1459 }
1460
1461 if (an_cmd(sc, AN_CMD_ACCESS|AN_ACCESS_WRITE, ltv->an_type))
1462 return(EIO);
1463 } else {
1464 /* MPI-350 */
1465
1466 for (i = 0; i != AN_TIMEOUT; i++) {
1467 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350))
1468 & AN_CMD_BUSY) {
1469 DELAY(10);
1470 } else
1471 break;
1472 }
1473 if (i == AN_TIMEOUT) {
1474 printf("BUSY\n");
1475 }
1476
1477 an_rid_desc.an_valid = 1;
1478 an_rid_desc.an_len = ltv->an_len - 2;
1479 an_rid_desc.an_rid = ltv->an_type;
1480 an_rid_desc.an_phys = sc->an_rid_buffer.an_dma_paddr;
1481
1482 bcopy(&ltv->an_type, sc->an_rid_buffer.an_dma_vaddr,
1483 an_rid_desc.an_len);
1484
1485 bzero(&cmd,sizeof(cmd));
1486 bzero(&reply,sizeof(reply));
1487 cmd.an_cmd = AN_CMD_ACCESS|AN_ACCESS_WRITE;
1488 cmd.an_parm0 = ltv->an_type;
1489
1490 for (i = 0; i < sizeof(an_rid_desc) / 4; i++)
1491 CSR_MEM_AUX_WRITE_4(sc, AN_HOST_DESC_OFFSET + i * 4,
1492 ((u_int32_t*)&an_rid_desc)[i]);
1493
1494 if ((i = an_cmd_struct(sc, &cmd, &reply))) {
1c70eebf
JS
1495 if_printf(&sc->arpcom.ac_if,
1496 "failed to write RID 1 %x %x %x %x %x, %d\n",
1497 ltv->an_type,
984263bc
MD
1498 reply.an_status,
1499 reply.an_resp0,
1500 reply.an_resp1,
1501 reply.an_resp2,
1502 i);
1503 return(EIO);
1504 }
1505
1506 ptr = (u_int16_t *)buf;
1507
1508 if (reply.an_status & AN_CMD_QUAL_MASK) {
1c70eebf
JS
1509 if_printf(&sc->arpcom.ac_if,
1510 "failed to write RID 2 %x %x %x %x %x, %d\n",
1511 ltv->an_type,
984263bc
MD
1512 reply.an_status,
1513 reply.an_resp0,
1514 reply.an_resp1,
1515 reply.an_resp2,
1516 i);
1517 return(EIO);
1518 }
1519 }
1520
1521 return(0);
1522}
1523
1524static void
1525an_dump_record(sc, ltv, string)
1526 struct an_softc *sc;
1527 struct an_ltv_gen *ltv;
1528 char *string;
1529{
1530 u_int8_t *ptr2;
1531 int len;
1532 int i;
1533 int count = 0;
1534 char buf[17], temp;
1535
1536 len = ltv->an_len - 4;
1c70eebf
JS
1537 if_printf(&sc->arpcom.ac_if, "RID %4x, Length %4d, Mode %s\n",
1538 ltv->an_type, ltv->an_len - 4, string);
984263bc
MD
1539
1540 if (an_dump == 1 || (an_dump == ltv->an_type)) {
1c70eebf 1541 if_printf(&sc->arpcom.ac_if, "\t");
984263bc
MD
1542 bzero(buf,sizeof(buf));
1543
1544 ptr2 = (u_int8_t *)&ltv->an_val;
1545 for (i = len; i > 0; i--) {
1546 printf("%02x ", *ptr2);
1547
1548 temp = *ptr2++;
1549 if (temp >= ' ' && temp <= '~')
1550 buf[count] = temp;
1551 else if (temp >= 'A' && temp <= 'Z')
1552 buf[count] = temp;
1553 else
1554 buf[count] = '.';
1555 if (++count == 16) {
1556 count = 0;
1557 printf("%s\n",buf);
1c70eebf 1558 if_printf(&sc->arpcom.ac_if, "\t");
984263bc
MD
1559 bzero(buf,sizeof(buf));
1560 }
1561 }
1562 for (; count != 16; count++) {
1563 printf(" ");
1564 }
1565 printf(" %s\n",buf);
1566 }
1567}
1568
1569static int
1570an_seek(sc, id, off, chan)
1571 struct an_softc *sc;
1572 int id, off, chan;
1573{
1574 int i;
1575 int selreg, offreg;
1576
1577 switch (chan) {
1578 case AN_BAP0:
1579 selreg = AN_SEL0;
1580 offreg = AN_OFF0;
1581 break;
1582 case AN_BAP1:
1583 selreg = AN_SEL1;
1584 offreg = AN_OFF1;
1585 break;
1586 default:
1c70eebf 1587 if_printf(&sc->arpcom.ac_if, "invalid data path: %x\n", chan);
984263bc
MD
1588 return(EIO);
1589 }
1590
1591 CSR_WRITE_2(sc, selreg, id);
1592 CSR_WRITE_2(sc, offreg, off);
1593
1594 for (i = 0; i < AN_TIMEOUT; i++) {
1595 if (!(CSR_READ_2(sc, offreg) & (AN_OFF_BUSY|AN_OFF_ERR)))
1596 break;
1597 }
1598
1599 if (i == AN_TIMEOUT)
1600 return(ETIMEDOUT);
1601
1602 return(0);
1603}
1604
1605static int
1606an_read_data(sc, id, off, buf, len)
1607 struct an_softc *sc;
1608 int id, off;
1609 caddr_t buf;
1610 int len;
1611{
1612 int i;
1613 u_int16_t *ptr;
1614 u_int8_t *ptr2;
1615
1616 if (off != -1) {
1617 if (an_seek(sc, id, off, AN_BAP1))
1618 return(EIO);
1619 }
1620
1621 ptr = (u_int16_t *)buf;
1622 for (i = len; i > 1; i -= 2)
1623 *ptr++ = CSR_READ_2(sc, AN_DATA1);
1624 if (i) {
1625 ptr2 = (u_int8_t *)ptr;
1626 *ptr2 = CSR_READ_1(sc, AN_DATA1);
1627 }
1628
1629 return(0);
1630}
1631
1632static int
1633an_write_data(sc, id, off, buf, len)
1634 struct an_softc *sc;
1635 int id, off;
1636 caddr_t buf;
1637 int len;
1638{
1639 int i;
1640 u_int16_t *ptr;
1641 u_int8_t *ptr2;
1642
1643 if (off != -1) {
1644 if (an_seek(sc, id, off, AN_BAP0))
1645 return(EIO);
1646 }
1647
1648 ptr = (u_int16_t *)buf;
1649 for (i = len; i > 1; i -= 2)
1650 CSR_WRITE_2(sc, AN_DATA0, *ptr++);
1651 if (i) {
1652 ptr2 = (u_int8_t *)ptr;
1653 CSR_WRITE_1(sc, AN_DATA0, *ptr2);
1654 }
1655
1656 return(0);
1657}
1658
1659/*
1660 * Allocate a region of memory inside the NIC and zero
1661 * it out.
1662 */
1663static int
1664an_alloc_nicmem(sc, len, id)
1665 struct an_softc *sc;
1666 int len;
1667 int *id;
1668{
1669 int i;
1670
1671 if (an_cmd(sc, AN_CMD_ALLOC_MEM, len)) {
1c70eebf
JS
1672 if_printf(&sc->arpcom.ac_if,
1673 "failed to allocate %d bytes on NIC\n", len);
984263bc
MD
1674 return(ENOMEM);
1675 }
1676
1677 for (i = 0; i < AN_TIMEOUT; i++) {
1678 if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_ALLOC)
1679 break;
1680 }
1681
1682 if (i == AN_TIMEOUT)
1683 return(ETIMEDOUT);
1684
1685 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_ALLOC);
1686 *id = CSR_READ_2(sc, AN_ALLOC_FID);
1687
1688 if (an_seek(sc, *id, 0, AN_BAP0))
1689 return(EIO);
1690
1691 for (i = 0; i < len / 2; i++)
1692 CSR_WRITE_2(sc, AN_DATA0, 0);
1693
1694 return(0);
1695}
1696
1697static void
1698an_setdef(sc, areq)
1699 struct an_softc *sc;
1700 struct an_req *areq;
1701{
984263bc
MD
1702 struct ifnet *ifp;
1703 struct an_ltv_genconfig *cfg;
1704 struct an_ltv_ssidlist *ssid;
1705 struct an_ltv_aplist *ap;
1706 struct an_ltv_gen *sp;
1707
1708 ifp = &sc->arpcom.ac_if;
1709
1710 switch (areq->an_type) {
1711 case AN_RID_GENCONFIG:
1712 cfg = (struct an_ltv_genconfig *)areq;
1713
984263bc
MD
1714 bcopy((char *)&cfg->an_macaddr, (char *)&sc->arpcom.ac_enaddr,
1715 ETHER_ADDR_LEN);
f2682cb9 1716 bcopy((char *)&cfg->an_macaddr, IF_LLADDR(ifp), ETHER_ADDR_LEN);
984263bc
MD
1717
1718 bcopy((char *)cfg, (char *)&sc->an_config,
1719 sizeof(struct an_ltv_genconfig));
1720 break;
1721 case AN_RID_SSIDLIST:
1722 ssid = (struct an_ltv_ssidlist *)areq;
1723 bcopy((char *)ssid, (char *)&sc->an_ssidlist,
1724 sizeof(struct an_ltv_ssidlist));
1725 break;
1726 case AN_RID_APLIST:
1727 ap = (struct an_ltv_aplist *)areq;
1728 bcopy((char *)ap, (char *)&sc->an_aplist,
1729 sizeof(struct an_ltv_aplist));
1730 break;
1731 case AN_RID_TX_SPEED:
1732 sp = (struct an_ltv_gen *)areq;
1733 sc->an_tx_rate = sp->an_val;
1734
1735 /* Read the current configuration */
1736 sc->an_config.an_type = AN_RID_GENCONFIG;
1737 sc->an_config.an_len = sizeof(struct an_ltv_genconfig);
1738 an_read_record(sc, (struct an_ltv_gen *)&sc->an_config);
1739 cfg = &sc->an_config;
1740
1741 /* clear other rates and set the only one we want */
1742 bzero(cfg->an_rates, sizeof(cfg->an_rates));
1743 cfg->an_rates[0] = sc->an_tx_rate;
1744
1745 /* Save the new rate */
1746 sc->an_config.an_type = AN_RID_GENCONFIG;
1747 sc->an_config.an_len = sizeof(struct an_ltv_genconfig);
1748 break;
1749 case AN_RID_WEP_TEMP:
1750 /* Cache the temp keys */
1751 bcopy(areq,
1752 &sc->an_temp_keys[((struct an_ltv_key *)areq)->kindex],
1753 sizeof(struct an_ltv_key));
1754 case AN_RID_WEP_PERM:
1755 case AN_RID_LEAPUSERNAME:
1756 case AN_RID_LEAPPASSWORD:
1757 /* Disable the MAC. */
1758 an_cmd(sc, AN_CMD_DISABLE, 0);
1759
1760 /* Write the key */
1761 an_write_record(sc, (struct an_ltv_gen *)areq);
1762
1763 /* Turn the MAC back on. */
1764 an_cmd(sc, AN_CMD_ENABLE, 0);
1765
1766 break;
1767 case AN_RID_MONITOR_MODE:
1768 cfg = (struct an_ltv_genconfig *)areq;
1769 bpfdetach(ifp);
1770 if (ng_ether_detach_p != NULL)
1771 (*ng_ether_detach_p) (ifp);
1772 sc->an_monitor = cfg->an_len;
1773
1774 if (sc->an_monitor & AN_MONITOR) {
1775 if (sc->an_monitor & AN_MONITOR_AIRONET_HEADER) {
1776 bpfattach(ifp, DLT_AIRONET_HEADER,
1777 sizeof(struct ether_header));
1778 } else {
1779 bpfattach(ifp, DLT_IEEE802_11,
1780 sizeof(struct ether_header));
1781 }
1782 } else {
1783 bpfattach(ifp, DLT_EN10MB,
1784 sizeof(struct ether_header));
1785 if (ng_ether_attach_p != NULL)
1786 (*ng_ether_attach_p) (ifp);
1787 }
1788 break;
1789 default:
1c70eebf 1790 if_printf(ifp, "unknown RID: %x\n", areq->an_type);
984263bc
MD
1791 return;
1792 break;
1793 }
1794
1795
1796 /* Reinitialize the card. */
1797 if (ifp->if_flags)
1798 an_init(sc);
1799
1800 return;
1801}
1802
1803/*
1804 * Derived from Linux driver to enable promiscious mode.
1805 */
1806
1807static void
1808an_promisc(sc, promisc)
1809 struct an_softc *sc;
1810 int promisc;
1811{
1812 if (sc->an_was_monitor)
1813 an_reset(sc);
1c70eebf
JS
1814 if (sc->mpi350)
1815 an_init_mpi350_desc(sc);
984263bc
MD
1816 if (sc->an_monitor || sc->an_was_monitor)
1817 an_init(sc);
1818
1819 sc->an_was_monitor = sc->an_monitor;
1820 an_cmd(sc, AN_CMD_SET_MODE, promisc ? 0xffff : 0);
1821
1822 return;
1823}
1824
1825static int
bd4539cc 1826an_ioctl(ifp, command, data, cr)
984263bc
MD
1827 struct ifnet *ifp;
1828 u_long command;
1829 caddr_t data;
bd4539cc 1830 struct ucred *cr;
984263bc 1831{
41d6c56f 1832 int error = 0;
984263bc
MD
1833 int len;
1834 int i;
1835 struct an_softc *sc;
1836 struct ifreq *ifr;
984263bc
MD
1837 struct ieee80211req *ireq;
1838 u_int8_t tmpstr[IEEE80211_NWID_LEN*2];
1839 u_int8_t *tmpptr;
1840 struct an_ltv_genconfig *config;
1841 struct an_ltv_key *key;
1842 struct an_ltv_status *status;
1843 struct an_ltv_ssidlist *ssids;
1844 int mode;
1845 struct aironet_ioctl l_ioctl;
1846
1847 sc = ifp->if_softc;
984263bc
MD
1848 ifr = (struct ifreq *)data;
1849 ireq = (struct ieee80211req *)data;
1850
41d6c56f
JS
1851 crit_enter();
1852
984263bc
MD
1853 config = (struct an_ltv_genconfig *)&sc->areq;
1854 key = (struct an_ltv_key *)&sc->areq;
1855 status = (struct an_ltv_status *)&sc->areq;
1856 ssids = (struct an_ltv_ssidlist *)&sc->areq;
1857
984263bc 1858 switch (command) {
984263bc
MD
1859 case SIOCSIFFLAGS:
1860 if (ifp->if_flags & IFF_UP) {
1861 if (ifp->if_flags & IFF_RUNNING &&
1862 ifp->if_flags & IFF_PROMISC &&
1863 !(sc->an_if_flags & IFF_PROMISC)) {
1864 an_promisc(sc, 1);
1865 } else if (ifp->if_flags & IFF_RUNNING &&
1866 !(ifp->if_flags & IFF_PROMISC) &&
1867 sc->an_if_flags & IFF_PROMISC) {
1868 an_promisc(sc, 0);
1869 } else
1870 an_init(sc);
1871 } else {
1872 if (ifp->if_flags & IFF_RUNNING)
1873 an_stop(sc);
1874 }
1875 sc->an_if_flags = ifp->if_flags;
1876 error = 0;
1877 break;
1878 case SIOCSIFMEDIA:
1879 case SIOCGIFMEDIA:
1880 error = ifmedia_ioctl(ifp, ifr, &sc->an_ifmedia, command);
1881 break;
1882 case SIOCADDMULTI:
1883 case SIOCDELMULTI:
1884 /* The Aironet has no multicast filter. */
1885 error = 0;
1886 break;
1887 case SIOCGAIRONET:
1888 error = copyin(ifr->ifr_data, &sc->areq, sizeof(sc->areq));
1889 if (error != 0)
1890 break;
1891#ifdef ANCACHE
1892 if (sc->areq.an_type == AN_RID_ZERO_CACHE) {
bd4539cc 1893 error = suser_cred(cr, NULL_CRED_OKAY);
984263bc
MD
1894 if (error)
1895 break;
1896 sc->an_sigitems = sc->an_nextitem = 0;
1897 break;
1898 } else if (sc->areq.an_type == AN_RID_READ_CACHE) {
1899 char *pt = (char *)&sc->areq.an_val;
1900 bcopy((char *)&sc->an_sigitems, (char *)pt,
1901 sizeof(int));
1902 pt += sizeof(int);
1903 sc->areq.an_len = sizeof(int) / 2;
1904 bcopy((char *)&sc->an_sigcache, (char *)pt,
1905 sizeof(struct an_sigcache) * sc->an_sigitems);
1906 sc->areq.an_len += ((sizeof(struct an_sigcache) *
1907 sc->an_sigitems) / 2) + 1;
1908 } else
1909#endif
1910 if (an_read_record(sc, (struct an_ltv_gen *)&sc->areq)) {
1911 error = EINVAL;
1912 break;
1913 }
1914 error = copyout(&sc->areq, ifr->ifr_data, sizeof(sc->areq));
1915 break;
1916 case SIOCSAIRONET:
bd4539cc 1917 if ((error = suser_cred(cr, NULL_CRED_OKAY)))
41d6c56f 1918 break;
984263bc
MD
1919 error = copyin(ifr->ifr_data, &sc->areq, sizeof(sc->areq));
1920 if (error != 0)
1921 break;
1922 an_setdef(sc, &sc->areq);
1923 break;
1924 case SIOCGPRIVATE_0: /* used by Cisco client utility */
bd4539cc 1925 if ((error = suser_cred(cr, NULL_CRED_OKAY)))
41d6c56f 1926 break;
984263bc
MD
1927 copyin(ifr->ifr_data, &l_ioctl, sizeof(l_ioctl));
1928 mode = l_ioctl.command;
1929
1930 if (mode >= AIROGCAP && mode <= AIROGSTATSD32) {
1931 error = readrids(ifp, &l_ioctl);
1932 } else if (mode >= AIROPCAP && mode <= AIROPLEAPUSR) {
1933 error = writerids(ifp, &l_ioctl);
1934 } else if (mode >= AIROFLSHRST && mode <= AIRORESTART) {
1935 error = flashcard(ifp, &l_ioctl);
1936 } else {
1937 error =-1;
1938 }
1939
1940 /* copy out the updated command info */
1941 copyout(&l_ioctl, ifr->ifr_data, sizeof(l_ioctl));
1942
1943 break;
1944 case SIOCGPRIVATE_1: /* used by Cisco client utility */
bd4539cc 1945 if ((error = suser_cred(cr, NULL_CRED_OKAY)))
41d6c56f 1946 break;
984263bc
MD
1947 copyin(ifr->ifr_data, &l_ioctl, sizeof(l_ioctl));
1948 l_ioctl.command = 0;
1949 error = AIROMAGIC;
1950 copyout(&error, l_ioctl.data, sizeof(error));
1951 error = 0;
1952 break;
1953 case SIOCG80211:
1954 sc->areq.an_len = sizeof(sc->areq);
1955 /* was that a good idea DJA we are doing a short-cut */
1956 switch (ireq->i_type) {
1957 case IEEE80211_IOC_SSID:
1958 if (ireq->i_val == -1) {
1959 sc->areq.an_type = AN_RID_STATUS;
1960 if (an_read_record(sc,
1961 (struct an_ltv_gen *)&sc->areq)) {
1962 error = EINVAL;
1963 break;
1964 }
1965 len = status->an_ssidlen;
1966 tmpptr = status->an_ssid;
1967 } else if (ireq->i_val >= 0) {
1968 sc->areq.an_type = AN_RID_SSIDLIST;
1969 if (an_read_record(sc,
1970 (struct an_ltv_gen *)&sc->areq)) {
1971 error = EINVAL;
1972 break;
1973 }
1974 if (ireq->i_val == 0) {
1975 len = ssids->an_ssid1_len;
1976 tmpptr = ssids->an_ssid1;
1977 } else if (ireq->i_val == 1) {
1978 len = ssids->an_ssid2_len;
1979 tmpptr = ssids->an_ssid2;
1980 } else if (ireq->i_val == 2) {
1981 len = ssids->an_ssid3_len;
1982 tmpptr = ssids->an_ssid3;
1983 } else {
1984 error = EINVAL;
1985 break;
1986 }
1987 } else {
1988 error = EINVAL;
1989 break;
1990 }
1991 if (len > IEEE80211_NWID_LEN) {
1992 error = EINVAL;
1993 break;
1994 }
1995 ireq->i_len = len;
1996 bzero(tmpstr, IEEE80211_NWID_LEN);
1997 bcopy(tmpptr, tmpstr, len);
1998 error = copyout(tmpstr, ireq->i_data,
1999 IEEE80211_NWID_LEN);
2000 break;
2001 case IEEE80211_IOC_NUMSSIDS:
2002 ireq->i_val = 3;
2003 break;
2004 case IEEE80211_IOC_WEP:
2005 sc->areq.an_type = AN_RID_ACTUALCFG;
2006 if (an_read_record(sc,
2007 (struct an_ltv_gen *)&sc->areq)) {
2008 error = EINVAL;
2009 break;
2010 }
2011 if (config->an_authtype & AN_AUTHTYPE_PRIVACY_IN_USE) {
2012 if (config->an_authtype &
2013 AN_AUTHTYPE_ALLOW_UNENCRYPTED)
2014 ireq->i_val = IEEE80211_WEP_MIXED;
2015 else
2016 ireq->i_val = IEEE80211_WEP_ON;
2017 } else {
2018 ireq->i_val = IEEE80211_WEP_OFF;
2019 }
2020 break;
2021 case IEEE80211_IOC_WEPKEY:
2022 /*
2023 * XXX: I'm not entierly convinced this is
2024 * correct, but it's what is implemented in
2025 * ancontrol so it will have to do until we get
2026 * access to actual Cisco code.
2027 */
2028 if (ireq->i_val < 0 || ireq->i_val > 8) {
2029 error = EINVAL;
2030 break;
2031 }
2032 len = 0;
2033 if (ireq->i_val < 5) {
2034 sc->areq.an_type = AN_RID_WEP_TEMP;
2035 for (i = 0; i < 5; i++) {
2036 if (an_read_record(sc,
2037 (struct an_ltv_gen *)&sc->areq)) {
2038 error = EINVAL;
2039 break;
2040 }
2041 if (key->kindex == 0xffff)
2042 break;
2043 if (key->kindex == ireq->i_val)
2044 len = key->klen;
2045 /* Required to get next entry */
2046 sc->areq.an_type = AN_RID_WEP_PERM;
2047 }
2048 if (error != 0)
2049 break;
2050 }
2051 /* We aren't allowed to read the value of the
2052 * key from the card so we just output zeros
2053 * like we would if we could read the card, but
2054 * denied the user access.
2055 */
2056 bzero(tmpstr, len);
2057 ireq->i_len = len;
2058 error = copyout(tmpstr, ireq->i_data, len);
2059 break;
2060 case IEEE80211_IOC_NUMWEPKEYS:
2061 ireq->i_val = 9; /* include home key */
2062 break;
2063 case IEEE80211_IOC_WEPTXKEY:
2064 /*
2065 * For some strange reason, you have to read all
2066 * keys before you can read the txkey.
2067 */
2068 sc->areq.an_type = AN_RID_WEP_TEMP;
2069 for (i = 0; i < 5; i++) {
2070 if (an_read_record(sc,
2071 (struct an_ltv_gen *) &sc->areq)) {
2072 error = EINVAL;
2073 break;
2074 }
2075 if (key->kindex == 0xffff)
2076 break;
2077 /* Required to get next entry */
2078 sc->areq.an_type = AN_RID_WEP_PERM;
2079 }
2080 if (error != 0)
2081 break;
2082
2083 sc->areq.an_type = AN_RID_WEP_PERM;
2084 key->kindex = 0xffff;
2085 if (an_read_record(sc,
2086 (struct an_ltv_gen *)&sc->areq)) {
2087 error = EINVAL;
2088 break;
2089 }
2090 ireq->i_val = key->mac[0];
2091 /*
2092 * Check for home mode. Map home mode into
2093 * 5th key since that is how it is stored on
2094 * the card
2095 */
2096 sc->areq.an_len = sizeof(struct an_ltv_genconfig);
2097 sc->areq.an_type = AN_RID_GENCONFIG;
2098 if (an_read_record(sc,
2099 (struct an_ltv_gen *)&sc->areq)) {
2100 error = EINVAL;
2101 break;
2102 }
2103 if (config->an_home_product & AN_HOME_NETWORK)
2104 ireq->i_val = 4;
2105 break;
2106 case IEEE80211_IOC_AUTHMODE:
2107 sc->areq.an_type = AN_RID_ACTUALCFG;
2108 if (an_read_record(sc,
2109 (struct an_ltv_gen *)&sc->areq)) {
2110 error = EINVAL;
2111 break;
2112 }
2113 if ((config->an_authtype & AN_AUTHTYPE_MASK) ==
2114 AN_AUTHTYPE_NONE) {
2115 ireq->i_val = IEEE80211_AUTH_NONE;
2116 } else if ((config->an_authtype & AN_AUTHTYPE_MASK) ==
2117 AN_AUTHTYPE_OPEN) {
2118 ireq->i_val = IEEE80211_AUTH_OPEN;
2119 } else if ((config->an_authtype & AN_AUTHTYPE_MASK) ==
2120 AN_AUTHTYPE_SHAREDKEY) {
2121 ireq->i_val = IEEE80211_AUTH_SHARED;
2122 } else
2123 error = EINVAL;
2124 break;
2125 case IEEE80211_IOC_STATIONNAME:
2126 sc->areq.an_type = AN_RID_ACTUALCFG;
2127 if (an_read_record(sc,
2128 (struct an_ltv_gen *)&sc->areq)) {
2129 error = EINVAL;
2130 break;
2131 }
2132 ireq->i_len = sizeof(config->an_nodename);
2133 tmpptr = config->an_nodename;
2134 bzero(tmpstr, IEEE80211_NWID_LEN);
2135 bcopy(tmpptr, tmpstr, ireq->i_len);
2136 error = copyout(tmpstr, ireq->i_data,
2137 IEEE80211_NWID_LEN);
2138 break;
2139 case IEEE80211_IOC_CHANNEL:
2140 sc->areq.an_type = AN_RID_STATUS;
2141 if (an_read_record(sc,
2142 (struct an_ltv_gen *)&sc->areq)) {
2143 error = EINVAL;
2144 break;
2145 }
2146 ireq->i_val = status->an_cur_channel;
2147 break;
2148 case IEEE80211_IOC_POWERSAVE:
2149 sc->areq.an_type = AN_RID_ACTUALCFG;
2150 if (an_read_record(sc,
2151 (struct an_ltv_gen *)&sc->areq)) {
2152 error = EINVAL;
2153 break;
2154 }
2155 if (config->an_psave_mode == AN_PSAVE_NONE) {
2156 ireq->i_val = IEEE80211_POWERSAVE_OFF;
2157 } else if (config->an_psave_mode == AN_PSAVE_CAM) {
2158 ireq->i_val = IEEE80211_POWERSAVE_CAM;
2159 } else if (config->an_psave_mode == AN_PSAVE_PSP) {
2160 ireq->i_val = IEEE80211_POWERSAVE_PSP;
2161 } else if (config->an_psave_mode == AN_PSAVE_PSP_CAM) {
2162 ireq->i_val = IEEE80211_POWERSAVE_PSP_CAM;
2163 } else
2164 error = EINVAL;
2165 break;
2166 case IEEE80211_IOC_POWERSAVESLEEP:
2167 sc->areq.an_type = AN_RID_ACTUALCFG;
2168 if (an_read_record(sc,
2169 (struct an_ltv_gen *)&sc->areq)) {
2170 error = EINVAL;
2171 break;
2172 }
2173 ireq->i_val = config->an_listen_interval;
2174 break;
2175 }
2176 break;
2177 case SIOCS80211:
bd4539cc 2178 if ((error = suser_cred(cr, NULL_CRED_OKAY)))
41d6c56f 2179 break;
984263bc
MD
2180 sc->areq.an_len = sizeof(sc->areq);
2181 /*
2182 * We need a config structure for everything but the WEP
2183 * key management and SSIDs so we get it now so avoid
2184 * duplicating this code every time.
2185 */
2186 if (ireq->i_type != IEEE80211_IOC_SSID &&
2187 ireq->i_type != IEEE80211_IOC_WEPKEY &&
2188 ireq->i_type != IEEE80211_IOC_WEPTXKEY) {
2189 sc->areq.an_type = AN_RID_GENCONFIG;
2190 if (an_read_record(sc,
2191 (struct an_ltv_gen *)&sc->areq)) {
2192 error = EINVAL;
2193 break;
2194 }
2195 }
2196 switch (ireq->i_type) {
2197 case IEEE80211_IOC_SSID:
2198 sc->areq.an_type = AN_RID_SSIDLIST;
2199 if (an_read_record(sc,
2200 (struct an_ltv_gen *)&sc->areq)) {
2201 error = EINVAL;
2202 break;
2203 }
2204 if (ireq->i_len > IEEE80211_NWID_LEN) {
2205 error = EINVAL;
2206 break;
2207 }
2208 switch (ireq->i_val) {
2209 case 0:
2210 error = copyin(ireq->i_data,
2211 ssids->an_ssid1, ireq->i_len);
2212 ssids->an_ssid1_len = ireq->i_len;
2213 break;
2214 case 1:
2215 error = copyin(ireq->i_data,
2216 ssids->an_ssid2, ireq->i_len);
2217 ssids->an_ssid2_len = ireq->i_len;
2218 break;
2219 case 2:
2220 error = copyin(ireq->i_data,
2221 ssids->an_ssid3, ireq->i_len);
2222 ssids->an_ssid3_len = ireq->i_len;
2223 break;
2224 default:
2225 error = EINVAL;
2226 break;
2227 }
2228 break;
2229 case IEEE80211_IOC_WEP:
2230 switch (ireq->i_val) {
2231 case IEEE80211_WEP_OFF:
2232 config->an_authtype &=
2233 ~(AN_AUTHTYPE_PRIVACY_IN_USE |
2234 AN_AUTHTYPE_ALLOW_UNENCRYPTED);
2235 break;
2236 case IEEE80211_WEP_ON:
2237 config->an_authtype |=
2238 AN_AUTHTYPE_PRIVACY_IN_USE;
2239 config->an_authtype &=
2240 ~AN_AUTHTYPE_ALLOW_UNENCRYPTED;
2241 break;
2242 case IEEE80211_WEP_MIXED:
2243 config->an_authtype |=
2244 AN_AUTHTYPE_PRIVACY_IN_USE |
2245 AN_AUTHTYPE_ALLOW_UNENCRYPTED;
2246 break;
2247 default:
2248 error = EINVAL;
2249 break;
2250 }
2251 break;
2252 case IEEE80211_IOC_WEPKEY:
2253 if (ireq->i_val < 0 || ireq->i_val > 8 ||
2254 ireq->i_len > 13) {
2255 error = EINVAL;
2256 break;
2257 }
2258 error = copyin(ireq->i_data, tmpstr, 13);
2259 if (error != 0)
2260 break;
2261 /*
2262 * Map the 9th key into the home mode
2263 * since that is how it is stored on
2264 * the card
2265 */
2266 bzero(&sc->areq, sizeof(struct an_ltv_key));
2267 sc->areq.an_len = sizeof(struct an_ltv_key);
2268 key->mac[0] = 1; /* The others are 0. */
2269 if (ireq->i_val < 4) {
2270 sc->areq.an_type = AN_RID_WEP_TEMP;
2271 key->kindex = ireq->i_val;
2272 } else {
2273 sc->areq.an_type = AN_RID_WEP_PERM;
2274 key->kindex = ireq->i_val - 4;
2275 }
2276 key->klen = ireq->i_len;
2277 bcopy(tmpstr, key->key, key->klen);
2278 break;
2279 case IEEE80211_IOC_WEPTXKEY:
2280 if (ireq->i_val < 0 || ireq->i_val > 4) {
2281 error = EINVAL;
2282 break;
2283 }
2284
2285 /*
2286 * Map the 5th key into the home mode
2287 * since that is how it is stored on
2288 * the card
2289 */
2290 sc->areq.an_len = sizeof(struct an_ltv_genconfig);
2291 sc->areq.an_type = AN_RID_ACTUALCFG;
2292 if (an_read_record(sc,
2293 (struct an_ltv_gen *)&sc->areq)) {
2294 error = EINVAL;
2295 break;
2296 }
2297 if (ireq->i_val == 4) {
2298 config->an_home_product |= AN_HOME_NETWORK;
2299 ireq->i_val = 0;
2300 } else {
2301 config->an_home_product &= ~AN_HOME_NETWORK;
2302 }
2303
2304 sc->an_config.an_home_product
2305 = config->an_home_product;
2306
2307 /* update configuration */
2308 an_init(sc);
2309
2310 bzero(&sc->areq, sizeof(struct an_ltv_key));
2311 sc->areq.an_len = sizeof(struct an_ltv_key);
2312 sc->areq.an_type = AN_RID_WEP_PERM;
2313 key->kindex = 0xffff;
2314 key->mac[0] = ireq->i_val;
2315 break;
2316 case IEEE80211_IOC_AUTHMODE:
2317 switch (ireq->i_val) {
2318 case IEEE80211_AUTH_NONE:
2319 config->an_authtype = AN_AUTHTYPE_NONE |
2320 (config->an_authtype & ~AN_AUTHTYPE_MASK);
2321 break;
2322 case IEEE80211_AUTH_OPEN:
2323 config->an_authtype = AN_AUTHTYPE_OPEN |
2324 (config->an_authtype & ~AN_AUTHTYPE_MASK);
2325 break;
2326 case IEEE80211_AUTH_SHARED:
2327 config->an_authtype = AN_AUTHTYPE_SHAREDKEY |
2328 (config->an_authtype & ~AN_AUTHTYPE_MASK);
2329 break;
2330 default:
2331 error = EINVAL;
2332 }
2333 break;
2334 case IEEE80211_IOC_STATIONNAME:
2335 if (ireq->i_len > 16) {
2336 error = EINVAL;
2337 break;
2338 }
2339 bzero(config->an_nodename, 16);
2340 error = copyin(ireq->i_data,
2341 config->an_nodename, ireq->i_len);
2342 break;
2343 case IEEE80211_IOC_CHANNEL:
2344 /*
2345 * The actual range is 1-14, but if you set it
2346 * to 0 you get the default so we let that work
2347 * too.
2348 */
2349 if (ireq->i_val < 0 || ireq->i_val >14) {
2350 error = EINVAL;
2351 break;
2352 }
2353 config->an_ds_channel = ireq->i_val;
2354 break;
2355 case IEEE80211_IOC_POWERSAVE:
2356 switch (ireq->i_val) {
2357 case IEEE80211_POWERSAVE_OFF:
2358 config->an_psave_mode = AN_PSAVE_NONE;
2359 break;
2360 case IEEE80211_POWERSAVE_CAM:
2361 config->an_psave_mode = AN_PSAVE_CAM;
2362 break;
2363 case IEEE80211_POWERSAVE_PSP:
2364 config->an_psave_mode = AN_PSAVE_PSP;
2365 break;
2366 case IEEE80211_POWERSAVE_PSP_CAM:
2367 config->an_psave_mode = AN_PSAVE_PSP_CAM;
2368 break;
2369 default:
2370 error = EINVAL;
2371 break;
2372 }
2373 break;
2374 case IEEE80211_IOC_POWERSAVESLEEP:
2375 config->an_listen_interval = ireq->i_val;
2376 break;
2377 }
2378
2379 if (!error)
2380 an_setdef(sc, &sc->areq);
2381 break;
2382 default:
4cde4dd5 2383 error = ether_ioctl(ifp, command, data);
984263bc
MD
2384 break;
2385 }
41d6c56f
JS
2386
2387 crit_exit();
984263bc
MD
2388
2389 return(error != 0);
2390}
2391
2392static int
2393an_init_tx_ring(sc)
2394 struct an_softc *sc;
2395{
2396 int i;
2397 int id;
2398
984263bc
MD
2399 if (!sc->mpi350) {
2400 for (i = 0; i < AN_TX_RING_CNT; i++) {
2401 if (an_alloc_nicmem(sc, 1518 +
2402 0x44, &id))
2403 return(ENOMEM);
2404 sc->an_rdata.an_tx_fids[i] = id;
2405 sc->an_rdata.an_tx_ring[i] = 0;
2406 }
2407 }
2408
2409 sc->an_rdata.an_tx_prod = 0;
2410 sc->an_rdata.an_tx_cons = 0;
2411 sc->an_rdata.an_tx_empty = 1;
2412
2413 return(0);
2414}
2415
2416static void
2417an_init(xsc)
2418 void *xsc;
2419{
2420 struct an_softc *sc = xsc;
2421 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 2422
41d6c56f 2423 crit_enter();
984263bc
MD
2424 if (ifp->if_flags & IFF_RUNNING)
2425 an_stop(sc);
2426
2427 sc->an_associated = 0;
2428
2429 /* Allocate the TX buffers */
2430 if (an_init_tx_ring(sc)) {
2431 an_reset(sc);
2432 if (sc->mpi350)
2433 an_init_mpi350_desc(sc);
2434 if (an_init_tx_ring(sc)) {
41d6c56f 2435 crit_exit();
1c70eebf 2436 if_printf(ifp, "tx buffer allocation failed\n");
984263bc
MD
2437 return;
2438 }
2439 }
2440
2441 /* Set our MAC address. */
2442 bcopy((char *)&sc->arpcom.ac_enaddr,
2443 (char *)&sc->an_config.an_macaddr, ETHER_ADDR_LEN);
2444
2445 if (ifp->if_flags & IFF_BROADCAST)
2446 sc->an_config.an_rxmode = AN_RXMODE_BC_ADDR;
2447 else
2448 sc->an_config.an_rxmode = AN_RXMODE_ADDR;
2449
2450 if (ifp->if_flags & IFF_MULTICAST)
2451 sc->an_config.an_rxmode = AN_RXMODE_BC_MC_ADDR;
2452
2453 if (ifp->if_flags & IFF_PROMISC) {
2454 if (sc->an_monitor & AN_MONITOR) {
2455 if (sc->an_monitor & AN_MONITOR_ANY_BSS) {
2456 sc->an_config.an_rxmode |=
2457 AN_RXMODE_80211_MONITOR_ANYBSS |
2458 AN_RXMODE_NO_8023_HEADER;
2459 } else {
2460 sc->an_config.an_rxmode |=
2461 AN_RXMODE_80211_MONITOR_CURBSS |
2462 AN_RXMODE_NO_8023_HEADER;
2463 }
2464 }
2465 }
2466
2467 if (sc->an_have_rssimap)
2468 sc->an_config.an_rxmode |= AN_RXMODE_NORMALIZED_RSSI;
2469
2470 /* Set the ssid list */
2471 sc->an_ssidlist.an_type = AN_RID_SSIDLIST;
2472 sc->an_ssidlist.an_len = sizeof(struct an_ltv_ssidlist);
2473 if (an_write_record(sc, (struct an_ltv_gen *)&sc->an_ssidlist)) {
41d6c56f 2474 crit_exit();
1c70eebf 2475 if_printf(ifp, "failed to set ssid list\n");
984263bc
MD
2476 return;
2477 }
2478
2479 /* Set the AP list */
2480 sc->an_aplist.an_type = AN_RID_APLIST;
2481 sc->an_aplist.an_len = sizeof(struct an_ltv_aplist);
2482 if (an_write_record(sc, (struct an_ltv_gen *)&sc->an_aplist)) {
41d6c56f 2483 crit_exit();
1c70eebf 2484 if_printf(ifp, "failed to set AP list\n");
984263bc
MD
2485 return;
2486 }
2487
2488 /* Set the configuration in the NIC */
2489 sc->an_config.an_len = sizeof(struct an_ltv_genconfig);
2490 sc->an_config.an_type = AN_RID_GENCONFIG;
2491 if (an_write_record(sc, (struct an_ltv_gen *)&sc->an_config)) {
41d6c56f 2492 crit_exit();
1c70eebf 2493 if_printf(ifp, "failed to set configuration\n");
984263bc
MD
2494 return;
2495 }
2496
2497 /* Enable the MAC */
2498 if (an_cmd(sc, AN_CMD_ENABLE, 0)) {
41d6c56f 2499 crit_exit();
1c70eebf 2500 if_printf(ifp, "failed to enable MAC\n");
984263bc
MD
2501 return;
2502 }
2503
2504 if (ifp->if_flags & IFF_PROMISC)
2505 an_cmd(sc, AN_CMD_SET_MODE, 0xffff);
2506
2507 /* enable interrupts */
2508 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), AN_INTRS);
2509
2510 ifp->if_flags |= IFF_RUNNING;
2511 ifp->if_flags &= ~IFF_OACTIVE;
2512
89c0f216 2513 callout_reset(&sc->an_stat_timer, hz, an_stats_update, sc);
984263bc 2514
41d6c56f 2515 crit_exit();
984263bc
MD
2516}
2517
2518static void
2519an_start(ifp)
2520 struct ifnet *ifp;
2521{
2522 struct an_softc *sc;
2523 struct mbuf *m0 = NULL;
2524 struct an_txframe_802_3 tx_frame_802_3;
2525 struct ether_header *eh;
2526 int id, idx, i;
2527 unsigned char txcontrol;
2528 struct an_card_tx_desc an_tx_desc;
2529 u_int8_t *ptr;
2530 u_int8_t *buf;
2531
2532 sc = ifp->if_softc;
2533
984263bc
MD
2534 if (ifp->if_flags & IFF_OACTIVE)
2535 return;
2536
2537 if (!sc->an_associated)
2538 return;
2539
2540 /* We can't send in monitor mode so toss any attempts. */
2541 if (sc->an_monitor && (ifp->if_flags & IFF_PROMISC)) {
38de8487 2542 ifq_purge(&ifp->if_snd);
984263bc
MD
2543 return;
2544 }
2545
2546 idx = sc->an_rdata.an_tx_prod;
2547
2548 if (!sc->mpi350) {
2549 bzero((char *)&tx_frame_802_3, sizeof(tx_frame_802_3));
2550
2551 while (sc->an_rdata.an_tx_ring[idx] == 0) {
38de8487 2552 m0 = ifq_dequeue(&ifp->if_snd);
984263bc
MD
2553 if (m0 == NULL)
2554 break;
2555
2556 id = sc->an_rdata.an_tx_fids[idx];
2557 eh = mtod(m0, struct ether_header *);
2558
2559 bcopy((char *)&eh->ether_dhost,
2560 (char *)&tx_frame_802_3.an_tx_dst_addr,
2561 ETHER_ADDR_LEN);
2562 bcopy((char *)&eh->ether_shost,
2563 (char *)&tx_frame_802_3.an_tx_src_addr,
2564 ETHER_ADDR_LEN);
2565
2566 /* minus src/dest mac & type */
2567 tx_frame_802_3.an_tx_802_3_payload_len =
2568 m0->m_pkthdr.len - 12;
2569
2570 m_copydata(m0, sizeof(struct ether_header) - 2 ,
2571 tx_frame_802_3.an_tx_802_3_payload_len,
2572 (caddr_t)&sc->an_txbuf);
2573
2574 txcontrol = AN_TXCTL_8023;
2575 /* write the txcontrol only */
2576 an_write_data(sc, id, 0x08, (caddr_t)&txcontrol,
2577 sizeof(txcontrol));
2578
2579 /* 802_3 header */
2580 an_write_data(sc, id, 0x34, (caddr_t)&tx_frame_802_3,
2581 sizeof(struct an_txframe_802_3));
2582
2583 /* in mbuf header type is just before payload */
2584 an_write_data(sc, id, 0x44, (caddr_t)&sc->an_txbuf,
2585 tx_frame_802_3.an_tx_802_3_payload_len);
2586
7600679e 2587 BPF_MTAP(ifp, m0);
984263bc
MD
2588
2589 m_freem(m0);
2590 m0 = NULL;
2591
2592 sc->an_rdata.an_tx_ring[idx] = id;
2593 if (an_cmd(sc, AN_CMD_TX, id))
1c70eebf 2594 if_printf(ifp, "xmit failed\n");
984263bc
MD
2595
2596 AN_INC(idx, AN_TX_RING_CNT);
2597 }
2598 } else { /* MPI-350 */
2599 while (sc->an_rdata.an_tx_empty ||
2600 idx != sc->an_rdata.an_tx_cons) {
38de8487 2601 m0 = ifq_dequeue(&ifp->if_snd);
984263bc
MD
2602 if (m0 == NULL) {
2603 break;
2604 }
2605 buf = sc->an_tx_buffer[idx].an_dma_vaddr;
2606
2607 eh = mtod(m0, struct ether_header *);
2608
2609 /* DJA optimize this to limit bcopy */
2610 bcopy((char *)&eh->ether_dhost,
2611 (char *)&tx_frame_802_3.an_tx_dst_addr,
2612 ETHER_ADDR_LEN);
2613 bcopy((char *)&eh->ether_shost,
2614 (char *)&tx_frame_802_3.an_tx_src_addr,
2615 ETHER_ADDR_LEN);
2616
2617 /* minus src/dest mac & type */
2618 tx_frame_802_3.an_tx_802_3_payload_len =
2619 m0->m_pkthdr.len - 12;
2620
2621 m_copydata(m0, sizeof(struct ether_header) - 2 ,
2622 tx_frame_802_3.an_tx_802_3_payload_len,
2623 (caddr_t)&sc->an_txbuf);
2624
2625 txcontrol = AN_TXCTL_8023;
2626 /* write the txcontrol only */
2627 bcopy((caddr_t)&txcontrol, &buf[0x08],
2628 sizeof(txcontrol));
2629
2630 /* 802_3 header */
2631 bcopy((caddr_t)&tx_frame_802_3, &buf[0x34],
2632 sizeof(struct an_txframe_802_3));
2633
2634 /* in mbuf header type is just before payload */
2635 bcopy((caddr_t)&sc->an_txbuf, &buf[0x44],
2636 tx_frame_802_3.an_tx_802_3_payload_len);
2637
2638
2639 bzero(&an_tx_desc, sizeof(an_tx_desc));
2640 an_tx_desc.an_offset = 0;
2641 an_tx_desc.an_eoc = 1;
2642 an_tx_desc.an_valid = 1;
2643 an_tx_desc.an_len = 0x44 +
2644 tx_frame_802_3.an_tx_802_3_payload_len;
2645 an_tx_desc.an_phys = sc->an_tx_buffer[idx].an_dma_paddr;
2646 ptr = (u_int8_t*)&an_tx_desc;
2647 for (i = 0; i < sizeof(an_tx_desc); i++) {
2648 CSR_MEM_AUX_WRITE_1(sc, AN_TX_DESC_OFFSET + i,
2649 ptr[i]);
2650 }
2651
7600679e 2652 BPF_MTAP(ifp, m0);
984263bc
MD
2653
2654 m_freem(m0);
2655 m0 = NULL;
2656
2657 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_ALLOC);
2658
2659 AN_INC(idx, AN_MAX_TX_DESC);
2660 sc->an_rdata.an_tx_empty = 0;
2661 }
2662 }
2663
2664 if (m0 != NULL)
2665 ifp->if_flags |= IFF_OACTIVE;
2666
2667 sc->an_rdata.an_tx_prod = idx;
2668
2669 /*
2670 * Set a timeout in case the chip goes out to lunch.
2671 */
2672 ifp->if_timer = 5;
2673
2674 return;
2675}
2676
2677void
2678an_stop(sc)
2679 struct an_softc *sc;
2680{
2681 struct ifnet *ifp;
2682 int i;
984263bc 2683
984263bc
MD
2684 ifp = &sc->arpcom.ac_if;
2685
41d6c56f
JS
2686 crit_enter();
2687
984263bc
MD
2688 an_cmd(sc, AN_CMD_FORCE_SYNCLOSS, 0);
2689 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
2690 an_cmd(sc, AN_CMD_DISABLE, 0);
2691
2692 for (i = 0; i < AN_TX_RING_CNT; i++)
2693 an_cmd(sc, AN_CMD_DEALLOC_MEM, sc->an_rdata.an_tx_fids[i]);
2694
89c0f216 2695 callout_stop(&sc->an_stat_timer);
984263bc
MD
2696
2697 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2698
2699 if (sc->an_flash_buffer) {
2700 free(sc->an_flash_buffer, M_DEVBUF);
2701 sc->an_flash_buffer = NULL;
2702 }
2703
41d6c56f 2704 crit_exit();
984263bc
MD
2705}
2706
2707static void
2708an_watchdog(ifp)
2709 struct ifnet *ifp;
2710{
2711 struct an_softc *sc;
984263bc
MD
2712
2713 sc = ifp->if_softc;
984263bc 2714
41d6c56f 2715 crit_enter();
984263bc
MD
2716 an_reset(sc);
2717 if (sc->mpi350)
2718 an_init_mpi350_desc(sc);
2719 an_init(sc);
2720
2721 ifp->if_oerrors++;
41d6c56f 2722 crit_exit();
984263bc 2723
41d6c56f 2724 if_printf(ifp, "device timeout\n");
984263bc
MD
2725}
2726
2727void
2728an_shutdown(dev)
2729 device_t dev;
2730{
2731 struct an_softc *sc;
2732
2733 sc = device_get_softc(dev);
2734 an_stop(sc);
2735
2736 return;
2737}
2738
2739void
2740an_resume(dev)
2741 device_t dev;
2742{
2743 struct an_softc *sc;
2744 struct ifnet *ifp;
2745 int i;
2746
2747 sc = device_get_softc(dev);
2748 ifp = &sc->arpcom.ac_if;
2749
2750 an_reset(sc);
2751 if (sc->mpi350)
2752 an_init_mpi350_desc(sc);
2753 an_init(sc);
2754
2755 /* Recovery temporary keys */
2756 for (i = 0; i < 4; i++) {
2757 sc->areq.an_type = AN_RID_WEP_TEMP;
2758 sc->areq.an_len = sizeof(struct an_ltv_key);
2759 bcopy(&sc->an_temp_keys[i],
2760 &sc->areq, sizeof(struct an_ltv_key));
2761 an_setdef(sc, &sc->areq);
2762 }
2763
2764 if (ifp->if_flags & IFF_UP)
2765 an_start(ifp);
2766
2767 return;
2768}
2769
2770#ifdef ANCACHE
2771/* Aironet signal strength cache code.
2772 * store signal/noise/quality on per MAC src basis in
2773 * a small fixed cache. The cache wraps if > MAX slots
2774 * used. The cache may be zeroed out to start over.
2775 * Two simple filters exist to reduce computation:
2776 * 1. ip only (literally 0x800, ETHERTYPE_IP) which may be used
2777 * to ignore some packets. It defaults to ip only.
2778 * it could be used to focus on broadcast, non-IP 802.11 beacons.
2779 * 2. multicast/broadcast only. This may be used to
2780 * ignore unicast packets and only cache signal strength
2781 * for multicast/broadcast packets (beacons); e.g., Mobile-IP
2782 * beacons and not unicast traffic.
2783 *
2784 * The cache stores (MAC src(index), IP src (major clue), signal,
2785 * quality, noise)
2786 *
2787 * No apologies for storing IP src here. It's easy and saves much
2788 * trouble elsewhere. The cache is assumed to be INET dependent,
2789 * although it need not be.
2790 *
2791 * Note: the Aironet only has a single byte of signal strength value
2792 * in the rx frame header, and it's not scaled to anything sensible.
2793 * This is kind of lame, but it's all we've got.
2794 */
2795
2796#ifdef documentation
2797
2798int an_sigitems; /* number of cached entries */
2799struct an_sigcache an_sigcache[MAXANCACHE]; /* array of cache entries */
2800int an_nextitem; /* index/# of entries */
2801
2802
2803#endif
2804
2805/* control variables for cache filtering. Basic idea is
2806 * to reduce cost (e.g., to only Mobile-IP agent beacons
2807 * which are broadcast or multicast). Still you might
2808 * want to measure signal strength anth unicast ping packets
2809 * on a pt. to pt. ant. setup.
2810 */
2811/* set true if you want to limit cache items to broadcast/mcast
2812 * only packets (not unicast). Useful for mobile-ip beacons which
2813 * are broadcast/multicast at network layer. Default is all packets
2814 * so ping/unicast anll work say anth pt. to pt. antennae setup.
2815 */
2816static int an_cache_mcastonly = 0;
2817SYSCTL_INT(_hw_an, OID_AUTO, an_cache_mcastonly, CTLFLAG_RW,
2818 &an_cache_mcastonly, 0, "");
2819
2820/* set true if you want to limit cache items to IP packets only
2821*/
2822static int an_cache_iponly = 1;
2823SYSCTL_INT(_hw_an, OID_AUTO, an_cache_iponly, CTLFLAG_RW,
2824 &an_cache_iponly, 0, "");
2825
2826/*
2827 * an_cache_store, per rx packet store signal
2828 * strength in MAC (src) indexed cache.
2829 */
2830static void
3013ac0e 2831an_cache_store (sc, m, rx_rssi, rx_quality)
984263bc 2832 struct an_softc *sc;
984263bc
MD
2833 struct mbuf *m;
2834 u_int8_t rx_rssi;
2835 u_int8_t rx_quality;
2836{
3013ac0e
JS
2837 struct ether_header *eh = mtod(m, struct ether_header *);
2838 struct ip *ip = NULL;
984263bc
MD
2839 int i;
2840 static int cache_slot = 0; /* use this cache entry */
2841 static int wrapindex = 0; /* next "free" cache entry */
984263bc
MD
2842
2843 /* filters:
2844 * 1. ip only
2845 * 2. configurable filter to throw out unicast packets,
2846 * keep multicast only.
2847 */
2848
3013ac0e
JS
2849 if ((ntohs(eh->ether_type) == ETHERTYPE_IP))
2850 ip = (struct ip *)(mtod(m, uint8_t *) + ETHER_HDR_LEN);
2851 else if (an_cache_iponly)
984263bc 2852 return;
984263bc
MD
2853
2854 /* filter for broadcast/multicast only
2855 */
2856 if (an_cache_mcastonly && ((eh->ether_dhost[0] & 1) == 0)) {
2857 return;
2858 }
2859
2860#ifdef SIGDEBUG
1c70eebf
JS
2861 if_printf(&sc->arpcom.ac_if, "q value %x (MSB=0x%x, LSB=0x%x)\n",
2862 rx_rssi & 0xffff, rx_rssi >> 8, rx_rssi & 0xff);
984263bc
MD
2863#endif
2864
984263bc
MD
2865 /* do a linear search for a matching MAC address
2866 * in the cache table
2867 * . MAC address is 6 bytes,
2868 * . var w_nextitem holds total number of entries already cached
2869 */
2870 for (i = 0; i < sc->an_nextitem; i++) {
2871 if (! bcmp(eh->ether_shost , sc->an_sigcache[i].macsrc, 6 )) {
2872 /* Match!,
2873 * so we already have this entry,
2874 * update the data
2875 */
2876 break;
2877 }
2878 }
2879
2880 /* did we find a matching mac address?
2881 * if yes, then overwrite a previously existing cache entry
2882 */
2883 if (i < sc->an_nextitem ) {
2884 cache_slot = i;
2885 }
2886 /* else, have a new address entry,so
2887 * add this new entry,
2888 * if table full, then we need to replace LRU entry
2889 */
2890 else {
2891
2892 /* check for space in cache table
2893 * note: an_nextitem also holds number of entries
2894 * added in the cache table
2895 */
2896 if ( sc->an_nextitem < MAXANCACHE ) {
2897 cache_slot = sc->an_nextitem;
2898 sc->an_nextitem++;
2899 sc->an_sigitems = sc->an_nextitem;
2900 }
2901 /* no space found, so simply wrap anth wrap index
2902 * and "zap" the next entry
2903 */
2904 else {
2905 if (wrapindex == MAXANCACHE) {
2906 wrapindex = 0;
2907 }
2908 cache_slot = wrapindex++;
2909 }
2910 }
2911
2912 /* invariant: cache_slot now points at some slot
2913 * in cache.
2914 */
2915 if (cache_slot < 0 || cache_slot >= MAXANCACHE) {
2916 log(LOG_ERR, "an_cache_store, bad index: %d of "
2917 "[0..%d], gross cache error\n",
2918 cache_slot, MAXANCACHE);
2919 return;
2920 }
2921
2922 /* store items in cache
2923 * .ip source address
2924 * .mac src
2925 * .signal, etc.
2926 */
3013ac0e 2927 if (ip != NULL) {
984263bc
MD
2928 sc->an_sigcache[cache_slot].ipsrc = ip->ip_src.s_addr;
2929 }
2930 bcopy( eh->ether_shost, sc->an_sigcache[cache_slot].macsrc, 6);
2931
2932
2933 switch (an_cache_mode) {
2934 case DBM:
2935 if (sc->an_have_rssimap) {
2936 sc->an_sigcache[cache_slot].signal =
2937 - sc->an_rssimap.an_entries[rx_rssi].an_rss_dbm;
2938 sc->an_sigcache[cache_slot].quality =
2939 - sc->an_rssimap.an_entries[rx_quality].an_rss_dbm;
2940 } else {
2941 sc->an_sigcache[cache_slot].signal = rx_rssi - 100;
2942 sc->an_sigcache[cache_slot].quality = rx_quality - 100;
2943 }
2944 break;
2945 case PERCENT:
2946 if (sc->an_have_rssimap) {
2947 sc->an_sigcache[cache_slot].signal =
2948 sc->an_rssimap.an_entries[rx_rssi].an_rss_pct;
2949 sc->an_sigcache[cache_slot].quality =
2950 sc->an_rssimap.an_entries[rx_quality].an_rss_pct;
2951 } else {
2952 if (rx_rssi > 100)
2953 rx_rssi = 100;
2954 if (rx_quality > 100)
2955 rx_quality = 100;
2956 sc->an_sigcache[cache_slot].signal = rx_rssi;
2957 sc->an_sigcache[cache_slot].quality = rx_quality;
2958 }
2959 break;
2960 case RAW:
2961 sc->an_sigcache[cache_slot].signal = rx_rssi;
2962 sc->an_sigcache[cache_slot].quality = rx_quality;
2963 break;
2964 }
2965
2966 sc->an_sigcache[cache_slot].noise = 0;
2967
2968 return;
2969}
2970#endif
2971
2972static int
2973an_media_change(ifp)
2974 struct ifnet *ifp;
2975{
2976 struct an_softc *sc = ifp->if_softc;
2977 struct an_ltv_genconfig *cfg;
2978 int otype = sc->an_config.an_opmode;
2979 int orate = sc->an_tx_rate;
2980
2981 if ((sc->an_ifmedia.ifm_cur->ifm_media & IFM_IEEE80211_ADHOC) != 0)
2982 sc->an_config.an_opmode = AN_OPMODE_IBSS_ADHOC;
2983 else
2984 sc->an_config.an_opmode = AN_OPMODE_INFRASTRUCTURE_STATION;
2985
2986 switch (IFM_SUBTYPE(sc->an_ifmedia.ifm_cur->ifm_media)) {
2987 case IFM_IEEE80211_DS1:
2988 sc->an_tx_rate = AN_RATE_1MBPS;
2989 break;
2990 case IFM_IEEE80211_DS2:
2991 sc->an_tx_rate = AN_RATE_2MBPS;
2992 break;
2993 case IFM_IEEE80211_DS5:
2994 sc->an_tx_rate = AN_RATE_5_5MBPS;
2995 break;
2996 case IFM_IEEE80211_DS11:
2997 sc->an_tx_rate = AN_RATE_11MBPS;
2998 break;
2999 case IFM_AUTO:
3000 sc->an_tx_rate = 0;
3001 break;
3002 }
3003
3004 if (orate != sc->an_tx_rate) {
3005 /* Read the current configuration */
3006 sc->an_config.an_type = AN_RID_GENCONFIG;
3007 sc->an_config.an_len = sizeof(struct an_ltv_genconfig);
3008 an_read_record(sc, (struct an_ltv_gen *)&sc->an_config);
3009 cfg = &sc->an_config;
3010
3011 /* clear other rates and set the only one we want */
3012 bzero(cfg->an_rates, sizeof(cfg->an_rates));
3013 cfg->an_rates[0] = sc->an_tx_rate;
3014
3015 /* Save the new rate */
3016 sc->an_config.an_type = AN_RID_GENCONFIG;
3017 sc->an_config.an_len = sizeof(struct an_ltv_genconfig);
3018 }
3019
3020 if (otype != sc->an_config.an_opmode ||
3021 orate != sc->an_tx_rate)
3022 an_init(sc);
3023
3024 return(0);
3025}
3026
3027static void
3028an_media_status(ifp, imr)
3029 struct ifnet *ifp;
3030 struct ifmediareq *imr;
3031{
3032 struct an_ltv_status status;
3033 struct an_softc *sc = ifp->if_softc;
3034
3035 status.an_len = sizeof(status);
3036 status.an_type = AN_RID_STATUS;
3037 if (an_read_record(sc, (struct an_ltv_gen *)&status)) {
3038 /* If the status read fails, just lie. */
3039 imr->ifm_active = sc->an_ifmedia.ifm_cur->ifm_media;
3040 imr->ifm_status = IFM_AVALID|IFM_ACTIVE;
3041 }
3042
3043 if (sc->an_tx_rate == 0) {
3044 imr->ifm_active = IFM_IEEE80211|IFM_AUTO;
3045 if (sc->an_config.an_opmode == AN_OPMODE_IBSS_ADHOC)
3046 imr->ifm_active |= IFM_IEEE80211_ADHOC;
3047 switch (status.an_current_tx_rate) {
3048 case AN_RATE_1MBPS:
3049 imr->ifm_active |= IFM_IEEE80211_DS1;
3050 break;
3051 case AN_RATE_2MBPS:
3052 imr->ifm_active |= IFM_IEEE80211_DS2;
3053 break;
3054 case AN_RATE_5_5MBPS:
3055 imr->ifm_active |= IFM_IEEE80211_DS5;
3056 break;
3057 case AN_RATE_11MBPS:
3058 imr->ifm_active |= IFM_IEEE80211_DS11;
3059 break;
3060 }
3061 } else {
3062 imr->ifm_active = sc->an_ifmedia.ifm_cur->ifm_media;
3063 }
3064
3065 imr->ifm_status = IFM_AVALID;
3066 if (status.an_opmode & AN_STATUS_OPMODE_ASSOCIATED)
3067 imr->ifm_status |= IFM_ACTIVE;
3068}
3069
3070/********************** Cisco utility support routines *************/
3071
3072/*
3073 * ReadRids & WriteRids derived from Cisco driver additions to Ben Reed's
3074 * Linux driver
3075 */
3076
3077static int
3078readrids(ifp, l_ioctl)
3079 struct ifnet *ifp;
3080 struct aironet_ioctl *l_ioctl;
3081{
3082 unsigned short rid;
3083 struct an_softc *sc;
3084
3085 switch (l_ioctl->command) {
3086 case AIROGCAP:
3087 rid = AN_RID_CAPABILITIES;
3088 break;
3089 case AIROGCFG:
3090 rid = AN_RID_GENCONFIG;
3091 break;
3092 case AIROGSLIST:
3093 rid = AN_RID_SSIDLIST;
3094 break;
3095 case AIROGVLIST:
3096 rid = AN_RID_APLIST;
3097 break;
3098 case AIROGDRVNAM:
3099 rid = AN_RID_DRVNAME;
3100 break;
3101 case AIROGEHTENC:
3102 rid = AN_RID_ENCAPPROTO;
3103 break;
3104 case AIROGWEPKTMP:
3105 rid = AN_RID_WEP_TEMP;
3106 break;
3107 case AIROGWEPKNV:
3108 rid = AN_RID_WEP_PERM;
3109 break;
3110 case AIROGSTAT:
3111 rid = AN_RID_STATUS;
3112 break;
3113 case AIROGSTATSD32:
3114 rid = AN_RID_32BITS_DELTA;
3115 break;
3116 case AIROGSTATSC32:
3117 rid = AN_RID_32BITS_CUM;
3118 break;
3119 default:
3120 rid = 999;
3121 break;
3122 }
3123
3124 if (rid == 999) /* Is bad command */
3125 return -EINVAL;
3126
3127 sc = ifp->if_softc;
3128 sc->areq.an_len = AN_MAX_DATALEN;
3129 sc->areq.an_type = rid;
3130
3131 an_read_record(sc, (struct an_ltv_gen *)&sc->areq);
3132
3133 l_ioctl->len = sc->areq.an_len - 4; /* just data */
3134
3135 /* the data contains the length at first */
3136 if (copyout(&(sc->areq.an_len), l_ioctl->data,
3137 sizeof(sc->areq.an_len))) {
3138 return -EFAULT;
3139 }
3140 /* Just copy the data back */
3141 if (copyout(&(sc->areq.an_val), l_ioctl->data + 2,
3142 l_ioctl->len)) {
3143 return -EFAULT;
3144 }
3145 return 0;
3146}
3147
3148static int
3149writerids(ifp, l_ioctl)
3150 struct ifnet *ifp;
3151 struct aironet_ioctl *l_ioctl;
3152{
3153 struct an_softc *sc;
3154 int rid, command;
3155
3156 sc = ifp->if_softc;
3157 rid = 0;
3158 command = l_ioctl->command;
3159
3160 switch (command) {
3161 case AIROPSIDS:
3162 rid = AN_RID_SSIDLIST;
3163 break;
3164 case AIROPCAP:
3165 rid = AN_RID_CAPABILITIES;
3166 break;
3167 case AIROPAPLIST:
3168 rid = AN_RID_APLIST;
3169 break;
3170 case AIROPCFG:
3171 rid = AN_RID_GENCONFIG;
3172 break;
3173 case AIROPMACON:
3174 an_cmd(sc, AN_CMD_ENABLE, 0);
3175 return 0;
3176 break;
3177 case AIROPMACOFF:
3178 an_cmd(sc, AN_CMD_DISABLE, 0);
3179 return 0;
3180 break;
3181 case AIROPSTCLR:
3182 /*
3183 * This command merely clears the counts does not actually
3184 * store any data only reads rid. But as it changes the cards
3185 * state, I put it in the writerid routines.
3186 */
3187
3188 rid = AN_RID_32BITS_DELTACLR;
3189 sc = ifp->if_softc;
3190 sc->areq.an_len = AN_MAX_DATALEN;
3191 sc->areq.an_type = rid;
3192
3193 an_read_record(sc, (struct an_ltv_gen *)&sc->areq);
3194 l_ioctl->len = sc->areq.an_len - 4; /* just data */
3195
3196 /* the data contains the length at first */
3197 if (copyout(&(sc->areq.an_len), l_ioctl->data,
3198 sizeof(sc->areq.an_len))) {
3199 return -EFAULT;
3200 }
3201 /* Just copy the data */
3202 if (copyout(&(sc->areq.an_val), l_ioctl->data + 2,
3203 l_ioctl->len)) {
3204 return -EFAULT;
3205 }
3206 return 0;
3207 break;
3208 case AIROPWEPKEY:
3209 rid = AN_RID_WEP_TEMP;
3210 break;
3211 case AIROPWEPKEYNV:
3212 rid = AN_RID_WEP_PERM;
3213 break;
3214 case AIROPLEAPUSR:
3215 rid = AN_RID_LEAPUSERNAME;
3216 break;
3217 case AIROPLEAPPWD:
3218 rid = AN_RID_LEAPPASSWORD;
3219 break;
3220 default:
3221 return -EOPNOTSUPP;
3222 }
3223
3224 if (rid) {
3225 if (l_ioctl->len > sizeof(sc->areq.an_val) + 4)
3226 return -EINVAL;
3227 sc->areq.an_len = l_ioctl->len + 4; /* add type & length */
3228 sc->areq.an_type = rid;
3229
3230 /* Just copy the data back */
3231 copyin((l_ioctl->data) + 2, &sc->areq.an_val,
3232 l_ioctl->len);
3233
3234 an_cmd(sc, AN_CMD_DISABLE, 0);
3235 an_write_record(sc, (struct an_ltv_gen *)&sc->areq);
3236 an_cmd(sc, AN_CMD_ENABLE, 0);
3237 return 0;
3238 }
3239 return -EOPNOTSUPP;
3240}
3241
3242/*
3243 * General Flash utilities derived from Cisco driver additions to Ben Reed's
3244 * Linux driver
3245 */
3246
377d4740 3247#define FLASH_DELAY(x) tsleep(ifp, 0, "flash", ((x) / hz) + 1);
984263bc
MD
3248#define FLASH_COMMAND 0x7e7e
3249#define FLASH_SIZE 32 * 1024
3250
3251static int
3252unstickbusy(ifp)
3253 struct ifnet *ifp;
3254{
3255 struct an_softc *sc = ifp->if_softc;
3256
3257 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY) {
3258 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350),
3259 AN_EV_CLR_STUCK_BUSY);
3260 return 1;
3261 }
3262 return 0;
3263}
3264
3265/*
3266 * Wait for busy completion from card wait for delay uSec's Return true for
3267 * success meaning command reg is clear
3268 */
3269
3270static int
3271WaitBusy(ifp, uSec)
3272 struct ifnet *ifp;
3273 int uSec;
3274{
3275 int statword = 0xffff;
3276 int delay = 0;
3277 struct an_softc *sc = ifp->if_softc;
3278
3279 while ((statword & AN_CMD_BUSY) && delay <= (1000 * 100)) {
3280 FLASH_DELAY(10);
3281 delay += 10;
3282 statword = CSR_READ_2(sc, AN_COMMAND(sc->mpi350));
3283
3284 if ((AN_CMD_BUSY & statword) && (delay % 200)) {
3285 unstickbusy(ifp);
3286 }
3287 }
3288
3289 return 0 == (AN_CMD_BUSY & statword);
3290}
3291
3292/*
3293 * STEP 1) Disable MAC and do soft reset on card.
3294 */
3295
3296static int
3297cmdreset(ifp)
3298 struct ifnet *ifp;
3299{
3300 int status;
3301 struct an_softc *sc = ifp->if_softc;
3302
3303 an_stop(sc);
3304
3305 an_cmd(sc, AN_CMD_DISABLE, 0);
3306
3307 if (!(status = WaitBusy(ifp, AN_TIMEOUT))) {
1c70eebf 3308 if_printf(ifp, "Waitbusy hang b4 RESET =%d\n", status);
984263bc
MD
3309 return -EBUSY;
3310 }
3311 CSR_WRITE_2(sc, AN_COMMAND(sc->mpi350), AN_CMD_FW_RESTART);
3312
3313 FLASH_DELAY(1000); /* WAS 600 12/7/00 */
3314
3315
3316 if (!(status = WaitBusy(ifp, 100))) {
1c70eebf 3317 if_printf(ifp, "Waitbusy hang AFTER RESET =%d\n", status);
984263bc
MD
3318 return -EBUSY;
3319 }
3320 return 0;
3321}
3322
3323/*
3324 * STEP 2) Put the card in legendary flash mode
3325 */
3326
3327static int
3328setflashmode(ifp)
3329 struct ifnet *ifp;
3330{
3331 int status;
3332 struct an_softc *sc = ifp->if_softc;
3333
3334 CSR_WRITE_2(sc, AN_SW0(sc->mpi350), FLASH_COMMAND);
3335 CSR_WRITE_2(sc, AN_SW1(sc->mpi350), FLASH_COMMAND);
3336 CSR_WRITE_2(sc, AN_SW0(sc->mpi350), FLASH_COMMAND);
3337 CSR_WRITE_2(sc, AN_COMMAND(sc->mpi350), FLASH_COMMAND);
3338
3339 /*
3340 * mdelay(500); // 500ms delay
3341 */
3342
3343 FLASH_DELAY(500);
3344
3345 if (!(status = WaitBusy(ifp, AN_TIMEOUT))) {
3346 printf("Waitbusy hang after setflash mode\n");
3347 return -EIO;
3348 }
3349 return 0;
3350}
3351
3352/*
3353 * Get a character from the card matching matchbyte Step 3)
3354 */
3355
3356static int
3357flashgchar(ifp, matchbyte, dwelltime)
3358 struct ifnet *ifp;
3359 int matchbyte;
3360 int dwelltime;
3361{
3362 int rchar;
3363 unsigned char rbyte = 0;
3364 int success = -1;
3365 struct an_softc *sc = ifp->if_softc;
3366
3367
3368 do {
3369 rchar = CSR_READ_2(sc, AN_SW1(sc->mpi350));
3370
3371 if (dwelltime && !(0x8000 & rchar)) {
3372 dwelltime -= 10;
3373 FLASH_DELAY(10);
3374 continue;
3375 }
3376 rbyte = 0xff & rchar;
3377
3378 if ((rbyte == matchbyte) && (0x8000 & rchar)) {
3379 CSR_WRITE_2(sc, AN_SW1(sc->mpi350), 0);
3380 success = 1;
3381 break;
3382 }
3383 if (rbyte == 0x81 || rbyte == 0x82 || rbyte == 0x83 || rbyte == 0x1a || 0xffff == rchar)
3384 break;
3385 CSR_WRITE_2(sc, AN_SW1(sc->mpi350), 0);
3386
3387 } while (dwelltime > 0);
3388 return success;
3389}
3390
3391/*
3392 * Put character to SWS0 wait for dwelltime x 50us for echo .
3393 */
3394
3395static int
3396flashpchar(ifp, byte, dwelltime)
3397 struct ifnet *ifp;
3398 int byte;
3399 int dwelltime;
3400{
3401 int echo;
3402 int pollbusy, waittime;
3403 struct an_softc *sc = ifp->if_softc;
3404
3405 byte |= 0x8000;
3406
3407 if (dwelltime == 0)
3408 dwelltime = 200;
3409
3410 waittime = dwelltime;
3411
3412 /*
3413 * Wait for busy bit d15 to go false indicating buffer empty
3414 */
3415 do {
3416 pollbusy = CSR_READ_2(sc, AN_SW0(sc->mpi350));
3417
3418 if (pollbusy & 0x8000) {
3419 FLASH_DELAY(50);
3420 waittime -= 50;
3421 continue;
3422 } else
3423 break;
3424 }
3425 while (waittime >= 0);
3426
3427 /* timeout for busy clear wait */
3428
3429 if (waittime <= 0) {
1c70eebf 3430 if_printf(ifp, "flash putchar busywait timeout!\n");
984263bc
MD
3431 return -1;
3432 }
3433 /*
3434 * Port is clear now write byte and wait for it to echo back
3435 */
3436 do {
3437 CSR_WRITE_2(sc, AN_SW0(sc->mpi350), byte);
3438 FLASH_DELAY(50);
3439 dwelltime -= 50;
3440 echo = CSR_READ_2(sc, AN_SW1(sc->mpi350));
3441 } while (dwelltime >= 0 && echo != byte);
3442
3443
3444 CSR_WRITE_2(sc, AN_SW1(sc->mpi350), 0);
3445
3446 return echo == byte;
3447}
3448
3449/*
3450 * Transfer 32k of firmware data from user buffer to our buffer and send to
3451 * the card
3452 */
3453
3454static int
3455flashputbuf(ifp)
3456 struct ifnet *ifp;
3457{
3458 unsigned short *bufp;
3459 int nwords;
3460 struct an_softc *sc = ifp->if_softc;
3461
3462 /* Write stuff */
3463
3464 bufp = sc->an_flash_buffer;
3465
3466 if (!sc->mpi350) {
3467 CSR_WRITE_2(sc, AN_AUX_PAGE, 0x100);
3468 CSR_WRITE_2(sc, AN_AUX_OFFSET, 0);
3469
3470 for (nwords = 0; nwords != FLASH_SIZE / 2; nwords++) {
3471 CSR_WRITE_2(sc, AN_AUX_DATA, bufp[nwords] & 0xffff);
3472 }
3473 } else {
3474 for (nwords = 0; nwords != FLASH_SIZE / 4; nwords++) {
3475 CSR_MEM_AUX_WRITE_4(sc, 0x8000,
3476 ((u_int32_t *)bufp)[nwords] & 0xffff);
3477 }
3478 }
3479
3480 CSR_WRITE_2(sc, AN_SW0(sc->mpi350), 0x8000);
3481
3482 return 0;
3483}
3484
3485/*
3486 * After flashing restart the card.
3487 */
3488
3489static int
3490flashrestart(ifp)
3491 struct ifnet *ifp;
3492{
3493 int status = 0;
3494 struct an_softc *sc = ifp->if_softc;
3495
3496 FLASH_DELAY(1024); /* Added 12/7/00 */
3497
3498 an_init(sc);
3499
3500 FLASH_DELAY(1024); /* Added 12/7/00 */
3501 return status;
3502}
3503
3504/*
3505 * Entry point for flash ioclt.
3506 */
3507
3508static int
3509flashcard(ifp, l_ioctl)
3510 struct ifnet *ifp;
3511 struct aironet_ioctl *l_ioctl;
3512{
3513 int z = 0, status;
3514 struct an_softc *sc;
3515
3516 sc = ifp->if_softc;
3517 if (sc->mpi350) {
1c70eebf 3518 if_printf(ifp, "flashing not supported on MPI 350 yet\n");
984263bc
MD
3519 return(-1);
3520 }
3521 status = l_ioctl->command;
3522
3523 switch (l_ioctl->command) {
3524 case AIROFLSHRST:
3525 return cmdreset(ifp);
3526 break;
3527 case AIROFLSHSTFL:
3528 if (sc->an_flash_buffer) {
3529 free(sc->an_flash_buffer, M_DEVBUF);
3530 sc->an_flash_buffer = NULL;
3531 }
3532 sc->an_flash_buffer = malloc(FLASH_SIZE, M_DEVBUF, 0);
3533 if (sc->an_flash_buffer)
3534 return setflashmode(ifp);
3535 else
3536 return ENOBUFS;
3537 break;
3538 case AIROFLSHGCHR: /* Get char from aux */
3539 copyin(l_ioctl->data, &sc->areq, l_ioctl->len);
3540 z = *(int *)&sc->areq;
3541 if ((status = flashgchar(ifp, z, 8000)) == 1)
3542 return 0;
3543 else
3544 return -1;
3545 break;
3546 case AIROFLSHPCHR: /* Send char to card. */
3547 copyin(l_ioctl->data, &sc->areq, l_ioctl->len);
3548 z = *(int *)&sc->areq;
3549 if ((status = flashpchar(ifp, z, 8000)) == -1)
3550 return -EIO;
3551 else
3552 return 0;
3553 break;
3554 case AIROFLPUTBUF: /* Send 32k to card */
3555 if (l_ioctl->len > FLASH_SIZE) {
1c70eebf
JS
3556 if_printf(ifp, "Buffer to big, %x %x\n",
3557 l_ioctl->len, FLASH_SIZE);
984263bc
MD
3558 return -EINVAL;
3559 }
3560 copyin(l_ioctl->data, sc->an_flash_buffer, l_ioctl->len);
3561
3562 if ((status = flashputbuf(ifp)) != 0)
3563 return -EIO;
3564 else
3565 return 0;
3566 break;
3567 case AIRORESTART:
3568 if ((status = flashrestart(ifp)) != 0) {
1c70eebf 3569 if_printf(ifp, "FLASHRESTART returned %d\n", status);
984263bc
MD
3570 return -EIO;
3571 } else
3572 return 0;
3573
3574 break;
3575 default:
3576 return -EINVAL;
3577 }
3578
3579 return -EINVAL;
3580}