proc->thread stage 3.5: Add an IO_CORE flag so coda doesn't have to dig
[dragonfly.git] / sys / dev / serial / sio / sio.c
CommitLineData
984263bc
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/isa/sio.c,v 1.291.2.35 2003/05/18 08:51:15 murray Exp $
41c20dac 34 * $DragonFly: src/sys/dev/serial/sio/sio.c,v 1.3 2003/06/23 17:55:40 dillon Exp $
984263bc
MD
35 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
36 * from: i386/isa sio.c,v 1.234
37 */
38
39#include "opt_comconsole.h"
40#include "opt_compat.h"
41#include "opt_ddb.h"
42#include "opt_sio.h"
43#include "card.h"
44#include "pci.h"
45#ifdef __i386__
46#include "puc.h"
47#endif
48#include "sio.h"
49
50/*
51 * Serial driver, based on 386BSD-0.1 com driver.
52 * Mostly rewritten to use pseudo-DMA.
53 * Works for National Semiconductor NS8250-NS16550AF UARTs.
54 * COM driver, based on HP dca driver.
55 *
56 * Changes for PC-Card integration:
57 * - Added PC-Card driver table and handlers
58 */
59#include <sys/param.h>
60#include <sys/systm.h>
61#include <sys/reboot.h>
62#include <sys/malloc.h>
63#include <sys/tty.h>
64#include <sys/proc.h>
65#include <sys/module.h>
66#include <sys/conf.h>
67#include <sys/dkstat.h>
68#include <sys/fcntl.h>
69#include <sys/interrupt.h>
70#include <sys/kernel.h>
71#include <sys/syslog.h>
72#include <sys/sysctl.h>
73#include <sys/bus.h>
74#include <machine/bus_pio.h>
75#include <machine/bus.h>
76#include <sys/rman.h>
77#include <sys/timepps.h>
78
79#include <machine/limits.h>
80
81#include <isa/isareg.h>
82#include <isa/isavar.h>
83#if NPCI > 0
84#include <pci/pcireg.h>
85#include <pci/pcivar.h>
86#endif
87#if NPUC > 0
88#include <dev/puc/pucvar.h>
89#endif
90#include <machine/lock.h>
91
92#include <machine/clock.h>
93#include <machine/ipl.h>
94#ifndef SMP
95#include <machine/lock.h>
96#endif
97#include <machine/resource.h>
98
99#include <isa/sioreg.h>
100
101#ifdef COM_ESP
102#include <dev/ic/esp.h>
103#endif
104#include <dev/ic/ns16550.h>
105
106#ifndef __i386__
107#define disable_intr()
108#define enable_intr()
109#endif
110
111#ifdef SMP
112#define disable_intr() COM_DISABLE_INTR()
113#define enable_intr() COM_ENABLE_INTR()
114#endif /* SMP */
115
116#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
117
118#define CALLOUT_MASK 0x80
119#define CONTROL_MASK 0x60
120#define CONTROL_INIT_STATE 0x20
121#define CONTROL_LOCK_STATE 0x40
122#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
123#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \
124 | ((mynor) & 0x1f))
125#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \
126 | ((unit) & 0x1f))
127
128#ifdef COM_MULTIPORT
129/* checks in flags for multiport and which is multiport "master chip"
130 * for a given card
131 */
132#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
133#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
134#define COM_NOTAST4(flags) ((flags) & 0x04)
135#endif /* COM_MULTIPORT */
136
137#define COM_CONSOLE(flags) ((flags) & 0x10)
138#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
139#define COM_LLCONSOLE(flags) ((flags) & 0x40)
140#define COM_DEBUGGER(flags) ((flags) & 0x80)
141#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
142#define COM_NOFIFO(flags) ((flags) & 0x02)
143#define COM_ST16650A(flags) ((flags) & 0x20000)
144#define COM_C_NOPROBE (0x40000)
145#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
146#define COM_C_IIR_TXRDYBUG (0x80000)
147#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
148#define COM_TI16754(flags) ((flags) & 0x200000)
149#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
150
151#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
152
153#define sio_getreg(com, off) \
154 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
155#define sio_setreg(com, off, value) \
156 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
157
158/*
159 * com state bits.
160 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
161 * than the other bits so that they can be tested as a group without masking
162 * off the low bits.
163 *
164 * The following com and tty flags correspond closely:
165 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
166 * comstop())
167 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
168 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
169 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
170 * TS_FLUSH is not used.
171 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
172 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
173 */
174#define CS_BUSY 0x80 /* output in progress */
175#define CS_TTGO 0x40 /* output not stopped by XOFF */
176#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
177#define CS_CHECKMSR 1 /* check of MSR scheduled */
178#define CS_CTS_OFLOW 2 /* use CTS output flow control */
179#define CS_DTR_OFF 0x10 /* DTR held off */
180#define CS_ODONE 4 /* output completed */
181#define CS_RTS_IFLOW 8 /* use RTS input flow control */
182#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
183
184static char const * const error_desc[] = {
185#define CE_OVERRUN 0
186 "silo overflow",
187#define CE_INTERRUPT_BUF_OVERFLOW 1
188 "interrupt-level buffer overflow",
189#define CE_TTY_BUF_OVERFLOW 2
190 "tty-level buffer overflow",
191};
192
193#define CE_NTYPES 3
194#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
195
196/* types. XXX - should be elsewhere */
197typedef u_int Port_t; /* hardware port */
198typedef u_char bool_t; /* boolean */
199
200/* queue of linear buffers */
201struct lbq {
202 u_char *l_head; /* next char to process */
203 u_char *l_tail; /* one past the last char to process */
204 struct lbq *l_next; /* next in queue */
205 bool_t l_queued; /* nonzero if queued */
206};
207
208/* com device structure */
209struct com_s {
210 u_int flags; /* Copy isa device flags */
211 u_char state; /* miscellaneous flag bits */
212 bool_t active_out; /* nonzero if the callout device is open */
213 u_char cfcr_image; /* copy of value written to CFCR */
214#ifdef COM_ESP
215 bool_t esp; /* is this unit a hayes esp board? */
216#endif
217 u_char extra_state; /* more flag bits, separate for order trick */
218 u_char fifo_image; /* copy of value written to FIFO */
219 bool_t hasfifo; /* nonzero for 16550 UARTs */
220 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
221 bool_t loses_outints; /* nonzero if device loses output interrupts */
222 u_char mcr_image; /* copy of value written to MCR */
223#ifdef COM_MULTIPORT
224 bool_t multiport; /* is this unit part of a multiport device? */
225#endif /* COM_MULTIPORT */
226 bool_t no_irq; /* nonzero if irq is not attached */
227 bool_t gone; /* hardware disappeared */
228 bool_t poll; /* nonzero if polling is required */
229 bool_t poll_output; /* nonzero if polling for output is required */
230 int unit; /* unit number */
231 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
232 u_int tx_fifo_size;
233 u_int wopeners; /* # processes waiting for DCD in open() */
234
235 /*
236 * The high level of the driver never reads status registers directly
237 * because there would be too many side effects to handle conveniently.
238 * Instead, it reads copies of the registers stored here by the
239 * interrupt handler.
240 */
241 u_char last_modem_status; /* last MSR read by intr handler */
242 u_char prev_modem_status; /* last MSR handled by high level */
243
244 u_char hotchar; /* ldisc-specific char to be handled ASAP */
245 u_char *ibuf; /* start of input buffer */
246 u_char *ibufend; /* end of input buffer */
247 u_char *ibufold; /* old input buffer, to be freed */
248 u_char *ihighwater; /* threshold in input buffer */
249 u_char *iptr; /* next free spot in input buffer */
250 int ibufsize; /* size of ibuf (not include error bytes) */
251 int ierroff; /* offset of error bytes in ibuf */
252
253 struct lbq obufq; /* head of queue of output buffers */
254 struct lbq obufs[2]; /* output buffers */
255
256 bus_space_tag_t bst;
257 bus_space_handle_t bsh;
258
259 Port_t data_port; /* i/o ports */
260#ifdef COM_ESP
261 Port_t esp_port;
262#endif
263 Port_t int_id_port;
264 Port_t modem_ctl_port;
265 Port_t line_status_port;
266 Port_t modem_status_port;
267 Port_t intr_ctl_port; /* Ports of IIR register */
268
269 struct tty *tp; /* cross reference */
270
271 /* Initial state. */
272 struct termios it_in; /* should be in struct tty */
273 struct termios it_out;
274
275 /* Lock state. */
276 struct termios lt_in; /* should be in struct tty */
277 struct termios lt_out;
278
279 bool_t do_timestamp;
280 bool_t do_dcd_timestamp;
281 struct timeval timestamp;
282 struct timeval dcd_timestamp;
283 struct pps_state pps;
284
285 u_long bytes_in; /* statistics */
286 u_long bytes_out;
287 u_int delta_error_counts[CE_NTYPES];
288 u_long error_counts[CE_NTYPES];
289
290 u_long rclk;
291
292 struct resource *irqres;
293 struct resource *ioportres;
294 void *cookie;
295
296 /*
297 * Data area for output buffers. Someday we should build the output
298 * buffer queue without copying data.
299 */
300 u_char obuf1[256];
301 u_char obuf2[256];
302};
303
304#ifdef COM_ESP
305static int espattach __P((struct com_s *com, Port_t esp_port));
306#endif
307static int sioattach __P((device_t dev, int rid, u_long rclk));
308static int sio_isa_attach __P((device_t dev));
309
310static timeout_t siobusycheck;
311static u_int siodivisor __P((u_long rclk, speed_t speed));
312static timeout_t siodtrwakeup;
313static void comhardclose __P((struct com_s *com));
314static void sioinput __P((struct com_s *com));
315static void siointr1 __P((struct com_s *com));
316static void siointr __P((void *arg));
317static int commctl __P((struct com_s *com, int bits, int how));
318static int comparam __P((struct tty *tp, struct termios *t));
319static swihand_t siopoll;
320static int sioprobe __P((device_t dev, int xrid, u_long rclk));
321static int sio_isa_probe __P((device_t dev));
322static void siosettimeout __P((void));
323static int siosetwater __P((struct com_s *com, speed_t speed));
324static void comstart __P((struct tty *tp));
325static void comstop __P((struct tty *tp, int rw));
326static timeout_t comwakeup;
327static void disc_optim __P((struct tty *tp, struct termios *t,
328 struct com_s *com));
329
330#if NCARD > 0
331static int sio_pccard_attach __P((device_t dev));
332static int sio_pccard_detach __P((device_t dev));
333static int sio_pccard_probe __P((device_t dev));
334#endif /* NCARD > 0 */
335
336#if NPCI > 0
337static int sio_pci_attach __P((device_t dev));
338static void sio_pci_kludge_unit __P((device_t dev));
339static int sio_pci_probe __P((device_t dev));
340#endif /* NPCI > 0 */
341
342#if NPUC > 0
343static int sio_puc_attach __P((device_t dev));
344static int sio_puc_probe __P((device_t dev));
345#endif /* NPUC > 0 */
346
347static char driver_name[] = "sio";
348
349/* table and macro for fast conversion from a unit number to its com struct */
350static devclass_t sio_devclass;
351#define com_addr(unit) ((struct com_s *) \
352 devclass_get_softc(sio_devclass, unit))
353
354static device_method_t sio_isa_methods[] = {
355 /* Device interface */
356 DEVMETHOD(device_probe, sio_isa_probe),
357 DEVMETHOD(device_attach, sio_isa_attach),
358
359 { 0, 0 }
360};
361
362static driver_t sio_isa_driver = {
363 driver_name,
364 sio_isa_methods,
365 sizeof(struct com_s),
366};
367
368#if NCARD > 0
369static device_method_t sio_pccard_methods[] = {
370 /* Device interface */
371 DEVMETHOD(device_probe, sio_pccard_probe),
372 DEVMETHOD(device_attach, sio_pccard_attach),
373 DEVMETHOD(device_detach, sio_pccard_detach),
374
375 { 0, 0 }
376};
377
378static driver_t sio_pccard_driver = {
379 driver_name,
380 sio_pccard_methods,
381 sizeof(struct com_s),
382};
383#endif /* NCARD > 0 */
384
385#if NPCI > 0
386static device_method_t sio_pci_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, sio_pci_probe),
389 DEVMETHOD(device_attach, sio_pci_attach),
390
391 { 0, 0 }
392};
393
394static driver_t sio_pci_driver = {
395 driver_name,
396 sio_pci_methods,
397 sizeof(struct com_s),
398};
399#endif /* NPCI > 0 */
400
401#if NPUC > 0
402static device_method_t sio_puc_methods[] = {
403 /* Device interface */
404 DEVMETHOD(device_probe, sio_puc_probe),
405 DEVMETHOD(device_attach, sio_puc_attach),
406
407 { 0, 0 }
408};
409
410static driver_t sio_puc_driver = {
411 driver_name,
412 sio_puc_methods,
413 sizeof(struct com_s),
414};
415#endif /* NPUC > 0 */
416
417static d_open_t sioopen;
418static d_close_t sioclose;
419static d_read_t sioread;
420static d_write_t siowrite;
421static d_ioctl_t sioioctl;
422
423#define CDEV_MAJOR 28
424static struct cdevsw sio_cdevsw = {
425 /* open */ sioopen,
426 /* close */ sioclose,
427 /* read */ sioread,
428 /* write */ siowrite,
429 /* ioctl */ sioioctl,
430 /* poll */ ttypoll,
431 /* mmap */ nommap,
432 /* strategy */ nostrategy,
433 /* name */ driver_name,
434 /* maj */ CDEV_MAJOR,
435 /* dump */ nodump,
436 /* psize */ nopsize,
437 /* flags */ D_TTY | D_KQFILTER,
438 /* bmaj */ -1,
439 /* kqfilter */ ttykqfilter,
440};
441
442int comconsole = -1;
443static volatile speed_t comdefaultrate = CONSPEED;
444static u_long comdefaultrclk = DEFAULT_RCLK;
445SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
446#ifdef __alpha__
447static volatile speed_t gdbdefaultrate = CONSPEED;
448#endif
449static u_int com_events; /* input chars + weighted output completions */
450static Port_t siocniobase;
451static int siocnunit;
452static Port_t siogdbiobase;
453static int siogdbunit = -1;
454static bool_t sio_registered;
455static int sio_timeout;
456static int sio_timeouts_until_log;
457static struct callout_handle sio_timeout_handle
458 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
459static int sio_numunits;
460
461#ifdef COM_ESP
462/* XXX configure this properly. */
463static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
464static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
465#endif
466
467/*
468 * handle sysctl read/write requests for console speed
469 *
470 * In addition to setting comdefaultrate for I/O through /dev/console,
471 * also set the initial and lock values for the /dev/ttyXX device
472 * if there is one associated with the console. Finally, if the /dev/tty
473 * device has already been open, change the speed on the open running port
474 * itself.
475 */
476
477static int
478sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
479{
480 int error, s;
481 speed_t newspeed;
482 struct com_s *com;
483 struct tty *tp;
484
485 newspeed = comdefaultrate;
486
487 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
488 if (error || !req->newptr)
489 return (error);
490
491 comdefaultrate = newspeed;
492
493 if (comconsole < 0) /* serial console not selected? */
494 return (0);
495
496 com = com_addr(comconsole);
497 if (com == NULL)
498 return (ENXIO);
499
500 /*
501 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
502 * (note, the lock rates really are boolean -- if non-zero, disallow
503 * speed changes)
504 */
505 com->it_in.c_ispeed = com->it_in.c_ospeed =
506 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
507 com->it_out.c_ispeed = com->it_out.c_ospeed =
508 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
509
510 /*
511 * if we're open, change the running rate too
512 */
513 tp = com->tp;
514 if (tp && (tp->t_state & TS_ISOPEN)) {
515 tp->t_termios.c_ispeed =
516 tp->t_termios.c_ospeed = comdefaultrate;
517 s = spltty();
518 error = comparam(tp, &tp->t_termios);
519 splx(s);
520 }
521 return error;
522}
523
524SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
525 0, 0, sysctl_machdep_comdefaultrate, "I", "");
526
527#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
528#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
529
530#if NCARD > 0
531static int
532sio_pccard_probe(dev)
533 device_t dev;
534{
535 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */
536 /* until bus_setup_intr */
537 SET_FLAG(dev, COM_C_NOPROBE);
538
539 return (sioprobe(dev, 0, 0UL));
540}
541
542static int
543sio_pccard_attach(dev)
544 device_t dev;
545{
546 return (sioattach(dev, 0, 0UL));
547}
548
549/*
550 * sio_detach - unload the driver and clear the table.
551 * XXX TODO:
552 * This is usually called when the card is ejected, but
553 * can be caused by a modunload of a controller driver.
554 * The idea is to reset the driver's view of the device
555 * and ensure that any driver entry points such as
556 * read and write do not hang.
557 */
558static int
559sio_pccard_detach(dev)
560 device_t dev;
561{
562 struct com_s *com;
563
564 com = (struct com_s *) device_get_softc(dev);
565 if (com == NULL) {
566 device_printf(dev, "NULL com in siounload\n");
567 return (0);
568 }
569 com->gone = 1;
570 if (com->irqres) {
571 bus_teardown_intr(dev, com->irqres, com->cookie);
572 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
573 }
574 if (com->ioportres)
575 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
576 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
577 device_printf(dev, "still open, forcing close\n");
578 com->tp->t_gen++;
579 ttyclose(com->tp);
580 ttwakeup(com->tp);
581 ttwwakeup(com->tp);
582 } else {
583 if (com->ibuf != NULL)
584 free(com->ibuf, M_DEVBUF);
585 }
586 device_printf(dev, "unloaded\n");
587 return (0);
588}
589#endif /* NCARD > 0 */
590
591#if NPCI > 0
592struct pci_ids {
593 u_int32_t type;
594 const char *desc;
595 int rid;
596};
597
598static struct pci_ids pci_ids[] = {
599 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
600 { 0x2000131f, "CyberSerial (1-port) 16550", 0x10 },
601 { 0x01101407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
602 { 0x01111407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
603 { 0x048011c1, "Lucent kermit based PCI Modem", 0x14 },
604 { 0x95211415, "Oxford Semiconductor PCI Dual Port Serial", 0x10 },
605 { 0x7101135e, "SeaLevel Ultra 530.PCI Single Port Serial", 0x18 },
606 { 0x0000151f, "SmartLink 5634PCV SurfRider", 0x10 },
607 { 0x98459710, "Netmos Nm9845 PCI Bridge with Dual UART", 0x10 },
608 { 0x00000000, NULL, 0 }
609};
610
611static int
612sio_pci_attach(dev)
613 device_t dev;
614{
615 u_int32_t type;
616 struct pci_ids *id;
617
618 type = pci_get_devid(dev);
619 id = pci_ids;
620 while (id->type && id->type != type)
621 id++;
622 if (id->desc == NULL)
623 return (ENXIO);
624 sio_pci_kludge_unit(dev);
625 return (sioattach(dev, id->rid, 0UL));
626}
627
628/*
629 * Don't cut and paste this to other drivers. It is a horrible kludge
630 * which will fail to work and also be unnecessary in future versions.
631 */
632static void
633sio_pci_kludge_unit(dev)
634 device_t dev;
635{
636 devclass_t dc;
637 int err;
638 int start;
639 int unit;
640
641 unit = 0;
642 start = 0;
643 while (resource_int_value("sio", unit, "port", &start) == 0 &&
644 start > 0)
645 unit++;
646 if (device_get_unit(dev) < unit) {
647 dc = device_get_devclass(dev);
648 while (devclass_get_device(dc, unit))
649 unit++;
650 device_printf(dev, "moving to sio%d\n", unit);
651 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
652 if (err)
653 device_printf(dev, "error moving device %d\n", err);
654 }
655}
656
657static int
658sio_pci_probe(dev)
659 device_t dev;
660{
661 u_int32_t type;
662 struct pci_ids *id;
663
664 type = pci_get_devid(dev);
665 id = pci_ids;
666 while (id->type && id->type != type)
667 id++;
668 if (id->desc == NULL)
669 return (ENXIO);
670 device_set_desc(dev, id->desc);
671 return (sioprobe(dev, id->rid, 0UL));
672}
673#endif /* NPCI > 0 */
674
675#if NPUC > 0
676static int
677sio_puc_attach(dev)
678 device_t dev;
679{
680 u_int rclk;
681
682 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
683 &rclk) != 0)
684 rclk = DEFAULT_RCLK;
685 return (sioattach(dev, 0, rclk));
686}
687
688static int
689sio_puc_probe(dev)
690 device_t dev;
691{
692 u_int rclk;
693
694 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
695 &rclk) != 0)
696 rclk = DEFAULT_RCLK;
697 return (sioprobe(dev, 0, rclk));
698}
699#endif /* NPUC */
700
701static struct isa_pnp_id sio_ids[] = {
702 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
703 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
704 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
705 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
706 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
707 /* Devices that do not have a compatid */
708 {0x12206804, NULL}, /* ACH2012 - 5634BTS 56K Video Ready Modem */
709 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
710 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
711 {0x21107905, NULL}, /* AKY1021 - 56K Plug&Play Modem */
712 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
713 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
714 {0x56159008, NULL}, /* BDP1556 - B.D. Smart One 56SPS,Voice Modem*/
715 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
716 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
717 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
718 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
719 {0x0094490a, NULL}, /* BRI9400 - Boca K56Flex PnP */
720 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
721 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
722 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
723 {0x01308c0e, NULL}, /* CTL3001 - Creative Labs Phoneblaster */
724 {0x36033610, NULL}, /* DAV0336 - DAVICOM 336PNP MODEM */
725 {0x01009416, NULL}, /* ETT0001 - E-Tech Bullet 33k6 PnP */
726 {0x0000aa1a, NULL}, /* FUJ0000 - FUJITSU Modem 33600 PNP/I2 */
727 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
728 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
729 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
730 {0x0116c31e, NULL}, /* GVC1601 - Rockwell V.34 Plug & Play Modem */
731 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
732 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
733 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
734 {0x8100e425, NULL}, /* IOD0081 - I-O DATA DEVICE,INC. IFML-560 */
735 {0x21002534, NULL}, /* MAE0021 - Jetstream Int V.90 56k Voice Series 2*/
736 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
737 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
738 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
739 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
740 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
741 {0x08804f3f, NULL}, /* OZO8008 - Zoom (33.6k Modem) */
742 {0x0f804f3f, NULL}, /* OZO800f - Zoom 2812 (56k Modem) */
743 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
744 {0x00914f3f, NULL}, /* OZO9100 - Zoom 2919 (K56 Faxmodem) */
745 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
746 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
747 {0x1200b23d, NULL}, /* RSS0012 - OMRON ME5614ISA */
748 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
749 {0x6202734a, NULL}, /* RSS0262 - 5614Jx3[G] V90+K56Flex Modem */
750 {0x1010104d, NULL}, /* SHP1010 - Rockwell 33600bps Modem */
751 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
752 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
753 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
754 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
755 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
756 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
757 {0x7016b04e, NULL}, /* SUP1670 - Supra 336i V+ Intl */
758 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
759 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
760 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
761 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
762 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
763 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
764 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
765 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
766 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
767 {0x11007256, NULL}, /* USR0011 - USR ? */
768 {0x01017256, NULL}, /* USR0101 - USR ? */
769 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
770 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
771 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
772 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
773 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
774 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
775 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
776 {0x90307256, NULL}, /* USR3090 - USR ? */
777 {0x70917256, NULL}, /* USR9170 - U.S. Robotics 56K FAX INT */
778 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
779 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
780 {0x01a0896a, NULL}, /* ZTIA001 - Zoom Internal V90 Faxmodem */
781 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
782 {0}
783};
784
785
786
787static int
788sio_isa_probe(dev)
789 device_t dev;
790{
791 /* Check isapnp ids */
792 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
793 return (ENXIO);
794 return (sioprobe(dev, 0, 0UL));
795}
796
797static int
798sioprobe(dev, xrid, rclk)
799 device_t dev;
800 int xrid;
801 u_long rclk;
802{
803#if 0
804 static bool_t already_init;
805 device_t xdev;
806#endif
807 struct com_s *com;
808 u_int divisor;
809 bool_t failures[10];
810 int fn;
811 device_t idev;
812 Port_t iobase;
813 intrmask_t irqmap[4];
814 intrmask_t irqs;
815 u_char mcr_image;
816 int result;
817 u_long xirq;
818 u_int flags = device_get_flags(dev);
819 int rid;
820 struct resource *port;
821
822 rid = xrid;
823 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
824 0, ~0, IO_COMSIZE, RF_ACTIVE);
825 if (!port)
826 return (ENXIO);
827
828 com = device_get_softc(dev);
829 com->bst = rman_get_bustag(port);
830 com->bsh = rman_get_bushandle(port);
831 if (rclk == 0)
832 rclk = DEFAULT_RCLK;
833 com->rclk = rclk;
834
835#if 0
836 /*
837 * XXX this is broken - when we are first called, there are no
838 * previously configured IO ports. We could hard code
839 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
840 * This code has been doing nothing since the conversion since
841 * "count" is zero the first time around.
842 */
843 if (!already_init) {
844 /*
845 * Turn off MCR_IENABLE for all likely serial ports. An unused
846 * port with its MCR_IENABLE gate open will inhibit interrupts
847 * from any used port that shares the interrupt vector.
848 * XXX the gate enable is elsewhere for some multiports.
849 */
850 device_t *devs;
851 int count, i, xioport;
852
853 devclass_get_devices(sio_devclass, &devs, &count);
854 for (i = 0; i < count; i++) {
855 xdev = devs[i];
856 if (device_is_enabled(xdev) &&
857 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
858 NULL) == 0)
859 outb(xioport + com_mcr, 0);
860 }
861 free(devs, M_TEMP);
862 already_init = TRUE;
863 }
864#endif
865
866 if (COM_LLCONSOLE(flags)) {
867 printf("sio%d: reserved for low-level i/o\n",
868 device_get_unit(dev));
869 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
870 return (ENXIO);
871 }
872
873 /*
874 * If the device is on a multiport card and has an AST/4
875 * compatible interrupt control register, initialize this
876 * register and prepare to leave MCR_IENABLE clear in the mcr.
877 * Otherwise, prepare to set MCR_IENABLE in the mcr.
878 * Point idev to the device struct giving the correct id_irq.
879 * This is the struct for the master device if there is one.
880 */
881 idev = dev;
882 mcr_image = MCR_IENABLE;
883#ifdef COM_MULTIPORT
884 if (COM_ISMULTIPORT(flags)) {
885 Port_t xiobase;
886 u_long io;
887
888 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
889 if (idev == NULL) {
890 printf("sio%d: master device %d not configured\n",
891 device_get_unit(dev), COM_MPMASTER(flags));
892 idev = dev;
893 }
894 if (!COM_NOTAST4(flags)) {
895 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
896 NULL) == 0) {
897 xiobase = io;
898 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
899 NULL, NULL) == 0)
900 outb(xiobase + com_scr, 0x80);
901 else
902 outb(xiobase + com_scr, 0);
903 }
904 mcr_image = 0;
905 }
906 }
907#endif /* COM_MULTIPORT */
908 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
909 mcr_image = 0;
910
911 bzero(failures, sizeof failures);
912 iobase = rman_get_start(port);
913
914 /*
915 * We don't want to get actual interrupts, just masked ones.
916 * Interrupts from this line should already be masked in the ICU,
917 * but mask them in the processor as well in case there are some
918 * (misconfigured) shared interrupts.
919 */
920 disable_intr();
921/* EXTRA DELAY? */
922
923 /*
924 * For the TI16754 chips, set prescaler to 1 (4 is often the
925 * default after-reset value) as otherwise it's impossible to
926 * get highest baudrates.
927 */
928 if (COM_TI16754(flags)) {
929 u_char cfcr, efr;
930
931 cfcr = sio_getreg(com, com_cfcr);
932 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
933 efr = sio_getreg(com, com_efr);
934 /* Unlock extended features to turn off prescaler. */
935 sio_setreg(com, com_efr, efr | EFR_EFE);
936 /* Disable EFR. */
937 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
938 /* Turn off prescaler. */
939 sio_setreg(com, com_mcr,
940 sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
941 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
942 sio_setreg(com, com_efr, efr);
943 sio_setreg(com, com_cfcr, cfcr);
944 }
945
946 /*
947 * Initialize the speed and the word size and wait long enough to
948 * drain the maximum of 16 bytes of junk in device output queues.
949 * The speed is undefined after a master reset and must be set
950 * before relying on anything related to output. There may be
951 * junk after a (very fast) soft reboot and (apparently) after
952 * master reset.
953 * XXX what about the UART bug avoided by waiting in comparam()?
954 * We don't want to to wait long enough to drain at 2 bps.
955 */
956 if (iobase == siocniobase)
957 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
958 else {
959 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
960 divisor = siodivisor(rclk, SIO_TEST_SPEED);
961 sio_setreg(com, com_dlbl, divisor & 0xff);
962 sio_setreg(com, com_dlbh, divisor >> 8);
963 sio_setreg(com, com_cfcr, CFCR_8BITS);
964 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
965 }
966
967 /*
968 * Enable the interrupt gate and disable device interupts. This
969 * should leave the device driving the interrupt line low and
970 * guarantee an edge trigger if an interrupt can be generated.
971 */
972/* EXTRA DELAY? */
973 sio_setreg(com, com_mcr, mcr_image);
974 sio_setreg(com, com_ier, 0);
975 DELAY(1000); /* XXX */
976 irqmap[0] = isa_irq_pending();
977
978 /*
979 * Attempt to set loopback mode so that we can send a null byte
980 * without annoying any external device.
981 */
982/* EXTRA DELAY? */
983 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
984
985 /*
986 * Attempt to generate an output interrupt. On 8250's, setting
987 * IER_ETXRDY generates an interrupt independent of the current
988 * setting and independent of whether the THR is empty. On 16450's,
989 * setting IER_ETXRDY generates an interrupt independent of the
990 * current setting. On 16550A's, setting IER_ETXRDY only
991 * generates an interrupt when IER_ETXRDY is not already set.
992 */
993 sio_setreg(com, com_ier, IER_ETXRDY);
994
995 /*
996 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
997 * an interrupt. They'd better generate one for actually doing
998 * output. Loopback may be broken on the same incompatibles but
999 * it's unlikely to do more than allow the null byte out.
1000 */
1001 sio_setreg(com, com_data, 0);
1002 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1003
1004 /*
1005 * Turn off loopback mode so that the interrupt gate works again
1006 * (MCR_IENABLE was hidden). This should leave the device driving
1007 * an interrupt line high. It doesn't matter if the interrupt
1008 * line oscillates while we are not looking at it, since interrupts
1009 * are disabled.
1010 */
1011/* EXTRA DELAY? */
1012 sio_setreg(com, com_mcr, mcr_image);
1013
1014 /*
1015 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1016 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1017 */
1018 if (COM_NOPROBE(flags)) {
1019 /* Reading IIR register twice */
1020 for (fn = 0; fn < 2; fn ++) {
1021 DELAY(10000);
1022 failures[6] = sio_getreg(com, com_iir);
1023 }
1024 /* Check IIR_TXRDY clear ? */
1025 result = 0;
1026 if (failures[6] & IIR_TXRDY) {
1027 /* Nop, Double check with clearing IER */
1028 sio_setreg(com, com_ier, 0);
1029 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1030 /* Ok. we're familia this gang */
1031 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1032 } else {
1033 /* Unknown, Just omit this chip.. XXX */
1034 result = ENXIO;
1035 sio_setreg(com, com_mcr, 0);
1036 }
1037 } else {
1038 /* OK. this is well-known guys */
1039 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1040 }
1041 sio_setreg(com, com_ier, 0);
1042 sio_setreg(com, com_cfcr, CFCR_8BITS);
1043 enable_intr();
1044 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1045 return (iobase == siocniobase ? 0 : result);
1046 }
1047
1048 /*
1049 * Check that
1050 * o the CFCR, IER and MCR in UART hold the values written to them
1051 * (the values happen to be all distinct - this is good for
1052 * avoiding false positive tests from bus echoes).
1053 * o an output interrupt is generated and its vector is correct.
1054 * o the interrupt goes away when the IIR in the UART is read.
1055 */
1056/* EXTRA DELAY? */
1057 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1058 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1059 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1060 DELAY(10000); /* Some internal modems need this time */
1061 irqmap[1] = isa_irq_pending();
1062 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1063 DELAY(1000); /* XXX */
1064 irqmap[2] = isa_irq_pending();
1065 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1066
1067 /*
1068 * Turn off all device interrupts and check that they go off properly.
1069 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1070 * the OUT2 output of the UART to
1071 * the ICU input. Closing the gate would give a floating ICU input
1072 * (unless there is another device driving it) and spurious interrupts.
1073 * (On the system that this was first tested on, the input floats high
1074 * and gives a (masked) interrupt as soon as the gate is closed.)
1075 */
1076 sio_setreg(com, com_ier, 0);
1077 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1078 failures[7] = sio_getreg(com, com_ier);
1079 DELAY(1000); /* XXX */
1080 irqmap[3] = isa_irq_pending();
1081 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1082
1083 enable_intr();
1084
1085 irqs = irqmap[1] & ~irqmap[0];
1086 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1087 ((1 << xirq) & irqs) == 0)
1088 printf(
1089 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1090 device_get_unit(dev), xirq, irqs);
1091 if (bootverbose)
1092 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1093 device_get_unit(dev),
1094 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1095
1096 result = 0;
1097 for (fn = 0; fn < sizeof failures; ++fn)
1098 if (failures[fn]) {
1099 sio_setreg(com, com_mcr, 0);
1100 result = ENXIO;
1101 if (bootverbose) {
1102 printf("sio%d: probe failed test(s):",
1103 device_get_unit(dev));
1104 for (fn = 0; fn < sizeof failures; ++fn)
1105 if (failures[fn])
1106 printf(" %d", fn);
1107 printf("\n");
1108 }
1109 break;
1110 }
1111 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1112 return (iobase == siocniobase ? 0 : result);
1113}
1114
1115#ifdef COM_ESP
1116static int
1117espattach(com, esp_port)
1118 struct com_s *com;
1119 Port_t esp_port;
1120{
1121 u_char dips;
1122 u_char val;
1123
1124 /*
1125 * Check the ESP-specific I/O port to see if we're an ESP
1126 * card. If not, return failure immediately.
1127 */
1128 if ((inb(esp_port) & 0xf3) == 0) {
1129 printf(" port 0x%x is not an ESP board?\n", esp_port);
1130 return (0);
1131 }
1132
1133 /*
1134 * We've got something that claims to be a Hayes ESP card.
1135 * Let's hope so.
1136 */
1137
1138 /* Get the dip-switch configuration */
1139 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1140 dips = inb(esp_port + ESP_STATUS1);
1141
1142 /*
1143 * Bits 0,1 of dips say which COM port we are.
1144 */
1145 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1146 printf(" : ESP");
1147 else {
1148 printf(" esp_port has com %d\n", dips & 0x03);
1149 return (0);
1150 }
1151
1152 /*
1153 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1154 */
1155 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1156 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1157 val = inb(esp_port + ESP_STATUS2);
1158 if ((val & 0x70) < 0x20) {
1159 printf("-old (%o)", val & 0x70);
1160 return (0);
1161 }
1162
1163 /*
1164 * Check for ability to emulate 16550: bit 7 == 1
1165 */
1166 if ((dips & 0x80) == 0) {
1167 printf(" slave");
1168 return (0);
1169 }
1170
1171 /*
1172 * Okay, we seem to be a Hayes ESP card. Whee.
1173 */
1174 com->esp = TRUE;
1175 com->esp_port = esp_port;
1176 return (1);
1177}
1178#endif /* COM_ESP */
1179
1180static int
1181sio_isa_attach(dev)
1182 device_t dev;
1183{
1184 return (sioattach(dev, 0, 0UL));
1185}
1186
1187static int
1188sioattach(dev, xrid, rclk)
1189 device_t dev;
1190 int xrid;
1191 u_long rclk;
1192{
1193 struct com_s *com;
1194#ifdef COM_ESP
1195 Port_t *espp;
1196#endif
1197 Port_t iobase;
1198 int minorbase;
1199 int unit;
1200 u_int flags;
1201 int rid;
1202 struct resource *port;
1203 int ret;
1204
1205 rid = xrid;
1206 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1207 0, ~0, IO_COMSIZE, RF_ACTIVE);
1208 if (!port)
1209 return (ENXIO);
1210
1211 iobase = rman_get_start(port);
1212 unit = device_get_unit(dev);
1213 com = device_get_softc(dev);
1214 flags = device_get_flags(dev);
1215
1216 if (unit >= sio_numunits)
1217 sio_numunits = unit + 1;
1218 /*
1219 * sioprobe() has initialized the device registers as follows:
1220 * o cfcr = CFCR_8BITS.
1221 * It is most important that CFCR_DLAB is off, so that the
1222 * data port is not hidden when we enable interrupts.
1223 * o ier = 0.
1224 * Interrupts are only enabled when the line is open.
1225 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1226 * interrupt control register or the config specifies no irq.
1227 * Keeping MCR_DTR and MCR_RTS off might stop the external
1228 * device from sending before we are ready.
1229 */
1230 bzero(com, sizeof *com);
1231 com->unit = unit;
1232 com->ioportres = port;
1233 com->bst = rman_get_bustag(port);
1234 com->bsh = rman_get_bushandle(port);
1235 com->cfcr_image = CFCR_8BITS;
1236 com->dtr_wait = 3 * hz;
1237 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1238 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1239 com->tx_fifo_size = 1;
1240 com->obufs[0].l_head = com->obuf1;
1241 com->obufs[1].l_head = com->obuf2;
1242
1243 com->data_port = iobase + com_data;
1244 com->int_id_port = iobase + com_iir;
1245 com->modem_ctl_port = iobase + com_mcr;
1246 com->mcr_image = inb(com->modem_ctl_port);
1247 com->line_status_port = iobase + com_lsr;
1248 com->modem_status_port = iobase + com_msr;
1249 com->intr_ctl_port = iobase + com_ier;
1250
1251 if (rclk == 0)
1252 rclk = DEFAULT_RCLK;
1253 com->rclk = rclk;
1254
1255 /*
1256 * We don't use all the flags from <sys/ttydefaults.h> since they
1257 * are only relevant for logins. It's important to have echo off
1258 * initially so that the line doesn't start blathering before the
1259 * echo flag can be turned off.
1260 */
1261 com->it_in.c_iflag = 0;
1262 com->it_in.c_oflag = 0;
1263 com->it_in.c_cflag = TTYDEF_CFLAG;
1264 com->it_in.c_lflag = 0;
1265 if (unit == comconsole) {
1266 com->it_in.c_iflag = TTYDEF_IFLAG;
1267 com->it_in.c_oflag = TTYDEF_OFLAG;
1268 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1269 com->it_in.c_lflag = TTYDEF_LFLAG;
1270 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1271 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1272 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1273 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1274 } else
1275 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1276 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1277 enable_intr();
1278 /*
1279 * Leave i/o resources allocated if this is a `cn'-level
1280 * console, so that other devices can't snarf them.
1281 */
1282 if (iobase != siocniobase)
1283 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1284 return (ENOMEM);
1285 }
1286 enable_intr();
1287 termioschars(&com->it_in);
1288 com->it_out = com->it_in;
1289
1290 /* attempt to determine UART type */
1291 printf("sio%d: type", unit);
1292
1293
1294#ifdef COM_MULTIPORT
1295 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1296#else
1297 if (!COM_IIR_TXRDYBUG(flags))
1298#endif
1299 {
1300 u_char scr;
1301 u_char scr1;
1302 u_char scr2;
1303
1304 scr = sio_getreg(com, com_scr);
1305 sio_setreg(com, com_scr, 0xa5);
1306 scr1 = sio_getreg(com, com_scr);
1307 sio_setreg(com, com_scr, 0x5a);
1308 scr2 = sio_getreg(com, com_scr);
1309 sio_setreg(com, com_scr, scr);
1310 if (scr1 != 0xa5 || scr2 != 0x5a) {
1311 printf(" 8250");
1312 goto determined_type;
1313 }
1314 }
1315 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1316 DELAY(100);
1317 com->st16650a = 0;
1318 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1319 case FIFO_RX_LOW:
1320 printf(" 16450");
1321 break;
1322 case FIFO_RX_MEDL:
1323 printf(" 16450?");
1324 break;
1325 case FIFO_RX_MEDH:
1326 printf(" 16550?");
1327 break;
1328 case FIFO_RX_HIGH:
1329 if (COM_NOFIFO(flags)) {
1330 printf(" 16550A fifo disabled");
1331 } else {
1332 com->hasfifo = TRUE;
1333 if (COM_ST16650A(flags)) {
1334 com->st16650a = 1;
1335 com->tx_fifo_size = 32;
1336 printf(" ST16650A");
1337 } else if (COM_TI16754(flags)) {
1338 com->tx_fifo_size = 64;
1339 printf(" TI16754");
1340 } else {
1341 com->tx_fifo_size = COM_FIFOSIZE(flags);
1342 printf(" 16550A");
1343 }
1344 }
1345#ifdef COM_ESP
1346 for (espp = likely_esp_ports; *espp != 0; espp++)
1347 if (espattach(com, *espp)) {
1348 com->tx_fifo_size = 1024;
1349 break;
1350 }
1351#endif
1352 if (!com->st16650a && !COM_TI16754(flags)) {
1353 if (!com->tx_fifo_size)
1354 com->tx_fifo_size = 16;
1355 else
1356 printf(" lookalike with %d bytes FIFO",
1357 com->tx_fifo_size);
1358 }
1359
1360 break;
1361 }
1362
1363#ifdef COM_ESP
1364 if (com->esp) {
1365 /*
1366 * Set 16550 compatibility mode.
1367 * We don't use the ESP_MODE_SCALE bit to increase the
1368 * fifo trigger levels because we can't handle large
1369 * bursts of input.
1370 * XXX flow control should be set in comparam(), not here.
1371 */
1372 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1373 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1374
1375 /* Set RTS/CTS flow control. */
1376 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1377 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1378 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1379
1380 /* Set flow-control levels. */
1381 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1382 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1383 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1384 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1385 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1386 }
1387#endif /* COM_ESP */
1388 sio_setreg(com, com_fifo, 0);
1389determined_type: ;
1390
1391#ifdef COM_MULTIPORT
1392 if (COM_ISMULTIPORT(flags)) {
1393 device_t masterdev;
1394
1395 com->multiport = TRUE;
1396 printf(" (multiport");
1397 if (unit == COM_MPMASTER(flags))
1398 printf(" master");
1399 printf(")");
1400 masterdev = devclass_get_device(sio_devclass,
1401 COM_MPMASTER(flags));
1402 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1403 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1404 }
1405#endif /* COM_MULTIPORT */
1406 if (unit == comconsole)
1407 printf(", console");
1408 if (COM_IIR_TXRDYBUG(flags))
1409 printf(" with a bogus IIR_TXRDY register");
1410 printf("\n");
1411
1412 if (!sio_registered) {
1413 register_swi(SWI_TTY, siopoll);
1414 sio_registered = TRUE;
1415 }
1416 minorbase = UNIT_TO_MINOR(unit);
1417 make_dev(&sio_cdevsw, minorbase,
1418 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1419 make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE,
1420 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1421 make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE,
1422 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1423 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK,
1424 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1425 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_INIT_STATE,
1426 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1427 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE,
1428 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1429 com->flags = flags;
1430 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1431 pps_init(&com->pps);
1432
1433 rid = 0;
1434 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1435 RF_ACTIVE);
1436 if (com->irqres) {
1437 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1438 INTR_TYPE_TTY | INTR_TYPE_FAST,
1439 siointr, com, &com->cookie);
1440 if (ret) {
1441 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1442 com->irqres, INTR_TYPE_TTY,
1443 siointr, com, &com->cookie);
1444 if (ret == 0)
1445 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1446 }
1447 if (ret)
1448 device_printf(dev, "could not activate interrupt\n");
1449#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1450 defined(ALT_BREAK_TO_DEBUGGER))
1451 /*
1452 * Enable interrupts for early break-to-debugger support
1453 * on the console.
1454 */
1455 if (ret == 0 && unit == comconsole)
1456 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1457 IER_EMSC);
1458#endif
1459 }
1460
1461 return (0);
1462}
1463
1464static int
41c20dac 1465sioopen(dev_t dev, int flag, int mode, struct thread *td)
984263bc
MD
1466{
1467 struct com_s *com;
1468 int error;
1469 int mynor;
1470 int s;
1471 struct tty *tp;
1472 int unit;
1473
1474 mynor = minor(dev);
1475 unit = MINOR_TO_UNIT(mynor);
1476 com = com_addr(unit);
1477 if (com == NULL)
1478 return (ENXIO);
1479 if (com->gone)
1480 return (ENXIO);
1481 if (mynor & CONTROL_MASK)
1482 return (0);
1483 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1484 s = spltty();
1485 /*
1486 * We jump to this label after all non-interrupted sleeps to pick
1487 * up any changes of the device state.
1488 */
1489open_top:
1490 while (com->state & CS_DTR_OFF) {
1491 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1492 if (com_addr(unit) == NULL)
1493 return (ENXIO);
1494 if (error != 0 || com->gone)
1495 goto out;
1496 }
1497 if (tp->t_state & TS_ISOPEN) {
1498 /*
1499 * The device is open, so everything has been initialized.
1500 * Handle conflicts.
1501 */
1502 if (mynor & CALLOUT_MASK) {
1503 if (!com->active_out) {
1504 error = EBUSY;
1505 goto out;
1506 }
1507 } else {
1508 if (com->active_out) {
1509 if (flag & O_NONBLOCK) {
1510 error = EBUSY;
1511 goto out;
1512 }
1513 error = tsleep(&com->active_out,
1514 TTIPRI | PCATCH, "siobi", 0);
1515 if (com_addr(unit) == NULL)
1516 return (ENXIO);
1517 if (error != 0 || com->gone)
1518 goto out;
1519 goto open_top;
1520 }
1521 }
1522 if (tp->t_state & TS_XCLUDE &&
41c20dac 1523 suser_xxx(td->td_proc->p_ucred, 0)) {
984263bc
MD
1524 error = EBUSY;
1525 goto out;
1526 }
1527 } else {
1528 /*
1529 * The device isn't open, so there are no conflicts.
1530 * Initialize it. Initialization is done twice in many
1531 * cases: to preempt sleeping callin opens if we are
1532 * callout, and to complete a callin open after DCD rises.
1533 */
1534 tp->t_oproc = comstart;
1535 tp->t_param = comparam;
1536 tp->t_stop = comstop;
1537 tp->t_dev = dev;
1538 tp->t_termios = mynor & CALLOUT_MASK
1539 ? com->it_out : com->it_in;
1540 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1541 com->poll = com->no_irq;
1542 com->poll_output = com->loses_outints;
1543 ++com->wopeners;
1544 error = comparam(tp, &tp->t_termios);
1545 --com->wopeners;
1546 if (error != 0)
1547 goto out;
1548 /*
1549 * XXX we should goto open_top if comparam() slept.
1550 */
1551 if (com->hasfifo) {
1552 /*
1553 * (Re)enable and drain fifos.
1554 *
1555 * Certain SMC chips cause problems if the fifos
1556 * are enabled while input is ready. Turn off the
1557 * fifo if necessary to clear the input. We test
1558 * the input ready bit after enabling the fifos
1559 * since we've already enabled them in comparam()
1560 * and to handle races between enabling and fresh
1561 * input.
1562 */
1563 while (TRUE) {
1564 sio_setreg(com, com_fifo,
1565 FIFO_RCV_RST | FIFO_XMT_RST
1566 | com->fifo_image);
1567 /*
1568 * XXX the delays are for superstitious
1569 * historical reasons. It must be less than
1570 * the character time at the maximum
1571 * supported speed (87 usec at 115200 bps
1572 * 8N1). Otherwise we might loop endlessly
1573 * if data is streaming in. We used to use
1574 * delays of 100. That usually worked
1575 * because DELAY(100) used to usually delay
1576 * for about 85 usec instead of 100.
1577 */
1578 DELAY(50);
1579 if (!(inb(com->line_status_port) & LSR_RXRDY))
1580 break;
1581 sio_setreg(com, com_fifo, 0);
1582 DELAY(50);
1583 (void) inb(com->data_port);
1584 }
1585 }
1586
1587 disable_intr();
1588 (void) inb(com->line_status_port);
1589 (void) inb(com->data_port);
1590 com->prev_modem_status = com->last_modem_status
1591 = inb(com->modem_status_port);
1592 if (COM_IIR_TXRDYBUG(com->flags)) {
1593 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1594 | IER_EMSC);
1595 } else {
1596 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1597 | IER_ERLS | IER_EMSC);
1598 }
1599 enable_intr();
1600 /*
1601 * Handle initial DCD. Callout devices get a fake initial
1602 * DCD (trapdoor DCD). If we are callout, then any sleeping
1603 * callin opens get woken up and resume sleeping on "siobi"
1604 * instead of "siodcd".
1605 */
1606 /*
1607 * XXX `mynor & CALLOUT_MASK' should be
1608 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1609 * TRAPDOOR_CARRIER is the default initial state for callout
1610 * devices and SOFT_CARRIER is like CLOCAL except it hides
1611 * the true carrier.
1612 */
1613 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1614 (*linesw[tp->t_line].l_modem)(tp, 1);
1615 }
1616 /*
1617 * Wait for DCD if necessary.
1618 */
1619 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1620 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1621 ++com->wopeners;
1622 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
1623 if (com_addr(unit) == NULL)
1624 return (ENXIO);
1625 --com->wopeners;
1626 if (error != 0 || com->gone)
1627 goto out;
1628 goto open_top;
1629 }
1630 error = (*linesw[tp->t_line].l_open)(dev, tp);
1631 disc_optim(tp, &tp->t_termios, com);
1632 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1633 com->active_out = TRUE;
1634 siosettimeout();
1635out:
1636 splx(s);
1637 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1638 comhardclose(com);
1639 return (error);
1640}
1641
1642static int
41c20dac 1643sioclose(dev_t dev, int flag, int mode, struct thread *td)
984263bc
MD
1644{
1645 struct com_s *com;
1646 int mynor;
1647 int s;
1648 struct tty *tp;
1649
1650 mynor = minor(dev);
1651 if (mynor & CONTROL_MASK)
1652 return (0);
1653 com = com_addr(MINOR_TO_UNIT(mynor));
1654 if (com == NULL)
1655 return (ENODEV);
1656 tp = com->tp;
1657 s = spltty();
1658 (*linesw[tp->t_line].l_close)(tp, flag);
1659 disc_optim(tp, &tp->t_termios, com);
1660 comstop(tp, FREAD | FWRITE);
1661 comhardclose(com);
1662 ttyclose(tp);
1663 siosettimeout();
1664 splx(s);
1665 if (com->gone) {
1666 printf("sio%d: gone\n", com->unit);
1667 s = spltty();
1668 if (com->ibuf != NULL)
1669 free(com->ibuf, M_DEVBUF);
1670 bzero(tp, sizeof *tp);
1671 splx(s);
1672 }
1673 return (0);
1674}
1675
1676static void
1677comhardclose(com)
1678 struct com_s *com;
1679{
1680 int s;
1681 struct tty *tp;
1682 int unit;
1683
1684 unit = com->unit;
1685 s = spltty();
1686 com->poll = FALSE;
1687 com->poll_output = FALSE;
1688 com->do_timestamp = FALSE;
1689 com->do_dcd_timestamp = FALSE;
1690 com->pps.ppsparam.mode = 0;
1691 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1692 tp = com->tp;
1693
1694#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1695 defined(ALT_BREAK_TO_DEBUGGER))
1696 /*
1697 * Leave interrupts enabled and don't clear DTR if this is the
1698 * console. This allows us to detect break-to-debugger events
1699 * while the console device is closed.
1700 */
1701 if (com->unit != comconsole)
1702#endif
1703 {
1704 sio_setreg(com, com_ier, 0);
1705 if (tp->t_cflag & HUPCL
1706 /*
1707 * XXX we will miss any carrier drop between here and the
1708 * next open. Perhaps we should watch DCD even when the
1709 * port is closed; it is not sufficient to check it at
1710 * the next open because it might go up and down while
1711 * we're not watching.
1712 */
1713 || (!com->active_out
1714 && !(com->prev_modem_status & MSR_DCD)
1715 && !(com->it_in.c_cflag & CLOCAL))
1716 || !(tp->t_state & TS_ISOPEN)) {
1717 (void)commctl(com, TIOCM_DTR, DMBIC);
1718 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1719 timeout(siodtrwakeup, com, com->dtr_wait);
1720 com->state |= CS_DTR_OFF;
1721 }
1722 }
1723 }
1724 if (com->hasfifo) {
1725 /*
1726 * Disable fifos so that they are off after controlled
1727 * reboots. Some BIOSes fail to detect 16550s when the
1728 * fifos are enabled.
1729 */
1730 sio_setreg(com, com_fifo, 0);
1731 }
1732 com->active_out = FALSE;
1733 wakeup(&com->active_out);
1734 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1735 splx(s);
1736}
1737
1738static int
1739sioread(dev, uio, flag)
1740 dev_t dev;
1741 struct uio *uio;
1742 int flag;
1743{
1744 int mynor;
1745 struct com_s *com;
1746
1747 mynor = minor(dev);
1748 if (mynor & CONTROL_MASK)
1749 return (ENODEV);
1750 com = com_addr(MINOR_TO_UNIT(mynor));
1751 if (com == NULL || com->gone)
1752 return (ENODEV);
1753 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1754}
1755
1756static int
1757siowrite(dev, uio, flag)
1758 dev_t dev;
1759 struct uio *uio;
1760 int flag;
1761{
1762 int mynor;
1763 struct com_s *com;
1764 int unit;
1765
1766 mynor = minor(dev);
1767 if (mynor & CONTROL_MASK)
1768 return (ENODEV);
1769
1770 unit = MINOR_TO_UNIT(mynor);
1771 com = com_addr(unit);
1772 if (com == NULL || com->gone)
1773 return (ENODEV);
1774 /*
1775 * (XXX) We disallow virtual consoles if the physical console is
1776 * a serial port. This is in case there is a display attached that
1777 * is not the console. In that situation we don't need/want the X
1778 * server taking over the console.
1779 */
1780 if (constty != NULL && unit == comconsole)
1781 constty = NULL;
1782 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1783}
1784
1785static void
1786siobusycheck(chan)
1787 void *chan;
1788{
1789 struct com_s *com;
1790 int s;
1791
1792 com = (struct com_s *)chan;
1793
1794 /*
1795 * Clear TS_BUSY if low-level output is complete.
1796 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1797 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1798 * called again. Reading the line status port outside of siointr1()
1799 * is safe because CS_BUSY is clear so there are no output interrupts
1800 * to lose.
1801 */
1802 s = spltty();
1803 if (com->state & CS_BUSY)
1804 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1805 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1806 == (LSR_TSRE | LSR_TXRDY)) {
1807 com->tp->t_state &= ~TS_BUSY;
1808 ttwwakeup(com->tp);
1809 com->extra_state &= ~CSE_BUSYCHECK;
1810 } else
1811 timeout(siobusycheck, com, hz / 100);
1812 splx(s);
1813}
1814
1815static u_int
1816siodivisor(rclk, speed)
1817 u_long rclk;
1818 speed_t speed;
1819{
1820 long actual_speed;
1821 u_int divisor;
1822 int error;
1823
1824 if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1825 return (0);
1826 divisor = (rclk / (8UL * speed) + 1) / 2;
1827 if (divisor == 0 || divisor >= 65536)
1828 return (0);
1829 actual_speed = rclk / (16UL * divisor);
1830
1831 /* 10 times error in percent: */
1832 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1833
1834 /* 3.0% maximum error tolerance: */
1835 if (error < -30 || error > 30)
1836 return (0);
1837
1838 return (divisor);
1839}
1840
1841static void
1842siodtrwakeup(chan)
1843 void *chan;
1844{
1845 struct com_s *com;
1846
1847 com = (struct com_s *)chan;
1848 com->state &= ~CS_DTR_OFF;
1849 wakeup(&com->dtr_wait);
1850}
1851
1852static void
1853sioinput(com)
1854 struct com_s *com;
1855{
1856 u_char *buf;
1857 int incc;
1858 u_char line_status;
1859 int recv_data;
1860 struct tty *tp;
1861
1862 buf = com->ibuf;
1863 tp = com->tp;
1864 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1865 com_events -= (com->iptr - com->ibuf);
1866 com->iptr = com->ibuf;
1867 return;
1868 }
1869 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1870 /*
1871 * Avoid the grotesquely inefficient lineswitch routine
1872 * (ttyinput) in "raw" mode. It usually takes about 450
1873 * instructions (that's without canonical processing or echo!).
1874 * slinput is reasonably fast (usually 40 instructions plus
1875 * call overhead).
1876 */
1877 do {
1878 enable_intr();
1879 incc = com->iptr - buf;
1880 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1881 && (com->state & CS_RTS_IFLOW
1882 || tp->t_iflag & IXOFF)
1883 && !(tp->t_state & TS_TBLOCK))
1884 ttyblock(tp);
1885 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1886 += b_to_q((char *)buf, incc, &tp->t_rawq);
1887 buf += incc;
1888 tk_nin += incc;
1889 tk_rawcc += incc;
1890 tp->t_rawcc += incc;
1891 ttwakeup(tp);
1892 if (tp->t_state & TS_TTSTOP
1893 && (tp->t_iflag & IXANY
1894 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1895 tp->t_state &= ~TS_TTSTOP;
1896 tp->t_lflag &= ~FLUSHO;
1897 comstart(tp);
1898 }
1899 disable_intr();
1900 } while (buf < com->iptr);
1901 } else {
1902 do {
1903 enable_intr();
1904 line_status = buf[com->ierroff];
1905 recv_data = *buf++;
1906 if (line_status
1907 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1908 if (line_status & LSR_BI)
1909 recv_data |= TTY_BI;
1910 if (line_status & LSR_FE)
1911 recv_data |= TTY_FE;
1912 if (line_status & LSR_OE)
1913 recv_data |= TTY_OE;
1914 if (line_status & LSR_PE)
1915 recv_data |= TTY_PE;
1916 }
1917 (*linesw[tp->t_line].l_rint)(recv_data, tp);
1918 disable_intr();
1919 } while (buf < com->iptr);
1920 }
1921 com_events -= (com->iptr - com->ibuf);
1922 com->iptr = com->ibuf;
1923
1924 /*
1925 * There is now room for another low-level buffer full of input,
1926 * so enable RTS if it is now disabled and there is room in the
1927 * high-level buffer.
1928 */
1929 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1930 !(tp->t_state & TS_TBLOCK))
1931 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1932}
1933
1934void
1935siointr(arg)
1936 void *arg;
1937{
1938#ifndef COM_MULTIPORT
1939 COM_LOCK();
1940 siointr1((struct com_s *) arg);
1941 COM_UNLOCK();
1942#else /* COM_MULTIPORT */
1943 bool_t possibly_more_intrs;
1944 int unit;
1945 struct com_s *com;
1946
1947 /*
1948 * Loop until there is no activity on any port. This is necessary
1949 * to get an interrupt edge more than to avoid another interrupt.
1950 * If the IRQ signal is just an OR of the IRQ signals from several
1951 * devices, then the edge from one may be lost because another is
1952 * on.
1953 */
1954 COM_LOCK();
1955 do {
1956 possibly_more_intrs = FALSE;
1957 for (unit = 0; unit < sio_numunits; ++unit) {
1958 com = com_addr(unit);
1959 /*
1960 * XXX COM_LOCK();
1961 * would it work here, or be counter-productive?
1962 */
1963 if (com != NULL
1964 && !com->gone
1965 && (inb(com->int_id_port) & IIR_IMASK)
1966 != IIR_NOPEND) {
1967 siointr1(com);
1968 possibly_more_intrs = TRUE;
1969 }
1970 /* XXX COM_UNLOCK(); */
1971 }
1972 } while (possibly_more_intrs);
1973 COM_UNLOCK();
1974#endif /* COM_MULTIPORT */
1975}
1976
1977static void
1978siointr1(com)
1979 struct com_s *com;
1980{
1981 u_char line_status;
1982 u_char modem_status;
1983 u_char *ioptr;
1984 u_char recv_data;
1985 u_char int_ctl;
1986 u_char int_ctl_new;
1987 struct timecounter *tc;
1988 u_int count;
1989
1990 int_ctl = inb(com->intr_ctl_port);
1991 int_ctl_new = int_ctl;
1992
1993 while (!com->gone) {
1994 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1995 modem_status = inb(com->modem_status_port);
1996 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
1997 tc = timecounter;
1998 count = tc->tc_get_timecount(tc);
1999 pps_event(&com->pps, tc, count,
2000 (modem_status & MSR_DCD) ?
2001 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2002 }
2003 }
2004 line_status = inb(com->line_status_port);
2005
2006 /* input event? (check first to help avoid overruns) */
2007 while (line_status & LSR_RCV_MASK) {
2008 /* break/unnattached error bits or real input? */
2009 if (!(line_status & LSR_RXRDY))
2010 recv_data = 0;
2011 else
2012 recv_data = inb(com->data_port);
2013#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
2014 /*
2015 * Solaris implements a new BREAK which is initiated
2016 * by a character sequence CR ~ ^b which is similar
2017 * to a familiar pattern used on Sun servers by the
2018 * Remote Console.
2019 */
2020#define KEY_CRTLB 2 /* ^B */
2021#define KEY_CR 13 /* CR '\r' */
2022#define KEY_TILDE 126 /* ~ */
2023
2024 if (com->unit == comconsole) {
2025 static int brk_state1 = 0, brk_state2 = 0;
2026 if (recv_data == KEY_CR) {
2027 brk_state1 = recv_data;
2028 brk_state2 = 0;
2029 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) {
2030 if (recv_data == KEY_TILDE)
2031 brk_state2 = recv_data;
2032 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) {
2033 breakpoint();
2034 brk_state1 = brk_state2 = 0;
2035 goto cont;
2036 } else
2037 brk_state2 = 0;
2038 } else
2039 brk_state1 = 0;
2040 }
2041#endif
2042 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2043 /*
2044 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2045 * Otherwise, push the work to a higher level
2046 * (to handle PARMRK) if we're bypassing.
2047 * Otherwise, convert BI/FE and PE+INPCK to 0.
2048 *
2049 * This makes bypassing work right in the
2050 * usual "raw" case (IGNBRK set, and IGNPAR
2051 * and INPCK clear).
2052 *
2053 * Note: BI together with FE/PE means just BI.
2054 */
2055 if (line_status & LSR_BI) {
2056#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2057 if (com->unit == comconsole) {
2058 breakpoint();
2059 goto cont;
2060 }
2061#endif
2062 if (com->tp == NULL
2063 || com->tp->t_iflag & IGNBRK)
2064 goto cont;
2065 } else {
2066 if (com->tp == NULL
2067 || com->tp->t_iflag & IGNPAR)
2068 goto cont;
2069 }
2070 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2071 && (line_status & (LSR_BI | LSR_FE)
2072 || com->tp->t_iflag & INPCK))
2073 recv_data = 0;
2074 }
2075 ++com->bytes_in;
2076 if (com->hotchar != 0 && recv_data == com->hotchar)
2077 setsofttty();
2078 ioptr = com->iptr;
2079 if (ioptr >= com->ibufend)
2080 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2081 else {
2082 if (com->do_timestamp)
2083 microtime(&com->timestamp);
2084 ++com_events;
2085 schedsofttty();
2086#if 0 /* for testing input latency vs efficiency */
2087if (com->iptr - com->ibuf == 8)
2088 setsofttty();
2089#endif
2090 ioptr[0] = recv_data;
2091 ioptr[com->ierroff] = line_status;
2092 com->iptr = ++ioptr;
2093 if (ioptr == com->ihighwater
2094 && com->state & CS_RTS_IFLOW)
2095 outb(com->modem_ctl_port,
2096 com->mcr_image &= ~MCR_RTS);
2097 if (line_status & LSR_OE)
2098 CE_RECORD(com, CE_OVERRUN);
2099 }
2100cont:
2101 /*
2102 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2103 * jump from the top of the loop to here
2104 */
2105 line_status = inb(com->line_status_port) & 0x7F;
2106 }
2107
2108 /* modem status change? (always check before doing output) */
2109 modem_status = inb(com->modem_status_port);
2110 if (modem_status != com->last_modem_status) {
2111 if (com->do_dcd_timestamp
2112 && !(com->last_modem_status & MSR_DCD)
2113 && modem_status & MSR_DCD)
2114 microtime(&com->dcd_timestamp);
2115
2116 /*
2117 * Schedule high level to handle DCD changes. Note
2118 * that we don't use the delta bits anywhere. Some
2119 * UARTs mess them up, and it's easy to remember the
2120 * previous bits and calculate the delta.
2121 */
2122 com->last_modem_status = modem_status;
2123 if (!(com->state & CS_CHECKMSR)) {
2124 com_events += LOTS_OF_EVENTS;
2125 com->state |= CS_CHECKMSR;
2126 setsofttty();
2127 }
2128
2129 /* handle CTS change immediately for crisp flow ctl */
2130 if (com->state & CS_CTS_OFLOW) {
2131 if (modem_status & MSR_CTS)
2132 com->state |= CS_ODEVREADY;
2133 else
2134 com->state &= ~CS_ODEVREADY;
2135 }
2136 }
2137
2138 /* output queued and everything ready? */
2139 if (line_status & LSR_TXRDY
2140 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2141 ioptr = com->obufq.l_head;
2142 if (com->tx_fifo_size > 1) {
2143 u_int ocount;
2144
2145 ocount = com->obufq.l_tail - ioptr;
2146 if (ocount > com->tx_fifo_size)
2147 ocount = com->tx_fifo_size;
2148 com->bytes_out += ocount;
2149 do
2150 outb(com->data_port, *ioptr++);
2151 while (--ocount != 0);
2152 } else {
2153 outb(com->data_port, *ioptr++);
2154 ++com->bytes_out;
2155 }
2156 com->obufq.l_head = ioptr;
2157 if (COM_IIR_TXRDYBUG(com->flags)) {
2158 int_ctl_new = int_ctl | IER_ETXRDY;
2159 }
2160 if (ioptr >= com->obufq.l_tail) {
2161 struct lbq *qp;
2162
2163 qp = com->obufq.l_next;
2164 qp->l_queued = FALSE;
2165 qp = qp->l_next;
2166 if (qp != NULL) {
2167 com->obufq.l_head = qp->l_head;
2168 com->obufq.l_tail = qp->l_tail;
2169 com->obufq.l_next = qp;
2170 } else {
2171 /* output just completed */
2172 if (COM_IIR_TXRDYBUG(com->flags)) {
2173 int_ctl_new = int_ctl & ~IER_ETXRDY;
2174 }
2175 com->state &= ~CS_BUSY;
2176 }
2177 if (!(com->state & CS_ODONE)) {
2178 com_events += LOTS_OF_EVENTS;
2179 com->state |= CS_ODONE;
2180 setsofttty(); /* handle at high level ASAP */
2181 }
2182 }
2183 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2184 outb(com->intr_ctl_port, int_ctl_new);
2185 }
2186 }
2187
2188 /* finished? */
2189#ifndef COM_MULTIPORT
2190 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2191#endif /* COM_MULTIPORT */
2192 return;
2193 }
2194}
2195
2196static int
41c20dac 2197sioioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc
MD
2198{
2199 struct com_s *com;
2200 int error;
2201 int mynor;
2202 int s;
2203 struct tty *tp;
2204#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2205 u_long oldcmd;
2206 struct termios term;
2207#endif
2208
2209 mynor = minor(dev);
2210 com = com_addr(MINOR_TO_UNIT(mynor));
2211 if (com == NULL || com->gone)
2212 return (ENODEV);
2213 if (mynor & CONTROL_MASK) {
2214 struct termios *ct;
2215
2216 switch (mynor & CONTROL_MASK) {
2217 case CONTROL_INIT_STATE:
2218 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2219 break;
2220 case CONTROL_LOCK_STATE:
2221 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2222 break;
2223 default:
2224 return (ENODEV); /* /dev/nodev */
2225 }
2226 switch (cmd) {
2227 case TIOCSETA:
41c20dac 2228 error = suser_xxx(td->td_proc->p_ucred, 0);
984263bc
MD
2229 if (error != 0)
2230 return (error);
2231 *ct = *(struct termios *)data;
2232 return (0);
2233 case TIOCGETA:
2234 *(struct termios *)data = *ct;
2235 return (0);
2236 case TIOCGETD:
2237 *(int *)data = TTYDISC;
2238 return (0);
2239 case TIOCGWINSZ:
2240 bzero(data, sizeof(struct winsize));
2241 return (0);
2242 default:
2243 return (ENOTTY);
2244 }
2245 }
2246 tp = com->tp;
2247#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2248 term = tp->t_termios;
2249 oldcmd = cmd;
2250 error = ttsetcompat(tp, &cmd, data, &term);
2251 if (error != 0)
2252 return (error);
2253 if (cmd != oldcmd)
2254 data = (caddr_t)&term;
2255#endif
2256 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2257 int cc;
2258 struct termios *dt = (struct termios *)data;
2259 struct termios *lt = mynor & CALLOUT_MASK
2260 ? &com->lt_out : &com->lt_in;
2261
2262 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2263 | (dt->c_iflag & ~lt->c_iflag);
2264 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2265 | (dt->c_oflag & ~lt->c_oflag);
2266 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2267 | (dt->c_cflag & ~lt->c_cflag);
2268 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2269 | (dt->c_lflag & ~lt->c_lflag);
2270 for (cc = 0; cc < NCCS; ++cc)
2271 if (lt->c_cc[cc] != 0)
2272 dt->c_cc[cc] = tp->t_cc[cc];
2273 if (lt->c_ispeed != 0)
2274 dt->c_ispeed = tp->t_ispeed;
2275 if (lt->c_ospeed != 0)
2276 dt->c_ospeed = tp->t_ospeed;
2277 }
41c20dac 2278 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
984263bc
MD
2279 if (error != ENOIOCTL)
2280 return (error);
2281 s = spltty();
2282 error = ttioctl(tp, cmd, data, flag);
2283 disc_optim(tp, &tp->t_termios, com);
2284 if (error != ENOIOCTL) {
2285 splx(s);
2286 return (error);
2287 }
2288 switch (cmd) {
2289 case TIOCSBRK:
2290 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2291 break;
2292 case TIOCCBRK:
2293 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2294 break;
2295 case TIOCSDTR:
2296 (void)commctl(com, TIOCM_DTR, DMBIS);
2297 break;
2298 case TIOCCDTR:
2299 (void)commctl(com, TIOCM_DTR, DMBIC);
2300 break;
2301 /*
2302 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2303 * changes get undone on the next call to comparam().
2304 */
2305 case TIOCMSET:
2306 (void)commctl(com, *(int *)data, DMSET);
2307 break;
2308 case TIOCMBIS:
2309 (void)commctl(com, *(int *)data, DMBIS);
2310 break;
2311 case TIOCMBIC:
2312 (void)commctl(com, *(int *)data, DMBIC);
2313 break;
2314 case TIOCMGET:
2315 *(int *)data = commctl(com, 0, DMGET);
2316 break;
2317 case TIOCMSDTRWAIT:
2318 /* must be root since the wait applies to following logins */
41c20dac 2319 error = suser_xxx(td->td_proc->p_ucred, 0);
984263bc
MD
2320 if (error != 0) {
2321 splx(s);
2322 return (error);
2323 }
2324 com->dtr_wait = *(int *)data * hz / 100;
2325 break;
2326 case TIOCMGDTRWAIT:
2327 *(int *)data = com->dtr_wait * 100 / hz;
2328 break;
2329 case TIOCTIMESTAMP:
2330 com->do_timestamp = TRUE;
2331 *(struct timeval *)data = com->timestamp;
2332 break;
2333 case TIOCDCDTIMESTAMP:
2334 com->do_dcd_timestamp = TRUE;
2335 *(struct timeval *)data = com->dcd_timestamp;
2336 break;
2337 default:
2338 splx(s);
2339 error = pps_ioctl(cmd, data, &com->pps);
2340 if (error == ENODEV)
2341 error = ENOTTY;
2342 return (error);
2343 }
2344 splx(s);
2345 return (0);
2346}
2347
2348static void
2349siopoll()
2350{
2351 int unit;
2352
2353 if (com_events == 0)
2354 return;
2355repeat:
2356 for (unit = 0; unit < sio_numunits; ++unit) {
2357 struct com_s *com;
2358 int incc;
2359 struct tty *tp;
2360
2361 com = com_addr(unit);
2362 if (com == NULL)
2363 continue;
2364 tp = com->tp;
2365 if (tp == NULL || com->gone) {
2366 /*
2367 * Discard any events related to never-opened or
2368 * going-away devices.
2369 */
2370 disable_intr();
2371 incc = com->iptr - com->ibuf;
2372 com->iptr = com->ibuf;
2373 if (com->state & CS_CHECKMSR) {
2374 incc += LOTS_OF_EVENTS;
2375 com->state &= ~CS_CHECKMSR;
2376 }
2377 com_events -= incc;
2378 enable_intr();
2379 continue;
2380 }
2381 if (com->iptr != com->ibuf) {
2382 disable_intr();
2383 sioinput(com);
2384 enable_intr();
2385 }
2386 if (com->state & CS_CHECKMSR) {
2387 u_char delta_modem_status;
2388
2389 disable_intr();
2390 delta_modem_status = com->last_modem_status
2391 ^ com->prev_modem_status;
2392 com->prev_modem_status = com->last_modem_status;
2393 com_events -= LOTS_OF_EVENTS;
2394 com->state &= ~CS_CHECKMSR;
2395 enable_intr();
2396 if (delta_modem_status & MSR_DCD)
2397 (*linesw[tp->t_line].l_modem)
2398 (tp, com->prev_modem_status & MSR_DCD);
2399 }
2400 if (com->state & CS_ODONE) {
2401 disable_intr();
2402 com_events -= LOTS_OF_EVENTS;
2403 com->state &= ~CS_ODONE;
2404 enable_intr();
2405 if (!(com->state & CS_BUSY)
2406 && !(com->extra_state & CSE_BUSYCHECK)) {
2407 timeout(siobusycheck, com, hz / 100);
2408 com->extra_state |= CSE_BUSYCHECK;
2409 }
2410 (*linesw[tp->t_line].l_start)(tp);
2411 }
2412 if (com_events == 0)
2413 break;
2414 }
2415 if (com_events >= LOTS_OF_EVENTS)
2416 goto repeat;
2417}
2418
2419static int
2420comparam(tp, t)
2421 struct tty *tp;
2422 struct termios *t;
2423{
2424 u_int cfcr;
2425 int cflag;
2426 struct com_s *com;
2427 u_int divisor;
2428 u_char dlbh;
2429 u_char dlbl;
2430 int s;
2431 int unit;
2432
2433 unit = DEV_TO_UNIT(tp->t_dev);
2434 com = com_addr(unit);
2435 if (com == NULL)
2436 return (ENODEV);
2437
2438 /* do historical conversions */
2439 if (t->c_ispeed == 0)
2440 t->c_ispeed = t->c_ospeed;
2441
2442 /* check requested parameters */
2443 if (t->c_ospeed == 0)
2444 divisor = 0;
2445 else {
2446 if (t->c_ispeed != t->c_ospeed)
2447 return (EINVAL);
2448 divisor = siodivisor(com->rclk, t->c_ispeed);
2449 if (divisor == 0)
2450 return (EINVAL);
2451 }
2452
2453 /* parameters are OK, convert them to the com struct and the device */
2454 s = spltty();
2455 if (divisor == 0)
2456 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2457 else
2458 (void)commctl(com, TIOCM_DTR, DMBIS);
2459 cflag = t->c_cflag;
2460 switch (cflag & CSIZE) {
2461 case CS5:
2462 cfcr = CFCR_5BITS;
2463 break;
2464 case CS6:
2465 cfcr = CFCR_6BITS;
2466 break;
2467 case CS7:
2468 cfcr = CFCR_7BITS;
2469 break;
2470 default:
2471 cfcr = CFCR_8BITS;
2472 break;
2473 }
2474 if (cflag & PARENB) {
2475 cfcr |= CFCR_PENAB;
2476 if (!(cflag & PARODD))
2477 cfcr |= CFCR_PEVEN;
2478 }
2479 if (cflag & CSTOPB)
2480 cfcr |= CFCR_STOPB;
2481
2482 if (com->hasfifo && divisor != 0) {
2483 /*
2484 * Use a fifo trigger level low enough so that the input
2485 * latency from the fifo is less than about 16 msec and
2486 * the total latency is less than about 30 msec. These
2487 * latencies are reasonable for humans. Serial comms
2488 * protocols shouldn't expect anything better since modem
2489 * latencies are larger.
2490 *
2491 * Interrupts can be held up for long periods of time
2492 * due to inefficiencies in other parts of the kernel,
2493 * certain video cards, etc. Setting the FIFO trigger
2494 * point to MEDH instead of HIGH gives us 694uS of slop
2495 * (8 character times) instead of 173uS (2 character times)
2496 * @ 115200 bps.
2497 */
2498 com->fifo_image = t->c_ospeed <= 4800
2499 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2500#ifdef COM_ESP
2501 /*
2502 * The Hayes ESP card needs the fifo DMA mode bit set
2503 * in compatibility mode. If not, it will interrupt
2504 * for each character received.
2505 */
2506 if (com->esp)
2507 com->fifo_image |= FIFO_DMA_MODE;
2508#endif
2509 sio_setreg(com, com_fifo, com->fifo_image);
2510 }
2511
2512 /*
2513 * This returns with interrupts disabled so that we can complete
2514 * the speed change atomically. Keeping interrupts disabled is
2515 * especially important while com_data is hidden.
2516 */
2517 (void) siosetwater(com, t->c_ispeed);
2518
2519 if (divisor != 0) {
2520 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2521 /*
2522 * Only set the divisor registers if they would change,
2523 * since on some 16550 incompatibles (UMC8669F), setting
2524 * them while input is arriving them loses sync until
2525 * data stops arriving.
2526 */
2527 dlbl = divisor & 0xFF;
2528 if (sio_getreg(com, com_dlbl) != dlbl)
2529 sio_setreg(com, com_dlbl, dlbl);
2530 dlbh = divisor >> 8;
2531 if (sio_getreg(com, com_dlbh) != dlbh)
2532 sio_setreg(com, com_dlbh, dlbh);
2533 }
2534
2535 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2536
2537 if (!(tp->t_state & TS_TTSTOP))
2538 com->state |= CS_TTGO;
2539
2540 if (cflag & CRTS_IFLOW) {
2541 if (com->st16650a) {
2542 sio_setreg(com, com_cfcr, 0xbf);
2543 sio_setreg(com, com_fifo,
2544 sio_getreg(com, com_fifo) | 0x40);
2545 }
2546 com->state |= CS_RTS_IFLOW;
2547 /*
2548 * If CS_RTS_IFLOW just changed from off to on, the change
2549 * needs to be propagated to MCR_RTS. This isn't urgent,
2550 * so do it later by calling comstart() instead of repeating
2551 * a lot of code from comstart() here.
2552 */
2553 } else if (com->state & CS_RTS_IFLOW) {
2554 com->state &= ~CS_RTS_IFLOW;
2555 /*
2556 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2557 * on here, since comstart() won't do it later.
2558 */
2559 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2560 if (com->st16650a) {
2561 sio_setreg(com, com_cfcr, 0xbf);
2562 sio_setreg(com, com_fifo,
2563 sio_getreg(com, com_fifo) & ~0x40);
2564 }
2565 }
2566
2567
2568 /*
2569 * Set up state to handle output flow control.
2570 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2571 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2572 */
2573 com->state |= CS_ODEVREADY;
2574 com->state &= ~CS_CTS_OFLOW;
2575 if (cflag & CCTS_OFLOW) {
2576 com->state |= CS_CTS_OFLOW;
2577 if (!(com->last_modem_status & MSR_CTS))
2578 com->state &= ~CS_ODEVREADY;
2579 if (com->st16650a) {
2580 sio_setreg(com, com_cfcr, 0xbf);
2581 sio_setreg(com, com_fifo,
2582 sio_getreg(com, com_fifo) | 0x80);
2583 }
2584 } else {
2585 if (com->st16650a) {
2586 sio_setreg(com, com_cfcr, 0xbf);
2587 sio_setreg(com, com_fifo,
2588 sio_getreg(com, com_fifo) & ~0x80);
2589 }
2590 }
2591
2592 sio_setreg(com, com_cfcr, com->cfcr_image);
2593
2594 /* XXX shouldn't call functions while intrs are disabled. */
2595 disc_optim(tp, t, com);
2596 /*
2597 * Recover from fiddling with CS_TTGO. We used to call siointr1()
2598 * unconditionally, but that defeated the careful discarding of
2599 * stale input in sioopen().
2600 */
2601 if (com->state >= (CS_BUSY | CS_TTGO))
2602 siointr1(com);
2603
2604 enable_intr();
2605 splx(s);
2606 comstart(tp);
2607 if (com->ibufold != NULL) {
2608 free(com->ibufold, M_DEVBUF);
2609 com->ibufold = NULL;
2610 }
2611 return (0);
2612}
2613
2614static int
2615siosetwater(com, speed)
2616 struct com_s *com;
2617 speed_t speed;
2618{
2619 int cp4ticks;
2620 u_char *ibuf;
2621 int ibufsize;
2622 struct tty *tp;
2623
2624 /*
2625 * Make the buffer size large enough to handle a softtty interrupt
2626 * latency of about 2 ticks without loss of throughput or data
2627 * (about 3 ticks if input flow control is not used or not honoured,
2628 * but a bit less for CS5-CS7 modes).
2629 */
2630 cp4ticks = speed / 10 / hz * 4;
2631 for (ibufsize = 128; ibufsize < cp4ticks;)
2632 ibufsize <<= 1;
2633 if (ibufsize == com->ibufsize) {
2634 disable_intr();
2635 return (0);
2636 }
2637
2638 /*
2639 * Allocate input buffer. The extra factor of 2 in the size is
2640 * to allow for an error byte for each input byte.
2641 */
2642 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2643 if (ibuf == NULL) {
2644 disable_intr();
2645 return (ENOMEM);
2646 }
2647
2648 /* Initialize non-critical variables. */
2649 com->ibufold = com->ibuf;
2650 com->ibufsize = ibufsize;
2651 tp = com->tp;
2652 if (tp != NULL) {
2653 tp->t_ififosize = 2 * ibufsize;
2654 tp->t_ispeedwat = (speed_t)-1;
2655 tp->t_ospeedwat = (speed_t)-1;
2656 }
2657
2658 /*
2659 * Read current input buffer, if any. Continue with interrupts
2660 * disabled.
2661 */
2662 disable_intr();
2663 if (com->iptr != com->ibuf)
2664 sioinput(com);
2665
2666 /*-
2667 * Initialize critical variables, including input buffer watermarks.
2668 * The external device is asked to stop sending when the buffer
2669 * exactly reaches high water, or when the high level requests it.
2670 * The high level is notified immediately (rather than at a later
2671 * clock tick) when this watermark is reached.
2672 * The buffer size is chosen so the watermark should almost never
2673 * be reached.
2674 * The low watermark is invisibly 0 since the buffer is always
2675 * emptied all at once.
2676 */
2677 com->iptr = com->ibuf = ibuf;
2678 com->ibufend = ibuf + ibufsize;
2679 com->ierroff = ibufsize;
2680 com->ihighwater = ibuf + 3 * ibufsize / 4;
2681 return (0);
2682}
2683
2684static void
2685comstart(tp)
2686 struct tty *tp;
2687{
2688 struct com_s *com;
2689 int s;
2690 int unit;
2691
2692 unit = DEV_TO_UNIT(tp->t_dev);
2693 com = com_addr(unit);
2694 if (com == NULL)
2695 return;
2696 s = spltty();
2697 disable_intr();
2698 if (tp->t_state & TS_TTSTOP)
2699 com->state &= ~CS_TTGO;
2700 else
2701 com->state |= CS_TTGO;
2702 if (tp->t_state & TS_TBLOCK) {
2703 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2704 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2705 } else {
2706 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2707 && com->state & CS_RTS_IFLOW)
2708 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2709 }
2710 enable_intr();
2711 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2712 ttwwakeup(tp);
2713 splx(s);
2714 return;
2715 }
2716 if (tp->t_outq.c_cc != 0) {
2717 struct lbq *qp;
2718 struct lbq *next;
2719
2720 if (!com->obufs[0].l_queued) {
2721 com->obufs[0].l_tail
2722 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2723 sizeof com->obuf1);
2724 com->obufs[0].l_next = NULL;
2725 com->obufs[0].l_queued = TRUE;
2726 disable_intr();
2727 if (com->state & CS_BUSY) {
2728 qp = com->obufq.l_next;
2729 while ((next = qp->l_next) != NULL)
2730 qp = next;
2731 qp->l_next = &com->obufs[0];
2732 } else {
2733 com->obufq.l_head = com->obufs[0].l_head;
2734 com->obufq.l_tail = com->obufs[0].l_tail;
2735 com->obufq.l_next = &com->obufs[0];
2736 com->state |= CS_BUSY;
2737 }
2738 enable_intr();
2739 }
2740 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2741 com->obufs[1].l_tail
2742 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2743 sizeof com->obuf2);
2744 com->obufs[1].l_next = NULL;
2745 com->obufs[1].l_queued = TRUE;
2746 disable_intr();
2747 if (com->state & CS_BUSY) {
2748 qp = com->obufq.l_next;
2749 while ((next = qp->l_next) != NULL)
2750 qp = next;
2751 qp->l_next = &com->obufs[1];
2752 } else {
2753 com->obufq.l_head = com->obufs[1].l_head;
2754 com->obufq.l_tail = com->obufs[1].l_tail;
2755 com->obufq.l_next = &com->obufs[1];
2756 com->state |= CS_BUSY;
2757 }
2758 enable_intr();
2759 }
2760 tp->t_state |= TS_BUSY;
2761 }
2762 disable_intr();
2763 if (com->state >= (CS_BUSY | CS_TTGO))
2764 siointr1(com); /* fake interrupt to start output */
2765 enable_intr();
2766 ttwwakeup(tp);
2767 splx(s);
2768}
2769
2770static void
2771comstop(tp, rw)
2772 struct tty *tp;
2773 int rw;
2774{
2775 struct com_s *com;
2776
2777 com = com_addr(DEV_TO_UNIT(tp->t_dev));
2778 if (com == NULL || com->gone)
2779 return;
2780 disable_intr();
2781 if (rw & FWRITE) {
2782 if (com->hasfifo)
2783#ifdef COM_ESP
2784 /* XXX avoid h/w bug. */
2785 if (!com->esp)
2786#endif
2787 sio_setreg(com, com_fifo,
2788 FIFO_XMT_RST | com->fifo_image);
2789 com->obufs[0].l_queued = FALSE;
2790 com->obufs[1].l_queued = FALSE;
2791 if (com->state & CS_ODONE)
2792 com_events -= LOTS_OF_EVENTS;
2793 com->state &= ~(CS_ODONE | CS_BUSY);
2794 com->tp->t_state &= ~TS_BUSY;
2795 }
2796 if (rw & FREAD) {
2797 if (com->hasfifo)
2798#ifdef COM_ESP
2799 /* XXX avoid h/w bug. */
2800 if (!com->esp)
2801#endif
2802 sio_setreg(com, com_fifo,
2803 FIFO_RCV_RST | com->fifo_image);
2804 com_events -= (com->iptr - com->ibuf);
2805 com->iptr = com->ibuf;
2806 }
2807 enable_intr();
2808 comstart(tp);
2809}
2810
2811static int
2812commctl(com, bits, how)
2813 struct com_s *com;
2814 int bits;
2815 int how;
2816{
2817 int mcr;
2818 int msr;
2819
2820 if (how == DMGET) {
2821 bits = TIOCM_LE; /* XXX - always enabled while open */
2822 mcr = com->mcr_image;
2823 if (mcr & MCR_DTR)
2824 bits |= TIOCM_DTR;
2825 if (mcr & MCR_RTS)
2826 bits |= TIOCM_RTS;
2827 msr = com->prev_modem_status;
2828 if (msr & MSR_CTS)
2829 bits |= TIOCM_CTS;
2830 if (msr & MSR_DCD)
2831 bits |= TIOCM_CD;
2832 if (msr & MSR_DSR)
2833 bits |= TIOCM_DSR;
2834 /*
2835 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2836 * more volatile by reading the modem status a lot. Perhaps
2837 * we should latch both bits until the status is read here.
2838 */
2839 if (msr & (MSR_RI | MSR_TERI))
2840 bits |= TIOCM_RI;
2841 return (bits);
2842 }
2843 mcr = 0;
2844 if (bits & TIOCM_DTR)
2845 mcr |= MCR_DTR;
2846 if (bits & TIOCM_RTS)
2847 mcr |= MCR_RTS;
2848 if (com->gone)
2849 return(0);
2850 disable_intr();
2851 switch (how) {
2852 case DMSET:
2853 outb(com->modem_ctl_port,
2854 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2855 break;
2856 case DMBIS:
2857 outb(com->modem_ctl_port, com->mcr_image |= mcr);
2858 break;
2859 case DMBIC:
2860 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2861 break;
2862 }
2863 enable_intr();
2864 return (0);
2865}
2866
2867static void
2868siosettimeout()
2869{
2870 struct com_s *com;
2871 bool_t someopen;
2872 int unit;
2873
2874 /*
2875 * Set our timeout period to 1 second if no polled devices are open.
2876 * Otherwise set it to max(1/200, 1/hz).
2877 * Enable timeouts iff some device is open.
2878 */
2879 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2880 sio_timeout = hz;
2881 someopen = FALSE;
2882 for (unit = 0; unit < sio_numunits; ++unit) {
2883 com = com_addr(unit);
2884 if (com != NULL && com->tp != NULL
2885 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2886 someopen = TRUE;
2887 if (com->poll || com->poll_output) {
2888 sio_timeout = hz > 200 ? hz / 200 : 1;
2889 break;
2890 }
2891 }
2892 }
2893 if (someopen) {
2894 sio_timeouts_until_log = hz / sio_timeout;
2895 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2896 sio_timeout);
2897 } else {
2898 /* Flush error messages, if any. */
2899 sio_timeouts_until_log = 1;
2900 comwakeup((void *)NULL);
2901 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2902 }
2903}
2904
2905static void
2906comwakeup(chan)
2907 void *chan;
2908{
2909 struct com_s *com;
2910 int unit;
2911
2912 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2913
2914 /*
2915 * Recover from lost output interrupts.
2916 * Poll any lines that don't use interrupts.
2917 */
2918 for (unit = 0; unit < sio_numunits; ++unit) {
2919 com = com_addr(unit);
2920 if (com != NULL && !com->gone
2921 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2922 disable_intr();
2923 siointr1(com);
2924 enable_intr();
2925 }
2926 }
2927
2928 /*
2929 * Check for and log errors, but not too often.
2930 */
2931 if (--sio_timeouts_until_log > 0)
2932 return;
2933 sio_timeouts_until_log = hz / sio_timeout;
2934 for (unit = 0; unit < sio_numunits; ++unit) {
2935 int errnum;
2936
2937 com = com_addr(unit);
2938 if (com == NULL)
2939 continue;
2940 if (com->gone)
2941 continue;
2942 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2943 u_int delta;
2944 u_long total;
2945
2946 disable_intr();
2947 delta = com->delta_error_counts[errnum];
2948 com->delta_error_counts[errnum] = 0;
2949 enable_intr();
2950 if (delta == 0)
2951 continue;
2952 total = com->error_counts[errnum] += delta;
2953 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2954 unit, delta, error_desc[errnum],
2955 delta == 1 ? "" : "s", total);
2956 }
2957 }
2958}
2959
2960static void
2961disc_optim(tp, t, com)
2962 struct tty *tp;
2963 struct termios *t;
2964 struct com_s *com;
2965{
2966 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2967 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2968 && (!(t->c_iflag & PARMRK)
2969 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2970 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2971 && linesw[tp->t_line].l_rint == ttyinput)
2972 tp->t_state |= TS_CAN_BYPASS_L_RINT;
2973 else
2974 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2975 com->hotchar = linesw[tp->t_line].l_hotchar;
2976}
2977
2978/*
2979 * Following are all routines needed for SIO to act as console
2980 */
2981#include <sys/cons.h>
2982
2983struct siocnstate {
2984 u_char dlbl;
2985 u_char dlbh;
2986 u_char ier;
2987 u_char cfcr;
2988 u_char mcr;
2989};
2990
2991static speed_t siocngetspeed __P((Port_t, u_long rclk));
2992static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
2993static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
2994static void siocntxwait __P((Port_t iobase));
2995
2996static cn_probe_t siocnprobe;
2997static cn_init_t siocninit;
2998static cn_checkc_t siocncheckc;
2999static cn_getc_t siocngetc;
3000static cn_putc_t siocnputc;
3001
3002#ifdef __i386__
3003CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc,
3004 siocnputc, NULL);
3005#endif
3006
3007/* To get the GDB related variables */
3008#if DDB > 0
3009#include <ddb/ddb.h>
3010#endif
3011
3012static void
3013siocntxwait(iobase)
3014 Port_t iobase;
3015{
3016 int timo;
3017
3018 /*
3019 * Wait for any pending transmission to finish. Required to avoid
3020 * the UART lockup bug when the speed is changed, and for normal
3021 * transmits.
3022 */
3023 timo = 100000;
3024 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3025 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3026 ;
3027}
3028
3029/*
3030 * Read the serial port specified and try to figure out what speed
3031 * it's currently running at. We're assuming the serial port has
3032 * been initialized and is basicly idle. This routine is only intended
3033 * to be run at system startup.
3034 *
3035 * If the value read from the serial port doesn't make sense, return 0.
3036 */
3037
3038static speed_t
3039siocngetspeed(iobase, rclk)
3040 Port_t iobase;
3041 u_long rclk;
3042{
3043 u_int divisor;
3044 u_char dlbh;
3045 u_char dlbl;
3046 u_char cfcr;
3047
3048 cfcr = inb(iobase + com_cfcr);
3049 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3050
3051 dlbl = inb(iobase + com_dlbl);
3052 dlbh = inb(iobase + com_dlbh);
3053
3054 outb(iobase + com_cfcr, cfcr);
3055
3056 divisor = dlbh << 8 | dlbl;
3057
3058 /* XXX there should be more sanity checking. */
3059 if (divisor == 0)
3060 return (CONSPEED);
3061 return (rclk / (16UL * divisor));
3062}
3063
3064static void
3065siocnopen(sp, iobase, speed)
3066 struct siocnstate *sp;
3067 Port_t iobase;
3068 int speed;
3069{
3070 u_int divisor;
3071 u_char dlbh;
3072 u_char dlbl;
3073
3074 /*
3075 * Save all the device control registers except the fifo register
3076 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3077 * We can't save the fifo register since it is read-only.
3078 */
3079 sp->ier = inb(iobase + com_ier);
3080 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3081 siocntxwait(iobase);
3082 sp->cfcr = inb(iobase + com_cfcr);
3083 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3084 sp->dlbl = inb(iobase + com_dlbl);
3085 sp->dlbh = inb(iobase + com_dlbh);
3086 /*
3087 * Only set the divisor registers if they would change, since on
3088 * some 16550 incompatibles (Startech), setting them clears the
3089 * data input register. This also reduces the effects of the
3090 * UMC8669F bug.
3091 */
3092 divisor = siodivisor(comdefaultrclk, speed);
3093 dlbl = divisor & 0xFF;
3094 if (sp->dlbl != dlbl)
3095 outb(iobase + com_dlbl, dlbl);
3096 dlbh = divisor >> 8;
3097 if (sp->dlbh != dlbh)
3098 outb(iobase + com_dlbh, dlbh);
3099 outb(iobase + com_cfcr, CFCR_8BITS);
3100 sp->mcr = inb(iobase + com_mcr);
3101 /*
3102 * We don't want interrupts, but must be careful not to "disable"
3103 * them by clearing the MCR_IENABLE bit, since that might cause
3104 * an interrupt by floating the IRQ line.
3105 */
3106 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3107}
3108
3109static void
3110siocnclose(sp, iobase)
3111 struct siocnstate *sp;
3112 Port_t iobase;
3113{
3114 /*
3115 * Restore the device control registers.
3116 */
3117 siocntxwait(iobase);
3118 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3119 if (sp->dlbl != inb(iobase + com_dlbl))
3120 outb(iobase + com_dlbl, sp->dlbl);
3121 if (sp->dlbh != inb(iobase + com_dlbh))
3122 outb(iobase + com_dlbh, sp->dlbh);
3123 outb(iobase + com_cfcr, sp->cfcr);
3124 /*
3125 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3126 */
3127 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3128 outb(iobase + com_ier, sp->ier);
3129}
3130
3131static void
3132siocnprobe(cp)
3133 struct consdev *cp;
3134{
3135 speed_t boot_speed;
3136 u_char cfcr;
3137 u_int divisor;
3138 int s, unit;
3139 struct siocnstate sp;
3140
3141 /*
3142 * Find our first enabled console, if any. If it is a high-level
3143 * console device, then initialize it and return successfully.
3144 * If it is a low-level console device, then initialize it and
3145 * return unsuccessfully. It must be initialized in both cases
3146 * for early use by console drivers and debuggers. Initializing
3147 * the hardware is not necessary in all cases, since the i/o
3148 * routines initialize it on the fly, but it is necessary if
3149 * input might arrive while the hardware is switched back to an
3150 * uninitialized state. We can't handle multiple console devices
3151 * yet because our low-level routines don't take a device arg.
3152 * We trust the user to set the console flags properly so that we
3153 * don't need to probe.
3154 */
3155 cp->cn_pri = CN_DEAD;
3156
3157 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
3158 int flags;
3159 int disabled;
3160 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
3161 if (disabled)
3162 continue;
3163 }
3164 if (resource_int_value("sio", unit, "flags", &flags))
3165 continue;
3166 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
3167 int port;
3168 Port_t iobase;
3169
3170 if (resource_int_value("sio", unit, "port", &port))
3171 continue;
3172 iobase = port;
3173 s = spltty();
3174 if (boothowto & RB_SERIAL) {
3175 boot_speed =
3176 siocngetspeed(iobase, comdefaultrclk);
3177 if (boot_speed)
3178 comdefaultrate = boot_speed;
3179 }
3180
3181 /*
3182 * Initialize the divisor latch. We can't rely on
3183 * siocnopen() to do this the first time, since it
3184 * avoids writing to the latch if the latch appears
3185 * to have the correct value. Also, if we didn't
3186 * just read the speed from the hardware, then we
3187 * need to set the speed in hardware so that
3188 * switching it later is null.
3189 */
3190 cfcr = inb(iobase + com_cfcr);
3191 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3192 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3193 outb(iobase + com_dlbl, divisor & 0xff);
3194 outb(iobase + com_dlbh, divisor >> 8);
3195 outb(iobase + com_cfcr, cfcr);
3196
3197 siocnopen(&sp, iobase, comdefaultrate);
3198
3199 splx(s);
3200 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
3201 cp->cn_dev = makedev(CDEV_MAJOR, unit);
3202 cp->cn_pri = COM_FORCECONSOLE(flags)
3203 || boothowto & RB_SERIAL
3204 ? CN_REMOTE : CN_NORMAL;
3205 siocniobase = iobase;
3206 siocnunit = unit;
3207 }
3208 if (COM_DEBUGGER(flags)) {
3209 printf("sio%d: gdb debugging port\n", unit);
3210 siogdbiobase = iobase;
3211 siogdbunit = unit;
3212#if DDB > 0
3213 gdbdev = makedev(CDEV_MAJOR, unit);
3214 gdb_getc = siocngetc;
3215 gdb_putc = siocnputc;
3216#endif
3217 }
3218 }
3219 }
3220#ifdef __i386__
3221#if DDB > 0
3222 /*
3223 * XXX Ugly Compatability.
3224 * If no gdb port has been specified, set it to be the console
3225 * as some configuration files don't specify the gdb port.
3226 */
3227 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
3228 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
3229 siocnunit);
3230 printf("Set flag 0x80 on desired GDB port in your\n");
3231 printf("configuration file (currently sio only).\n");
3232 siogdbiobase = siocniobase;
3233 siogdbunit = siocnunit;
3234 gdbdev = makedev(CDEV_MAJOR, siocnunit);
3235 gdb_getc = siocngetc;
3236 gdb_putc = siocnputc;
3237 }
3238#endif
3239#endif
3240}
3241
3242#ifdef __alpha__
3243
3244CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
3245
3246int
3247siocnattach(port, speed)
3248 int port;
3249 int speed;
3250{
3251 int s;
3252 u_char cfcr;
3253 u_int divisor;
3254 struct siocnstate sp;
3255
3256 siocniobase = port;
3257 comdefaultrate = speed;
3258 sio_consdev.cn_pri = CN_NORMAL;
3259 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
3260
3261 s = spltty();
3262
3263 /*
3264 * Initialize the divisor latch. We can't rely on
3265 * siocnopen() to do this the first time, since it
3266 * avoids writing to the latch if the latch appears
3267 * to have the correct value. Also, if we didn't
3268 * just read the speed from the hardware, then we
3269 * need to set the speed in hardware so that
3270 * switching it later is null.
3271 */
3272 cfcr = inb(siocniobase + com_cfcr);
3273 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
3274 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3275 outb(siocniobase + com_dlbl, divisor & 0xff);
3276 outb(siocniobase + com_dlbh, divisor >> 8);
3277 outb(siocniobase + com_cfcr, cfcr);
3278
3279 siocnopen(&sp, siocniobase, comdefaultrate);
3280 splx(s);
3281
3282 cn_tab = &sio_consdev;
3283 return (0);
3284}
3285
3286int
3287siogdbattach(port, speed)
3288 int port;
3289 int speed;
3290{
3291 int s;
3292 u_char cfcr;
3293 u_int divisor;
3294 struct siocnstate sp;
3295
3296 siogdbiobase = port;
3297 gdbdefaultrate = speed;
3298
3299 s = spltty();
3300
3301 /*
3302 * Initialize the divisor latch. We can't rely on
3303 * siocnopen() to do this the first time, since it
3304 * avoids writing to the latch if the latch appears
3305 * to have the correct value. Also, if we didn't
3306 * just read the speed from the hardware, then we
3307 * need to set the speed in hardware so that
3308 * switching it later is null.
3309 */
3310 cfcr = inb(siogdbiobase + com_cfcr);
3311 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3312 divisor = siodivisor(comdefaultrclk, gdbdefaultrate);
3313 outb(siogdbiobase + com_dlbl, divisor & 0xff);
3314 outb(siogdbiobase + com_dlbh, divisor >> 8);
3315 outb(siogdbiobase + com_cfcr, cfcr);
3316
3317 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3318 splx(s);
3319
3320 return (0);
3321}
3322
3323#endif
3324
3325static void
3326siocninit(cp)
3327 struct consdev *cp;
3328{
3329 comconsole = DEV_TO_UNIT(cp->cn_dev);
3330}
3331
3332static int
3333siocncheckc(dev)
3334 dev_t dev;
3335{
3336 int c;
3337 Port_t iobase;
3338 int s;
3339 struct siocnstate sp;
3340
3341 if (minor(dev) == siogdbunit)
3342 iobase = siogdbiobase;
3343 else
3344 iobase = siocniobase;
3345 s = spltty();
3346 siocnopen(&sp, iobase, comdefaultrate);
3347 if (inb(iobase + com_lsr) & LSR_RXRDY)
3348 c = inb(iobase + com_data);
3349 else
3350 c = -1;
3351 siocnclose(&sp, iobase);
3352 splx(s);
3353 return (c);
3354}
3355
3356
3357int
3358siocngetc(dev)
3359 dev_t dev;
3360{
3361 int c;
3362 Port_t iobase;
3363 int s;
3364 struct siocnstate sp;
3365
3366 if (minor(dev) == siogdbunit)
3367 iobase = siogdbiobase;
3368 else
3369 iobase = siocniobase;
3370 s = spltty();
3371 siocnopen(&sp, iobase, comdefaultrate);
3372 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3373 ;
3374 c = inb(iobase + com_data);
3375 siocnclose(&sp, iobase);
3376 splx(s);
3377 return (c);
3378}
3379
3380void
3381siocnputc(dev, c)
3382 dev_t dev;
3383 int c;
3384{
3385 int s;
3386 struct siocnstate sp;
3387 Port_t iobase;
3388
3389 if (minor(dev) == siogdbunit)
3390 iobase = siogdbiobase;
3391 else
3392 iobase = siocniobase;
3393 s = spltty();
3394 siocnopen(&sp, iobase, comdefaultrate);
3395 siocntxwait(iobase);
3396 outb(iobase + com_data, c);
3397 siocnclose(&sp, iobase);
3398 splx(s);
3399}
3400
3401#ifdef __alpha__
3402int
3403siogdbgetc()
3404{
3405 int c;
3406 Port_t iobase;
3407 int s;
3408 struct siocnstate sp;
3409
3410 iobase = siogdbiobase;
3411 s = spltty();
3412 siocnopen(&sp, iobase, gdbdefaultrate);
3413 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3414 ;
3415 c = inb(iobase + com_data);
3416 siocnclose(&sp, iobase);
3417 splx(s);
3418 return (c);
3419}
3420
3421void
3422siogdbputc(c)
3423 int c;
3424{
3425 int s;
3426 struct siocnstate sp;
3427
3428 s = spltty();
3429 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3430 siocntxwait(siogdbiobase);
3431 outb(siogdbiobase + com_data, c);
3432 siocnclose(&sp, siogdbiobase);
3433 splx(s);
3434}
3435#endif
3436
3437DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
3438#if NCARD > 0
3439DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0);
3440#endif
3441#if NPCI > 0
3442DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
3443#endif
3444#if NPUC > 0
3445DRIVER_MODULE(sio, puc, sio_puc_driver, sio_devclass, 0, 0);
3446#endif