kernel -- vm locking: Lock kernel_object in kmem_alloc3.
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
d916dbc1 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
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46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
87cf6827 51#include <machine/intr_machdep.h>
0b692e79 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
5f456c40 56
9e0e3f85 57#include <machine_base/apic/ioapic_abi.h>
a3dd9120 58#include <machine_base/isa/elcr_var.h>
9e0e3f85 59
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60#include "icu.h"
61#include "icu_ipl.h"
37e7efec 62
10ff1029 63extern inthand_t
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64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029 72
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73static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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82};
83
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84static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
87} icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
88
89#define ICU_IMT_UNUSED 0 /* KEEP THIS */
90#define ICU_IMT_RESERVED 1
91#define ICU_IMT_LINE 2
92
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93extern void ICU_INTREN(int);
94extern void ICU_INTRDIS(int);
95
96static int icu_vectorctl(int, int, int);
97static int icu_setvar(int, const void *);
98static int icu_getvar(int, void *);
99static void icu_finalize(void);
100static void icu_cleanup(void);
101static void icu_setdefault(void);
7bf5fa56 102static void icu_stabilize(void);
a3dd9120 103static void icu_initmap(void);
10db3cc6 104
30c5f287 105struct machintr_abi MachIntrABI_ICU = {
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106 MACHINTR_ICU,
107 .intrdis = ICU_INTRDIS,
108 .intren = ICU_INTREN,
109 .vectorctl = icu_vectorctl,
110 .setvar = icu_setvar,
111 .getvar = icu_getvar,
112 .finalize = icu_finalize,
10db3cc6 113 .cleanup = icu_cleanup,
7bf5fa56 114 .setdefault = icu_setdefault,
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115 .stabilize = icu_stabilize,
116 .initmap = icu_initmap
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117};
118
54e1df6b 119static int icu_imcr_present;
e96ee753 120
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121/*
122 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
123 */
54e1df6b 124static int
d916dbc1 125icu_setvar(int varid, const void *buf)
37e7efec 126{
54e1df6b 127 int error = 0;
e96ee753 128
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129 switch (varid) {
130 case MACHINTR_VAR_IMCR_PRESENT:
131 icu_imcr_present = *(const int *)buf;
132 break;
133
134 default:
135 error = ENOENT;
136 break;
137 }
138 return error;
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139}
140
54e1df6b 141static int
d916dbc1 142icu_getvar(int varid, void *buf)
37e7efec 143{
54e1df6b 144 int error = 0;
e96ee753 145
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146 switch (varid) {
147 case MACHINTR_VAR_IMCR_PRESENT:
148 *(int *)buf = icu_imcr_present;
149 break;
150
151 default:
152 error = ENOENT;
153 break;
154 }
155 return error;
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156}
157
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158/*
159 * Called before interrupts are physically enabled
160 */
37e7efec 161static void
7bf5fa56 162icu_stabilize(void)
37e7efec 163{
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164 int intr;
165
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166 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
167 machintr_intrdis(intr);
168 machintr_intren(ICU_IRQ_SLAVE);
169}
170
171/*
172 * Called after interrupts physically enabled but before the
173 * critical section is released.
174 */
175static void
176icu_cleanup(void)
177{
178 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
179}
180
181/*
182 * Called after stablize and cleanup; critical section is not
183 * held and interrupts are not physically disabled.
184 *
185 * For SMP:
186 * Further delayed after BSP's LAPIC is initialized
187 */
188static void
189icu_finalize(void)
190{
191 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
192
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193#ifdef SMP
194 if (apic_io_enable) {
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195 /*
196 * MachIntrABI switching will happen in
197 * MachIntrABI_IOAPIC.finalize()
198 */
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199 MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
200 &icu_imcr_present);
201 MachIntrABI_IOAPIC.finalize();
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202 return;
203 }
54e1df6b 204
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205 /*
206 * If an IMCR is present, programming bit 0 disconnects the 8259
207 * from the BSP. The 8259 may still be connected to LINT0 on the
208 * BSP's LAPIC.
209 *
210 * If we are running SMP the LAPIC is active, try to use virtual
211 * wire mode so we can use other interrupt sources within the LAPIC
212 * in addition to the 8259.
213 */
214 if (icu_imcr_present) {
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215 u_long ef;
216
217 crit_enter();
218
219 ef = read_eflags();
220 cpu_disable_intr();
221
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222 outb(0x22, 0x70);
223 outb(0x23, 0x01);
37e7efec 224
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225 write_eflags(ef);
226
227 crit_exit();
228 }
229#endif /* SMP */
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230}
231
54e1df6b 232static int
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233icu_vectorctl(int op, int intr, int flags)
234{
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235 int error;
236 u_long ef;
237
238 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
239 return EINVAL;
240
241 ef = read_eflags();
242 cpu_disable_intr();
243 error = 0;
244
245 switch (op) {
246 case MACHINTR_VECTOR_SETUP:
081be8a5 247 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
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248 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
249 machintr_intren(intr);
250 break;
251
252 case MACHINTR_VECTOR_TEARDOWN:
10db3cc6 253 machintr_intrdis(intr);
081be8a5 254 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
54e1df6b 255 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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256 break;
257
258 default:
259 error = EOPNOTSUPP;
260 break;
261 }
262 write_eflags(ef);
263 return error;
10ff1029 264}
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265
266static void
267icu_setdefault(void)
268{
269 int intr;
270
271 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
272 if (intr == ICU_IRQ_SLAVE)
273 continue;
274 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
275 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
276 }
277}
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278
279static void
280icu_initmap(void)
281{
282 int i;
283
284 for (i = 0; i < ICU_HWI_VECTORS; ++i)
285 icu_irqmaps[i].im_type = ICU_IMT_LINE;
286 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
287
288 if (elcr_found) {
289 for (i = 0; i < ICU_HWI_VECTORS; ++i)
290 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
291 } else {
292 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
293 switch (i) {
294 case 0:
295 case 1:
296 case 2:
297 case 8:
298 case 13:
299 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
300 break;
301
302 default:
303 icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;
304 break;
305 }
306 }
307 }
308}