AMD64 - Fix many compile-time warnings. int/ptr type mismatches, %llx, etc.
[dragonfly.git] / sys / dev / serial / sio / sio.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/isa/sio.c,v 1.291.2.35 2003/05/18 08:51:15 murray Exp $
8d565796 34 * $DragonFly: src/sys/dev/serial/sio/sio.c,v 1.44 2008/07/23 16:39:33 dillon Exp $
984263bc
MD
35 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
36 * from: i386/isa sio.c,v 1.234
37 */
38
39#include "opt_comconsole.h"
40#include "opt_compat.h"
41#include "opt_ddb.h"
42#include "opt_sio.h"
1f2de5d4 43#include "use_pci.h"
984263bc 44#ifdef __i386__
1f2de5d4 45#include "use_puc.h"
984263bc 46#endif
1f2de5d4 47#include "use_sio.h"
984263bc
MD
48
49/*
50 * Serial driver, based on 386BSD-0.1 com driver.
51 * Mostly rewritten to use pseudo-DMA.
52 * Works for National Semiconductor NS8250-NS16550AF UARTs.
53 * COM driver, based on HP dca driver.
54 *
55 * Changes for PC-Card integration:
56 * - Added PC-Card driver table and handlers
57 */
58#include <sys/param.h>
59#include <sys/systm.h>
60#include <sys/reboot.h>
61#include <sys/malloc.h>
62#include <sys/tty.h>
63#include <sys/proc.h>
895c1f85 64#include <sys/priv.h>
984263bc
MD
65#include <sys/module.h>
66#include <sys/conf.h>
67#include <sys/dkstat.h>
68#include <sys/fcntl.h>
69#include <sys/interrupt.h>
70#include <sys/kernel.h>
71#include <sys/syslog.h>
72#include <sys/sysctl.h>
73#include <sys/bus.h>
984263bc
MD
74#include <sys/rman.h>
75#include <sys/timepps.h>
8d77660e 76#include <sys/thread2.h>
984263bc
MD
77
78#include <machine/limits.h>
79
1f2de5d4
MD
80#include <bus/isa/isareg.h>
81#include <bus/isa/isavar.h>
984263bc 82#if NPCI > 0
1f2de5d4
MD
83#include <bus/pci/pcireg.h>
84#include <bus/pci/pcivar.h>
984263bc
MD
85#endif
86#if NPUC > 0
1f2de5d4 87#include <dev/misc/puc/pucvar.h>
984263bc
MD
88#endif
89#include <machine/lock.h>
90
91#include <machine/clock.h>
984263bc
MD
92#ifndef SMP
93#include <machine/lock.h>
94#endif
984263bc 95
1f2de5d4 96#include "sioreg.h"
8c5c0470 97#include "sio_private.h"
984263bc
MD
98
99#ifdef COM_ESP
1f2de5d4 100#include "../ic_layer/esp.h"
984263bc 101#endif
984263bc 102
984263bc
MD
103#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
104
105#define CALLOUT_MASK 0x80
106#define CONTROL_MASK 0x60
107#define CONTROL_INIT_STATE 0x20
108#define CONTROL_LOCK_STATE 0x40
109#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
110#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \
111 | ((mynor) & 0x1f))
112#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \
113 | ((unit) & 0x1f))
114
984263bc
MD
115#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
116
117#define sio_getreg(com, off) \
118 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
119#define sio_setreg(com, off, value) \
120 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
121
122/*
123 * com state bits.
124 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
125 * than the other bits so that they can be tested as a group without masking
126 * off the low bits.
127 *
128 * The following com and tty flags correspond closely:
129 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
130 * comstop())
131 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
132 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
133 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
134 * TS_FLUSH is not used.
135 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
136 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
137 */
138#define CS_BUSY 0x80 /* output in progress */
139#define CS_TTGO 0x40 /* output not stopped by XOFF */
140#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
141#define CS_CHECKMSR 1 /* check of MSR scheduled */
142#define CS_CTS_OFLOW 2 /* use CTS output flow control */
143#define CS_DTR_OFF 0x10 /* DTR held off */
144#define CS_ODONE 4 /* output completed */
145#define CS_RTS_IFLOW 8 /* use RTS input flow control */
146#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
147
148static char const * const error_desc[] = {
149#define CE_OVERRUN 0
150 "silo overflow",
151#define CE_INTERRUPT_BUF_OVERFLOW 1
152 "interrupt-level buffer overflow",
153#define CE_TTY_BUF_OVERFLOW 2
154 "tty-level buffer overflow",
155};
156
984263bc 157#ifdef COM_ESP
5ca58d54 158static int espattach (struct com_s *com, Port_t esp_port);
984263bc 159#endif
5ca58d54 160static int sio_isa_attach (device_t dev);
984263bc
MD
161
162static timeout_t siobusycheck;
5ca58d54 163static u_int siodivisor (u_long rclk, speed_t speed);
984263bc 164static timeout_t siodtrwakeup;
5ca58d54
RG
165static void comhardclose (struct com_s *com);
166static void sioinput (struct com_s *com);
167static void siointr1 (struct com_s *com);
168static void siointr (void *arg);
169static int commctl (struct com_s *com, int bits, int how);
170static int comparam (struct tty *tp, struct termios *t);
ef0fdad1 171static inthand2_t siopoll;
5ca58d54
RG
172static int sio_isa_probe (device_t dev);
173static void siosettimeout (void);
174static int siosetwater (struct com_s *com, speed_t speed);
175static void comstart (struct tty *tp);
176static void comstop (struct tty *tp, int rw);
984263bc 177static timeout_t comwakeup;
5ca58d54
RG
178static void disc_optim (struct tty *tp, struct termios *t,
179 struct com_s *com);
984263bc 180
984263bc 181#if NPCI > 0
5ca58d54
RG
182static int sio_pci_attach (device_t dev);
183static void sio_pci_kludge_unit (device_t dev);
184static int sio_pci_probe (device_t dev);
984263bc
MD
185#endif /* NPCI > 0 */
186
187#if NPUC > 0
5ca58d54
RG
188static int sio_puc_attach (device_t dev);
189static int sio_puc_probe (device_t dev);
984263bc
MD
190#endif /* NPUC > 0 */
191
192static char driver_name[] = "sio";
193
194/* table and macro for fast conversion from a unit number to its com struct */
8c5c0470 195devclass_t sio_devclass;
984263bc
MD
196#define com_addr(unit) ((struct com_s *) \
197 devclass_get_softc(sio_devclass, unit))
198
199static device_method_t sio_isa_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, sio_isa_probe),
202 DEVMETHOD(device_attach, sio_isa_attach),
203
204 { 0, 0 }
205};
206
207static driver_t sio_isa_driver = {
208 driver_name,
209 sio_isa_methods,
210 sizeof(struct com_s),
211};
212
984263bc
MD
213#if NPCI > 0
214static device_method_t sio_pci_methods[] = {
215 /* Device interface */
216 DEVMETHOD(device_probe, sio_pci_probe),
217 DEVMETHOD(device_attach, sio_pci_attach),
218
219 { 0, 0 }
220};
221
222static driver_t sio_pci_driver = {
223 driver_name,
224 sio_pci_methods,
225 sizeof(struct com_s),
226};
227#endif /* NPCI > 0 */
228
229#if NPUC > 0
230static device_method_t sio_puc_methods[] = {
231 /* Device interface */
232 DEVMETHOD(device_probe, sio_puc_probe),
233 DEVMETHOD(device_attach, sio_puc_attach),
234
235 { 0, 0 }
236};
237
238static driver_t sio_puc_driver = {
239 driver_name,
240 sio_puc_methods,
241 sizeof(struct com_s),
242};
243#endif /* NPUC > 0 */
244
245static d_open_t sioopen;
246static d_close_t sioclose;
247static d_read_t sioread;
248static d_write_t siowrite;
249static d_ioctl_t sioioctl;
250
251#define CDEV_MAJOR 28
fef8985e
MD
252static struct dev_ops sio_ops = {
253 { driver_name, CDEV_MAJOR, D_TTY | D_KQFILTER },
254 .d_open = sioopen,
255 .d_close = sioclose,
256 .d_read = sioread,
257 .d_write = siowrite,
258 .d_ioctl = sioioctl,
259 .d_poll = ttypoll,
260 .d_kqfilter = ttykqfilter
984263bc
MD
261};
262
263int comconsole = -1;
264static volatile speed_t comdefaultrate = CONSPEED;
265static u_long comdefaultrclk = DEFAULT_RCLK;
266SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
984263bc
MD
267static u_int com_events; /* input chars + weighted output completions */
268static Port_t siocniobase;
269static int siocnunit;
270static Port_t siogdbiobase;
271static int siogdbunit = -1;
272static bool_t sio_registered;
273static int sio_timeout;
274static int sio_timeouts_until_log;
54607efb 275static struct callout sio_timeout_handle;
984263bc
MD
276static int sio_numunits;
277
278#ifdef COM_ESP
279/* XXX configure this properly. */
280static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
281static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
282#endif
283
284/*
285 * handle sysctl read/write requests for console speed
286 *
287 * In addition to setting comdefaultrate for I/O through /dev/console,
288 * also set the initial and lock values for the /dev/ttyXX device
289 * if there is one associated with the console. Finally, if the /dev/tty
290 * device has already been open, change the speed on the open running port
291 * itself.
292 */
293
294static int
295sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
296{
8d77660e 297 int error;
984263bc
MD
298 speed_t newspeed;
299 struct com_s *com;
300 struct tty *tp;
301
302 newspeed = comdefaultrate;
303
304 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
305 if (error || !req->newptr)
306 return (error);
307
308 comdefaultrate = newspeed;
309
310 if (comconsole < 0) /* serial console not selected? */
311 return (0);
312
313 com = com_addr(comconsole);
314 if (com == NULL)
315 return (ENXIO);
316
317 /*
318 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
319 * (note, the lock rates really are boolean -- if non-zero, disallow
320 * speed changes)
321 */
322 com->it_in.c_ispeed = com->it_in.c_ospeed =
323 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
324 com->it_out.c_ispeed = com->it_out.c_ospeed =
325 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
326
327 /*
328 * if we're open, change the running rate too
329 */
330 tp = com->tp;
331 if (tp && (tp->t_state & TS_ISOPEN)) {
332 tp->t_termios.c_ispeed =
333 tp->t_termios.c_ospeed = comdefaultrate;
8d77660e 334 crit_enter();
984263bc 335 error = comparam(tp, &tp->t_termios);
8d77660e 336 crit_exit();
984263bc
MD
337 }
338 return error;
339}
340
341SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
342 0, 0, sysctl_machdep_comdefaultrate, "I", "");
343
984263bc
MD
344#if NPCI > 0
345struct pci_ids {
346 u_int32_t type;
347 const char *desc;
348 int rid;
349};
350
351static struct pci_ids pci_ids[] = {
352 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
353 { 0x2000131f, "CyberSerial (1-port) 16550", 0x10 },
354 { 0x01101407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
355 { 0x01111407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
356 { 0x048011c1, "Lucent kermit based PCI Modem", 0x14 },
357 { 0x95211415, "Oxford Semiconductor PCI Dual Port Serial", 0x10 },
358 { 0x7101135e, "SeaLevel Ultra 530.PCI Single Port Serial", 0x18 },
359 { 0x0000151f, "SmartLink 5634PCV SurfRider", 0x10 },
360 { 0x98459710, "Netmos Nm9845 PCI Bridge with Dual UART", 0x10 },
361 { 0x00000000, NULL, 0 }
362};
363
364static int
ce63e0fa 365sio_pci_attach(device_t dev)
984263bc
MD
366{
367 u_int32_t type;
368 struct pci_ids *id;
369
370 type = pci_get_devid(dev);
371 id = pci_ids;
372 while (id->type && id->type != type)
373 id++;
374 if (id->desc == NULL)
375 return (ENXIO);
376 sio_pci_kludge_unit(dev);
377 return (sioattach(dev, id->rid, 0UL));
378}
379
380/*
381 * Don't cut and paste this to other drivers. It is a horrible kludge
382 * which will fail to work and also be unnecessary in future versions.
383 */
384static void
ce63e0fa 385sio_pci_kludge_unit(device_t dev)
984263bc
MD
386{
387 devclass_t dc;
388 int err;
389 int start;
390 int unit;
391
392 unit = 0;
393 start = 0;
394 while (resource_int_value("sio", unit, "port", &start) == 0 &&
395 start > 0)
396 unit++;
397 if (device_get_unit(dev) < unit) {
398 dc = device_get_devclass(dev);
399 while (devclass_get_device(dc, unit))
400 unit++;
401 device_printf(dev, "moving to sio%d\n", unit);
402 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
403 if (err)
404 device_printf(dev, "error moving device %d\n", err);
405 }
406}
407
408static int
ce63e0fa 409sio_pci_probe(device_t dev)
984263bc
MD
410{
411 u_int32_t type;
412 struct pci_ids *id;
413
414 type = pci_get_devid(dev);
415 id = pci_ids;
416 while (id->type && id->type != type)
417 id++;
418 if (id->desc == NULL)
419 return (ENXIO);
420 device_set_desc(dev, id->desc);
421 return (sioprobe(dev, id->rid, 0UL));
422}
423#endif /* NPCI > 0 */
424
425#if NPUC > 0
426static int
ce63e0fa 427sio_puc_attach(device_t dev)
984263bc
MD
428{
429 u_int rclk;
430
431 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
432 &rclk) != 0)
433 rclk = DEFAULT_RCLK;
434 return (sioattach(dev, 0, rclk));
435}
436
437static int
ce63e0fa 438sio_puc_probe(device_t dev)
984263bc
MD
439{
440 u_int rclk;
441
442 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
443 &rclk) != 0)
444 rclk = DEFAULT_RCLK;
445 return (sioprobe(dev, 0, rclk));
446}
447#endif /* NPUC */
448
449static struct isa_pnp_id sio_ids[] = {
450 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
451 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
452 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
453 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
454 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
455 /* Devices that do not have a compatid */
456 {0x12206804, NULL}, /* ACH2012 - 5634BTS 56K Video Ready Modem */
457 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
458 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
459 {0x21107905, NULL}, /* AKY1021 - 56K Plug&Play Modem */
460 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
461 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
462 {0x56159008, NULL}, /* BDP1556 - B.D. Smart One 56SPS,Voice Modem*/
463 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
464 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
465 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
466 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
467 {0x0094490a, NULL}, /* BRI9400 - Boca K56Flex PnP */
468 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
469 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
470 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
471 {0x01308c0e, NULL}, /* CTL3001 - Creative Labs Phoneblaster */
472 {0x36033610, NULL}, /* DAV0336 - DAVICOM 336PNP MODEM */
473 {0x01009416, NULL}, /* ETT0001 - E-Tech Bullet 33k6 PnP */
474 {0x0000aa1a, NULL}, /* FUJ0000 - FUJITSU Modem 33600 PNP/I2 */
475 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
476 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
477 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
478 {0x0116c31e, NULL}, /* GVC1601 - Rockwell V.34 Plug & Play Modem */
479 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
480 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
481 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
482 {0x8100e425, NULL}, /* IOD0081 - I-O DATA DEVICE,INC. IFML-560 */
483 {0x21002534, NULL}, /* MAE0021 - Jetstream Int V.90 56k Voice Series 2*/
484 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
485 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
486 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
487 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
488 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
489 {0x08804f3f, NULL}, /* OZO8008 - Zoom (33.6k Modem) */
490 {0x0f804f3f, NULL}, /* OZO800f - Zoom 2812 (56k Modem) */
491 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
492 {0x00914f3f, NULL}, /* OZO9100 - Zoom 2919 (K56 Faxmodem) */
493 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
494 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
495 {0x1200b23d, NULL}, /* RSS0012 - OMRON ME5614ISA */
496 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
497 {0x6202734a, NULL}, /* RSS0262 - 5614Jx3[G] V90+K56Flex Modem */
498 {0x1010104d, NULL}, /* SHP1010 - Rockwell 33600bps Modem */
499 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
500 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
501 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
502 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
503 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
504 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
505 {0x7016b04e, NULL}, /* SUP1670 - Supra 336i V+ Intl */
506 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
507 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
508 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
509 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
510 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
511 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
512 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
513 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
514 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
515 {0x11007256, NULL}, /* USR0011 - USR ? */
516 {0x01017256, NULL}, /* USR0101 - USR ? */
517 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
518 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
519 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
520 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
521 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
522 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
523 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
524 {0x90307256, NULL}, /* USR3090 - USR ? */
525 {0x70917256, NULL}, /* USR9170 - U.S. Robotics 56K FAX INT */
526 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
527 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
528 {0x01a0896a, NULL}, /* ZTIA001 - Zoom Internal V90 Faxmodem */
529 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
530 {0}
531};
532
533
534
535static int
ce63e0fa 536sio_isa_probe(device_t dev)
984263bc
MD
537{
538 /* Check isapnp ids */
539 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
540 return (ENXIO);
541 return (sioprobe(dev, 0, 0UL));
542}
543
8c5c0470 544int
ce63e0fa 545sioprobe(device_t dev, int xrid, u_long rclk)
984263bc
MD
546{
547#if 0
548 static bool_t already_init;
549 device_t xdev;
550#endif
551 struct com_s *com;
552 u_int divisor;
553 bool_t failures[10];
554 int fn;
555 device_t idev;
556 Port_t iobase;
557 intrmask_t irqmap[4];
558 intrmask_t irqs;
559 u_char mcr_image;
560 int result;
561 u_long xirq;
562 u_int flags = device_get_flags(dev);
563 int rid;
564 struct resource *port;
565
566 rid = xrid;
567 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
568 0, ~0, IO_COMSIZE, RF_ACTIVE);
569 if (!port)
570 return (ENXIO);
571
572 com = device_get_softc(dev);
573 com->bst = rman_get_bustag(port);
574 com->bsh = rman_get_bushandle(port);
575 if (rclk == 0)
576 rclk = DEFAULT_RCLK;
577 com->rclk = rclk;
578
579#if 0
580 /*
581 * XXX this is broken - when we are first called, there are no
582 * previously configured IO ports. We could hard code
583 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
584 * This code has been doing nothing since the conversion since
585 * "count" is zero the first time around.
586 */
587 if (!already_init) {
588 /*
589 * Turn off MCR_IENABLE for all likely serial ports. An unused
590 * port with its MCR_IENABLE gate open will inhibit interrupts
591 * from any used port that shares the interrupt vector.
592 * XXX the gate enable is elsewhere for some multiports.
593 */
594 device_t *devs;
595 int count, i, xioport;
596
597 devclass_get_devices(sio_devclass, &devs, &count);
598 for (i = 0; i < count; i++) {
599 xdev = devs[i];
600 if (device_is_enabled(xdev) &&
601 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
602 NULL) == 0)
603 outb(xioport + com_mcr, 0);
604 }
efda3bd0 605 kfree(devs, M_TEMP);
984263bc
MD
606 already_init = TRUE;
607 }
608#endif
609
610 if (COM_LLCONSOLE(flags)) {
e3869ec7 611 kprintf("sio%d: reserved for low-level i/o\n",
984263bc
MD
612 device_get_unit(dev));
613 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
614 return (ENXIO);
615 }
616
617 /*
618 * If the device is on a multiport card and has an AST/4
619 * compatible interrupt control register, initialize this
620 * register and prepare to leave MCR_IENABLE clear in the mcr.
621 * Otherwise, prepare to set MCR_IENABLE in the mcr.
622 * Point idev to the device struct giving the correct id_irq.
623 * This is the struct for the master device if there is one.
624 */
625 idev = dev;
626 mcr_image = MCR_IENABLE;
627#ifdef COM_MULTIPORT
628 if (COM_ISMULTIPORT(flags)) {
629 Port_t xiobase;
630 u_long io;
631
632 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
633 if (idev == NULL) {
e3869ec7 634 kprintf("sio%d: master device %d not configured\n",
984263bc
MD
635 device_get_unit(dev), COM_MPMASTER(flags));
636 idev = dev;
637 }
638 if (!COM_NOTAST4(flags)) {
639 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
640 NULL) == 0) {
641 xiobase = io;
642 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
643 NULL, NULL) == 0)
644 outb(xiobase + com_scr, 0x80);
645 else
646 outb(xiobase + com_scr, 0);
647 }
648 mcr_image = 0;
649 }
650 }
651#endif /* COM_MULTIPORT */
652 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
653 mcr_image = 0;
654
655 bzero(failures, sizeof failures);
656 iobase = rman_get_start(port);
657
658 /*
659 * We don't want to get actual interrupts, just masked ones.
660 * Interrupts from this line should already be masked in the ICU,
661 * but mask them in the processor as well in case there are some
662 * (misconfigured) shared interrupts.
663 */
8a8d5d85 664 com_lock();
984263bc
MD
665/* EXTRA DELAY? */
666
667 /*
668 * For the TI16754 chips, set prescaler to 1 (4 is often the
669 * default after-reset value) as otherwise it's impossible to
670 * get highest baudrates.
671 */
672 if (COM_TI16754(flags)) {
673 u_char cfcr, efr;
674
675 cfcr = sio_getreg(com, com_cfcr);
676 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
677 efr = sio_getreg(com, com_efr);
678 /* Unlock extended features to turn off prescaler. */
679 sio_setreg(com, com_efr, efr | EFR_EFE);
680 /* Disable EFR. */
681 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
682 /* Turn off prescaler. */
683 sio_setreg(com, com_mcr,
684 sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
685 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
686 sio_setreg(com, com_efr, efr);
687 sio_setreg(com, com_cfcr, cfcr);
688 }
689
690 /*
691 * Initialize the speed and the word size and wait long enough to
692 * drain the maximum of 16 bytes of junk in device output queues.
693 * The speed is undefined after a master reset and must be set
694 * before relying on anything related to output. There may be
695 * junk after a (very fast) soft reboot and (apparently) after
696 * master reset.
697 * XXX what about the UART bug avoided by waiting in comparam()?
698 * We don't want to to wait long enough to drain at 2 bps.
699 */
a936b321 700 if (iobase == siocniobase) {
984263bc 701 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
a936b321 702 } else {
984263bc
MD
703 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
704 divisor = siodivisor(rclk, SIO_TEST_SPEED);
705 sio_setreg(com, com_dlbl, divisor & 0xff);
706 sio_setreg(com, com_dlbh, divisor >> 8);
707 sio_setreg(com, com_cfcr, CFCR_8BITS);
708 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
709 }
710
711 /*
3252589c
MD
712 * Make sure we can drain the receiver. If we can't, the serial
713 * port may not exist.
714 */
715 for (fn = 0; fn < 256; ++fn) {
716 if ((sio_getreg(com, com_lsr) & LSR_RXRDY) == 0)
717 break;
718 (void)sio_getreg(com, com_data);
719 }
720 if (fn == 256) {
e3869ec7 721 kprintf("sio%d: can't drain, serial port might "
3252589c 722 "not exist, disabling\n", device_get_unit(dev));
a936b321 723 com_unlock();
3252589c
MD
724 return (ENXIO);
725 }
726
727 /*
984263bc
MD
728 * Enable the interrupt gate and disable device interupts. This
729 * should leave the device driving the interrupt line low and
730 * guarantee an edge trigger if an interrupt can be generated.
731 */
732/* EXTRA DELAY? */
733 sio_setreg(com, com_mcr, mcr_image);
734 sio_setreg(com, com_ier, 0);
735 DELAY(1000); /* XXX */
736 irqmap[0] = isa_irq_pending();
737
738 /*
739 * Attempt to set loopback mode so that we can send a null byte
740 * without annoying any external device.
741 */
742/* EXTRA DELAY? */
743 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
744
745 /*
746 * Attempt to generate an output interrupt. On 8250's, setting
747 * IER_ETXRDY generates an interrupt independent of the current
748 * setting and independent of whether the THR is empty. On 16450's,
749 * setting IER_ETXRDY generates an interrupt independent of the
750 * current setting. On 16550A's, setting IER_ETXRDY only
751 * generates an interrupt when IER_ETXRDY is not already set.
752 */
753 sio_setreg(com, com_ier, IER_ETXRDY);
754
755 /*
756 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
757 * an interrupt. They'd better generate one for actually doing
758 * output. Loopback may be broken on the same incompatibles but
759 * it's unlikely to do more than allow the null byte out.
760 */
761 sio_setreg(com, com_data, 0);
762 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
763
764 /*
765 * Turn off loopback mode so that the interrupt gate works again
766 * (MCR_IENABLE was hidden). This should leave the device driving
767 * an interrupt line high. It doesn't matter if the interrupt
768 * line oscillates while we are not looking at it, since interrupts
769 * are disabled.
770 */
771/* EXTRA DELAY? */
772 sio_setreg(com, com_mcr, mcr_image);
773
774 /*
775 * Some pcmcia cards have the "TXRDY bug", so we check everyone
776 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
777 */
778 if (COM_NOPROBE(flags)) {
779 /* Reading IIR register twice */
780 for (fn = 0; fn < 2; fn ++) {
781 DELAY(10000);
782 failures[6] = sio_getreg(com, com_iir);
783 }
784 /* Check IIR_TXRDY clear ? */
785 result = 0;
786 if (failures[6] & IIR_TXRDY) {
787 /* Nop, Double check with clearing IER */
788 sio_setreg(com, com_ier, 0);
789 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
790 /* Ok. we're familia this gang */
791 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
792 } else {
793 /* Unknown, Just omit this chip.. XXX */
794 result = ENXIO;
795 sio_setreg(com, com_mcr, 0);
796 }
797 } else {
798 /* OK. this is well-known guys */
799 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
800 }
801 sio_setreg(com, com_ier, 0);
802 sio_setreg(com, com_cfcr, CFCR_8BITS);
8a8d5d85 803 com_unlock();
984263bc
MD
804 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
805 return (iobase == siocniobase ? 0 : result);
806 }
807
808 /*
809 * Check that
810 * o the CFCR, IER and MCR in UART hold the values written to them
811 * (the values happen to be all distinct - this is good for
812 * avoiding false positive tests from bus echoes).
813 * o an output interrupt is generated and its vector is correct.
814 * o the interrupt goes away when the IIR in the UART is read.
815 */
816/* EXTRA DELAY? */
817 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
818 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
819 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
820 DELAY(10000); /* Some internal modems need this time */
821 irqmap[1] = isa_irq_pending();
822 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
823 DELAY(1000); /* XXX */
824 irqmap[2] = isa_irq_pending();
825 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
826
827 /*
828 * Turn off all device interrupts and check that they go off properly.
829 * Leave MCR_IENABLE alone. For ports without a master port, it gates
830 * the OUT2 output of the UART to
831 * the ICU input. Closing the gate would give a floating ICU input
832 * (unless there is another device driving it) and spurious interrupts.
833 * (On the system that this was first tested on, the input floats high
834 * and gives a (masked) interrupt as soon as the gate is closed.)
835 */
836 sio_setreg(com, com_ier, 0);
837 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
838 failures[7] = sio_getreg(com, com_ier);
839 DELAY(1000); /* XXX */
840 irqmap[3] = isa_irq_pending();
841 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
842
8a8d5d85 843 com_unlock();
984263bc
MD
844
845 irqs = irqmap[1] & ~irqmap[0];
846 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
847 ((1 << xirq) & irqs) == 0)
e3869ec7 848 kprintf(
984263bc
MD
849 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
850 device_get_unit(dev), xirq, irqs);
851 if (bootverbose)
e3869ec7 852 kprintf("sio%d: irq maps: %#x %#x %#x %#x\n",
984263bc
MD
853 device_get_unit(dev),
854 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
855
856 result = 0;
857 for (fn = 0; fn < sizeof failures; ++fn)
858 if (failures[fn]) {
859 sio_setreg(com, com_mcr, 0);
860 result = ENXIO;
861 if (bootverbose) {
e3869ec7 862 kprintf("sio%d: probe failed test(s):",
984263bc
MD
863 device_get_unit(dev));
864 for (fn = 0; fn < sizeof failures; ++fn)
865 if (failures[fn])
e3869ec7
SW
866 kprintf(" %d", fn);
867 kprintf("\n");
984263bc
MD
868 }
869 break;
870 }
871 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
872 return (iobase == siocniobase ? 0 : result);
873}
874
875#ifdef COM_ESP
876static int
ce63e0fa 877espattach(struct com_s *com, Port_t esp_port)
984263bc
MD
878{
879 u_char dips;
880 u_char val;
881
882 /*
883 * Check the ESP-specific I/O port to see if we're an ESP
884 * card. If not, return failure immediately.
885 */
886 if ((inb(esp_port) & 0xf3) == 0) {
e3869ec7 887 kprintf(" port 0x%x is not an ESP board?\n", esp_port);
984263bc
MD
888 return (0);
889 }
890
891 /*
892 * We've got something that claims to be a Hayes ESP card.
893 * Let's hope so.
894 */
895
896 /* Get the dip-switch configuration */
897 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
898 dips = inb(esp_port + ESP_STATUS1);
899
900 /*
901 * Bits 0,1 of dips say which COM port we are.
902 */
903 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
e3869ec7 904 kprintf(" : ESP");
984263bc 905 else {
e3869ec7 906 kprintf(" esp_port has com %d\n", dips & 0x03);
984263bc
MD
907 return (0);
908 }
909
910 /*
911 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
912 */
913 outb(esp_port + ESP_CMD1, ESP_GETTEST);
914 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
915 val = inb(esp_port + ESP_STATUS2);
916 if ((val & 0x70) < 0x20) {
e3869ec7 917 kprintf("-old (%o)", val & 0x70);
984263bc
MD
918 return (0);
919 }
920
921 /*
922 * Check for ability to emulate 16550: bit 7 == 1
923 */
924 if ((dips & 0x80) == 0) {
e3869ec7 925 kprintf(" slave");
984263bc
MD
926 return (0);
927 }
928
929 /*
930 * Okay, we seem to be a Hayes ESP card. Whee.
931 */
932 com->esp = TRUE;
933 com->esp_port = esp_port;
934 return (1);
935}
936#endif /* COM_ESP */
937
938static int
ce63e0fa 939sio_isa_attach(device_t dev)
984263bc
MD
940{
941 return (sioattach(dev, 0, 0UL));
942}
943
8c5c0470 944int
ce63e0fa 945sioattach(device_t dev, int xrid, u_long rclk)
984263bc
MD
946{
947 struct com_s *com;
948#ifdef COM_ESP
949 Port_t *espp;
950#endif
951 Port_t iobase;
952 int minorbase;
953 int unit;
954 u_int flags;
955 int rid;
956 struct resource *port;
957 int ret;
54607efb
MD
958 static int did_init;
959
960 if (did_init == 0) {
961 did_init = 1;
962 callout_init(&sio_timeout_handle);
963 }
984263bc
MD
964
965 rid = xrid;
966 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
967 0, ~0, IO_COMSIZE, RF_ACTIVE);
968 if (!port)
969 return (ENXIO);
970
971 iobase = rman_get_start(port);
972 unit = device_get_unit(dev);
973 com = device_get_softc(dev);
974 flags = device_get_flags(dev);
975
976 if (unit >= sio_numunits)
977 sio_numunits = unit + 1;
978 /*
979 * sioprobe() has initialized the device registers as follows:
980 * o cfcr = CFCR_8BITS.
981 * It is most important that CFCR_DLAB is off, so that the
982 * data port is not hidden when we enable interrupts.
983 * o ier = 0.
984 * Interrupts are only enabled when the line is open.
985 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
986 * interrupt control register or the config specifies no irq.
987 * Keeping MCR_DTR and MCR_RTS off might stop the external
988 * device from sending before we are ready.
989 */
990 bzero(com, sizeof *com);
991 com->unit = unit;
992 com->ioportres = port;
993 com->bst = rman_get_bustag(port);
994 com->bsh = rman_get_bushandle(port);
995 com->cfcr_image = CFCR_8BITS;
996 com->dtr_wait = 3 * hz;
917e5fda
MD
997 callout_init(&com->dtr_ch);
998 callout_init(&com->busy_ch);
984263bc
MD
999 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1000 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1001 com->tx_fifo_size = 1;
1002 com->obufs[0].l_head = com->obuf1;
1003 com->obufs[1].l_head = com->obuf2;
1004
1005 com->data_port = iobase + com_data;
1006 com->int_id_port = iobase + com_iir;
1007 com->modem_ctl_port = iobase + com_mcr;
1008 com->mcr_image = inb(com->modem_ctl_port);
1009 com->line_status_port = iobase + com_lsr;
1010 com->modem_status_port = iobase + com_msr;
1011 com->intr_ctl_port = iobase + com_ier;
1012
1013 if (rclk == 0)
1014 rclk = DEFAULT_RCLK;
1015 com->rclk = rclk;
1016
1017 /*
1018 * We don't use all the flags from <sys/ttydefaults.h> since they
1019 * are only relevant for logins. It's important to have echo off
1020 * initially so that the line doesn't start blathering before the
1021 * echo flag can be turned off.
1022 */
1023 com->it_in.c_iflag = 0;
1024 com->it_in.c_oflag = 0;
1025 com->it_in.c_cflag = TTYDEF_CFLAG;
1026 com->it_in.c_lflag = 0;
1027 if (unit == comconsole) {
1028 com->it_in.c_iflag = TTYDEF_IFLAG;
1029 com->it_in.c_oflag = TTYDEF_OFLAG;
1030 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1031 com->it_in.c_lflag = TTYDEF_LFLAG;
1032 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1033 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1034 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1035 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1036 } else
1037 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1038 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
8a8d5d85 1039 com_unlock();
984263bc
MD
1040 /*
1041 * Leave i/o resources allocated if this is a `cn'-level
1042 * console, so that other devices can't snarf them.
1043 */
1044 if (iobase != siocniobase)
1045 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1046 return (ENOMEM);
1047 }
8a8d5d85 1048 com_unlock();
984263bc
MD
1049 termioschars(&com->it_in);
1050 com->it_out = com->it_in;
1051
1052 /* attempt to determine UART type */
e3869ec7 1053 kprintf("sio%d: type", unit);
984263bc
MD
1054
1055
1056#ifdef COM_MULTIPORT
1057 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1058#else
1059 if (!COM_IIR_TXRDYBUG(flags))
1060#endif
1061 {
1062 u_char scr;
1063 u_char scr1;
1064 u_char scr2;
1065
1066 scr = sio_getreg(com, com_scr);
1067 sio_setreg(com, com_scr, 0xa5);
1068 scr1 = sio_getreg(com, com_scr);
1069 sio_setreg(com, com_scr, 0x5a);
1070 scr2 = sio_getreg(com, com_scr);
1071 sio_setreg(com, com_scr, scr);
1072 if (scr1 != 0xa5 || scr2 != 0x5a) {
e3869ec7 1073 kprintf(" 8250");
984263bc
MD
1074 goto determined_type;
1075 }
1076 }
1077 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1078 DELAY(100);
1079 com->st16650a = 0;
1080 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1081 case FIFO_RX_LOW:
e3869ec7 1082 kprintf(" 16450");
984263bc
MD
1083 break;
1084 case FIFO_RX_MEDL:
e3869ec7 1085 kprintf(" 16450?");
984263bc
MD
1086 break;
1087 case FIFO_RX_MEDH:
e3869ec7 1088 kprintf(" 16550?");
984263bc
MD
1089 break;
1090 case FIFO_RX_HIGH:
1091 if (COM_NOFIFO(flags)) {
e3869ec7 1092 kprintf(" 16550A fifo disabled");
984263bc
MD
1093 } else {
1094 com->hasfifo = TRUE;
1095 if (COM_ST16650A(flags)) {
1096 com->st16650a = 1;
1097 com->tx_fifo_size = 32;
e3869ec7 1098 kprintf(" ST16650A");
984263bc
MD
1099 } else if (COM_TI16754(flags)) {
1100 com->tx_fifo_size = 64;
e3869ec7 1101 kprintf(" TI16754");
984263bc
MD
1102 } else {
1103 com->tx_fifo_size = COM_FIFOSIZE(flags);
e3869ec7 1104 kprintf(" 16550A");
984263bc
MD
1105 }
1106 }
1107#ifdef COM_ESP
1108 for (espp = likely_esp_ports; *espp != 0; espp++)
1109 if (espattach(com, *espp)) {
1110 com->tx_fifo_size = 1024;
1111 break;
1112 }
1113#endif
1114 if (!com->st16650a && !COM_TI16754(flags)) {
1115 if (!com->tx_fifo_size)
1116 com->tx_fifo_size = 16;
1117 else
e3869ec7 1118 kprintf(" lookalike with %d bytes FIFO",
984263bc
MD
1119 com->tx_fifo_size);
1120 }
1121
1122 break;
1123 }
1124
1125#ifdef COM_ESP
1126 if (com->esp) {
1127 /*
1128 * Set 16550 compatibility mode.
1129 * We don't use the ESP_MODE_SCALE bit to increase the
1130 * fifo trigger levels because we can't handle large
1131 * bursts of input.
1132 * XXX flow control should be set in comparam(), not here.
1133 */
1134 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1135 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1136
1137 /* Set RTS/CTS flow control. */
1138 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1139 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1140 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1141
1142 /* Set flow-control levels. */
1143 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1144 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1145 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1146 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1147 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1148 }
1149#endif /* COM_ESP */
1150 sio_setreg(com, com_fifo, 0);
1151determined_type: ;
1152
1153#ifdef COM_MULTIPORT
1154 if (COM_ISMULTIPORT(flags)) {
1155 device_t masterdev;
1156
1157 com->multiport = TRUE;
e3869ec7 1158 kprintf(" (multiport");
984263bc 1159 if (unit == COM_MPMASTER(flags))
e3869ec7
SW
1160 kprintf(" master");
1161 kprintf(")");
984263bc
MD
1162 masterdev = devclass_get_device(sio_devclass,
1163 COM_MPMASTER(flags));
1164 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1165 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1166 }
1167#endif /* COM_MULTIPORT */
1168 if (unit == comconsole)
e3869ec7 1169 kprintf(", console");
984263bc 1170 if (COM_IIR_TXRDYBUG(flags))
e3869ec7
SW
1171 kprintf(" with a bogus IIR_TXRDY register");
1172 kprintf("\n");
984263bc
MD
1173
1174 if (!sio_registered) {
477d3c1c 1175 register_swi(SWI_TTY, siopoll, NULL ,"swi_siopoll", NULL);
984263bc
MD
1176 sio_registered = TRUE;
1177 }
1178 minorbase = UNIT_TO_MINOR(unit);
fef8985e
MD
1179 dev_ops_add(&sio_ops, UNIT_TO_MINOR(-1), minorbase);
1180 make_dev(&sio_ops, minorbase,
984263bc 1181 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
fef8985e 1182 make_dev(&sio_ops, minorbase | CONTROL_INIT_STATE,
984263bc 1183 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
fef8985e 1184 make_dev(&sio_ops, minorbase | CONTROL_LOCK_STATE,
984263bc 1185 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
fef8985e 1186 make_dev(&sio_ops, minorbase | CALLOUT_MASK,
984263bc 1187 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
fef8985e 1188 make_dev(&sio_ops, minorbase | CALLOUT_MASK | CONTROL_INIT_STATE,
984263bc 1189 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
fef8985e 1190 make_dev(&sio_ops, minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE,
984263bc
MD
1191 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1192 com->flags = flags;
1193 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1194 pps_init(&com->pps);
1195
1196 rid = 0;
1197 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1198 RF_ACTIVE);
1199 if (com->irqres) {
1200 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
ee61f228
MD
1201 INTR_FAST, siointr, com,
1202 &com->cookie, NULL);
984263bc
MD
1203 if (ret) {
1204 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
ee61f228
MD
1205 com->irqres, 0, siointr, com,
1206 &com->cookie, NULL);
984263bc
MD
1207 if (ret == 0)
1208 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1209 }
1210 if (ret)
1211 device_printf(dev, "could not activate interrupt\n");
1212#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1213 defined(ALT_BREAK_TO_DEBUGGER))
1214 /*
1215 * Enable interrupts for early break-to-debugger support
1216 * on the console.
1217 */
1218 if (ret == 0 && unit == comconsole)
1219 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1220 IER_EMSC);
1221#endif
1222 }
1223
1224 return (0);
1225}
1226
1227static int
fef8985e 1228sioopen(struct dev_open_args *ap)
984263bc 1229{
b13267a5 1230 cdev_t dev = ap->a_head.a_dev;
984263bc
MD
1231 struct com_s *com;
1232 int error;
1233 int mynor;
984263bc
MD
1234 struct tty *tp;
1235 int unit;
1236
1237 mynor = minor(dev);
1238 unit = MINOR_TO_UNIT(mynor);
1239 com = com_addr(unit);
1240 if (com == NULL)
1241 return (ENXIO);
1242 if (com->gone)
1243 return (ENXIO);
1244 if (mynor & CONTROL_MASK)
1245 return (0);
1246 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
8d77660e 1247 crit_enter();
984263bc
MD
1248 /*
1249 * We jump to this label after all non-interrupted sleeps to pick
1250 * up any changes of the device state.
1251 */
1252open_top:
1253 while (com->state & CS_DTR_OFF) {
377d4740 1254 error = tsleep(&com->dtr_wait, PCATCH, "siodtr", 0);
d66e93a3
MD
1255 if (com_addr(unit) == NULL) {
1256 crit_exit();
984263bc 1257 return (ENXIO);
d66e93a3 1258 }
984263bc
MD
1259 if (error != 0 || com->gone)
1260 goto out;
1261 }
1262 if (tp->t_state & TS_ISOPEN) {
1263 /*
1264 * The device is open, so everything has been initialized.
1265 * Handle conflicts.
1266 */
1267 if (mynor & CALLOUT_MASK) {
1268 if (!com->active_out) {
1269 error = EBUSY;
1270 goto out;
1271 }
1272 } else {
1273 if (com->active_out) {
fef8985e 1274 if (ap->a_oflags & O_NONBLOCK) {
984263bc
MD
1275 error = EBUSY;
1276 goto out;
1277 }
1278 error = tsleep(&com->active_out,
377d4740 1279 PCATCH, "siobi", 0);
d66e93a3
MD
1280 if (com_addr(unit) == NULL) {
1281 crit_exit();
984263bc 1282 return (ENXIO);
d66e93a3 1283 }
984263bc
MD
1284 if (error != 0 || com->gone)
1285 goto out;
1286 goto open_top;
1287 }
1288 }
895c1f85 1289 if (tp->t_state & TS_XCLUDE && priv_check_cred(ap->a_cred, PRIV_ROOT, 0)) {
984263bc
MD
1290 error = EBUSY;
1291 goto out;
1292 }
1293 } else {
1294 /*
1295 * The device isn't open, so there are no conflicts.
1296 * Initialize it. Initialization is done twice in many
1297 * cases: to preempt sleeping callin opens if we are
1298 * callout, and to complete a callin open after DCD rises.
1299 */
1300 tp->t_oproc = comstart;
1301 tp->t_param = comparam;
1302 tp->t_stop = comstop;
1303 tp->t_dev = dev;
1304 tp->t_termios = mynor & CALLOUT_MASK
1305 ? com->it_out : com->it_in;
1306 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1307 com->poll = com->no_irq;
1308 com->poll_output = com->loses_outints;
1309 ++com->wopeners;
1310 error = comparam(tp, &tp->t_termios);
1311 --com->wopeners;
1312 if (error != 0)
1313 goto out;
1314 /*
1315 * XXX we should goto open_top if comparam() slept.
1316 */
1317 if (com->hasfifo) {
1318 /*
1319 * (Re)enable and drain fifos.
1320 *
1321 * Certain SMC chips cause problems if the fifos
1322 * are enabled while input is ready. Turn off the
1323 * fifo if necessary to clear the input. We test
1324 * the input ready bit after enabling the fifos
1325 * since we've already enabled them in comparam()
1326 * and to handle races between enabling and fresh
1327 * input.
1328 */
1329 while (TRUE) {
1330 sio_setreg(com, com_fifo,
1331 FIFO_RCV_RST | FIFO_XMT_RST
1332 | com->fifo_image);
1333 /*
1334 * XXX the delays are for superstitious
1335 * historical reasons. It must be less than
1336 * the character time at the maximum
1337 * supported speed (87 usec at 115200 bps
1338 * 8N1). Otherwise we might loop endlessly
1339 * if data is streaming in. We used to use
1340 * delays of 100. That usually worked
1341 * because DELAY(100) used to usually delay
1342 * for about 85 usec instead of 100.
1343 */
1344 DELAY(50);
1345 if (!(inb(com->line_status_port) & LSR_RXRDY))
1346 break;
1347 sio_setreg(com, com_fifo, 0);
1348 DELAY(50);
1349 (void) inb(com->data_port);
1350 }
1351 }
1352
8a8d5d85 1353 com_lock();
984263bc
MD
1354 (void) inb(com->line_status_port);
1355 (void) inb(com->data_port);
1356 com->prev_modem_status = com->last_modem_status
1357 = inb(com->modem_status_port);
1358 if (COM_IIR_TXRDYBUG(com->flags)) {
1359 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1360 | IER_EMSC);
1361 } else {
1362 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1363 | IER_ERLS | IER_EMSC);
1364 }
8a8d5d85 1365 com_unlock();
984263bc
MD
1366 /*
1367 * Handle initial DCD. Callout devices get a fake initial
1368 * DCD (trapdoor DCD). If we are callout, then any sleeping
1369 * callin opens get woken up and resume sleeping on "siobi"
1370 * instead of "siodcd".
1371 */
1372 /*
1373 * XXX `mynor & CALLOUT_MASK' should be
1374 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1375 * TRAPDOOR_CARRIER is the default initial state for callout
1376 * devices and SOFT_CARRIER is like CLOCAL except it hides
1377 * the true carrier.
1378 */
1379 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1380 (*linesw[tp->t_line].l_modem)(tp, 1);
1381 }
1382 /*
1383 * Wait for DCD if necessary.
1384 */
1385 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
fef8985e 1386 && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
984263bc 1387 ++com->wopeners;
377d4740 1388 error = tsleep(TSA_CARR_ON(tp), PCATCH, "siodcd", 0);
d66e93a3
MD
1389 if (com_addr(unit) == NULL) {
1390 crit_exit();
984263bc 1391 return (ENXIO);
d66e93a3 1392 }
984263bc
MD
1393 --com->wopeners;
1394 if (error != 0 || com->gone)
1395 goto out;
1396 goto open_top;
1397 }
1398 error = (*linesw[tp->t_line].l_open)(dev, tp);
1399 disc_optim(tp, &tp->t_termios, com);
1400 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1401 com->active_out = TRUE;
1402 siosettimeout();
1403out:
8d77660e 1404 crit_exit();
984263bc
MD
1405 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1406 comhardclose(com);
1407 return (error);
1408}
1409
1410static int
fef8985e 1411sioclose(struct dev_close_args *ap)
984263bc 1412{
b13267a5 1413 cdev_t dev = ap->a_head.a_dev;
984263bc
MD
1414 struct com_s *com;
1415 int mynor;
984263bc
MD
1416 struct tty *tp;
1417
1418 mynor = minor(dev);
1419 if (mynor & CONTROL_MASK)
1420 return (0);
1421 com = com_addr(MINOR_TO_UNIT(mynor));
1422 if (com == NULL)
1423 return (ENODEV);
1424 tp = com->tp;
8d77660e 1425 crit_enter();
fef8985e 1426 (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
984263bc
MD
1427 disc_optim(tp, &tp->t_termios, com);
1428 comstop(tp, FREAD | FWRITE);
1429 comhardclose(com);
1430 ttyclose(tp);
1431 siosettimeout();
8d77660e 1432 crit_exit();
984263bc 1433 if (com->gone) {
e3869ec7 1434 kprintf("sio%d: gone\n", com->unit);
8d77660e 1435 crit_enter();
984263bc 1436 if (com->ibuf != NULL)
efda3bd0 1437 kfree(com->ibuf, M_DEVBUF);
984263bc 1438 bzero(tp, sizeof *tp);
8d77660e 1439 crit_exit();
984263bc
MD
1440 }
1441 return (0);
1442}
1443
1444static void
ce63e0fa 1445comhardclose(struct com_s *com)
984263bc 1446{
984263bc
MD
1447 struct tty *tp;
1448 int unit;
1449
1450 unit = com->unit;
8d77660e 1451 crit_enter();
984263bc
MD
1452 com->poll = FALSE;
1453 com->poll_output = FALSE;
1454 com->do_timestamp = FALSE;
1455 com->do_dcd_timestamp = FALSE;
1456 com->pps.ppsparam.mode = 0;
1457 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1458 tp = com->tp;
1459
1460#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1461 defined(ALT_BREAK_TO_DEBUGGER))
1462 /*
1463 * Leave interrupts enabled and don't clear DTR if this is the
1464 * console. This allows us to detect break-to-debugger events
1465 * while the console device is closed.
1466 */
1467 if (com->unit != comconsole)
1468#endif
1469 {
1470 sio_setreg(com, com_ier, 0);
1471 if (tp->t_cflag & HUPCL
1472 /*
1473 * XXX we will miss any carrier drop between here and the
1474 * next open. Perhaps we should watch DCD even when the
1475 * port is closed; it is not sufficient to check it at
1476 * the next open because it might go up and down while
1477 * we're not watching.
1478 */
1479 || (!com->active_out
1480 && !(com->prev_modem_status & MSR_DCD)
1481 && !(com->it_in.c_cflag & CLOCAL))
1482 || !(tp->t_state & TS_ISOPEN)) {
1483 (void)commctl(com, TIOCM_DTR, DMBIC);
1484 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
917e5fda
MD
1485 callout_reset(&com->dtr_ch, com->dtr_wait,
1486 siodtrwakeup, com);
984263bc
MD
1487 com->state |= CS_DTR_OFF;
1488 }
1489 }
1490 }
1491 if (com->hasfifo) {
1492 /*
1493 * Disable fifos so that they are off after controlled
1494 * reboots. Some BIOSes fail to detect 16550s when the
1495 * fifos are enabled.
1496 */
1497 sio_setreg(com, com_fifo, 0);
1498 }
1499 com->active_out = FALSE;
1500 wakeup(&com->active_out);
1501 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
8d77660e 1502 crit_exit();
984263bc
MD
1503}
1504
1505static int
fef8985e 1506sioread(struct dev_read_args *ap)
984263bc 1507{
b13267a5 1508 cdev_t dev = ap->a_head.a_dev;
984263bc
MD
1509 int mynor;
1510 struct com_s *com;
1511
1512 mynor = minor(dev);
1513 if (mynor & CONTROL_MASK)
1514 return (ENODEV);
1515 com = com_addr(MINOR_TO_UNIT(mynor));
1516 if (com == NULL || com->gone)
1517 return (ENODEV);
fef8985e 1518 return ((*linesw[com->tp->t_line].l_read)(com->tp, ap->a_uio, ap->a_ioflag));
984263bc
MD
1519}
1520
1521static int
fef8985e 1522siowrite(struct dev_write_args *ap)
984263bc 1523{
b13267a5 1524 cdev_t dev = ap->a_head.a_dev;
984263bc
MD
1525 int mynor;
1526 struct com_s *com;
1527 int unit;
1528
1529 mynor = minor(dev);
1530 if (mynor & CONTROL_MASK)
1531 return (ENODEV);
1532
1533 unit = MINOR_TO_UNIT(mynor);
1534 com = com_addr(unit);
1535 if (com == NULL || com->gone)
1536 return (ENODEV);
1537 /*
1538 * (XXX) We disallow virtual consoles if the physical console is
1539 * a serial port. This is in case there is a display attached that
1540 * is not the console. In that situation we don't need/want the X
1541 * server taking over the console.
1542 */
1543 if (constty != NULL && unit == comconsole)
1544 constty = NULL;
fef8985e 1545 return ((*linesw[com->tp->t_line].l_write)(com->tp, ap->a_uio, ap->a_ioflag));
984263bc
MD
1546}
1547
1548static void
ce63e0fa 1549siobusycheck(void *chan)
984263bc
MD
1550{
1551 struct com_s *com;
984263bc
MD
1552
1553 com = (struct com_s *)chan;
1554
1555 /*
1556 * Clear TS_BUSY if low-level output is complete.
1557 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1558 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1559 * called again. Reading the line status port outside of siointr1()
1560 * is safe because CS_BUSY is clear so there are no output interrupts
1561 * to lose.
1562 */
8d77660e 1563 crit_enter();
984263bc
MD
1564 if (com->state & CS_BUSY)
1565 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1566 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1567 == (LSR_TSRE | LSR_TXRDY)) {
1568 com->tp->t_state &= ~TS_BUSY;
1569 ttwwakeup(com->tp);
1570 com->extra_state &= ~CSE_BUSYCHECK;
917e5fda
MD
1571 } else {
1572 callout_reset(&com->busy_ch, hz / 100, siobusycheck, com);
1573 }
8d77660e 1574 crit_exit();
984263bc
MD
1575}
1576
1577static u_int
ce63e0fa 1578siodivisor(u_long rclk, speed_t speed)
984263bc
MD
1579{
1580 long actual_speed;
1581 u_int divisor;
1582 int error;
1583
1584 if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1585 return (0);
1586 divisor = (rclk / (8UL * speed) + 1) / 2;
1587 if (divisor == 0 || divisor >= 65536)
1588 return (0);
1589 actual_speed = rclk / (16UL * divisor);
1590
1591 /* 10 times error in percent: */
1592 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1593
1594 /* 3.0% maximum error tolerance: */
1595 if (error < -30 || error > 30)
1596 return (0);
1597
1598 return (divisor);
1599}
1600
1601static void
ce63e0fa 1602siodtrwakeup(void *chan)
984263bc
MD
1603{
1604 struct com_s *com;
1605
1606 com = (struct com_s *)chan;
1607 com->state &= ~CS_DTR_OFF;
1608 wakeup(&com->dtr_wait);
1609}
1610
1611static void
ce63e0fa 1612sioinput(struct com_s *com)
984263bc
MD
1613{
1614 u_char *buf;
1615 int incc;
1616 u_char line_status;
1617 int recv_data;
1618 struct tty *tp;
1619
1620 buf = com->ibuf;
1621 tp = com->tp;
1622 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1623 com_events -= (com->iptr - com->ibuf);
1624 com->iptr = com->ibuf;
1625 return;
1626 }
1627 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1628 /*
1629 * Avoid the grotesquely inefficient lineswitch routine
1630 * (ttyinput) in "raw" mode. It usually takes about 450
1631 * instructions (that's without canonical processing or echo!).
1632 * slinput is reasonably fast (usually 40 instructions plus
1633 * call overhead).
1634 */
1635 do {
8a8d5d85 1636 com_unlock();
984263bc
MD
1637 incc = com->iptr - buf;
1638 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1639 && (com->state & CS_RTS_IFLOW
1640 || tp->t_iflag & IXOFF)
1641 && !(tp->t_state & TS_TBLOCK))
1642 ttyblock(tp);
1643 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1644 += b_to_q((char *)buf, incc, &tp->t_rawq);
1645 buf += incc;
1646 tk_nin += incc;
1647 tk_rawcc += incc;
1648 tp->t_rawcc += incc;
1649 ttwakeup(tp);
1650 if (tp->t_state & TS_TTSTOP
1651 && (tp->t_iflag & IXANY
1652 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1653 tp->t_state &= ~TS_TTSTOP;
1654 tp->t_lflag &= ~FLUSHO;
1655 comstart(tp);
1656 }
8a8d5d85 1657 com_lock();
984263bc
MD
1658 } while (buf < com->iptr);
1659 } else {
1660 do {
8a8d5d85 1661 com_unlock();
984263bc
MD
1662 line_status = buf[com->ierroff];
1663 recv_data = *buf++;
1664 if (line_status
1665 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1666 if (line_status & LSR_BI)
1667 recv_data |= TTY_BI;
1668 if (line_status & LSR_FE)
1669 recv_data |= TTY_FE;
1670 if (line_status & LSR_OE)
1671 recv_data |= TTY_OE;
1672 if (line_status & LSR_PE)
1673 recv_data |= TTY_PE;
1674 }
1675 (*linesw[tp->t_line].l_rint)(recv_data, tp);
8a8d5d85 1676 com_lock();
984263bc
MD
1677 } while (buf < com->iptr);
1678 }
1679 com_events -= (com->iptr - com->ibuf);
1680 com->iptr = com->ibuf;
1681
1682 /*
1683 * There is now room for another low-level buffer full of input,
1684 * so enable RTS if it is now disabled and there is room in the
1685 * high-level buffer.
1686 */
1687 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1688 !(tp->t_state & TS_TBLOCK))
1689 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1690}
1691
1692void
ce63e0fa 1693siointr(void *arg)
984263bc
MD
1694{
1695#ifndef COM_MULTIPORT
8a8d5d85 1696 com_lock();
984263bc 1697 siointr1((struct com_s *) arg);
8a8d5d85 1698 com_unlock();
984263bc
MD
1699#else /* COM_MULTIPORT */
1700 bool_t possibly_more_intrs;
1701 int unit;
1702 struct com_s *com;
1703
1704 /*
1705 * Loop until there is no activity on any port. This is necessary
1706 * to get an interrupt edge more than to avoid another interrupt.
1707 * If the IRQ signal is just an OR of the IRQ signals from several
1708 * devices, then the edge from one may be lost because another is
1709 * on.
1710 */
8a8d5d85 1711 com_lock();
984263bc
MD
1712 do {
1713 possibly_more_intrs = FALSE;
1714 for (unit = 0; unit < sio_numunits; ++unit) {
1715 com = com_addr(unit);
1716 /*
8a8d5d85 1717 * XXX com_lock();
984263bc
MD
1718 * would it work here, or be counter-productive?
1719 */
1720 if (com != NULL
1721 && !com->gone
1722 && (inb(com->int_id_port) & IIR_IMASK)
1723 != IIR_NOPEND) {
1724 siointr1(com);
1725 possibly_more_intrs = TRUE;
1726 }
8a8d5d85 1727 /* XXX com_unlock(); */
984263bc
MD
1728 }
1729 } while (possibly_more_intrs);
8a8d5d85 1730 com_unlock();
984263bc
MD
1731#endif /* COM_MULTIPORT */
1732}
1733
1734static void
ce63e0fa 1735siointr1(struct com_s *com)
984263bc
MD
1736{
1737 u_char line_status;
1738 u_char modem_status;
1739 u_char *ioptr;
1740 u_char recv_data;
1741 u_char int_ctl;
1742 u_char int_ctl_new;
984263bc
MD
1743 u_int count;
1744
1745 int_ctl = inb(com->intr_ctl_port);
1746 int_ctl_new = int_ctl;
1747
1748 while (!com->gone) {
1749 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1750 modem_status = inb(com->modem_status_port);
1751 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
044ee7c4 1752 count = sys_cputimer->count();
88c4d2f6 1753 pps_event(&com->pps, count,
984263bc
MD
1754 (modem_status & MSR_DCD) ?
1755 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
1756 }
1757 }
1758 line_status = inb(com->line_status_port);
1759
1760 /* input event? (check first to help avoid overruns) */
1761 while (line_status & LSR_RCV_MASK) {
1762 /* break/unnattached error bits or real input? */
1763 if (!(line_status & LSR_RXRDY))
1764 recv_data = 0;
1765 else
1766 recv_data = inb(com->data_port);
1767#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
1768 /*
1769 * Solaris implements a new BREAK which is initiated
1770 * by a character sequence CR ~ ^b which is similar
1771 * to a familiar pattern used on Sun servers by the
1772 * Remote Console.
1773 */
1774#define KEY_CRTLB 2 /* ^B */
1775#define KEY_CR 13 /* CR '\r' */
1776#define KEY_TILDE 126 /* ~ */
1777
1778 if (com->unit == comconsole) {
1779 static int brk_state1 = 0, brk_state2 = 0;
1780 if (recv_data == KEY_CR) {
1781 brk_state1 = recv_data;
1782 brk_state2 = 0;
1783 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) {
1784 if (recv_data == KEY_TILDE)
1785 brk_state2 = recv_data;
1786 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) {
1787 breakpoint();
1788 brk_state1 = brk_state2 = 0;
1789 goto cont;
1790 } else
1791 brk_state2 = 0;
1792 } else
1793 brk_state1 = 0;
1794 }
1795#endif
1796 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
1797 /*
1798 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
1799 * Otherwise, push the work to a higher level
1800 * (to handle PARMRK) if we're bypassing.
1801 * Otherwise, convert BI/FE and PE+INPCK to 0.
1802 *
1803 * This makes bypassing work right in the
1804 * usual "raw" case (IGNBRK set, and IGNPAR
1805 * and INPCK clear).
1806 *
1807 * Note: BI together with FE/PE means just BI.
1808 */
1809 if (line_status & LSR_BI) {
1810#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
1811 if (com->unit == comconsole) {
1812 breakpoint();
1813 goto cont;
1814 }
1815#endif
1816 if (com->tp == NULL
1817 || com->tp->t_iflag & IGNBRK)
1818 goto cont;
1819 } else {
1820 if (com->tp == NULL
1821 || com->tp->t_iflag & IGNPAR)
1822 goto cont;
1823 }
1824 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
1825 && (line_status & (LSR_BI | LSR_FE)
1826 || com->tp->t_iflag & INPCK))
1827 recv_data = 0;
1828 }
1829 ++com->bytes_in;
1830 if (com->hotchar != 0 && recv_data == com->hotchar)
1831 setsofttty();
1832 ioptr = com->iptr;
1833 if (ioptr >= com->ibufend)
1834 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
1835 else {
1836 if (com->do_timestamp)
1837 microtime(&com->timestamp);
1838 ++com_events;
1839 schedsofttty();
1840#if 0 /* for testing input latency vs efficiency */
1841if (com->iptr - com->ibuf == 8)
1842 setsofttty();
1843#endif
1844 ioptr[0] = recv_data;
1845 ioptr[com->ierroff] = line_status;
1846 com->iptr = ++ioptr;
1847 if (ioptr == com->ihighwater
1848 && com->state & CS_RTS_IFLOW)
1849 outb(com->modem_ctl_port,
1850 com->mcr_image &= ~MCR_RTS);
1851 if (line_status & LSR_OE)
1852 CE_RECORD(com, CE_OVERRUN);
1853 }
1854cont:
1855 /*
1856 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
1857 * jump from the top of the loop to here
1858 */
1859 line_status = inb(com->line_status_port) & 0x7F;
1860 }
1861
1862 /* modem status change? (always check before doing output) */
1863 modem_status = inb(com->modem_status_port);
1864 if (modem_status != com->last_modem_status) {
1865 if (com->do_dcd_timestamp
1866 && !(com->last_modem_status & MSR_DCD)
1867 && modem_status & MSR_DCD)
1868 microtime(&com->dcd_timestamp);
1869
1870 /*
1871 * Schedule high level to handle DCD changes. Note
1872 * that we don't use the delta bits anywhere. Some
1873 * UARTs mess them up, and it's easy to remember the
1874 * previous bits and calculate the delta.
1875 */
1876 com->last_modem_status = modem_status;
1877 if (!(com->state & CS_CHECKMSR)) {
1878 com_events += LOTS_OF_EVENTS;
1879 com->state |= CS_CHECKMSR;
1880 setsofttty();
1881 }
1882
1883 /* handle CTS change immediately for crisp flow ctl */
1884 if (com->state & CS_CTS_OFLOW) {
1885 if (modem_status & MSR_CTS)
1886 com->state |= CS_ODEVREADY;
1887 else
1888 com->state &= ~CS_ODEVREADY;
1889 }
1890 }
1891
1892 /* output queued and everything ready? */
1893 if (line_status & LSR_TXRDY
1894 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
1895 ioptr = com->obufq.l_head;
1896 if (com->tx_fifo_size > 1) {
1897 u_int ocount;
1898
1899 ocount = com->obufq.l_tail - ioptr;
1900 if (ocount > com->tx_fifo_size)
1901 ocount = com->tx_fifo_size;
1902 com->bytes_out += ocount;
1903 do
1904 outb(com->data_port, *ioptr++);
1905 while (--ocount != 0);
1906 } else {
1907 outb(com->data_port, *ioptr++);
1908 ++com->bytes_out;
1909 }
1910 com->obufq.l_head = ioptr;
1911 if (COM_IIR_TXRDYBUG(com->flags)) {
1912 int_ctl_new = int_ctl | IER_ETXRDY;
1913 }
1914 if (ioptr >= com->obufq.l_tail) {
1915 struct lbq *qp;
1916
1917 qp = com->obufq.l_next;
1918 qp->l_queued = FALSE;
1919 qp = qp->l_next;
1920 if (qp != NULL) {
1921 com->obufq.l_head = qp->l_head;
1922 com->obufq.l_tail = qp->l_tail;
1923 com->obufq.l_next = qp;
1924 } else {
1925 /* output just completed */
1926 if (COM_IIR_TXRDYBUG(com->flags)) {
1927 int_ctl_new = int_ctl & ~IER_ETXRDY;
1928 }
1929 com->state &= ~CS_BUSY;
1930 }
1931 if (!(com->state & CS_ODONE)) {
1932 com_events += LOTS_OF_EVENTS;
1933 com->state |= CS_ODONE;
1934 setsofttty(); /* handle at high level ASAP */
1935 }
1936 }
1937 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
1938 outb(com->intr_ctl_port, int_ctl_new);
1939 }
1940 }
1941
1942 /* finished? */
1943#ifndef COM_MULTIPORT
1944 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
1945#endif /* COM_MULTIPORT */
1946 return;
1947 }
1948}
1949
1950static int
fef8985e 1951sioioctl(struct dev_ioctl_args *ap)
984263bc 1952{
b13267a5 1953 cdev_t dev = ap->a_head.a_dev;
fef8985e 1954 caddr_t data = ap->a_data;
984263bc
MD
1955 struct com_s *com;
1956 int error;
1957 int mynor;
984263bc
MD
1958 struct tty *tp;
1959#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1960 u_long oldcmd;
1961 struct termios term;
1962#endif
1963
1964 mynor = minor(dev);
1965 com = com_addr(MINOR_TO_UNIT(mynor));
1966 if (com == NULL || com->gone)
1967 return (ENODEV);
1968 if (mynor & CONTROL_MASK) {
1969 struct termios *ct;
1970
1971 switch (mynor & CONTROL_MASK) {
1972 case CONTROL_INIT_STATE:
1973 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
1974 break;
1975 case CONTROL_LOCK_STATE:
1976 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
1977 break;
1978 default:
1979 return (ENODEV); /* /dev/nodev */
1980 }
fef8985e 1981 switch (ap->a_cmd) {
984263bc 1982 case TIOCSETA:
895c1f85 1983 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
984263bc
MD
1984 if (error != 0)
1985 return (error);
1986 *ct = *(struct termios *)data;
1987 return (0);
1988 case TIOCGETA:
1989 *(struct termios *)data = *ct;
1990 return (0);
1991 case TIOCGETD:
1992 *(int *)data = TTYDISC;
1993 return (0);
1994 case TIOCGWINSZ:
1995 bzero(data, sizeof(struct winsize));
1996 return (0);
1997 default:
1998 return (ENOTTY);
1999 }
2000 }
2001 tp = com->tp;
2002#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2003 term = tp->t_termios;
fef8985e
MD
2004 oldcmd = ap->a_cmd;
2005 error = ttsetcompat(tp, &ap->a_cmd, data, &term);
984263bc
MD
2006 if (error != 0)
2007 return (error);
fef8985e 2008 if (ap->a_cmd != oldcmd)
984263bc
MD
2009 data = (caddr_t)&term;
2010#endif
fef8985e
MD
2011 if (ap->a_cmd == TIOCSETA || ap->a_cmd == TIOCSETAW ||
2012 ap->a_cmd == TIOCSETAF) {
984263bc
MD
2013 int cc;
2014 struct termios *dt = (struct termios *)data;
2015 struct termios *lt = mynor & CALLOUT_MASK
2016 ? &com->lt_out : &com->lt_in;
2017
2018 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2019 | (dt->c_iflag & ~lt->c_iflag);
2020 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2021 | (dt->c_oflag & ~lt->c_oflag);
2022 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2023 | (dt->c_cflag & ~lt->c_cflag);
2024 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2025 | (dt->c_lflag & ~lt->c_lflag);
2026 for (cc = 0; cc < NCCS; ++cc)
2027 if (lt->c_cc[cc] != 0)
2028 dt->c_cc[cc] = tp->t_cc[cc];
2029 if (lt->c_ispeed != 0)
2030 dt->c_ispeed = tp->t_ispeed;
2031 if (lt->c_ospeed != 0)
2032 dt->c_ospeed = tp->t_ospeed;
2033 }
fef8985e 2034 error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, data, ap->a_fflag, ap->a_cred);
984263bc
MD
2035 if (error != ENOIOCTL)
2036 return (error);
8d77660e 2037 crit_enter();
fef8985e 2038 error = ttioctl(tp, ap->a_cmd, data, ap->a_fflag);
984263bc
MD
2039 disc_optim(tp, &tp->t_termios, com);
2040 if (error != ENOIOCTL) {
8d77660e 2041 crit_exit();
984263bc
MD
2042 return (error);
2043 }
fef8985e 2044 switch (ap->a_cmd) {
984263bc
MD
2045 case TIOCSBRK:
2046 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2047 break;
2048 case TIOCCBRK:
2049 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2050 break;
2051 case TIOCSDTR:
2052 (void)commctl(com, TIOCM_DTR, DMBIS);
2053 break;
2054 case TIOCCDTR:
2055 (void)commctl(com, TIOCM_DTR, DMBIC);
2056 break;
2057 /*
2058 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2059 * changes get undone on the next call to comparam().
2060 */
2061 case TIOCMSET:
2062 (void)commctl(com, *(int *)data, DMSET);
2063 break;
2064 case TIOCMBIS:
2065 (void)commctl(com, *(int *)data, DMBIS);
2066 break;
2067 case TIOCMBIC:
2068 (void)commctl(com, *(int *)data, DMBIC);
2069 break;
2070 case TIOCMGET:
2071 *(int *)data = commctl(com, 0, DMGET);
2072 break;
2073 case TIOCMSDTRWAIT:
2074 /* must be root since the wait applies to following logins */
895c1f85 2075 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
984263bc 2076 if (error != 0) {
8d77660e 2077 crit_exit();
984263bc
MD
2078 return (error);
2079 }
2080 com->dtr_wait = *(int *)data * hz / 100;
2081 break;
2082 case TIOCMGDTRWAIT:
2083 *(int *)data = com->dtr_wait * 100 / hz;
2084 break;
2085 case TIOCTIMESTAMP:
2086 com->do_timestamp = TRUE;
2087 *(struct timeval *)data = com->timestamp;
2088 break;
2089 case TIOCDCDTIMESTAMP:
2090 com->do_dcd_timestamp = TRUE;
2091 *(struct timeval *)data = com->dcd_timestamp;
2092 break;
2093 default:
8d77660e 2094 crit_exit();
fef8985e 2095 error = pps_ioctl(ap->a_cmd, data, &com->pps);
984263bc
MD
2096 if (error == ENODEV)
2097 error = ENOTTY;
2098 return (error);
2099 }
8d77660e 2100 crit_exit();
984263bc
MD
2101 return (0);
2102}
2103
2104static void
477d3c1c 2105siopoll(void *dummy, void *frame)
984263bc
MD
2106{
2107 int unit;
2108
2109 if (com_events == 0)
2110 return;
2111repeat:
2112 for (unit = 0; unit < sio_numunits; ++unit) {
2113 struct com_s *com;
2114 int incc;
2115 struct tty *tp;
2116
2117 com = com_addr(unit);
2118 if (com == NULL)
2119 continue;
2120 tp = com->tp;
2121 if (tp == NULL || com->gone) {
2122 /*
2123 * Discard any events related to never-opened or
2124 * going-away devices.
2125 */
8a8d5d85 2126 com_lock();
984263bc
MD
2127 incc = com->iptr - com->ibuf;
2128 com->iptr = com->ibuf;
2129 if (com->state & CS_CHECKMSR) {
2130 incc += LOTS_OF_EVENTS;
2131 com->state &= ~CS_CHECKMSR;
2132 }
2133 com_events -= incc;
8a8d5d85 2134 com_unlock();
984263bc
MD
2135 continue;
2136 }
2137 if (com->iptr != com->ibuf) {
8a8d5d85 2138 com_lock();
984263bc 2139 sioinput(com);
8a8d5d85 2140 com_unlock();
984263bc
MD
2141 }
2142 if (com->state & CS_CHECKMSR) {
2143 u_char delta_modem_status;
2144
8a8d5d85 2145 com_lock();
984263bc
MD
2146 delta_modem_status = com->last_modem_status
2147 ^ com->prev_modem_status;
2148 com->prev_modem_status = com->last_modem_status;
2149 com_events -= LOTS_OF_EVENTS;
2150 com->state &= ~CS_CHECKMSR;
8a8d5d85 2151 com_unlock();
984263bc
MD
2152 if (delta_modem_status & MSR_DCD)
2153 (*linesw[tp->t_line].l_modem)
2154 (tp, com->prev_modem_status & MSR_DCD);
2155 }
2156 if (com->state & CS_ODONE) {
8a8d5d85 2157 com_lock();
984263bc
MD
2158 com_events -= LOTS_OF_EVENTS;
2159 com->state &= ~CS_ODONE;
8a8d5d85 2160 com_unlock();
984263bc
MD
2161 if (!(com->state & CS_BUSY)
2162 && !(com->extra_state & CSE_BUSYCHECK)) {
917e5fda
MD
2163 callout_reset(&com->busy_ch, hz / 100,
2164 siobusycheck, com);
984263bc
MD
2165 com->extra_state |= CSE_BUSYCHECK;
2166 }
2167 (*linesw[tp->t_line].l_start)(tp);
2168 }
2169 if (com_events == 0)
2170 break;
2171 }
2172 if (com_events >= LOTS_OF_EVENTS)
2173 goto repeat;
2174}
2175
2176static int
ce63e0fa 2177comparam(struct tty *tp, struct termios *t)
984263bc
MD
2178{
2179 u_int cfcr;
2180 int cflag;
2181 struct com_s *com;
2182 u_int divisor;
2183 u_char dlbh;
2184 u_char dlbl;
984263bc
MD
2185 int unit;
2186
2187 unit = DEV_TO_UNIT(tp->t_dev);
2188 com = com_addr(unit);
2189 if (com == NULL)
2190 return (ENODEV);
2191
2192 /* do historical conversions */
2193 if (t->c_ispeed == 0)
2194 t->c_ispeed = t->c_ospeed;
2195
2196 /* check requested parameters */
2197 if (t->c_ospeed == 0)
2198 divisor = 0;
2199 else {
2200 if (t->c_ispeed != t->c_ospeed)
2201 return (EINVAL);
2202 divisor = siodivisor(com->rclk, t->c_ispeed);
2203 if (divisor == 0)
2204 return (EINVAL);
2205 }
2206
2207 /* parameters are OK, convert them to the com struct and the device */
8d77660e 2208 crit_enter();
984263bc
MD
2209 if (divisor == 0)
2210 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2211 else
2212 (void)commctl(com, TIOCM_DTR, DMBIS);
2213 cflag = t->c_cflag;
2214 switch (cflag & CSIZE) {
2215 case CS5:
2216 cfcr = CFCR_5BITS;
2217 break;
2218 case CS6:
2219 cfcr = CFCR_6BITS;
2220 break;
2221 case CS7:
2222 cfcr = CFCR_7BITS;
2223 break;
2224 default:
2225 cfcr = CFCR_8BITS;
2226 break;
2227 }
2228 if (cflag & PARENB) {
2229 cfcr |= CFCR_PENAB;
2230 if (!(cflag & PARODD))
2231 cfcr |= CFCR_PEVEN;
2232 }
2233 if (cflag & CSTOPB)
2234 cfcr |= CFCR_STOPB;
2235
2236 if (com->hasfifo && divisor != 0) {
2237 /*
2238 * Use a fifo trigger level low enough so that the input
2239 * latency from the fifo is less than about 16 msec and
2240 * the total latency is less than about 30 msec. These
2241 * latencies are reasonable for humans. Serial comms
2242 * protocols shouldn't expect anything better since modem
2243 * latencies are larger.
2244 *
2245 * Interrupts can be held up for long periods of time
2246 * due to inefficiencies in other parts of the kernel,
2247 * certain video cards, etc. Setting the FIFO trigger
2248 * point to MEDH instead of HIGH gives us 694uS of slop
2249 * (8 character times) instead of 173uS (2 character times)
2250 * @ 115200 bps.
2251 */
2252 com->fifo_image = t->c_ospeed <= 4800
2253 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2254#ifdef COM_ESP
2255 /*
2256 * The Hayes ESP card needs the fifo DMA mode bit set
2257 * in compatibility mode. If not, it will interrupt
2258 * for each character received.
2259 */
2260 if (com->esp)
2261 com->fifo_image |= FIFO_DMA_MODE;
2262#endif
2263 sio_setreg(com, com_fifo, com->fifo_image);
2264 }
2265
2266 /*
2267 * This returns with interrupts disabled so that we can complete
2268 * the speed change atomically. Keeping interrupts disabled is
2269 * especially important while com_data is hidden.
2270 */
2271 (void) siosetwater(com, t->c_ispeed);
2272
2273 if (divisor != 0) {
2274 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2275 /*
2276 * Only set the divisor registers if they would change,
2277 * since on some 16550 incompatibles (UMC8669F), setting
2278 * them while input is arriving them loses sync until
2279 * data stops arriving.
2280 */
2281 dlbl = divisor & 0xFF;
2282 if (sio_getreg(com, com_dlbl) != dlbl)
2283 sio_setreg(com, com_dlbl, dlbl);
2284 dlbh = divisor >> 8;
2285 if (sio_getreg(com, com_dlbh) != dlbh)
2286 sio_setreg(com, com_dlbh, dlbh);
2287 }
2288
2289 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2290
2291 if (!(tp->t_state & TS_TTSTOP))
2292 com->state |= CS_TTGO;
2293
2294 if (cflag & CRTS_IFLOW) {
2295 if (com->st16650a) {
2296 sio_setreg(com, com_cfcr, 0xbf);
2297 sio_setreg(com, com_fifo,
2298 sio_getreg(com, com_fifo) | 0x40);
2299 }
2300 com->state |= CS_RTS_IFLOW;
2301 /*
2302 * If CS_RTS_IFLOW just changed from off to on, the change
2303 * needs to be propagated to MCR_RTS. This isn't urgent,
2304 * so do it later by calling comstart() instead of repeating
2305 * a lot of code from comstart() here.
2306 */
2307 } else if (com->state & CS_RTS_IFLOW) {
2308 com->state &= ~CS_RTS_IFLOW;
2309 /*
2310 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2311 * on here, since comstart() won't do it later.
2312 */
2313 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2314 if (com->st16650a) {
2315 sio_setreg(com, com_cfcr, 0xbf);
2316 sio_setreg(com, com_fifo,
2317 sio_getreg(com, com_fifo) & ~0x40);
2318 }
2319 }
2320
2321
2322 /*
2323 * Set up state to handle output flow control.
2324 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2325 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2326 */
2327 com->state |= CS_ODEVREADY;
2328 com->state &= ~CS_CTS_OFLOW;
2329 if (cflag & CCTS_OFLOW) {
2330 com->state |= CS_CTS_OFLOW;
2331 if (!(com->last_modem_status & MSR_CTS))
2332 com->state &= ~CS_ODEVREADY;
2333 if (com->st16650a) {
2334 sio_setreg(com, com_cfcr, 0xbf);
2335 sio_setreg(com, com_fifo,
2336 sio_getreg(com, com_fifo) | 0x80);
2337 }
2338 } else {
2339 if (com->st16650a) {
2340 sio_setreg(com, com_cfcr, 0xbf);
2341 sio_setreg(com, com_fifo,
2342 sio_getreg(com, com_fifo) & ~0x80);
2343 }
2344 }
2345
2346 sio_setreg(com, com_cfcr, com->cfcr_image);
2347
2348 /* XXX shouldn't call functions while intrs are disabled. */
2349 disc_optim(tp, t, com);
2350 /*
2351 * Recover from fiddling with CS_TTGO. We used to call siointr1()
2352 * unconditionally, but that defeated the careful discarding of
2353 * stale input in sioopen().
2354 */
2355 if (com->state >= (CS_BUSY | CS_TTGO))
2356 siointr1(com);
2357
8a8d5d85 2358 com_unlock();
8d77660e 2359 crit_exit();
984263bc
MD
2360 comstart(tp);
2361 if (com->ibufold != NULL) {
efda3bd0 2362 kfree(com->ibufold, M_DEVBUF);
984263bc
MD
2363 com->ibufold = NULL;
2364 }
2365 return (0);
2366}
2367
2368static int
ce63e0fa 2369siosetwater(struct com_s *com, speed_t speed)
984263bc
MD
2370{
2371 int cp4ticks;
2372 u_char *ibuf;
2373 int ibufsize;
2374 struct tty *tp;
2375
2376 /*
2377 * Make the buffer size large enough to handle a softtty interrupt
2378 * latency of about 2 ticks without loss of throughput or data
2379 * (about 3 ticks if input flow control is not used or not honoured,
2380 * but a bit less for CS5-CS7 modes).
2381 */
2382 cp4ticks = speed / 10 / hz * 4;
2383 for (ibufsize = 128; ibufsize < cp4ticks;)
2384 ibufsize <<= 1;
2385 if (ibufsize == com->ibufsize) {
8a8d5d85 2386 com_lock();
984263bc
MD
2387 return (0);
2388 }
2389
2390 /*
2391 * Allocate input buffer. The extra factor of 2 in the size is
2392 * to allow for an error byte for each input byte.
2393 */
efda3bd0 2394 ibuf = kmalloc(2 * ibufsize, M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
2395
2396 /* Initialize non-critical variables. */
2397 com->ibufold = com->ibuf;
2398 com->ibufsize = ibufsize;
2399 tp = com->tp;
2400 if (tp != NULL) {
2401 tp->t_ififosize = 2 * ibufsize;
2402 tp->t_ispeedwat = (speed_t)-1;
2403 tp->t_ospeedwat = (speed_t)-1;
2404 }
2405
2406 /*
2407 * Read current input buffer, if any. Continue with interrupts
2408 * disabled.
2409 */
8a8d5d85 2410 com_lock();
984263bc
MD
2411 if (com->iptr != com->ibuf)
2412 sioinput(com);
2413
2414 /*-
2415 * Initialize critical variables, including input buffer watermarks.
2416 * The external device is asked to stop sending when the buffer
2417 * exactly reaches high water, or when the high level requests it.
2418 * The high level is notified immediately (rather than at a later
2419 * clock tick) when this watermark is reached.
2420 * The buffer size is chosen so the watermark should almost never
2421 * be reached.
2422 * The low watermark is invisibly 0 since the buffer is always
2423 * emptied all at once.
2424 */
2425 com->iptr = com->ibuf = ibuf;
2426 com->ibufend = ibuf + ibufsize;
2427 com->ierroff = ibufsize;
2428 com->ihighwater = ibuf + 3 * ibufsize / 4;
2429 return (0);
2430}
2431
2432static void
ce63e0fa 2433comstart(struct tty *tp)
984263bc
MD
2434{
2435 struct com_s *com;
984263bc
MD
2436 int unit;
2437
2438 unit = DEV_TO_UNIT(tp->t_dev);
2439 com = com_addr(unit);
2440 if (com == NULL)
2441 return;
8d77660e 2442 crit_enter();
8a8d5d85 2443 com_lock();
984263bc
MD
2444 if (tp->t_state & TS_TTSTOP)
2445 com->state &= ~CS_TTGO;
2446 else
2447 com->state |= CS_TTGO;
2448 if (tp->t_state & TS_TBLOCK) {
2449 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2450 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2451 } else {
2452 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2453 && com->state & CS_RTS_IFLOW)
2454 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2455 }
8a8d5d85 2456 com_unlock();
984263bc
MD
2457 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2458 ttwwakeup(tp);
8d77660e 2459 crit_exit();
984263bc
MD
2460 return;
2461 }
2462 if (tp->t_outq.c_cc != 0) {
2463 struct lbq *qp;
2464 struct lbq *next;
2465
2466 if (!com->obufs[0].l_queued) {
2467 com->obufs[0].l_tail
2468 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2469 sizeof com->obuf1);
2470 com->obufs[0].l_next = NULL;
2471 com->obufs[0].l_queued = TRUE;
8a8d5d85 2472 com_lock();
984263bc
MD
2473 if (com->state & CS_BUSY) {
2474 qp = com->obufq.l_next;
2475 while ((next = qp->l_next) != NULL)
2476 qp = next;
2477 qp->l_next = &com->obufs[0];
2478 } else {
2479 com->obufq.l_head = com->obufs[0].l_head;
2480 com->obufq.l_tail = com->obufs[0].l_tail;
2481 com->obufq.l_next = &com->obufs[0];
2482 com->state |= CS_BUSY;
2483 }
8a8d5d85 2484 com_unlock();
984263bc
MD
2485 }
2486 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2487 com->obufs[1].l_tail
2488 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2489 sizeof com->obuf2);
2490 com->obufs[1].l_next = NULL;
2491 com->obufs[1].l_queued = TRUE;
8a8d5d85 2492 com_lock();
984263bc
MD
2493 if (com->state & CS_BUSY) {
2494 qp = com->obufq.l_next;
2495 while ((next = qp->l_next) != NULL)
2496 qp = next;
2497 qp->l_next = &com->obufs[1];
2498 } else {
2499 com->obufq.l_head = com->obufs[1].l_head;
2500 com->obufq.l_tail = com->obufs[1].l_tail;
2501 com->obufq.l_next = &com->obufs[1];
2502 com->state |= CS_BUSY;
2503 }
8a8d5d85 2504 com_unlock();
984263bc
MD
2505 }
2506 tp->t_state |= TS_BUSY;
2507 }
8a8d5d85 2508 com_lock();
984263bc
MD
2509 if (com->state >= (CS_BUSY | CS_TTGO))
2510 siointr1(com); /* fake interrupt to start output */
8a8d5d85 2511 com_unlock();
984263bc 2512 ttwwakeup(tp);
8d77660e 2513 crit_exit();
984263bc
MD
2514}
2515
2516static void
ce63e0fa 2517comstop(struct tty *tp, int rw)
984263bc
MD
2518{
2519 struct com_s *com;
2520
2521 com = com_addr(DEV_TO_UNIT(tp->t_dev));
2522 if (com == NULL || com->gone)
2523 return;
8a8d5d85 2524 com_lock();
984263bc
MD
2525 if (rw & FWRITE) {
2526 if (com->hasfifo)
2527#ifdef COM_ESP
2528 /* XXX avoid h/w bug. */
2529 if (!com->esp)
2530#endif
2531 sio_setreg(com, com_fifo,
2532 FIFO_XMT_RST | com->fifo_image);
2533 com->obufs[0].l_queued = FALSE;
2534 com->obufs[1].l_queued = FALSE;
2535 if (com->state & CS_ODONE)
2536 com_events -= LOTS_OF_EVENTS;
2537 com->state &= ~(CS_ODONE | CS_BUSY);
2538 com->tp->t_state &= ~TS_BUSY;
2539 }
2540 if (rw & FREAD) {
2541 if (com->hasfifo)
2542#ifdef COM_ESP
2543 /* XXX avoid h/w bug. */
2544 if (!com->esp)
2545#endif
2546 sio_setreg(com, com_fifo,
2547 FIFO_RCV_RST | com->fifo_image);
2548 com_events -= (com->iptr - com->ibuf);
2549 com->iptr = com->ibuf;
2550 }
8a8d5d85 2551 com_unlock();
984263bc
MD
2552 comstart(tp);
2553}
2554
2555static int
ce63e0fa 2556commctl(struct com_s *com, int bits, int how)
984263bc
MD
2557{
2558 int mcr;
2559 int msr;
2560
2561 if (how == DMGET) {
2562 bits = TIOCM_LE; /* XXX - always enabled while open */
2563 mcr = com->mcr_image;
2564 if (mcr & MCR_DTR)
2565 bits |= TIOCM_DTR;
2566 if (mcr & MCR_RTS)
2567 bits |= TIOCM_RTS;
2568 msr = com->prev_modem_status;
2569 if (msr & MSR_CTS)
2570 bits |= TIOCM_CTS;
2571 if (msr & MSR_DCD)
2572 bits |= TIOCM_CD;
2573 if (msr & MSR_DSR)
2574 bits |= TIOCM_DSR;
2575 /*
2576 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2577 * more volatile by reading the modem status a lot. Perhaps
2578 * we should latch both bits until the status is read here.
2579 */
2580 if (msr & (MSR_RI | MSR_TERI))
2581 bits |= TIOCM_RI;
2582 return (bits);
2583 }
2584 mcr = 0;
2585 if (bits & TIOCM_DTR)
2586 mcr |= MCR_DTR;
2587 if (bits & TIOCM_RTS)
2588 mcr |= MCR_RTS;
2589 if (com->gone)
2590 return(0);
8a8d5d85 2591 com_lock();
984263bc
MD
2592 switch (how) {
2593 case DMSET:
2594 outb(com->modem_ctl_port,
2595 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2596 break;
2597 case DMBIS:
2598 outb(com->modem_ctl_port, com->mcr_image |= mcr);
2599 break;
2600 case DMBIC:
2601 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2602 break;
2603 }
8a8d5d85 2604 com_unlock();
984263bc
MD
2605 return (0);
2606}
2607
2608static void
ce63e0fa 2609siosettimeout(void)
984263bc
MD
2610{
2611 struct com_s *com;
2612 bool_t someopen;
2613 int unit;
2614
2615 /*
2616 * Set our timeout period to 1 second if no polled devices are open.
2617 * Otherwise set it to max(1/200, 1/hz).
2618 * Enable timeouts iff some device is open.
2619 */
54607efb 2620 callout_stop(&sio_timeout_handle);
984263bc
MD
2621 sio_timeout = hz;
2622 someopen = FALSE;
2623 for (unit = 0; unit < sio_numunits; ++unit) {
2624 com = com_addr(unit);
2625 if (com != NULL && com->tp != NULL
2626 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2627 someopen = TRUE;
2628 if (com->poll || com->poll_output) {
2629 sio_timeout = hz > 200 ? hz / 200 : 1;
2630 break;
2631 }
2632 }
2633 }
2634 if (someopen) {
2635 sio_timeouts_until_log = hz / sio_timeout;
54607efb
MD
2636 callout_reset(&sio_timeout_handle, sio_timeout,
2637 comwakeup, NULL);
984263bc
MD
2638 } else {
2639 /* Flush error messages, if any. */
2640 sio_timeouts_until_log = 1;
3641b7ca 2641 comwakeup(NULL);
54607efb 2642 callout_stop(&sio_timeout_handle);
984263bc
MD
2643 }
2644}
2645
2646static void
ce63e0fa 2647comwakeup(void *chan)
984263bc
MD
2648{
2649 struct com_s *com;
2650 int unit;
2651
54607efb 2652 callout_reset(&sio_timeout_handle, sio_timeout, comwakeup, NULL);
984263bc
MD
2653
2654 /*
2655 * Recover from lost output interrupts.
2656 * Poll any lines that don't use interrupts.
2657 */
2658 for (unit = 0; unit < sio_numunits; ++unit) {
2659 com = com_addr(unit);
2660 if (com != NULL && !com->gone
2661 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
8a8d5d85 2662 com_lock();
984263bc 2663 siointr1(com);
8a8d5d85 2664 com_unlock();
984263bc
MD
2665 }
2666 }
2667
2668 /*
2669 * Check for and log errors, but not too often.
2670 */
2671 if (--sio_timeouts_until_log > 0)
2672 return;
2673 sio_timeouts_until_log = hz / sio_timeout;
2674 for (unit = 0; unit < sio_numunits; ++unit) {
2675 int errnum;
2676
2677 com = com_addr(unit);
2678 if (com == NULL)
2679 continue;
2680 if (com->gone)
2681 continue;
2682 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2683 u_int delta;
2684 u_long total;
2685
8a8d5d85 2686 com_lock();
984263bc
MD
2687 delta = com->delta_error_counts[errnum];
2688 com->delta_error_counts[errnum] = 0;
8a8d5d85 2689 com_unlock();
984263bc
MD
2690 if (delta == 0)
2691 continue;
2692 total = com->error_counts[errnum] += delta;
2693 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2694 unit, delta, error_desc[errnum],
2695 delta == 1 ? "" : "s", total);
2696 }
2697 }
2698}
2699
2700static void
ce63e0fa 2701disc_optim(struct tty *tp, struct termios *t, struct com_s *com)
984263bc
MD
2702{
2703 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2704 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2705 && (!(t->c_iflag & PARMRK)
2706 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2707 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2708 && linesw[tp->t_line].l_rint == ttyinput)
2709 tp->t_state |= TS_CAN_BYPASS_L_RINT;
2710 else
2711 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2712 com->hotchar = linesw[tp->t_line].l_hotchar;
2713}
2714
2715/*
2716 * Following are all routines needed for SIO to act as console
2717 */
2718#include <sys/cons.h>
2719
2720struct siocnstate {
2721 u_char dlbl;
2722 u_char dlbh;
2723 u_char ier;
2724 u_char cfcr;
2725 u_char mcr;
2726};
2727
5ca58d54
RG
2728static speed_t siocngetspeed (Port_t, u_long rclk);
2729static void siocnclose (struct siocnstate *sp, Port_t iobase);
2730static void siocnopen (struct siocnstate *sp, Port_t iobase, int speed);
2731static void siocntxwait (Port_t iobase);
984263bc
MD
2732
2733static cn_probe_t siocnprobe;
2734static cn_init_t siocninit;
ce81f184 2735static cn_init_fini_t siocninit_fini;
984263bc
MD
2736static cn_checkc_t siocncheckc;
2737static cn_getc_t siocngetc;
2738static cn_putc_t siocnputc;
2739
8d565796 2740#if defined(__i386__) || defined(__amd64__)
ce81f184
MD
2741CONS_DRIVER(sio, siocnprobe, siocninit, siocninit_fini,
2742 NULL, siocngetc, siocncheckc, siocnputc, NULL);
984263bc
MD
2743#endif
2744
2745/* To get the GDB related variables */
2746#if DDB > 0
2747#include <ddb/ddb.h>
2748#endif
2749
2750static void
ce63e0fa 2751siocntxwait(Port_t iobase)
984263bc
MD
2752{
2753 int timo;
2754
2755 /*
2756 * Wait for any pending transmission to finish. Required to avoid
2757 * the UART lockup bug when the speed is changed, and for normal
2758 * transmits.
2759 */
2760 timo = 100000;
2761 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
2762 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
2763 ;
2764}
2765
2766/*
2767 * Read the serial port specified and try to figure out what speed
2768 * it's currently running at. We're assuming the serial port has
2769 * been initialized and is basicly idle. This routine is only intended
2770 * to be run at system startup.
2771 *
2772 * If the value read from the serial port doesn't make sense, return 0.
2773 */
2774
2775static speed_t
ce63e0fa 2776siocngetspeed(Port_t iobase, u_long rclk)
984263bc
MD
2777{
2778 u_int divisor;
2779 u_char dlbh;
2780 u_char dlbl;
2781 u_char cfcr;
2782
2783 cfcr = inb(iobase + com_cfcr);
2784 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2785
2786 dlbl = inb(iobase + com_dlbl);
2787 dlbh = inb(iobase + com_dlbh);
2788
2789 outb(iobase + com_cfcr, cfcr);
2790
2791 divisor = dlbh << 8 | dlbl;
2792
2793 /* XXX there should be more sanity checking. */
2794 if (divisor == 0)
2795 return (CONSPEED);
2796 return (rclk / (16UL * divisor));
2797}
2798
2799static void
ce63e0fa 2800siocnopen(struct siocnstate *sp, Port_t iobase, int speed)
984263bc
MD
2801{
2802 u_int divisor;
2803 u_char dlbh;
2804 u_char dlbl;
2805
2806 /*
2807 * Save all the device control registers except the fifo register
2808 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2809 * We can't save the fifo register since it is read-only.
2810 */
2811 sp->ier = inb(iobase + com_ier);
2812 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
2813 siocntxwait(iobase);
2814 sp->cfcr = inb(iobase + com_cfcr);
2815 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2816 sp->dlbl = inb(iobase + com_dlbl);
2817 sp->dlbh = inb(iobase + com_dlbh);
2818 /*
2819 * Only set the divisor registers if they would change, since on
2820 * some 16550 incompatibles (Startech), setting them clears the
2821 * data input register. This also reduces the effects of the
2822 * UMC8669F bug.
2823 */
2824 divisor = siodivisor(comdefaultrclk, speed);
2825 dlbl = divisor & 0xFF;
2826 if (sp->dlbl != dlbl)
2827 outb(iobase + com_dlbl, dlbl);
2828 dlbh = divisor >> 8;
2829 if (sp->dlbh != dlbh)
2830 outb(iobase + com_dlbh, dlbh);
2831 outb(iobase + com_cfcr, CFCR_8BITS);
2832 sp->mcr = inb(iobase + com_mcr);
2833 /*
2834 * We don't want interrupts, but must be careful not to "disable"
2835 * them by clearing the MCR_IENABLE bit, since that might cause
2836 * an interrupt by floating the IRQ line.
2837 */
2838 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
2839}
2840
2841static void
ce63e0fa 2842siocnclose(struct siocnstate *sp, Port_t iobase)
984263bc
MD
2843{
2844 /*
2845 * Restore the device control registers.
2846 */
2847 siocntxwait(iobase);
2848 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2849 if (sp->dlbl != inb(iobase + com_dlbl))
2850 outb(iobase + com_dlbl, sp->dlbl);
2851 if (sp->dlbh != inb(iobase + com_dlbh))
2852 outb(iobase + com_dlbh, sp->dlbh);
2853 outb(iobase + com_cfcr, sp->cfcr);
2854 /*
2855 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
2856 */
2857 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
2858 outb(iobase + com_ier, sp->ier);
2859}
2860
2861static void
ce63e0fa 2862siocnprobe(struct consdev *cp)
984263bc
MD
2863{
2864 speed_t boot_speed;
2865 u_char cfcr;
2866 u_int divisor;
a6a7d26b 2867 int unit;
984263bc
MD
2868 struct siocnstate sp;
2869
2870 /*
2871 * Find our first enabled console, if any. If it is a high-level
2872 * console device, then initialize it and return successfully.
2873 * If it is a low-level console device, then initialize it and
2874 * return unsuccessfully. It must be initialized in both cases
2875 * for early use by console drivers and debuggers. Initializing
2876 * the hardware is not necessary in all cases, since the i/o
2877 * routines initialize it on the fly, but it is necessary if
2878 * input might arrive while the hardware is switched back to an
2879 * uninitialized state. We can't handle multiple console devices
2880 * yet because our low-level routines don't take a device arg.
2881 * We trust the user to set the console flags properly so that we
2882 * don't need to probe.
2883 */
2884 cp->cn_pri = CN_DEAD;
2885
2886 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
2887 int flags;
2888 int disabled;
2889 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
2890 if (disabled)
2891 continue;
2892 }
2893 if (resource_int_value("sio", unit, "flags", &flags))
2894 continue;
2895 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
2896 int port;
2897 Port_t iobase;
2898
2899 if (resource_int_value("sio", unit, "port", &port))
2900 continue;
2901 iobase = port;
8d77660e 2902 crit_enter();
984263bc
MD
2903 if (boothowto & RB_SERIAL) {
2904 boot_speed =
2905 siocngetspeed(iobase, comdefaultrclk);
2906 if (boot_speed)
2907 comdefaultrate = boot_speed;
2908 }
2909
2910 /*
2911 * Initialize the divisor latch. We can't rely on
2912 * siocnopen() to do this the first time, since it
2913 * avoids writing to the latch if the latch appears
2914 * to have the correct value. Also, if we didn't
2915 * just read the speed from the hardware, then we
2916 * need to set the speed in hardware so that
2917 * switching it later is null.
2918 */
2919 cfcr = inb(iobase + com_cfcr);
2920 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2921 divisor = siodivisor(comdefaultrclk, comdefaultrate);
2922 outb(iobase + com_dlbl, divisor & 0xff);
2923 outb(iobase + com_dlbh, divisor >> 8);
2924 outb(iobase + com_cfcr, cfcr);
2925
2926 siocnopen(&sp, iobase, comdefaultrate);
2927
8d77660e 2928 crit_exit();
984263bc 2929 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
ce81f184 2930 cp->cn_probegood = 1;
973c11b9 2931 cp->cn_private = (void *)(intptr_t)unit;
984263bc
MD
2932 cp->cn_pri = COM_FORCECONSOLE(flags)
2933 || boothowto & RB_SERIAL
2934 ? CN_REMOTE : CN_NORMAL;
2935 siocniobase = iobase;
2936 siocnunit = unit;
2937 }
ce81f184 2938 if (COM_DEBUGGER(flags) && gdb_tab == NULL) {
e3869ec7 2939 kprintf("sio%d: gdb debugging port\n", unit);
984263bc
MD
2940 siogdbiobase = iobase;
2941 siogdbunit = unit;
2942#if DDB > 0
973c11b9 2943 cp->cn_gdbprivate = (void *)(intptr_t)unit;
ce81f184 2944 gdb_tab = cp;
984263bc
MD
2945#endif
2946 }
2947 }
2948 }
8d565796 2949#if defined(__i386__) || defined(__amd64__)
984263bc
MD
2950#if DDB > 0
2951 /*
2952 * XXX Ugly Compatability.
2953 * If no gdb port has been specified, set it to be the console
2954 * as some configuration files don't specify the gdb port.
2955 */
ce81f184 2956 if (gdb_tab == NULL && (boothowto & RB_GDB)) {
e3869ec7 2957 kprintf("Warning: no GDB port specified. Defaulting to sio%d.\n",
984263bc 2958 siocnunit);
e3869ec7
SW
2959 kprintf("Set flag 0x80 on desired GDB port in your\n");
2960 kprintf("configuration file (currently sio only).\n");
984263bc
MD
2961 siogdbiobase = siocniobase;
2962 siogdbunit = siocnunit;
973c11b9 2963 cp->cn_gdbprivate = (void *)(intptr_t)siocnunit;
ce81f184 2964 gdb_tab = cp;
984263bc
MD
2965 }
2966#endif
2967#endif
2968}
2969
984263bc 2970static void
ce63e0fa 2971siocninit(struct consdev *cp)
984263bc 2972{
ce81f184
MD
2973 comconsole = (int)(intptr_t)cp->cn_private;
2974}
2975
2976static void
2977siocninit_fini(struct consdev *cp)
2978{
2979 int unit;
2980
ce81f184
MD
2981 if (cp->cn_probegood) {
2982 unit = (int)(intptr_t)cp->cn_private;
2983 cp->cn_dev = make_dev(&sio_ops, unit,
2984 UID_ROOT, GID_WHEEL, 0600,
2985 "ttyd%r", unit);
2986 }
984263bc
MD
2987}
2988
2989static int
ce81f184 2990siocncheckc(void *private)
984263bc
MD
2991{
2992 int c;
ce81f184 2993 int unit = (int)(intptr_t)private;
984263bc 2994 Port_t iobase;
984263bc
MD
2995 struct siocnstate sp;
2996
ce81f184 2997 if (unit == siogdbunit)
984263bc
MD
2998 iobase = siogdbiobase;
2999 else
3000 iobase = siocniobase;
8d77660e 3001 crit_enter();
984263bc
MD
3002 siocnopen(&sp, iobase, comdefaultrate);
3003 if (inb(iobase + com_lsr) & LSR_RXRDY)
3004 c = inb(iobase + com_data);
3005 else
3006 c = -1;
3007 siocnclose(&sp, iobase);
8d77660e 3008 crit_exit();
984263bc
MD
3009 return (c);
3010}
3011
3012
3013int
ce81f184 3014siocngetc(void *private)
984263bc
MD
3015{
3016 int c;
ce81f184 3017 int unit = (int)(intptr_t)private;
984263bc 3018 Port_t iobase;
984263bc
MD
3019 struct siocnstate sp;
3020
ce81f184 3021 if (unit == siogdbunit)
984263bc
MD
3022 iobase = siogdbiobase;
3023 else
3024 iobase = siocniobase;
8d77660e 3025 crit_enter();
984263bc
MD
3026 siocnopen(&sp, iobase, comdefaultrate);
3027 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3028 ;
3029 c = inb(iobase + com_data);
3030 siocnclose(&sp, iobase);
8d77660e 3031 crit_exit();
984263bc
MD
3032 return (c);
3033}
3034
3035void
ce81f184 3036siocnputc(void *private, int c)
984263bc 3037{
ce81f184 3038 int unit = (int)(intptr_t)private;
984263bc
MD
3039 struct siocnstate sp;
3040 Port_t iobase;
3041
ce81f184 3042 if (unit == siogdbunit)
984263bc
MD
3043 iobase = siogdbiobase;
3044 else
3045 iobase = siocniobase;
8d77660e 3046 crit_enter();
984263bc
MD
3047 siocnopen(&sp, iobase, comdefaultrate);
3048 siocntxwait(iobase);
3049 outb(iobase + com_data, c);
3050 siocnclose(&sp, iobase);
8d77660e 3051 crit_exit();
984263bc
MD
3052}
3053
984263bc 3054DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
c8b4f0e6 3055DRIVER_MODULE(sio, acpi, sio_isa_driver, sio_devclass, 0, 0);
984263bc
MD
3056#if NPCI > 0
3057DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
3058#endif
3059#if NPUC > 0
3060DRIVER_MODULE(sio, puc, sio_puc_driver, sio_devclass, 0, 0);
3061#endif