ahci: Use MSI if device support it.
[dragonfly.git] / sys / dev / disk / ahci / ahci.h
CommitLineData
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1/*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
17 */
18
19#if defined(__DragonFly__)
20#include "ahci_dragonfly.h"
21#else
22#error "build for OS unknown"
23#endif
2cc2e845 24#include "pmreg.h"
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25#include "atascsi.h"
26
27/* change to AHCI_DEBUG for dmesg spam */
28#define NO_AHCI_DEBUG
29
30#ifdef AHCI_DEBUG
31#define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
32 while (0)
33#define AHCI_D_TIMEOUT 0x00
34#define AHCI_D_VERBOSE 0x01
35#define AHCI_D_INTR 0x02
36#define AHCI_D_XFER 0x08
37int ahcidebug = AHCI_D_VERBOSE;
38#else
39#define DPRINTF(m, f...)
40#endif
41
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42#define AHCI_PCI_ATI_SB600_MAGIC 0x40
43#define AHCI_PCI_ATI_SB600_LOCKED 0x01
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44
45#define AHCI_REG_CAP 0x000 /* HBA Capabilities */
46#define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
47#define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
48#define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
49#define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
50#define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
51#define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
52#define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
53#define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
54#define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */
55#define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
56#define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
57#define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
58#define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
59#define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
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60#define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */
61#define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */
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62#define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
63#define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
64#define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
65#define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
66#define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
67#define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
68#define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
69#define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
70#define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
71 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
72 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
73 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
74 "\010CCCS" "\007EMS" "\006SXS"
75
76#define AHCI_REG_GHC 0x004 /* Global HBA Control */
77#define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
78#define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
79#define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
80#define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
81#define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
82
83#define AHCI_REG_IS 0x008 /* Interrupt Status */
84#define AHCI_REG_PI 0x00c /* Ports Implemented */
85
86#define AHCI_REG_VS 0x010 /* AHCI Version */
87#define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
88#define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
89#define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
90#define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
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91#define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */
92#define AHCI_REG_VS_1_4 0x00010400 /* 1.4 */
93#define AHCI_REG_VS_1_5 0x00010500 /* 1.5 (future...) */
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94
95#define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
96#define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
97
98#define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
99#define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
100#define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
101
102#define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
103#define AHCI_PORT_SIZE 0x80
104
105#define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
106#define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
107#define AHCI_PREG_FB 0x08 /* FIS Base Addr */
108#define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
109
110#define AHCI_PREG_IS 0x10 /* Interrupt Status */
111#define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
112#define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
113#define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
114#define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
115#define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
116#define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
117#define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
118#define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
119#define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
120#define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
121#define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
122#define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
123#define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
124#define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
125#define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
126#define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
127#define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
128#define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
129 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
130 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
131 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
132 "\002PSS" "\001DHRS"
133
134#define AHCI_PREG_IE 0x14 /* Interrupt Enable */
135#define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
136#define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
137#define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
138#define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
139#define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
140#define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
141#define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
142#define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
143#define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
144#define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
145#define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
146#define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
147#define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
148#define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
149#define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
150#define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
151#define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
152#define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
153 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
154 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
155 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
156 "\002PSE" "\001DHRE"
157
158#define AHCI_PREG_CMD 0x18 /* Command and Status */
159#define AHCI_PREG_CMD_ST (1<<0) /* Start */
160#define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
161#define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
162#define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
163#define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
164#define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
165#define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
166#define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
167#define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
168#define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
169#define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
170#define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
171#define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
172#define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
173#define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
174#define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
175#define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
176#define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
177#define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
178#define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
179#define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
180#define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
181#define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
182#define AHCI_PREG_CMD_ICC_IDLE 0x00000000
183#define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
184 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \
185 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
186 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
187 "\003POD" "\002SUD" "\001ST"
188
189#define AHCI_PREG_TFD 0x20 /* Task File Data*/
190#define AHCI_PREG_TFD_STS 0xff
191#define AHCI_PREG_TFD_STS_ERR (1<<0)
192#define AHCI_PREG_TFD_STS_DRQ (1<<3)
193#define AHCI_PREG_TFD_STS_BSY (1<<7)
194#define AHCI_PREG_TFD_ERR 0xff00
195
196#define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
197#define AHCI_PREG_SIG 0x24 /* Signature */
198
199#define AHCI_PREG_SSTS 0x28 /* SATA Status */
200#define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
201#define AHCI_PREG_SSTS_DET_NONE 0x0
202#define AHCI_PREG_SSTS_DET_DEV_NE 0x1
203#define AHCI_PREG_SSTS_DET_DEV 0x3
204#define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
205#define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
206#define AHCI_PREG_SSTS_SPD_NONE 0x00
207#define AHCI_PREG_SSTS_SPD_GEN1 0x10
208#define AHCI_PREG_SSTS_SPD_GEN2 0x20
8986d351 209#define AHCI_PREG_SSTS_SPD_GEN3 0x30
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210#define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
211#define AHCI_PREG_SSTS_IPM_NONE 0x000
212#define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
213#define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
214#define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
215
216#define AHCI_PREG_SCTL 0x2c /* SATA Control */
217#define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
218#define AHCI_PREG_SCTL_DET_NONE 0x0
219#define AHCI_PREG_SCTL_DET_INIT 0x1
220#define AHCI_PREG_SCTL_DET_DISABLE 0x4
221#define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
222#define AHCI_PREG_SCTL_SPD_ANY 0x00
223#define AHCI_PREG_SCTL_SPD_GEN1 0x10
224#define AHCI_PREG_SCTL_SPD_GEN2 0x20
8986d351 225#define AHCI_PREG_SCTL_SPD_GEN3 0x30
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226#define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
227#define AHCI_PREG_SCTL_IPM_NONE 0x000
228#define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
229#define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
230#define AHCI_PREG_SCTL_IPM_DISABLED 0x300
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231#define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */
232#define AHCI_PREG_SCTL_SPM_NONE 0x0000
233#define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000
234#define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000
235#define AHCI_PREG_SCTL_SPM_DISABLED 0x3000
236#define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */
237#define AHCI_PREG_SCTL_PMP_SHIFT 16
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238
239#define AHCI_PREG_SERR 0x30 /* SATA Error */
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240#define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
241#define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
242#define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
243#define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
244#define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
245#define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
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246#define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */
247#define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */
248#define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */
249#define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */
250#define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */
251#define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */
252#define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */
253#define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */
254#define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */
255#define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */
256#define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */
257
258#define AHCI_PFMT_SERR "\020" \
259 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \
260 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \
261 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \
262 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \
263 "\002ERR.M" "\001ERR.I"
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264
265#define AHCI_PREG_SACT 0x34 /* SATA Active */
266#define AHCI_PREG_CI 0x38 /* Command Issue */
267#define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
268#define AHCI_PREG_SNTF 0x3c /* SNotification */
269
1980eff3 270/*
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271 * AHCI mapped structures
272 */
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273struct ahci_cmd_hdr {
274 u_int16_t flags;
275#define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
276#define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
277#define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
278#define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
279#define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
280#define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
281#define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
282#define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
1980eff3 283#define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
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284 u_int16_t prdtl; /* sgl len */
285
286 u_int32_t prdbc; /* transferred byte count */
287
288 u_int32_t ctba_lo;
289 u_int32_t ctba_hi;
290
291 u_int32_t reserved[4];
292} __packed;
293
294struct ahci_rfis {
295 u_int8_t dsfis[28];
296 u_int8_t reserved1[4];
297 u_int8_t psfis[24];
298 u_int8_t reserved2[8];
299 u_int8_t rfis[24];
300 u_int8_t reserved3[4];
301 u_int8_t sdbfis[4];
302 u_int8_t ufis[64];
303 u_int8_t reserved4[96];
304} __packed;
305
306struct ahci_prdt {
307 u_int32_t dba_lo;
308 u_int32_t dba_hi;
309 u_int32_t reserved;
310 u_int32_t flags;
311#define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
312} __packed;
313
314/*
315 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
316 * We need to accomodate MAXPHYS (128K) which is at least 32 entries,
317 * plus one for page slop.
318 *
319 * Making the ahci_cmd_table 1024 bytes (a reasonable power of 2)
320 * thus requires MAX_PRDT to be set to 56.
321 */
322#define AHCI_MAX_PRDT 56
1980eff3 323#define AHCI_MAX_PMPORTS 16
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324
325#if MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
326#error "AHCI_MAX_PRDT is not big enough"
327#endif
328
329struct ahci_cmd_table {
330 u_int8_t cfis[64]; /* Command FIS */
331 u_int8_t acmd[16]; /* ATAPI Command */
332 u_int8_t reserved[48];
333
334 struct ahci_prdt prdt[AHCI_MAX_PRDT];
335} __packed;
336
337#define AHCI_MAX_PORTS 32
338
339struct ahci_dmamem {
340 bus_dma_tag_t adm_tag;
341 bus_dmamap_t adm_map;
342 bus_dma_segment_t adm_seg;
343 bus_addr_t adm_busaddr;
344 caddr_t adm_kva;
345};
346#define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
347#define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
348#define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
349
350struct ahci_softc;
351struct ahci_port;
352struct ahci_device;
353
354struct ahci_ccb {
355 /* ATA xfer associated with this CCB. Must be 1st struct member. */
356 struct ata_xfer ccb_xa;
357 struct callout ccb_timeout;
358
359 int ccb_slot;
360 struct ahci_port *ccb_port;
361
362 bus_dmamap_t ccb_dmamap;
363 struct ahci_cmd_hdr *ccb_cmd_hdr;
364 struct ahci_cmd_table *ccb_cmd_table;
365
366 void (*ccb_done)(struct ahci_ccb *);
367
368 TAILQ_ENTRY(ahci_ccb) ccb_entry;
369};
370
371struct ahci_port {
372 struct ahci_softc *ap_sc;
373 bus_space_handle_t ap_ioh;
374
375 int ap_num;
1980eff3 376 int ap_pmcount;
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377 int ap_flags;
378#define AP_F_BUS_REGISTERED 0x0001
379#define AP_F_CAM_ATTACHED 0x0002
1980eff3 380#define AP_F_IN_RESET 0x0004
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381#define AP_F_SCAN_RUNNING 0x0008
382#define AP_F_SCAN_REQUESTED 0x0010
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383#define AP_F_SCAN_COMPLETED 0x0020
384#define AP_F_IGNORE_IFS 0x0040
385#define AP_F_IFS_IGNORED 0x0080
492bffaf 386#define AP_F_UNUSED_0100 0x0100
831bc9e3 387#define AP_F_EXCLUSIVE_ACCESS 0x0200
baef7501 388#define AP_F_ERR_CCB_RESERVED 0x0400
492bffaf 389#define AP_F_HARSH_REINIT 0x0800
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390 int ap_signal; /* os per-port thread sig */
391 thread_t ap_thread; /* os per-port thread */
392 struct lock ap_lock; /* os per-port lock */
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393 struct lock ap_sim_lock; /* cam sim lock */
394 struct lock ap_sig_lock; /* signal thread */
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395#define AP_SIGF_INIT 0x0001
396#define AP_SIGF_TIMEOUT 0x0002
397#define AP_SIGF_PORTINT 0x0004
e8cf3f55 398#define AP_SIGF_THREAD_SYNC 0x0008
f4553de1 399#define AP_SIGF_STOP 0x8000
258223a3 400 struct cam_sim *ap_sim;
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401
402 struct ahci_rfis *ap_rfis;
403 struct ahci_dmamem *ap_dmamem_rfis;
404
405 struct ahci_dmamem *ap_dmamem_cmd_list;
406 struct ahci_dmamem *ap_dmamem_cmd_table;
407
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408 u_int32_t ap_active; /* active CI command bmask */
409 u_int32_t ap_active_cnt; /* active CI command count */
410 u_int32_t ap_sactive; /* active SACT command bmask */
4c339a5f 411 u_int32_t ap_expired; /* deferred expired bmask */
12feb904 412 u_int32_t ap_intmask; /* interrupts we care about */
258223a3 413 struct ahci_ccb *ap_ccbs;
1067474a 414 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */
12feb904 415 int ap_run_flags; /* used to check excl mode */
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416
417 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
418 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
419 struct lock ap_ccb_lock;
420
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421 int ap_type; /* ATA_PORT_T_xxx */
422 int ap_probe; /* ATA_PROBE_xxx */
b012a2ca 423 struct ata_port *ap_ata[AHCI_MAX_PMPORTS];
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424
425 u_int32_t ap_state;
426#define AP_S_NORMAL 0
427#define AP_S_FATAL_ERROR 1
428
429 /* For error recovery. */
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430 u_int32_t ap_err_saved_sactive;
431 u_int32_t ap_err_saved_active;
432 u_int32_t ap_err_saved_active_cnt;
433
12feb904 434 u_int8_t *ap_err_scratch;
258223a3 435
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436 int link_pwr_mgmt;
437
438 struct sysctl_ctx_list sysctl_ctx;
439 struct sysctl_oid *sysctl_tree;
440
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441 char ap_name[16];
442};
443
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444#define PORTNAME(_ap) ((_ap)->ap_name)
445#define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name)
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446
447struct ahci_softc {
448 device_t sc_dev;
449 const struct ahci_device *sc_ad; /* special casing */
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450
451 struct resource *sc_irq; /* bus resources */
452 struct resource *sc_regs; /* bus resources */
453 bus_space_tag_t sc_iot; /* split from sc_regs */
454 bus_space_handle_t sc_ioh; /* split from sc_regs */
455
9783883a 456 int sc_irq_type;
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457 int sc_rid_irq; /* saved bus RIDs */
458 int sc_rid_regs;
459 u_int32_t sc_cap; /* capabilities */
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460 int sc_numports;
461 u_int32_t sc_portmask;
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462
463 void *sc_irq_handle; /* installed irq vector */
464
465 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
466 bus_dma_tag_t sc_tag_cmdh;
467 bus_dma_tag_t sc_tag_cmdt;
468 bus_dma_tag_t sc_tag_data;
469
470 int sc_flags;
471#define AHCI_F_NO_NCQ (1<<0)
472#define AHCI_F_IGN_FR (1<<1)
f4553de1 473#define AHCI_F_INT_GOOD (1<<2)
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474
475 u_int sc_ncmds;
476
477 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
478
479#ifdef AHCI_COALESCE
480 u_int32_t sc_ccc_mask;
481 u_int32_t sc_ccc_ports;
482 u_int32_t sc_ccc_ports_cur;
483#endif
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484
485 struct sysctl_ctx_list sysctl_ctx;
486 struct sysctl_oid *sysctl_tree;
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487};
488#define DEVNAME(_s) ((_s)->sc_dev.dv_xname)
489
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490#define AHCI_IRQ_TYPE_LEGACY 0
491#define AHCI_IRQ_TYPE_MSI 1
492
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493struct ahci_device {
494 pci_vendor_id_t ad_vendor;
495 pci_product_id_t ad_product;
496 int (*ad_attach)(device_t dev);
497 int (*ad_detach)(device_t dev);
498 char *name;
499};
500
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501/* Wait for all bits in _b to be cleared */
502#define ahci_pwait_clr(_ap, _r, _b) \
503 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0)
504#define ahci_pwait_clr_to(_ap, _to, _r, _b) \
505 ahci_pwait_eq((_ap), _to, (_r), (_b), 0)
506
507/* Wait for all bits in _b to be set */
508#define ahci_pwait_set(_ap, _r, _b) \
509 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b))
510#define ahci_pwait_set_to(_ap, _to, _r, _b) \
511 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b))
512
513#define AHCI_PWAIT_TIMEOUT 1000
514
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515const struct ahci_device *ahci_lookup_device(device_t dev);
516int ahci_init(struct ahci_softc *);
12feb904 517int ahci_port_init(struct ahci_port *ap);
258223a3 518int ahci_port_alloc(struct ahci_softc *, u_int);
831bc9e3 519void ahci_port_state_machine(struct ahci_port *ap, int initial);
258223a3 520void ahci_port_free(struct ahci_softc *, u_int);
1980eff3 521int ahci_port_reset(struct ahci_port *, struct ata_port *at, int);
f17a0ced 522void ahci_port_link_pwr_mgmt(struct ahci_port *, int link_pwr_mgmt);
795adb22 523int ahci_port_link_pwr_state(struct ahci_port *);
fd8bd957 524
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525u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
526void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
527int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
528u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
529void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
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530int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
531 u_int32_t, u_int32_t);
258223a3 532void ahci_intr(void *);
f4553de1 533void ahci_port_intr(struct ahci_port *ap, int blockable);
258223a3 534
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535int ahci_port_start(struct ahci_port *ap);
536int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx);
537int ahci_port_clo(struct ahci_port *ap);
538void ahci_flush_tfd(struct ahci_port *ap);
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539int ahci_set_feature(struct ahci_port *ap, struct ata_port *atx,
540 int feature, int enable);
12feb904 541
258223a3 542int ahci_cam_attach(struct ahci_port *ap);
3209f581 543void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found);
258223a3 544void ahci_cam_detach(struct ahci_port *ap);
3209f581 545int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at);
258223a3 546
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547struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at);
548void ahci_ata_put_xfer(struct ata_xfer *xa);
549int ahci_ata_cmd(struct ata_xfer *xa);
550
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551int ahci_pm_port_probe(struct ahci_port *ap, int);
552int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at);
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553int ahci_pm_identify(struct ahci_port *ap);
554int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard);
555int ahci_pm_softreset(struct ahci_port *ap, int target);
556int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap);
557int ahci_pm_read(struct ahci_port *ap, int target,
558 int which, u_int32_t *res);
559int ahci_pm_write(struct ahci_port *ap, int target,
560 int which, u_int32_t data);
3209f581 561void ahci_pm_check_good(struct ahci_port *ap, int target);
831bc9e3 562void ahci_ata_cmd_timeout(struct ahci_ccb *ccb);
12feb904 563void ahci_quick_timeout(struct ahci_ccb *ccb);
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564struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap);
565void ahci_put_ccb(struct ahci_ccb *ccb);
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566struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *);
567void ahci_put_err_ccb(struct ahci_ccb *);
1980eff3 568int ahci_poll(struct ahci_ccb *ccb, int timeout,
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569 void (*timeout_fn)(struct ahci_ccb *));
570
1980eff3 571int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at);
f4553de1 572void ahci_port_thread_core(struct ahci_port *ap, int mask);
1980eff3 573
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574void ahci_os_sleep(int ms);
575void ahci_os_hardsleep(int us);
576int ahci_os_softsleep(void);
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577void ahci_os_start_port(struct ahci_port *ap);
578void ahci_os_stop_port(struct ahci_port *ap);
579void ahci_os_signal_port_thread(struct ahci_port *ap, int mask);
580void ahci_os_lock_port(struct ahci_port *ap);
581int ahci_os_lock_port_nb(struct ahci_port *ap);
582void ahci_os_unlock_port(struct ahci_port *ap);
258223a3 583
8986d351 584extern u_int32_t AhciForceGen;
afa796d2 585extern u_int32_t AhciNoFeatures;
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586
587enum {AHCI_LINK_PWR_MGMT_NONE, AHCI_LINK_PWR_MGMT_MEDIUM,
588 AHCI_LINK_PWR_MGMT_AGGR};