projects / dragonfly.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | history | HEAD
ahci: Use MSI if device support it.
[dragonfly.git] / sys / dev / disk / ahci / ahci_attach.c
CommitLineData
258223a3 1/*
fb00c6ed
MD		 2 * (MPSAFE)
3 *
258223a3
MD		 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 *
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
20 *
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 * SUCH DAMAGE.
50 *
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
52 */
53
54#include "ahci.h"
55
56static int ahci_vt8251_attach(device_t);
57static int ahci_ati_sb600_attach(device_t);
58static int ahci_nvidia_mcp_attach(device_t);
59static int ahci_pci_attach(device_t);
60static int ahci_pci_detach(device_t);
61
62static const struct ahci_device ahci_devices[] = {
63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
73 { 0, 0,
74 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
75};
76
9783883a
SZ		 77static int ahci_msi_enable = 1;
78TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable);
79
258223a3
MD		 80/*
81 * Match during probe and attach. The device does not yet have a softc.
82 */
83const struct ahci_device *
84ahci_lookup_device(device_t dev)
85{
86 const struct ahci_device *ad;
87 u_int16_t vendor = pci_get_vendor(dev);
88 u_int16_t product = pci_get_device(dev);
89 u_int8_t class = pci_get_class(dev);
90 u_int8_t subclass = pci_get_subclass(dev);
91 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
e95151e4 92 int is_ahci;
258223a3 93
e95151e4
MD		 94 /*
95 * Generally speaking if the pci device does not identify as
96 * AHCI we skip it.
97 */
98 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
99 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
100 is_ahci = 1;
101 } else {
102 is_ahci = 0;
103 }
12feb904 104
258223a3
MD		 105 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
106 if (ad->ad_vendor == vendor && ad->ad_product == product)
107 return (ad);
108 }
109
110 /*
111 * Last ad is the default match if the PCI device matches SATA.
112 */
e95151e4
MD		 113 if (is_ahci == 0)
114 ad = NULL;
115 return (ad);
258223a3
MD		 116}
117
118/*
119 * Attach functions. They all eventually fall through to ahci_pci_attach().
120 */
121static int
122ahci_vt8251_attach(device_t dev)
123{
124 struct ahci_softc *sc = device_get_softc(dev);
125
126 sc->sc_flags |= AHCI_F_NO_NCQ;
127 return (ahci_pci_attach(dev));
128}
129
130static int
131ahci_ati_sb600_attach(device_t dev)
132{
133 struct ahci_softc *sc = device_get_softc(dev);
134 pcireg_t magic;
135 u_int8_t subclass = pci_get_subclass(dev);
136 u_int8_t revid;
137
138 if (subclass == PCIS_STORAGE_IDE) {
139 revid = pci_read_config(dev, PCIR_REVID, 1);
140 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
141 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
142 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
143 pci_write_config(dev, PCIR_REVID,
144 (PCIC_STORAGE << 24) |
145 (PCIS_STORAGE_SATA << 16) |
146 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
147 revid, 4);
148 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
149 }
150
151 sc->sc_flags |= AHCI_F_IGN_FR;
152 return (ahci_pci_attach(dev));
153}
154
155static int
156ahci_nvidia_mcp_attach(device_t dev)
157{
158 struct ahci_softc *sc = device_get_softc(dev);
159
160 sc->sc_flags |= AHCI_F_IGN_FR;
161 return (ahci_pci_attach(dev));
162}
163
164static int
165ahci_pci_attach(device_t dev)
166{
167 struct ahci_softc *sc = device_get_softc(dev);
f4553de1 168 struct ahci_port *ap;
258223a3
MD		 169 const char *gen;
170 u_int32_t cap, pi, reg;
9783883a 171 u_int irq_flags;
258223a3 172 bus_addr_t addr;
9783883a 173 int i, error, msi_enable;
258223a3 174 const char *revision;
9783883a 175 char env[64];
258223a3 176
12feb904 177 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
77f3425b
MD		 178 device_printf(dev, "BIOS disabled PCI interrupt, "
179 "re-enabling\n");
12feb904
MD		 180 pci_write_config(dev, PCIR_COMMAND,
181 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
182 }
12feb904 183
9783883a 184 sc->sc_dev = dev;
12feb904 185
258223a3
MD		 186 /*
187 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
188 */
9783883a
SZ		 189 msi_enable = ahci_msi_enable;
190 ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
191 device_get_nameunit(dev));
192 kgetenv_int(env, &msi_enable);
193
258223a3 194 sc->sc_rid_irq = AHCI_IRQ_RID;
9783883a
SZ		 195 sc->sc_irq_type = AHCI_IRQ_TYPE_LEGACY;
196 irq_flags = RF_SHAREABLE | RF_ACTIVE;
197
198 if (msi_enable) {
199 int cpu = -1;
200
201 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
202 device_get_nameunit(dev));
203 kgetenv_int(env, &cpu);
204 if (cpu >= ncpus)
205 cpu = ncpus - 1;
206
207 if (pci_alloc_msi(dev, &sc->sc_rid_irq, 1, cpu) == 0) {
208 irq_flags &= ~RF_SHAREABLE;
209 sc->sc_irq_type = AHCI_IRQ_TYPE_MSI;
210 }
211 }
212
258223a3 213 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
9783883a 214 irq_flags);
258223a3
MD		 215 if (sc->sc_irq == NULL) {
216 device_printf(dev, "unable to map interrupt\n");
258223a3
MD		 217 ahci_pci_detach(dev);
218 return (ENXIO);
219 }
220
221 /*
222 * When mapping the register window store the tag and handle
223 * separately so we can use the tag with per-port bus handle
224 * sub-spaces.
225 */
226 sc->sc_rid_regs = PCIR_BAR(5);
227 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
228 &sc->sc_rid_regs, RF_ACTIVE);
229 if (sc->sc_regs == NULL) {
230 device_printf(dev, "unable to map registers\n");
258223a3
MD		 231 ahci_pci_detach(dev);
232 return (ENXIO);
233 }
234 sc->sc_iot = rman_get_bustag(sc->sc_regs);
235 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
236
237 /*
238 * Initialize the chipset and then set the interrupt vector up
239 */
240 error = ahci_init(sc);
241 if (error) {
258223a3
MD		 242 ahci_pci_detach(dev);
243 return (ENXIO);
244 }
245
246 /*
247 * Get the AHCI capabilities and max number of concurrent
248 * command tags and set up the DMA tags.
249 */
250 cap = ahci_read(sc, AHCI_REG_CAP);
251 if (sc->sc_flags & AHCI_F_NO_NCQ)
252 cap &= ~AHCI_REG_CAP_SNCQ;
253 sc->sc_cap = cap;
1067474a
MD		 254
255 /*
256 * We assume at least 4 commands.
257 */
258223a3 258 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
1067474a
MD		 259 if (sc->sc_ncmds < 4) {
260 device_printf(dev, "NCS must probe a value >= 4\n");
261 ahci_pci_detach(dev);
262 return (ENXIO);
263 }
258223a3
MD		 264
265 addr = (cap & AHCI_REG_CAP_S64A) ?
266 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
267
268 /*
269 * DMA tags for allocation of DMA memory buffers, lists, and so
270 * forth. These are typically per-port.
271 */
272 error = 0;
273 error += bus_dma_tag_create(
274 NULL, /* parent tag */
275 256, /* alignment */
276 PAGE_SIZE, /* boundary */
277 addr, /* loaddr? */
278 BUS_SPACE_MAXADDR, /* hiaddr */
279 NULL, /* filter */
280 NULL, /* filterarg */
281 sizeof(struct ahci_rfis), /* [max]size */
282 1, /* maxsegs */
283 sizeof(struct ahci_rfis), /* maxsegsz */
284 0, /* flags */
285 &sc->sc_tag_rfis); /* return tag */
286
287 error += bus_dma_tag_create(
288 NULL, /* parent tag */
289 32, /* alignment */
290 4096 * 1024, /* boundary */
291 addr, /* loaddr? */
292 BUS_SPACE_MAXADDR, /* hiaddr */
293 NULL, /* filter */
294 NULL, /* filterarg */
295 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
296 1, /* maxsegs */
297 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
298 0, /* flags */
299 &sc->sc_tag_cmdh); /* return tag */
300
301 /*
302 * NOTE: ahci_cmd_table is sized to a power of 2
303 */
304 error += bus_dma_tag_create(
305 NULL, /* parent tag */
306 sizeof(struct ahci_cmd_table), /* alignment */
307 4096 * 1024, /* boundary */
308 addr, /* loaddr? */
309 BUS_SPACE_MAXADDR, /* hiaddr */
310 NULL, /* filter */
311 NULL, /* filterarg */
312 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
313 1, /* maxsegs */
314 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
315 0, /* flags */
316 &sc->sc_tag_cmdt); /* return tag */
317
318 /*
319 * The data tag is used for later dmamaps and not immediately
320 * allocated.
321 */
322 error += bus_dma_tag_create(
323 NULL, /* parent tag */
324 4, /* alignment */
325 0, /* boundary */
326 addr, /* loaddr? */
327 BUS_SPACE_MAXADDR, /* hiaddr */
328 NULL, /* filter */
329 NULL, /* filterarg */
330 4096 * 1024, /* maxiosize */
331 AHCI_MAX_PRDT, /* maxsegs */
332 65536, /* maxsegsz */
333 0, /* flags */
334 &sc->sc_tag_data); /* return tag */
335
336 if (error) {
337 device_printf(dev, "unable to create dma tags\n");
258223a3
MD		 338 ahci_pci_detach(dev);
339 return (ENXIO);
340 }
341
342 switch (cap & AHCI_REG_CAP_ISS) {
343 case AHCI_REG_CAP_ISS_G1:
344 gen = "1 (1.5Gbps)";
345 break;
8986d351
MD		 346 case AHCI_REG_CAP_ISS_G2:
347 gen = "2 (3Gbps)";
348 break;
349 case AHCI_REG_CAP_ISS_G3:
350 gen = "3 (6Gbps)";
258223a3
MD		 351 break;
352 default:
353 gen = "unknown";
354 break;
355 }
356
357 /* check the revision */
358 reg = ahci_read(sc, AHCI_REG_VS);
359 switch (reg) {
360 case AHCI_REG_VS_0_95:
361 revision = "AHCI 0.95";
362 break;
363 case AHCI_REG_VS_1_0:
364 revision = "AHCI 1.0";
365 break;
366 case AHCI_REG_VS_1_1:
367 revision = "AHCI 1.1";
368 break;
369 case AHCI_REG_VS_1_2:
370 revision = "AHCI 1.2";
371 break;
c520c99b
MD		 372 case AHCI_REG_VS_1_3:
373 revision = "AHCI 1.3";
374 break;
375 case AHCI_REG_VS_1_4:
376 revision = "AHCI 1.4";
377 break;
378 case AHCI_REG_VS_1_5:
379 revision = "AHCI 1.5"; /* future will catch up to us */
380 break;
258223a3
MD		 381 default:
382 device_printf(sc->sc_dev,
383 "Warning: Unknown AHCI revision 0x%08x\n", reg);
384 revision = "AHCI <unknown>";
385 break;
386 }
387
388 device_printf(dev,
389 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n",
390 revision,
391 cap, AHCI_FMT_CAP,
392 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
393
394 pi = ahci_read(sc, AHCI_REG_PI);
395 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
396 DEVNAME(sc), pi);
397
398#ifdef AHCI_COALESCE
399 /* Naive coalescing support - enable for all ports. */
400 if (cap & AHCI_REG_CAP_CCCS) {
401 u_int16_t ccc_timeout = 20;
402 u_int8_t ccc_numcomplete = 12;
403 u_int32_t ccc_ctl;
404
405 /* disable coalescing during reconfiguration. */
406 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
407 ccc_ctl &= ~0x00000001;
408 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
409
410 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
411 if (pi & sc->sc_ccc_mask) {
412 /* A conflict with the implemented port list? */
413 printf("%s: coalescing interrupt/implemented port list "
414 "conflict, PI: %08x, ccc_mask: %08x\n",
415 DEVNAME(sc), pi, sc->sc_ccc_mask);
416 sc->sc_ccc_mask = 0;
417 goto noccc;
418 }
419
420 /* ahci_port_start will enable each port when it starts. */
421 sc->sc_ccc_ports = pi;
422 sc->sc_ccc_ports_cur = 0;
423
424 /* program thresholds and enable overall coalescing. */
425 ccc_ctl &= ~0xffffff00;
426 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
427 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
428 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
429 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
430 }
431noccc:
432#endif
433 /*
434 * Allocate per-port resources
435 *
436 * Ignore attach errors, leave the port intact for
437 * rescan and continue the loop.
f4553de1
MD		 438 *
439 * All ports are attached in parallel but the CAM scan-bus
440 * is held up until all ports are attached so we get a deterministic
441 * order.
258223a3
MD		 442 */
443 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
444 if ((pi & (1 << i)) == 0) {
445 /* dont allocate stuff if the port isnt implemented */
446 continue;
447 }
448 error = ahci_port_alloc(sc, i);
258223a3
MD		 449 }
450
451 /*
452 * Setup the interrupt vector and enable interrupts. Note that
453 * since the irq may be shared we do not set it up until we are
454 * ready to go.
455 */
456 if (error == 0) {
fb00c6ed
MD		 457 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
458 ahci_intr, sc,
f4553de1 459 &sc->sc_irq_handle, NULL);
258223a3
MD		 460 }
461
462 if (error) {
463 device_printf(dev, "unable to install interrupt\n");
258223a3
MD		 464 ahci_pci_detach(dev);
465 return (ENXIO);
466 }
f4553de1
MD		 467
468 /*
e8cf3f55
MD		 469 * Before marking the sc as good, which allows the interrupt
470 * subsystem to operate on the ports, wait for all the port threads
471 * to get past their initial pre-probe init. Otherwise an interrupt
472 * may try to process the port before it has been initialized.
473 */
474 for (i = 0; i < AHCI_MAX_PORTS; i++) {
475 if ((ap = sc->sc_ports[i]) != NULL) {
476 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
477 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
478 }
479 }
480
481 /*
f4553de1
MD		 482 * Master interrupt enable, and call ahci_intr() in case we race
483 * our AHCI_F_INT_GOOD flag.
484 */
485 crit_enter();
258223a3 486 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
f4553de1
MD		 487 sc->sc_flags |= AHCI_F_INT_GOOD;
488 crit_exit();
489 ahci_intr(sc);
490
491 /*
492 * All ports are probing in parallel. Wait for them to finish
493 * and then issue the cam attachment and bus scan serially so
494 * the 'da' assignments are deterministic.
495 */
496 for (i = 0; i < AHCI_MAX_PORTS; i++) {
497 if ((ap = sc->sc_ports[i]) != NULL) {
498 while (ap->ap_signal & AP_SIGF_INIT)
e8cf3f55 499 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
831bc9e3 500 ahci_os_lock_port(ap);
f4553de1
MD		 501 if (ahci_cam_attach(ap) == 0) {
502 ahci_cam_changed(ap, NULL, -1);
831bc9e3 503 ahci_os_unlock_port(ap);
f4553de1
MD		 504 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
505 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
506 }
831bc9e3
MD		 507 } else {
508 ahci_os_unlock_port(ap);
f4553de1
MD		 509 }
510 }
511 }
258223a3
MD		 512
513 return(0);
514}
515
516/*
517 * Device unload / detachment
518 */
519static int
520ahci_pci_detach(device_t dev)
521{
522 struct ahci_softc *sc = device_get_softc(dev);
523 struct ahci_port *ap;
524 int i;
525
526 /*
527 * Disable the controller and de-register the interrupt, if any.
528 *
f4553de1 529 * XXX interlock last interrupt?
258223a3 530 */
f4553de1
MD		 531 sc->sc_flags &= ~AHCI_F_INT_GOOD;
532 if (sc->sc_regs)
258223a3 533 ahci_write(sc, AHCI_REG_GHC, 0);
f4553de1 534
258223a3
MD		 535 if (sc->sc_irq_handle) {
536 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
537 sc->sc_irq_handle = NULL;
538 }
539
540 /*
541 * Free port structures and DMA memory
542 */
543 for (i = 0; i < AHCI_MAX_PORTS; i++) {
544 ap = sc->sc_ports[i];
545 if (ap) {
546 ahci_cam_detach(ap);
547 ahci_port_free(sc, i);
548 }
549 }
550
551 /*
552 * Clean up the bus space
553 */
554 if (sc->sc_irq) {
555 bus_release_resource(dev, SYS_RES_IRQ,
556 sc->sc_rid_irq, sc->sc_irq);
557 sc->sc_irq = NULL;
558 }
9783883a
SZ		 559
560 if (sc->sc_irq_type == AHCI_IRQ_TYPE_MSI)
561 pci_release_msi(dev);
562
258223a3
MD		 563 if (sc->sc_regs) {
564 bus_release_resource(dev, SYS_RES_MEMORY,
565 sc->sc_rid_regs, sc->sc_regs);
566 sc->sc_regs = NULL;
567 }
568
569 if (sc->sc_tag_rfis) {
570 bus_dma_tag_destroy(sc->sc_tag_rfis);
571 sc->sc_tag_rfis = NULL;
572 }
573 if (sc->sc_tag_cmdh) {
574 bus_dma_tag_destroy(sc->sc_tag_cmdh);
575 sc->sc_tag_cmdh = NULL;
576 }
577 if (sc->sc_tag_cmdt) {
578 bus_dma_tag_destroy(sc->sc_tag_cmdt);
579 sc->sc_tag_cmdt = NULL;
580 }
581 if (sc->sc_tag_data) {
582 bus_dma_tag_destroy(sc->sc_tag_data);
583 sc->sc_tag_data = NULL;
584 }
585
586 return (0);
587}
DragonFly Project GIT Source repo