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[dragonfly.git] / sys / dev / atm / en / midway.c
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1/* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2/* (sync'd to midway.c 1.68) */
3
4/*
5 *
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/en/midway.c,v 1.19.2.1 2003/01/23 21:06:42 sam Exp $
36 */
37
38/*
39 *
40 * m i d w a y . c e n i 1 5 5 d r i v e r
41 *
42 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
43 * started: spring, 1996 (written from scratch).
44 *
45 * notes from the author:
46 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
47 * ENI driver was especially useful in figuring out how this card works.
48 * I would also like to thank Werner for promptly answering email and being
49 * generally helpful.
50 */
51
52#undef EN_DEBUG
53#undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
54#define EN_MBUF_OPT /* try and put more stuff in mbuf? */
55#define EN_DIAG
56#define EN_STAT
57#ifndef EN_DMA
58#define EN_DMA 1 /* use dma? */
59#endif
60#define EN_NOTXDMA 0 /* hook to disable tx dma only */
61#define EN_NORXDMA 0 /* hook to disable rx dma only */
62#define EN_DDBHOOK 1 /* compile in ddb functions */
63#if defined(MIDWAY_ADPONLY)
64#define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
65#else
66#define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
67#endif
68
69/*
70 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
71 * appears to be broken. it works just fine if there is no load... however
72 * when the card is loaded the data get corrupted. to see this, one only
73 * has to use "telnet" over ATM. do the following command in "telnet":
74 * cat /usr/share/misc/termcap
75 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
76 * use of the byte aligner). watch "netstat -s" for checksum errors.
77 *
78 * I further tested this by adding a function that compared the transmit
79 * data on the card's SRAM with the data in the mbuf chain _after_ the
80 * "transmit DMA complete" interrupt. using the "telnet" test I got data
81 * mismatches where the byte-aligned data should have been. using ddb
82 * and en_dumpmem() I verified that the DTQs fed into the card were
83 * absolutely correct. thus, we are forced to concluded that the ENI
84 * hardware is buggy. note that the Adaptec version of the card works
85 * just fine with byte DMA.
86 *
87 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
88 * card.
89 */
90
91#if defined(DIAGNOSTIC) && !defined(EN_DIAG)
92#define EN_DIAG /* link in with master DIAG option */
93#endif
94#ifdef EN_STAT
95#define EN_COUNT(X) (X)++
96#else
97#define EN_COUNT(X) /* nothing */
98#endif
99
100#ifdef EN_DEBUG
101#undef EN_DDBHOOK
102#define EN_DDBHOOK 1
103#define STATIC /* nothing */
104#define INLINE /* nothing */
105#else /* EN_DEBUG */
106#define STATIC static
107#define INLINE __inline
108#endif /* EN_DEBUG */
109
110#ifdef __FreeBSD__
111#include "en.h" /* XXX for midwayvar.h's NEN */
112#include "opt_inet.h"
113#include "opt_natm.h"
114#include "opt_ddb.h"
115/* enable DDBHOOK when DDB is available */
116#undef EN_DDBHOOK
117#ifdef DDB
118#define EN_DDBHOOK 1
119#endif
120#endif
121
122#include <sys/param.h>
123#include <sys/systm.h>
124#include <sys/queue.h>
125#if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)
126#include <sys/device.h>
127#endif
128#include <sys/sockio.h>
129#include <sys/mbuf.h>
130#include <sys/socket.h>
131#include <sys/proc.h>
132
133#include <net/if.h>
134#include <net/if_atm.h>
135
136#include <vm/vm.h>
137
138#if defined(INET) || defined(INET6)
139#include <netinet/in.h>
140#include <netinet/if_atm.h>
141#endif
142
143#ifdef NATM
144#include <netnatm/natm.h>
145#endif
146
147#if !defined(sparc) && !defined(__FreeBSD__)
148#include <machine/bus.h>
149#endif
150
151#if defined(__NetBSD__) || defined(__OpenBSD__)
152#include <dev/ic/midwayreg.h>
153#include <dev/ic/midwayvar.h>
154#if defined(__alpha__)
155/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
156#undef vtophys
157#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
158#endif
159#elif defined(__FreeBSD__)
160#include <machine/clock.h> /* for DELAY */
161#include <dev/en/midwayreg.h>
162#include <dev/en/midwayvar.h>
163#include <vm/pmap.h> /* for vtophys proto */
164
165#ifndef IFF_NOTRAILERS
166#define IFF_NOTRAILERS 0
167#endif
168
169#endif /* __FreeBSD__ */
170
171#include "bpf.h"
172#if NBPF > 0
173#include <net/bpf.h>
174#ifdef __FreeBSD__
175#define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
176#define BPF_MTAP(ifp, m) bpf_mtap((ifp), (m))
177#else
178#define BPFATTACH(ifp, dlt, hlen) bpfattach(&(ifp)->if_bpf, (ifp), (dlt), (hlen))
179#define BPF_MTAP(ifp, m) bpf_mtap((ifp)->if_bpf, (m))
180#endif
181#endif /* NBPF > 0 */
182
183/*
184 * params
185 */
186
187#ifndef EN_TXHIWAT
188#define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
189#endif
190
191#ifndef EN_MINDMA
192#define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
193#endif
194
195#define RX_NONE 0xffff /* recv VC not in use */
196
197#define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
198#define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailier in last mbuf ! */
199
200#define ENOTHER_FREE 0x01 /* free rxslot */
201#define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ dma) */
202#define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
203#define ENOTHER_SWSL 0x08 /* in software service list */
204
205static int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
206
207/*
208 * autoconfig attachments
209 */
210
211struct cfdriver en_cd = {
212 0, "en", DV_IFNET,
213};
214
215/*
216 * local structures
217 */
218
219/*
220 * params to en_txlaunch() function
221 */
222
223struct en_launch {
224 u_int32_t tbd1; /* TBD 1 */
225 u_int32_t tbd2; /* TBD 2 */
226 u_int32_t pdu1; /* PDU 1 (aal5) */
227 int nodma; /* don't use DMA */
228 int need; /* total space we need (pad out if less data) */
229 int mlen; /* length of mbuf (for dtq) */
230 struct mbuf *t; /* data */
231 u_int32_t aal; /* aal code */
232 u_int32_t atm_vci; /* vci */
233 u_int8_t atm_flags; /* flags */
234};
235
236
237/*
238 * dma table (index by # of words)
239 *
240 * plan A: use WMAYBE (obsolete)
241 * plan B: avoid WMAYBE
242 */
243
244struct en_dmatab {
245 u_int8_t bcode; /* code */
246 u_int8_t divshift; /* byte divisor */
247};
248
249static struct en_dmatab en_dma_planB[] = {
250 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
251 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
252 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
253 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
254 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
255 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
256 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
257 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
258 { MIDDMA_16WORD, 6}, /* 16 */
259};
260
261static struct en_dmatab *en_dmaplan = en_dma_planB;
262
263/*
264 * prototypes
265 */
266
267STATIC INLINE int en_b2sz __P((int)) __attribute__ ((unused));
268#ifdef EN_DDBHOOK
269 int en_dump __P((int,int));
270 int en_dumpmem __P((int,int,int));
271#endif
272STATIC void en_dmaprobe __P((struct en_softc *));
273STATIC int en_dmaprobe_doit __P((struct en_softc *, u_int8_t *,
274 u_int8_t *, int));
275STATIC INLINE int en_dqneed __P((struct en_softc *, caddr_t, u_int,
276 u_int)) __attribute__ ((unused));
277STATIC void en_init __P((struct en_softc *));
278STATIC int en_ioctl __P((struct ifnet *, EN_IOCTL_CMDT, caddr_t));
279STATIC INLINE int en_k2sz __P((int)) __attribute__ ((unused));
280STATIC void en_loadvc __P((struct en_softc *, int));
281STATIC int en_mfix __P((struct en_softc *, struct mbuf **,
282 struct mbuf *));
283STATIC INLINE struct mbuf *en_mget __P((struct en_softc *, u_int,
284 u_int *)) __attribute__ ((unused));
285STATIC INLINE u_int32_t en_read __P((struct en_softc *,
286 u_int32_t)) __attribute__ ((unused));
287STATIC int en_rxctl __P((struct en_softc *, struct atm_pseudoioctl *,
288 int));
289STATIC void en_txdma __P((struct en_softc *, int));
290STATIC void en_txlaunch __P((struct en_softc *, int,
291 struct en_launch *));
292STATIC void en_service __P((struct en_softc *));
293STATIC void en_start __P((struct ifnet *));
294STATIC INLINE int en_sz2b __P((int)) __attribute__ ((unused));
295STATIC INLINE void en_write __P((struct en_softc *, u_int32_t,
296 u_int32_t)) __attribute__ ((unused));
297
298/*
299 * macros/inline
300 */
301
302/*
303 * raw read/write macros
304 */
305
306#define EN_READDAT(SC,R) en_read(SC,R)
307#define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
308
309/*
310 * cooked read/write macros
311 */
312
313#define EN_READ(SC,R) ntohl(en_read(SC,R))
314#define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
315
316#define EN_WRAPADD(START,STOP,CUR,VAL) { \
317 (CUR) = (CUR) + (VAL); \
318 if ((CUR) >= (STOP)) \
319 (CUR) = (START) + ((CUR) - (STOP)); \
320 }
321
322#define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
323
324/* we store sc->dtq and sc->drq data in the following format... */
325#define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
326 /* the 0x80000 ensures we != 0 */
327#define EN_DQ_SLOT(X) ((X) >> 20)
328#define EN_DQ_LEN(X) ((X) & 0x3ffff)
329
330/* format of DTQ/DRQ word 1 differs between ENI and ADP */
331#if defined(MIDWAY_ENIONLY)
332
333#define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
334 EN_WRITE((SC), (SC)->dtq_us, \
335 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
336
337#define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
338 EN_WRITE((SC), (SC)->drq_us, \
339 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
340
341#elif defined(MIDWAY_ADPONLY)
342
343#define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
344 EN_WRITE((SC), (SC)->dtq_us, \
345 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
346
347#define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
348 EN_WRITE((SC), (SC)->drq_us, \
349 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
350
351#else
352
353#define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
354 if ((SC)->is_adaptec) \
355 EN_WRITE((SC), (SC)->dtq_us, \
356 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
357 else \
358 EN_WRITE((SC), (SC)->dtq_us, \
359 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
360 }
361
362#define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
363 if ((SC)->is_adaptec) \
364 EN_WRITE((SC), (SC)->drq_us, \
365 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
366 else \
367 EN_WRITE((SC), (SC)->drq_us, \
368 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
369 }
370
371#endif
372
373/* add an item to the DTQ */
374#define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
375 if (END) \
376 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
377 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
378 (SC)->dtq_us += 4; \
379 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
380 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
381 (SC)->dtq_free--; \
382 if (END) \
383 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
384}
385
386/* DRQ add macro */
387#define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
388 if (END) \
389 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
390 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
391 (SC)->drq_us += 4; \
392 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
393 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
394 (SC)->drq_free--; \
395 if (END) \
396 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
397}
398
399/*
400 * the driver code
401 *
402 * the code is arranged in a specific way:
403 * [1] short/inline functions
404 * [2] autoconfig stuff
405 * [3] ioctl stuff
406 * [4] reset -> init -> trasmit -> intr -> receive functions
407 *
408 */
409
410/***********************************************************************/
411
412/*
413 * en_read: read a word from the card. this is the only function
414 * that reads from the card.
415 */
416
417STATIC INLINE u_int32_t en_read(sc, r)
418
419struct en_softc *sc;
420u_int32_t r;
421
422{
423
424#ifdef EN_DEBUG_RANGE
425 if (r > MID_MAXOFF || (r % 4))
426 panic("en_read out of range, r=0x%x", r);
427#endif
428
429 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
430}
431
432/*
433 * en_write: write a word to the card. this is the only function that
434 * writes to the card.
435 */
436
437STATIC INLINE void en_write(sc, r, v)
438
439struct en_softc *sc;
440u_int32_t r, v;
441
442{
443#ifdef EN_DEBUG_RANGE
444 if (r > MID_MAXOFF || (r % 4))
445 panic("en_write out of range, r=0x%x", r);
446#endif
447
448 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
449}
450
451/*
452 * en_k2sz: convert KBytes to a size parameter (a log2)
453 */
454
455STATIC INLINE int en_k2sz(k)
456
457int k;
458
459{
460 switch(k) {
461 case 1: return(0);
462 case 2: return(1);
463 case 4: return(2);
464 case 8: return(3);
465 case 16: return(4);
466 case 32: return(5);
467 case 64: return(6);
468 case 128: return(7);
469 default: panic("en_k2sz");
470 }
471 return(0);
472}
473#define en_log2(X) en_k2sz(X)
474
475
476/*
477 * en_b2sz: convert a DMA burst code to its byte size
478 */
479
480STATIC INLINE int en_b2sz(b)
481
482int b;
483
484{
485 switch (b) {
486 case MIDDMA_WORD: return(1*4);
487 case MIDDMA_2WMAYBE:
488 case MIDDMA_2WORD: return(2*4);
489 case MIDDMA_4WMAYBE:
490 case MIDDMA_4WORD: return(4*4);
491 case MIDDMA_8WMAYBE:
492 case MIDDMA_8WORD: return(8*4);
493 case MIDDMA_16WMAYBE:
494 case MIDDMA_16WORD: return(16*4);
495 default: panic("en_b2sz");
496 }
497 return(0);
498}
499
500
501/*
502 * en_sz2b: convert a burst size (bytes) to DMA burst code
503 */
504
505STATIC INLINE int en_sz2b(sz)
506
507int sz;
508
509{
510 switch (sz) {
511 case 1*4: return(MIDDMA_WORD);
512 case 2*4: return(MIDDMA_2WORD);
513 case 4*4: return(MIDDMA_4WORD);
514 case 8*4: return(MIDDMA_8WORD);
515 case 16*4: return(MIDDMA_16WORD);
516 default: panic("en_sz2b");
517 }
518 return(0);
519}
520
521
522/*
523 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
524 */
525
526STATIC INLINE int en_dqneed(sc, data, len, tx)
527
528struct en_softc *sc;
529caddr_t data;
530u_int len, tx;
531
532{
533 int result, needalign, sz;
534
535#if !defined(MIDWAY_ENIONLY)
536#if !defined(MIDWAY_ADPONLY)
537 if (sc->is_adaptec)
538#endif /* !MIDWAY_ADPONLY */
539 return(1); /* adaptec can DMA anything in one go */
540#endif
541
542#if !defined(MIDWAY_ADPONLY)
543 result = 0;
544 if (len < EN_MINDMA) {
545 if (!tx) /* XXX: conservative */
546 return(1); /* will copy/DMA_JK */
547 }
548
549 if (tx) { /* byte burst? */
550 needalign = (((uintptr_t) (void *) data) % sizeof(u_int32_t));
551 if (needalign) {
552 result++;
553 sz = min(len, sizeof(u_int32_t) - needalign);
554 len -= sz;
555 data += sz;
556 }
557 }
558
559 if (sc->alburst && len) {
560 needalign = (((uintptr_t) (void *) data) & sc->bestburstmask);
561 if (needalign) {
562 result++; /* alburst */
563 sz = min(len, sc->bestburstlen - needalign);
564 len -= sz;
565 }
566 }
567
568 if (len >= sc->bestburstlen) {
569 sz = len / sc->bestburstlen;
570 sz = sz * sc->bestburstlen;
571 len -= sz;
572 result++; /* best shot */
573 }
574
575 if (len) {
576 result++; /* clean up */
577 if (tx && (len % sizeof(u_int32_t)) != 0)
578 result++; /* byte cleanup */
579 }
580
581 return(result);
582#endif /* !MIDWAY_ADPONLY */
583}
584
585
586/*
587 * en_mget: get an mbuf chain that can hold totlen bytes and return it
588 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
589 * after this call the sum of all the m_len's in the chain will be totlen.
590 */
591
592STATIC INLINE struct mbuf *en_mget(sc, totlen, drqneed)
593
594struct en_softc *sc;
595u_int totlen, *drqneed;
596
597{
598 struct mbuf *m;
599 struct mbuf *top, **mp;
600 *drqneed = 0;
601
602 MGETHDR(m, M_DONTWAIT, MT_DATA);
603 if (m == NULL)
604 return(NULL);
605 m->m_pkthdr.rcvif = &sc->enif;
606 m->m_pkthdr.len = totlen;
607 m->m_len = MHLEN;
608 top = NULL;
609 mp = &top;
610
611 /* if (top != NULL) then we've already got 1 mbuf on the chain */
612 while (totlen > 0) {
613 if (top) {
614 MGET(m, M_DONTWAIT, MT_DATA);
615 if (!m) {
616 m_freem(top);
617 return(NULL); /* out of mbufs */
618 }
619 m->m_len = MLEN;
620 }
621 if (totlen >= MINCLSIZE) {
622 MCLGET(m, M_DONTWAIT);
623 if ((m->m_flags & M_EXT) == 0) {
624 m_free(m);
625 m_freem(top);
626 return(NULL); /* out of mbuf clusters */
627 }
628 m->m_len = MCLBYTES;
629 }
630 m->m_len = min(totlen, m->m_len);
631 totlen -= m->m_len;
632 *mp = m;
633 mp = &m->m_next;
634
635 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
636
637 }
638 return(top);
639}
640
641/***********************************************************************/
642
643/*
644 * autoconfig stuff
645 */
646
647void en_attach(sc)
648
649struct en_softc *sc;
650
651{
652 struct ifnet *ifp = &sc->enif;
653 int sz;
654 u_int32_t reg, lcv, check, ptr, sav, midvloc;
655
656 /*
657 * probe card to determine memory size. the stupid ENI card always
658 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
659 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
660 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
661 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
662 */
663
664 if (sc->en_busreset)
665 sc->en_busreset(sc);
666 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
667 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
668 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
669 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
670 reg = EN_READ(sc, check);
671 if (reg != check) { /* found an alias! */
672 goto done_probe; /* and quit */
673 }
674 }
675 }
676done_probe:
677 lcv -= MID_PROBSIZE; /* take one step back */
678 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
679
680 /*
681 * determine the largest DMA burst supported
682 */
683
684 en_dmaprobe(sc);
685
686 /*
687 * "hello world"
688 */
689
690 if (sc->en_busreset)
691 sc->en_busreset(sc);
692 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
693 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
694 EN_WRITE(sc, lcv, 0); /* zero memory */
695
696 reg = EN_READ(sc, MID_RESID);
697
698 printf("%s: ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
699 sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
700 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
701 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
702 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
703 (long)(sc->en_obmemsz / 1024));
704
705 if (sc->is_adaptec) {
706 if (sc->bestburstlen == 64 && sc->alburst == 0)
707 printf("%s: passed 64 byte DMA test\n", sc->sc_dev.dv_xname);
708 else
709 printf("%s: FAILED DMA TEST: burst=%d, alburst=%d\n",
710 sc->sc_dev.dv_xname, sc->bestburstlen, sc->alburst);
711 } else {
712 printf("%s: maximum DMA burst length = %d bytes%s\n", sc->sc_dev.dv_xname,
713 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
714 }
715
716 /*
717 * link into network subsystem and prepare card
718 */
719
720#if defined(__NetBSD__) || defined(__OpenBSD__)
721 bcopy(sc->sc_dev.dv_xname, sc->enif.if_xname, IFNAMSIZ);
722#endif
723 sc->enif.if_softc = sc;
724 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
725 ifp->if_ioctl = en_ioctl;
726 ifp->if_output = atm_output;
727 ifp->if_start = en_start;
728
729 /*
730 * init softc
731 */
732
733 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
734 sc->rxvc2slot[lcv] = RX_NONE;
735 sc->txspeed[lcv] = 0; /* full */
736 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
737 }
738
739 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
740 ptr = sav = MID_BUFOFF;
741 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
742 sz = sz - (ptr - sav);
743 if (EN_TXSZ*1024 * EN_NTX > sz) {
744 printf("%s: EN_NTX/EN_TXSZ too big\n", sc->sc_dev.dv_xname);
745 return;
746 }
747 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
748 sc->txslot[lcv].mbsize = 0;
749 sc->txslot[lcv].start = ptr;
750 ptr += (EN_TXSZ * 1024);
751 sz -= (EN_TXSZ * 1024);
752 sc->txslot[lcv].stop = ptr;
753 sc->txslot[lcv].nref = 0;
754 bzero(&sc->txslot[lcv].indma, sizeof(sc->txslot[lcv].indma));
755 bzero(&sc->txslot[lcv].q, sizeof(sc->txslot[lcv].q));
756#ifdef EN_DEBUG
757 printf("%s: tx%d: start 0x%x, stop 0x%x\n", sc->sc_dev.dv_xname, lcv,
758 sc->txslot[lcv].start, sc->txslot[lcv].stop);
759#endif
760 }
761
762 sav = ptr;
763 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
764 sz = sz - (ptr - sav);
765 sc->en_nrx = sz / (EN_RXSZ * 1024);
766 if (sc->en_nrx <= 0) {
767 printf("%s: EN_NTX/EN_TXSZ/EN_RXSZ too big\n", sc->sc_dev.dv_xname);
768 return;
769 }
770
771 /*
772 * ensure that there is always one VC slot on the service list free
773 * so that we can tell the difference between a full and empty list.
774 */
775 if (sc->en_nrx >= MID_N_VC)
776 sc->en_nrx = MID_N_VC - 1;
777
778 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
779 sc->rxslot[lcv].rxhand = NULL;
780 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
781 bzero(&sc->rxslot[lcv].indma, sizeof(sc->rxslot[lcv].indma));
782 bzero(&sc->rxslot[lcv].q, sizeof(sc->rxslot[lcv].q));
783 midvloc = sc->rxslot[lcv].start = ptr;
784 ptr += (EN_RXSZ * 1024);
785 sz -= (EN_RXSZ * 1024);
786 sc->rxslot[lcv].stop = ptr;
787 midvloc = midvloc - MID_RAMOFF;
788 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
789 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
790 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
791 sc->rxslot[lcv].mode = midvloc |
792 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
793
794#ifdef EN_DEBUG
795 printf("%s: rx%d: start 0x%x, stop 0x%x, mode 0x%x\n", sc->sc_dev.dv_xname,
796 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
797#endif
798 }
799
800#ifdef EN_STAT
801 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
802 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
803 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
804 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
805 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
806#endif
807 sc->need_drqs = sc->need_dtqs = 0;
808
809 printf("%s: %d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
810 sc->sc_dev.dv_xname, sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
811
812 printf("%s: End Station Identifier (mac address) %6D\n",
813 sc->sc_dev.dv_xname, sc->macaddr, ":");
814
815 /*
816 * final commit
817 */
818
819 if_attach(ifp);
820 atm_ifattach(ifp);
821
822#if NBPF > 0
823 BPFATTACH(ifp, DLT_ATM_RFC1483, sizeof(struct atmllc));
824#endif
825}
826
827
828/*
829 * en_dmaprobe: helper function for en_attach.
830 *
831 * see how the card handles DMA by running a few DMA tests. we need
832 * to figure out the largest number of bytes we can DMA in one burst
833 * ("bestburstlen"), and if the starting address for a burst needs to
834 * be aligned on any sort of boundary or not ("alburst").
835 *
836 * typical findings:
837 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
838 * sparc2: bestburstlen=64, alburst=1
839 * p166: bestburstlen=64, alburst=0
840 */
841
842#if 1 /* __FreeBSD__ */
843#define NBURSTS 3 /* number of bursts to use for dmaprobe */
844#define BOUNDARY 1024 /* test misaligned dma crossing the bounday.
845 should be n * 64. at least 64*(NBURSTS+1).
846 dell P6 with EDO DRAM has 1K bounday problem */
847#endif
848
849STATIC void en_dmaprobe(sc)
850
851struct en_softc *sc;
852
853{
854#ifdef NBURSTS
855 /* be careful. kernel stack is only 8K */
856 u_int8_t buffer[BOUNDARY * 2 + 64 * (NBURSTS + 1)];
857#else
858 u_int32_t srcbuf[64], dstbuf[64];
859#endif
860 u_int8_t *sp, *dp;
861 int bestalgn, bestnotalgn, lcv, try;
862
863 sc->alburst = 0;
864
865#ifdef NBURSTS
866 /* setup src and dst buf at the end of the boundary */
867 sp = (u_int8_t *)roundup((uintptr_t)(void *)buffer, 64);
868 while (((uintptr_t)(void *)sp & (BOUNDARY - 1)) != (BOUNDARY - 64))
869 sp += 64;
870 dp = sp + BOUNDARY;
871
872 /*
873 * we can't dma across page boundary so that, if buf is at a page
874 * boundary, move it to the next page. but still either src or dst
875 * will be at the boundary, which should be ok.
876 */
877 if ((((uintptr_t)(void *)sp + 64) & PAGE_MASK) == 0)
878 sp += 64;
879 if ((((uintptr_t)(void *)dp + 64) & PAGE_MASK) == 0)
880 dp += 64;
881#else /* !NBURSTS */
882 sp = (u_int8_t *) srcbuf;
883 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
884 sp += 4;
885 dp = (u_int8_t *) dstbuf;
886 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
887 dp += 4;
888#endif /* !NBURSTS */
889
890 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
891
892 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
893 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
894#ifdef NBURSTS
895 if (try < bestnotalgn) {
896 bestnotalgn = try;
897 break;
898 }
899#else
900 if (try < bestnotalgn)
901 bestnotalgn = try;
902#endif
903 }
904
905 if (bestalgn != bestnotalgn) /* need bursts aligned */
906 sc->alburst = 1;
907
908 sc->bestburstlen = bestalgn;
909 sc->bestburstshift = en_log2(bestalgn);
910 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
911 sc->bestburstcode = en_sz2b(bestalgn);
912
913#if 1 /* __FreeBSD__ */
914 /*
915 * correct pci chipsets should be able to handle misaligned-64-byte DMA.
916 * but there are too many broken chipsets around. we try to work around
917 * by finding the best workable dma size, but still some broken machines
918 * exhibit the problem later. so warn it here.
919 */
920 if (bestalgn != 64 || sc->alburst != 0) {
921 printf("%s: WARNING: DMA test detects a broken PCI chipset!\n",
922 sc->sc_dev.dv_xname);
923 printf(" trying to work around the problem... but if this doesn't\n");
924 printf(" work for you, you'd better switch to a newer motherboard.\n");
925 }
926#endif /* 1 */
927 return;
928}
929
930
931/*
932 * en_dmaprobe_doit: do actual testing
933 */
934
935static int
936en_dmaprobe_doit(sc, sp, dp, wmtry)
937
938struct en_softc *sc;
939u_int8_t *sp, *dp;
940int wmtry;
941
942{
943 int lcv, retval = 4, cnt, count;
944 u_int32_t reg, bcode, midvloc;
945
946 /*
947 * set up a 1k buffer at MID_BUFOFF
948 */
949
950 if (sc->en_busreset)
951 sc->en_busreset(sc);
952 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
953
954 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
955 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
956 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
957 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
958 EN_WRITE(sc, MID_DST_RP(0), 0);
959 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
960
961#ifdef NBURSTS
962 for (lcv = 0 ; lcv < 64*NBURSTS; lcv++) /* set up sample data */
963#else
964 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
965#endif
966 sp[lcv] = lcv+1;
967 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
968
969 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
970 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
971
972 /*
973 * try it now . . . DMA it out, then DMA it back in and compare
974 *
975 * note: in order to get the dma stuff to reverse directions it wants
976 * the "end" flag set! since we are not dma'ing valid data we may
977 * get an ident mismatch interrupt (which we will ignore).
978 *
979 * note: we've got two different tests rolled up in the same loop
980 * if (wmtry)
981 * then we are doing a wmaybe test and wmtry is a byte count
982 * else we are doing a burst test
983 */
984
985 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
986
987#ifdef EN_DEBUG
988 printf("DMA test lcv=%d, sp=0x%x, dp=0x%x, wmtry=%d\n",
989 lcv, sp, dp, wmtry);
990#endif
991
992 /* zero SRAM and dest buffer */
993 for (cnt = 0 ; cnt < 1024; cnt += 4)
994 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
995#ifdef NBURSTS
996 for (cnt = 0 ; cnt < 64*NBURSTS; cnt++)
997#else
998 for (cnt = 0 ; cnt < 68 ; cnt++)
999#endif
1000 dp[cnt] = 0;
1001
1002 if (wmtry) {
1003 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
1004 bcode = en_dmaplan[count].bcode;
1005 count = wmtry >> en_dmaplan[count].divshift;
1006 } else {
1007 bcode = en_sz2b(lcv);
1008 count = 1;
1009 }
1010#ifdef NBURSTS
1011 /* build lcv-byte-DMA x NBURSTS */
1012 if (sc->is_adaptec)
1013 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1014 else
1015 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1016 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1017 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1018 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
1019 cnt = 1000;
1020 while (EN_READ(sc, MID_DMA_RDTX) != MID_DTQ_A2REG(sc->dtq_chip)) {
1021 DELAY(1);
1022 cnt--;
1023 if (cnt == 0) {
1024 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1025/*
1026 printf(" alignment=0x%x, burst size=%d, dma addr reg=0x%x\n",
1027 (u_long)sp & 63, lcv, EN_READ(sc, MID_DMA_ADDR));
1028*/
1029 return(retval); /* timeout, give up */
1030 }
1031 }
1032#else /* !NBURSTS */
1033 if (sc->is_adaptec)
1034 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
1035 else
1036 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
1037 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1038 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
1039 cnt = 1000;
1040 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
1041 DELAY(1);
1042 cnt--;
1043 if (cnt == 0) {
1044 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1045 return(retval); /* timeout, give up */
1046 }
1047 }
1048 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1049#endif /* !NBURSTS */
1050 reg = EN_READ(sc, MID_INTACK);
1051 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
1052 printf("%s: unexpected status in tx DMA test: 0x%x\n",
1053 sc->sc_dev.dv_xname, reg);
1054 return(retval);
1055 }
1056 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1057
1058 /* "return to sender..." address is known ... */
1059
1060#ifdef NBURSTS
1061 /* build lcv-byte-DMA x NBURSTS */
1062 if (sc->is_adaptec)
1063 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1064 else
1065 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1066 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1067 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1068 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1069 cnt = 1000;
1070 while (EN_READ(sc, MID_DMA_RDRX) != MID_DRQ_A2REG(sc->drq_chip)) {
1071 DELAY(1);
1072 cnt--;
1073 if (cnt == 0) {
1074 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1075 return(retval); /* timeout, give up */
1076 }
1077 }
1078#else /* !NBURSTS */
1079 if (sc->is_adaptec)
1080 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1081 else
1082 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1083 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1084 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1085 cnt = 1000;
1086 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1087 DELAY(1);
1088 cnt--;
1089 if (cnt == 0) {
1090 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1091 return(retval); /* timeout, give up */
1092 }
1093 }
1094 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1095#endif /* !NBURSTS */
1096 reg = EN_READ(sc, MID_INTACK);
1097 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1098 printf("%s: unexpected status in rx DMA test: 0x%x\n",
1099 sc->sc_dev.dv_xname, reg);
1100 return(retval);
1101 }
1102 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1103
1104 if (wmtry) {
1105 return(bcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1106 }
1107
1108#ifdef NBURSTS
1109 if (bcmp(sp, dp, lcv * NBURSTS)) {
1110/* printf("DMA test failed! lcv=%d, sp=0x%x, dp=0x%x\n", lcv, sp, dp); */
1111 return(retval); /* failed, use last value */
1112 }
1113#else
1114 if (bcmp(sp, dp, lcv))
1115 return(retval); /* failed, use last value */
1116#endif
1117
1118 retval = lcv;
1119
1120 }
1121 return(retval); /* studly 64 byte DMA present! oh baby!! */
1122}
1123
1124/***********************************************************************/
1125
1126/*
1127 * en_ioctl: handle ioctl requests
1128 *
1129 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1130 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1131 * value, subtract one from sc->txslot[0].nref, add one to the
1132 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1133 * txspeed[vci].
1134 */
1135
1136STATIC int en_ioctl(ifp, cmd, data)
1137
1138struct ifnet *ifp;
1139EN_IOCTL_CMDT cmd;
1140caddr_t data;
1141
1142{
1143 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1144 struct ifaddr *ifa = (struct ifaddr *) data;
1145 struct ifreq *ifr = (struct ifreq *) data;
1146 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1147#ifdef NATM
1148 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1149 int slot;
1150#endif
1151 int s, error = 0;
1152
1153 s = splnet();
1154
1155 switch (cmd) {
1156 case SIOCATMENA: /* enable circuit for recv */
1157 error = en_rxctl(sc, api, 1);
1158 break;
1159
1160 case SIOCATMDIS: /* disable circuit for recv */
1161 error = en_rxctl(sc, api, 0);
1162 break;
1163
1164#ifdef NATM
1165 case SIOCXRAWATM:
1166 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1167 error = EINVAL;
1168 break;
1169 }
1170 if (ario->rawvalue > EN_RXSZ*1024)
1171 ario->rawvalue = EN_RXSZ*1024;
1172 if (ario->rawvalue) {
1173 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1174 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1175 } else {
1176 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1177 sc->rxslot[slot].raw_threshold = 0;
1178 }
1179#ifdef EN_DEBUG
1180 printf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1181 sc->sc_dev.dv_xname, ario->npcb->npcb_vci,
1182 (ario->rawvalue) ? "on" : "off");
1183#endif
1184 break;
1185#endif
1186 case SIOCSIFADDR:
1187 ifp->if_flags |= IFF_UP;
1188#if defined(INET) || defined(INET6)
1189 if (ifa->ifa_addr->sa_family == AF_INET
1190 || ifa->ifa_addr->sa_family == AF_INET6) {
1191 en_reset(sc);
1192 en_init(sc);
1193 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1194 break;
1195 }
1196#endif /* INET */
1197 /* what to do if not INET? */
1198 en_reset(sc);
1199 en_init(sc);
1200 break;
1201
1202 case SIOCGIFADDR:
1203 error = EINVAL;
1204 break;
1205
1206 case SIOCSIFFLAGS:
1207 error = EINVAL;
1208 break;
1209
1210#if defined(SIOCSIFMTU) /* ??? copied from if_de */
1211#if !defined(ifr_mtu)
1212#define ifr_mtu ifr_metric
1213#endif
1214 case SIOCSIFMTU:
1215 /*
1216 * Set the interface MTU.
1217 */
1218#ifdef notsure
1219 if (ifr->ifr_mtu > ATMMTU) {
1220 error = EINVAL;
1221 break;
1222 }
1223#endif
1224 ifp->if_mtu = ifr->ifr_mtu;
1225 /* XXXCDC: do we really need to reset on MTU size change? */
1226 en_reset(sc);
1227 en_init(sc);
1228 break;
1229#endif /* SIOCSIFMTU */
1230
1231 default:
1232 error = EINVAL;
1233 break;
1234 }
1235 splx(s);
1236 return error;
1237}
1238
1239
1240/*
1241 * en_rxctl: turn on and off VCs for recv.
1242 */
1243
1244STATIC int en_rxctl(sc, pi, on)
1245
1246struct en_softc *sc;
1247struct atm_pseudoioctl *pi;
1248int on;
1249
1250{
1251 u_int s, vci, flags, slot;
1252 u_int32_t oldmode, newmode;
1253
1254 vci = ATM_PH_VCI(&pi->aph);
1255 flags = ATM_PH_FLAGS(&pi->aph);
1256
1257#ifdef EN_DEBUG
1258 printf("%s: %s vpi=%d, vci=%d, flags=%d\n", sc->sc_dev.dv_xname,
1259 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1260#endif
1261
1262 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1263 return(EINVAL);
1264
1265 /*
1266 * turn on VCI!
1267 */
1268
1269 if (on) {
1270 if (sc->rxvc2slot[vci] != RX_NONE)
1271 return(EINVAL);
1272 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1273 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1274 break;
1275 if (slot == sc->en_nrx)
1276 return(ENOSPC);
1277 sc->rxvc2slot[vci] = slot;
1278 sc->rxslot[slot].rxhand = NULL;
1279 oldmode = sc->rxslot[slot].mode;
1280 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1281 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1282 sc->rxslot[slot].atm_vci = vci;
1283 sc->rxslot[slot].atm_flags = flags;
1284 sc->rxslot[slot].oth_flags = 0;
1285 sc->rxslot[slot].rxhand = pi->rxhand;
1286 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1287 panic("en_rxctl: left over mbufs on enable");
1288 sc->txspeed[vci] = 0; /* full speed to start */
1289 sc->txvc2slot[vci] = 0; /* init value */
1290 sc->txslot[0].nref++; /* bump reference count */
1291 en_loadvc(sc, vci); /* does debug printf for us */
1292 return(0);
1293 }
1294
1295 /*
1296 * turn off VCI
1297 */
1298
1299 if (sc->rxvc2slot[vci] == RX_NONE)
1300 return(EINVAL);
1301 slot = sc->rxvc2slot[vci];
1302 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1303 return(EINVAL);
1304 s = splimp(); /* block out enintr() */
1305 oldmode = EN_READ(sc, MID_VC(vci));
1306 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1307 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1308 /* halt in tracks, be careful to preserve inserivce bit */
1309 DELAY(27);
1310 sc->rxslot[slot].rxhand = NULL;
1311 sc->rxslot[slot].mode = newmode;
1312
1313 sc->txslot[sc->txvc2slot[vci]].nref--;
1314 sc->txspeed[vci] = 0;
1315 sc->txvc2slot[vci] = 0;
1316
1317 /* if stuff is still going on we are going to have to drain it out */
1318 if (sc->rxslot[slot].indma.ifq_head ||
1319 sc->rxslot[slot].q.ifq_head ||
1320 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1321 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1322 } else {
1323 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1324 sc->rxslot[slot].atm_vci = RX_NONE;
1325 sc->rxvc2slot[vci] = RX_NONE;
1326 }
1327 splx(s); /* enable enintr() */
1328#ifdef EN_DEBUG
1329 printf("%s: rx%d: VCI %d is now %s\n", sc->sc_dev.dv_xname, slot, vci,
1330 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1331#endif
1332 return(0);
1333}
1334
1335/***********************************************************************/
1336
1337/*
1338 * en_reset: reset the board, throw away work in progress.
1339 * must en_init to recover.
1340 */
1341
1342void en_reset(sc)
1343
1344struct en_softc *sc;
1345
1346{
1347 struct mbuf *m;
1348 int lcv, slot;
1349
1350#ifdef EN_DEBUG
1351 printf("%s: reset\n", sc->sc_dev.dv_xname);
1352#endif
1353
1354 if (sc->en_busreset)
1355 sc->en_busreset(sc);
1356 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1357
1358 /*
1359 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1360 * will free us!
1361 */
1362
1363 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1364 if (sc->rxvc2slot[lcv] == RX_NONE)
1365 continue;
1366 slot = sc->rxvc2slot[lcv];
1367 while (1) {
1368 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1369 if (m == NULL)
1370 break; /* >>> exit 'while(1)' here <<< */
1371 m_freem(m);
1372 }
1373 while (1) {
1374 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1375 if (m == NULL)
1376 break; /* >>> exit 'while(1)' here <<< */
1377 m_freem(m);
1378 }
1379 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1380 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1381 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1382 sc->rxvc2slot[lcv] = RX_NONE;
1383#ifdef EN_DEBUG
1384 printf("%s: rx%d: VCI %d is now free\n", sc->sc_dev.dv_xname, slot, lcv);
1385#endif
1386 }
1387 }
1388
1389 /*
1390 * xmit: dump everything
1391 */
1392
1393 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1394 while (1) {
1395 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1396 if (m == NULL)
1397 break; /* >>> exit 'while(1)' here <<< */
1398 m_freem(m);
1399 }
1400 while (1) {
1401 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1402 if (m == NULL)
1403 break; /* >>> exit 'while(1)' here <<< */
1404 m_freem(m);
1405 }
1406
1407 sc->txslot[lcv].mbsize = 0;
1408 }
1409
1410 return;
1411}
1412
1413
1414/*
1415 * en_init: init board and sync the card with the data in the softc.
1416 */
1417
1418STATIC void en_init(sc)
1419
1420struct en_softc *sc;
1421
1422{
1423 int vc, slot;
1424 u_int32_t loc;
1425
1426 if ((sc->enif.if_flags & IFF_UP) == 0) {
1427#ifdef EN_DEBUG
1428 printf("%s: going down\n", sc->sc_dev.dv_xname);
1429#endif
1430 en_reset(sc); /* to be safe */
1431 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1432 return;
1433 }
1434
1435#ifdef EN_DEBUG
1436 printf("%s: going up\n", sc->sc_dev.dv_xname);
1437#endif
1438 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1439
1440 if (sc->en_busreset)
1441 sc->en_busreset(sc);
1442 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1443
1444 /*
1445 * init obmem data structures: vc tab, dma q's, slist.
1446 *
1447 * note that we set drq_free/dtq_free to one less than the total number
1448 * of DTQ/DRQs present. we do this because the card uses the condition
1449 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1450 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1451 * the drq_us pointer will wrap all the way around]. by restricting
1452 * the number of active requests to (N - 1) we prevent the list from
1453 * becoming completely full. note that the card will sometimes give
1454 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1455 * keep that interrupt from messing us up.
1456 */
1457
1458 for (vc = 0 ; vc < MID_N_VC ; vc++)
1459 en_loadvc(sc, vc);
1460
1461 bzero(&sc->drq, sizeof(sc->drq));
1462 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1463 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1464 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1465 /* ensure zero queue */
1466 sc->drq_us = sc->drq_chip;
1467
1468 bzero(&sc->dtq, sizeof(sc->dtq));
1469 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1470 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1471 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1472 /* ensure zero queue */
1473 sc->dtq_us = sc->dtq_chip;
1474
1475 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1476 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1477
1478#ifdef EN_DEBUG
1479 printf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1480 sc->sc_dev.dv_xname, sc->drq_free, sc->drq_chip,
1481 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1482#endif
1483
1484 for (slot = 0 ; slot < EN_NTX ; slot++) {
1485 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1486 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1487 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1488 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1489 loc = loc - MID_RAMOFF;
1490 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1491 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1492 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1493#ifdef EN_DEBUG
1494 printf("%s: tx%d: place 0x%x\n", sc->sc_dev.dv_xname, slot,
1495 EN_READ(sc, MIDX_PLACE(slot)));
1496#endif
1497 }
1498
1499 /*
1500 * enable!
1501 */
1502
1503 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1504 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1505 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1506 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1507 MID_MCSR_ENTX|MID_MCSR_ENRX);
1508
1509}
1510
1511
1512/*
1513 * en_loadvc: load a vc tab entry from a slot
1514 */
1515
1516STATIC void en_loadvc(sc, vc)
1517
1518struct en_softc *sc;
1519int vc;
1520
1521{
1522 int slot;
1523 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1524
1525 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1526 EN_WRITE(sc, MID_VC(vc), reg);
1527 DELAY(27);
1528
1529 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1530 return;
1531
1532 /* no need to set CRC */
1533 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1534 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1535 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1536 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1537
1538#ifdef EN_DEBUG
1539 printf("%s: rx%d: assigned to VCI %d\n", sc->sc_dev.dv_xname, slot, vc);
1540#endif
1541}
1542
1543
1544/*
1545 * en_start: start transmitting the next packet that needs to go out
1546 * if there is one. note that atm_output() has already splimp()'d us.
1547 */
1548
1549STATIC void en_start(ifp)
1550
1551struct ifnet *ifp;
1552
1553{
1554 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1555 struct ifqueue *ifq = &ifp->if_snd; /* if INPUT QUEUE */
1556 struct mbuf *m, *lastm, *prev;
1557 struct atm_pseudohdr *ap, *new_ap;
1558 int txchan, mlen, got, need, toadd, cellcnt, first;
1559 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1560 u_int8_t *cp;
1561
1562 if ((ifp->if_flags & IFF_RUNNING) == 0)
1563 return;
1564
1565 /*
1566 * remove everything from interface queue since we handle all queueing
1567 * locally ...
1568 */
1569
1570 while (1) {
1571
1572 IF_DEQUEUE(ifq, m);
1573 if (m == NULL)
1574 return; /* EMPTY: >>> exit here <<< */
1575
1576 /*
1577 * calculate size of packet (in bytes)
1578 * also, if we are not doing transmit DMA we eliminate all stupid
1579 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1580 * seem to be due to tcp retransmits for the most part.
1581 *
1582 * after this loop mlen total length of mbuf chain (including atm_ph),
1583 * and lastm is a pointer to the last mbuf on the chain.
1584 */
1585
1586 lastm = m;
1587 mlen = 0;
1588 prev = NULL;
1589 while (1) {
1590 /* no DMA? */
1591 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1592 if ( ((uintptr_t)mtod(lastm, void *) % sizeof(u_int32_t)) != 0 ||
1593 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1594 first = (lastm == m);
1595 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1596 m_freem(m);
1597 m = NULL;
1598 break;
1599 }
1600 if (first)
1601 m = lastm; /* update */
1602 }
1603 prev = lastm;
1604 }
1605
1606 mlen += lastm->m_len;
1607 if (lastm->m_next == NULL)
1608 break;
1609 lastm = lastm->m_next;
1610 }
1611
1612 if (m == NULL) /* happens only if mfix fails */
1613 continue;
1614
1615 ap = mtod(m, struct atm_pseudohdr *);
1616
1617 atm_vpi = ATM_PH_VPI(ap);
1618 atm_vci = ATM_PH_VCI(ap);
1619 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1620 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1621 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1622
1623 /*
1624 * check that vpi/vci is one we can use
1625 */
1626
1627 if (atm_vpi || atm_vci > MID_N_VC) {
1628 printf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1629 sc->sc_dev.dv_xname, atm_vpi, atm_vci);
1630 m_freem(m);
1631 continue;
1632 }
1633
1634 /*
1635 * computing how much padding we need on the end of the mbuf, then
1636 * see if we can put the TBD at the front of the mbuf where the
1637 * link header goes (well behaved protocols will reserve room for us).
1638 * last, check if room for PDU tail.
1639 *
1640 * got = number of bytes of data we have
1641 * cellcnt = number of cells in this mbuf
1642 * need = number of bytes of data + padding we need (excludes TBD)
1643 * toadd = number of bytes of data we need to add to end of mbuf,
1644 * [including AAL5 PDU, if AAL5]
1645 */
1646
1647 got = mlen - sizeof(struct atm_pseudohdr *);
1648 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1649 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1650 need = cellcnt * MID_ATMDATASZ;
1651 toadd = need - got; /* recompute, including zero padding */
1652
1653#ifdef EN_DEBUG
1654 printf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1655 sc->sc_dev.dv_xname, atm_vci, mlen, got, need, toadd, cellcnt);
1656 printf(" leading_space=%d, trailing_space=%d\n",
1657 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1658#endif
1659
1660#ifdef EN_MBUF_OPT
1661
1662 /*
1663 * note: external storage (M_EXT) can be shared between mbufs
1664 * to avoid copying (see m_copym()). this means that the same
1665 * data buffer could be shared by several mbufs, and thus it isn't
1666 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1667 */
1668
1669 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1670 m->m_data -= MID_TBD_SIZE;
1671 m->m_len += MID_TBD_SIZE;
1672 mlen += MID_TBD_SIZE;
1673 new_ap = mtod(m, struct atm_pseudohdr *);
1674 *new_ap = *ap; /* move it back */
1675 ap = new_ap;
1676 dat = ((u_int32_t *) ap) + 1;
1677 /* make sure the TBD is in proper byte order */
1678 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1679 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1680 atm_flags |= EN_OBHDR;
1681 }
1682
1683 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1684 M_TRAILINGSPACE(lastm) >= toadd) {
1685 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1686 lastm->m_len += toadd;
1687 mlen += toadd;
1688 if (aal == MID_TBD_AAL5) {
1689 bzero(cp, toadd - MID_PDU_SIZE);
1690 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1691 /* make sure the PDU is in proper byte order */
1692 *dat = htonl(MID_PDU_MK1(0, 0, got));
1693 } else {
1694 bzero(cp, toadd);
1695 }
1696 atm_flags |= EN_OBTRL;
1697 }
1698 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1699#endif /* EN_MBUF_OPT */
1700
1701 /*
1702 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1703 */
1704
1705 txchan = sc->txvc2slot[atm_vci];
1706
1707 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1708 EN_COUNT(sc->txmbovr);
1709 m_freem(m);
1710#ifdef EN_DEBUG
1711 printf("%s: tx%d: buffer space shortage\n", sc->sc_dev.dv_xname,
1712 txchan);
1713#endif
1714 continue;
1715 }
1716
1717 sc->txslot[txchan].mbsize += mlen;
1718
1719#ifdef EN_DEBUG
1720 printf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1721 sc->sc_dev.dv_xname, txchan, atm_vpi, atm_vci, atm_flags,
1722 sc->txspeed[atm_vci]);
1723 printf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1724 sc->txslot[txchan].mbsize);
1725#endif
1726
1727 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1728
1729 en_txdma(sc, txchan);
1730
1731 }
1732 /*NOTREACHED*/
1733}
1734
1735
1736/*
1737 * en_mfix: fix a stupid mbuf
1738 */
1739
1740#ifndef __FreeBSD__
1741
1742STATIC int en_mfix(sc, mm, prev)
1743
1744struct en_softc *sc;
1745struct mbuf **mm, *prev;
1746
1747{
1748 struct mbuf *m, *new;
1749 u_char *d, *cp;
1750 int off;
1751 struct mbuf *nxt;
1752
1753 m = *mm;
1754
1755 EN_COUNT(sc->mfix); /* count # of calls */
1756#ifdef EN_DEBUG
1757 printf("%s: mfix mbuf m_data=%p, m_len=%d\n", sc->sc_dev.dv_xname,
1758 m->m_data, m->m_len);
1759#endif
1760
1761 d = mtod(m, u_char *);
1762 off = ((unsigned long) d) % sizeof(u_int32_t);
1763
1764 if (off) {
1765 if ((m->m_flags & M_EXT) == 0) {
1766 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1767 d -= off;
1768 m->m_data = (caddr_t)d;
1769 } else {
1770 /* can't write to an M_EXT mbuf since it may be shared */
1771 MGET(new, M_DONTWAIT, MT_DATA);
1772 if (!new) {
1773 EN_COUNT(sc->mfixfail);
1774 return(0);
1775 }
1776 MCLGET(new, M_DONTWAIT);
1777 if ((new->m_flags & M_EXT) == 0) {
1778 m_free(new);
1779 EN_COUNT(sc->mfixfail);
1780 return(0);
1781 }
1782 bcopy(d, new->m_data, m->m_len); /* ALIGN! (with costly data copy...) */
1783 new->m_len = m->m_len;
1784 new->m_next = m->m_next;
1785 if (prev)
1786 prev->m_next = new;
1787 m_free(m);
1788 *mm = m = new; /* note: 'd' now invalid */
1789 }
1790 }
1791
1792 off = m->m_len % sizeof(u_int32_t);
1793 if (off == 0)
1794 return(1);
1795
1796 d = mtod(m, u_char *) + m->m_len;
1797 off = sizeof(u_int32_t) - off;
1798
1799 nxt = m->m_next;
1800 while (off--) {
1801 for ( ; nxt != NULL && nxt->m_len == 0 ; nxt = nxt->m_next)
1802 /*null*/;
1803 if (nxt == NULL) { /* out of data, zero fill */
1804 *d++ = 0;
1805 continue; /* next "off" */
1806 }
1807 cp = mtod(nxt, u_char *);
1808 *d++ = *cp++;
1809 m->m_len++;
1810 nxt->m_len--;
1811 nxt->m_data = (caddr_t)cp;
1812 }
1813 return(1);
1814}
1815
1816#else /* __FreeBSD__ */
1817
1818STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1819
1820STATIC int en_makeexclusive(sc, mm, prev)
1821 struct en_softc *sc;
1822 struct mbuf **mm, *prev;
1823{
1824 struct mbuf *m, *new;
1825
1826 m = *mm;
1827
1828 if (m->m_flags & M_EXT) {
1829 if (m->m_ext.ext_free) {
1830 /* external buffer isn't an ordinary mbuf cluster! */
1831 printf("%s: mfix: special buffer! can't make a copy!\n",
1832 sc->sc_dev.dv_xname);
1833 return (0);
1834 }
1835
1836 if (mclrefcnt[mtocl(m->m_ext.ext_buf)] > 1) {
1837 /* make a real copy of the M_EXT mbuf since it is shared */
1838 MGET(new, M_DONTWAIT, MT_DATA);
1839 if (!new) {
1840 EN_COUNT(sc->mfixfail);
1841 return(0);
1842 }
1843 if (m->m_flags & M_PKTHDR)
1844 M_MOVE_PKTHDR(new, m);
1845 MCLGET(new, M_DONTWAIT);
1846 if ((new->m_flags & M_EXT) == 0) {
1847 m_free(new);
1848 EN_COUNT(sc->mfixfail);
1849 return(0);
1850 }
1851 bcopy(m->m_data, new->m_data, m->m_len);
1852 new->m_len = m->m_len;
1853 new->m_next = m->m_next;
1854 if (prev)
1855 prev->m_next = new;
1856 m_free(m);
1857 *mm = new;
1858 }
1859 else {
1860 /* the buffer is not shared, align the data offset using
1861 this buffer. */
1862 u_char *d = mtod(m, u_char *);
1863 int off = ((uintptr_t)(void *)d) % sizeof(u_int32_t);
1864
1865 if (off > 0) {
1866 bcopy(d, d - off, m->m_len);
1867 m->m_data = (caddr_t)d - off;
1868 }
1869 }
1870 }
1871 return (1);
1872}
1873
1874STATIC int en_mfix(sc, mm, prev)
1875
1876struct en_softc *sc;
1877struct mbuf **mm, *prev;
1878
1879{
1880 struct mbuf *m;
1881 u_char *d, *cp;
1882 int off;
1883 struct mbuf *nxt;
1884
1885 m = *mm;
1886
1887 EN_COUNT(sc->mfix); /* count # of calls */
1888#ifdef EN_DEBUG
1889 printf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", sc->sc_dev.dv_xname,
1890 m->m_data, m->m_len);
1891#endif
1892
1893 d = mtod(m, u_char *);
1894 off = ((uintptr_t) (void *) d) % sizeof(u_int32_t);
1895
1896 if (off) {
1897 if ((m->m_flags & M_EXT) == 0) {
1898 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1899 d -= off;
1900 m->m_data = (caddr_t)d;
1901 } else {
1902 /* can't write to an M_EXT mbuf since it may be shared */
1903 if (en_makeexclusive(sc, &m, prev) == 0)
1904 return (0);
1905 *mm = m; /* note: 'd' now invalid */
1906 }
1907 }
1908
1909 off = m->m_len % sizeof(u_int32_t);
1910 if (off == 0)
1911 return(1);
1912
1913 if (m->m_flags & M_EXT) {
1914 /* can't write to an M_EXT mbuf since it may be shared */
1915 if (en_makeexclusive(sc, &m, prev) == 0)
1916 return (0);
1917 *mm = m; /* note: 'd' now invalid */
1918 }
1919
1920 d = mtod(m, u_char *) + m->m_len;
1921 off = sizeof(u_int32_t) - off;
1922
1923 nxt = m->m_next;
1924 while (off--) {
1925 if (nxt != NULL && nxt->m_len == 0) {
1926 /* remove an empty mbuf. this avoids odd byte padding to an empty
1927 last mbuf. */
1928 m->m_next = nxt = m_free(nxt);
1929 }
1930 if (nxt == NULL) { /* out of data, zero fill */
1931 *d++ = 0;
1932 continue; /* next "off" */
1933 }
1934 cp = mtod(nxt, u_char *);
1935 *d++ = *cp++;
1936 m->m_len++;
1937 nxt->m_len--;
1938 nxt->m_data = (caddr_t)cp;
1939 }
1940 if (nxt != NULL && nxt->m_len == 0)
1941 m->m_next = m_free(nxt);
1942 return(1);
1943}
1944
1945#endif /* __FreeBSD__ */
1946
1947/*
1948 * en_txdma: start trasmit DMA, if possible
1949 */
1950
1951STATIC void en_txdma(sc, chan)
1952
1953struct en_softc *sc;
1954int chan;
1955
1956{
1957 struct mbuf *tmp;
1958 struct atm_pseudohdr *ap;
1959 struct en_launch launch;
1960 int datalen = 0, dtqneed, len, ncells;
1961 u_int8_t *cp;
1962 struct ifnet *ifp;
1963
1964#ifdef EN_DEBUG
1965 printf("%s: tx%d: starting...\n", sc->sc_dev.dv_xname, chan);
1966#endif
1967
1968 /*
1969 * note: now that txlaunch handles non-word aligned/sized requests
1970 * the only time you can safely set launch.nodma is if you've en_mfix()'d
1971 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
1972 */
1973
1974 launch.nodma = (EN_NOTXDMA || !en_dma);
1975
1976again:
1977
1978 /*
1979 * get an mbuf waiting for DMA
1980 */
1981
1982 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
1983
1984 if (launch.t == NULL) {
1985#ifdef EN_DEBUG
1986 printf("%s: tx%d: ...done!\n", sc->sc_dev.dv_xname, chan);
1987#endif
1988 return; /* >>> exit here if no data waiting for DMA <<< */
1989 }
1990
1991 /*
1992 * get flags, vci
1993 *
1994 * note: launch.need = # bytes we need to get on the card
1995 * dtqneed = # of DTQs we need for this packet
1996 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
1997 */
1998
1999 ap = mtod(launch.t, struct atm_pseudohdr *);
2000 launch.atm_vci = ATM_PH_VCI(ap);
2001 launch.atm_flags = ATM_PH_FLAGS(ap);
2002 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
2003 MID_TBD_AAL5 : MID_TBD_NOAAL5;
2004
2005 /*
2006 * XXX: have to recompute the length again, even though we already did
2007 * it in en_start(). might as well compute dtqneed here as well, so
2008 * this isn't that bad.
2009 */
2010
2011 if ((launch.atm_flags & EN_OBHDR) == 0) {
2012 dtqneed = 1; /* header still needs to be added */
2013 launch.need = MID_TBD_SIZE; /* not includeded with mbuf */
2014 } else {
2015 dtqneed = 0; /* header on-board, dma with mbuf */
2016 launch.need = 0;
2017 }
2018
2019 launch.mlen = 0;
2020 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
2021 len = tmp->m_len;
2022 launch.mlen += len;
2023 cp = mtod(tmp, u_int8_t *);
2024 if (tmp == launch.t) {
2025 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
2026 cp += sizeof(struct atm_pseudohdr);
2027 }
2028 launch.need += len;
2029 if (len == 0)
2030 continue; /* atm_pseudohdr alone in first mbuf */
2031
2032 dtqneed += en_dqneed(sc, (caddr_t) cp, len, 1);
2033 }
2034
2035 if ((launch.need % sizeof(u_int32_t)) != 0)
2036 dtqneed++; /* need DTQ to FLUSH internal buffer */
2037
2038 if ((launch.atm_flags & EN_OBTRL) == 0) {
2039 if (launch.aal == MID_TBD_AAL5) {
2040 datalen = launch.need - MID_TBD_SIZE;
2041 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
2042 }
2043 dtqneed++; /* need to work on the end a bit */
2044 }
2045
2046 /*
2047 * finish calculation of launch.need (need to figure out how much padding
2048 * we will need). launch.need includes MID_TBD_SIZE, but we need to
2049 * remove that to so we can round off properly. we have to add
2050 * MID_TBD_SIZE back in after calculating ncells.
2051 */
2052
2053 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
2054 ncells = launch.need / MID_ATMDATASZ;
2055 launch.need += MID_TBD_SIZE;
2056
2057 if (launch.need > EN_TXSZ * 1024) {
2058 printf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
2059 sc->sc_dev.dv_xname, chan, launch.need, EN_TXSZ * 1024);
2060 goto dequeue_drop;
2061 }
2062
2063 /*
2064 * note: don't use the entire buffer space. if WRTX becomes equal
2065 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
2066 */
2067 if (launch.need >= sc->txslot[chan].bfree) {
2068 EN_COUNT(sc->txoutspace);
2069#ifdef EN_DEBUG
2070 printf("%s: tx%d: out of transmit space\n", sc->sc_dev.dv_xname, chan);
2071#endif
2072 return; /* >>> exit here if out of obmem buffer space <<< */
2073 }
2074
2075 /*
2076 * ensure we have enough dtqs to go, if not, wait for more.
2077 */
2078
2079 if (launch.nodma) {
2080 dtqneed = 1;
2081 }
2082 if (dtqneed > sc->dtq_free) {
2083 sc->need_dtqs = 1;
2084 EN_COUNT(sc->txdtqout);
2085#ifdef EN_DEBUG
2086 printf("%s: tx%d: out of transmit DTQs\n", sc->sc_dev.dv_xname, chan);
2087#endif
2088 return; /* >>> exit here if out of dtqs <<< */
2089 }
2090
2091 /*
2092 * it is a go, commit! dequeue mbuf start working on the xfer.
2093 */
2094
2095 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2096#ifdef EN_DIAG
2097 if (launch.t != tmp)
2098 panic("en dequeue");
2099#endif /* EN_DIAG */
2100
2101 /*
2102 * launch!
2103 */
2104
2105 EN_COUNT(sc->launch);
2106 ifp = &sc->enif;
2107 ifp->if_opackets++;
2108
2109 if ((launch.atm_flags & EN_OBHDR) == 0) {
2110 EN_COUNT(sc->lheader);
2111 /* store tbd1/tbd2 in host byte order */
2112 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
2113 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
2114 }
2115 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
2116 EN_COUNT(sc->ltail);
2117 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
2118 }
2119
2120 en_txlaunch(sc, chan, &launch);
2121
2122#if NBPF > 0
2123 if (ifp->if_bpf) {
2124 /*
2125 * adjust the top of the mbuf to skip the pseudo atm header
2126 * (and TBD, if present) before passing the packet to bpf,
2127 * restore it afterwards.
2128 */
2129 int size = sizeof(struct atm_pseudohdr);
2130 if (launch.atm_flags & EN_OBHDR)
2131 size += MID_TBD_SIZE;
2132
2133 launch.t->m_data += size;
2134 launch.t->m_len -= size;
2135
2136 BPF_MTAP(ifp, launch.t);
2137
2138 launch.t->m_data -= size;
2139 launch.t->m_len += size;
2140 }
2141#endif /* NBPF > 0 */
2142 /*
2143 * do some housekeeping and get the next packet
2144 */
2145
2146 sc->txslot[chan].bfree -= launch.need;
2147 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
2148 goto again;
2149
2150 /*
2151 * END of txdma loop!
2152 */
2153
2154 /*
2155 * error handles
2156 */
2157
2158dequeue_drop:
2159 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2160 if (launch.t != tmp)
2161 panic("en dequeue drop");
2162 m_freem(launch.t);
2163 sc->txslot[chan].mbsize -= launch.mlen;
2164 goto again;
2165}
2166
2167
2168/*
2169 * en_txlaunch: launch an mbuf into the dma pool!
2170 */
2171
2172STATIC void en_txlaunch(sc, chan, l)
2173
2174struct en_softc *sc;
2175int chan;
2176struct en_launch *l;
2177
2178{
2179 struct mbuf *tmp;
2180 u_int32_t cur = sc->txslot[chan].cur,
2181 start = sc->txslot[chan].start,
2182 stop = sc->txslot[chan].stop,
2183 dma, *data, *datastop, count, bcode;
2184 int pad, addtail, need, len, needalign, cnt, end, mx;
2185
2186
2187 /*
2188 * vars:
2189 * need = # bytes card still needs (decr. to zero)
2190 * len = # of bytes left in current mbuf
2191 * cur = our current pointer
2192 * dma = last place we programmed into the DMA
2193 * data = pointer into data area of mbuf that needs to go next
2194 * cnt = # of bytes to transfer in this DTQ
2195 * bcode/count = DMA burst code, and chip's version of cnt
2196 *
2197 * a single buffer can require up to 5 DTQs depending on its size
2198 * and alignment requirements. the 5 possible requests are:
2199 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2200 * [2] alburst DMA to align src data pointer to bestburstlen
2201 * [3] 1 or more bestburstlen DMAs
2202 * [4] clean up burst (to last word boundary)
2203 * [5] 1, 2, or 3 byte final clean up DMA
2204 */
2205
2206 need = l->need;
2207 dma = cur;
2208 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2209
2210#ifdef EN_DIAG
2211 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2212 printf("%s: tx%d: bogus trasmit needs (%d)\n", sc->sc_dev.dv_xname, chan,
2213 need);
2214#endif
2215#ifdef EN_DEBUG
2216 printf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2217 sc->sc_dev.dv_xname, chan, l->t, cur, (cur-start)/4, need, addtail);
2218 count = EN_READ(sc, MIDX_PLACE(chan));
2219 printf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2220 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2221 EN_READ(sc, MIDX_DESCSTART(chan)));
2222#endif
2223
2224 /*
2225 * do we need to insert the TBD by hand?
2226 * note that tbd1/tbd2/pdu1 are in host byte order.
2227 */
2228
2229 if ((l->atm_flags & EN_OBHDR) == 0) {
2230#ifdef EN_DEBUG
2231 printf("%s: tx%d: insert header 0x%x 0x%x\n", sc->sc_dev.dv_xname,
2232 chan, l->tbd1, l->tbd2);
2233#endif
2234 EN_WRITE(sc, cur, l->tbd1);
2235 EN_WRAPADD(start, stop, cur, 4);
2236 EN_WRITE(sc, cur, l->tbd2);
2237 EN_WRAPADD(start, stop, cur, 4);
2238 need -= 8;
2239 }
2240
2241 /*
2242 * now do the mbufs...
2243 */
2244
2245 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2246
2247 /* get pointer to data and length */
2248 data = mtod(tmp, u_int32_t *);
2249 len = tmp->m_len;
2250 if (tmp == l->t) {
2251 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2252 len -= sizeof(struct atm_pseudohdr);
2253 }
2254
2255 /* now, determine if we should copy it */
2256 if (l->nodma || (len < EN_MINDMA &&
2257 (len % 4) == 0 && ((uintptr_t) (void *) data % 4) == 0 &&
2258 (cur % 4) == 0)) {
2259
2260 /*
2261 * roundup len: the only time this will change the value of len
2262 * is when l->nodma is true, tmp is the last mbuf, and there is
2263 * a non-word number of bytes to transmit. in this case it is
2264 * safe to round up because we've en_mfix'd the mbuf (so the first
2265 * byte is word aligned there must be enough free bytes at the end
2266 * to round off to the next word boundary)...
2267 */
2268 len = roundup(len, sizeof(u_int32_t));
2269 datastop = data + (len / sizeof(u_int32_t));
2270 /* copy loop: preserve byte order!!! use WRITEDAT */
2271 while (data != datastop) {
2272 EN_WRITEDAT(sc, cur, *data);
2273 data++;
2274 EN_WRAPADD(start, stop, cur, 4);
2275 }
2276 need -= len;
2277#ifdef EN_DEBUG
2278 printf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2279 sc->sc_dev.dv_xname, chan, len, need, cur);
2280#endif
2281 continue; /* continue on to next mbuf */
2282 }
2283
2284 /* going to do DMA, first make sure the dtq is in sync. */
2285 if (dma != cur) {
2286 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2287#ifdef EN_DEBUG
2288 printf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2289 sc->sc_dev.dv_xname, chan, cur);
2290#endif
2291 }
2292
2293 /*
2294 * if this is the last buffer, and it looks like we are going to need to
2295 * flush the internal buffer, can we extend the length of this mbuf to
2296 * avoid the FLUSH?
2297 */
2298
2299 if (tmp->m_next == NULL) {
2300 cnt = (need - len) % sizeof(u_int32_t);
2301 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2302 len += cnt; /* pad for FLUSH */
2303 }
2304
2305#if !defined(MIDWAY_ENIONLY)
2306
2307 /*
2308 * the adaptec DMA engine is smart and handles everything for us.
2309 */
2310
2311 if (sc->is_adaptec) {
2312 /* need to DMA "len" bytes out to card */
2313 need -= len;
2314 EN_WRAPADD(start, stop, cur, len);
2315#ifdef EN_DEBUG
2316 printf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2317 sc->sc_dev.dv_xname, chan, len, need, cur);
2318#endif
2319 end = (need == 0) ? MID_DMA_END : 0;
2320 EN_DTQADD(sc, len, chan, 0, vtophys(data), l->mlen, end);
2321 if (end)
2322 goto done;
2323 dma = cur; /* update dma pointer */
2324 continue;
2325 }
2326#endif /* !MIDWAY_ENIONLY */
2327
2328#if !defined(MIDWAY_ADPONLY)
2329
2330 /*
2331 * the ENI DMA engine is not so smart and need more help from us
2332 */
2333
2334 /* do we need to do a DMA op to align to word boundary? */
2335 needalign = (uintptr_t) (void *) data % sizeof(u_int32_t);
2336 if (needalign) {
2337 EN_COUNT(sc->headbyte);
2338 cnt = sizeof(u_int32_t) - needalign;
2339 if (cnt == 2 && len >= cnt) {
2340 count = 1;
2341 bcode = MIDDMA_2BYTE;
2342 } else {
2343 cnt = min(cnt, len); /* prevent overflow */
2344 count = cnt;
2345 bcode = MIDDMA_BYTE;
2346 }
2347 need -= cnt;
2348 EN_WRAPADD(start, stop, cur, cnt);
2349#ifdef EN_DEBUG
2350 printf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2351 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2352#endif
2353 len -= cnt;
2354 end = (need == 0) ? MID_DMA_END : 0;
2355 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2356 if (end)
2357 goto done;
2358 data = (u_int32_t *) ((u_char *)data + cnt);
2359 }
2360
2361 /* do we need to do a DMA op to align? */
2362 if (sc->alburst &&
2363 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0
2364 && len >= sizeof(u_int32_t)) {
2365 cnt = sc->bestburstlen - needalign;
2366 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2367 if (cnt > mx) {
2368 cnt = mx;
2369 count = cnt / sizeof(u_int32_t);
2370 bcode = MIDDMA_WORD;
2371 } else {
2372 count = cnt / sizeof(u_int32_t);
2373 bcode = en_dmaplan[count].bcode;
2374 count = cnt >> en_dmaplan[count].divshift;
2375 }
2376 need -= cnt;
2377 EN_WRAPADD(start, stop, cur, cnt);
2378#ifdef EN_DEBUG
2379 printf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2380 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2381#endif
2382 len -= cnt;
2383 end = (need == 0) ? MID_DMA_END : 0;
2384 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2385 if (end)
2386 goto done;
2387 data = (u_int32_t *) ((u_char *)data + cnt);
2388 }
2389
2390 /* do we need to do a max-sized burst? */
2391 if (len >= sc->bestburstlen) {
2392 count = len >> sc->bestburstshift;
2393 cnt = count << sc->bestburstshift;
2394 bcode = sc->bestburstcode;
2395 need -= cnt;
2396 EN_WRAPADD(start, stop, cur, cnt);
2397#ifdef EN_DEBUG
2398 printf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2399 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2400#endif
2401 len -= cnt;
2402 end = (need == 0) ? MID_DMA_END : 0;
2403 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2404 if (end)
2405 goto done;
2406 data = (u_int32_t *) ((u_char *)data + cnt);
2407 }
2408
2409 /* do we need to do a cleanup burst? */
2410 cnt = len & ~(sizeof(u_int32_t)-1);
2411 if (cnt) {
2412 count = cnt / sizeof(u_int32_t);
2413 bcode = en_dmaplan[count].bcode;
2414 count = cnt >> en_dmaplan[count].divshift;
2415 need -= cnt;
2416 EN_WRAPADD(start, stop, cur, cnt);
2417#ifdef EN_DEBUG
2418 printf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2419 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2420#endif
2421 len -= cnt;
2422 end = (need == 0) ? MID_DMA_END : 0;
2423 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2424 if (end)
2425 goto done;
2426 data = (u_int32_t *) ((u_char *)data + cnt);
2427 }
2428
2429 /* any word fragments left? */
2430 if (len) {
2431 EN_COUNT(sc->tailbyte);
2432 if (len == 2) {
2433 count = 1;
2434 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2435 } else {
2436 count = len;
2437 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2438 }
2439 need -= len;
2440 EN_WRAPADD(start, stop, cur, len);
2441#ifdef EN_DEBUG
2442 printf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2443 sc->sc_dev.dv_xname, chan, len, need, cur);
2444#endif
2445 end = (need == 0) ? MID_DMA_END : 0;
2446 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2447 if (end)
2448 goto done;
2449 }
2450
2451 dma = cur; /* update dma pointer */
2452#endif /* !MIDWAY_ADPONLY */
2453
2454 } /* next mbuf, please */
2455
2456 /*
2457 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2458 * if the trailer or padding needs to be put in, do it now.
2459 *
2460 * NOTE: experimental results reveal the following fact:
2461 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2462 * then the card will internally buffer the last (X % 4) bytes (in
2463 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2464 * it is imporant to make sure we don't leave any important data in
2465 * this internal buffer because it is discarded on the last (end) DTQ.
2466 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2467 * the darn thing out.
2468 */
2469
2470 if (addtail) {
2471
2472 pad = need % sizeof(u_int32_t);
2473 if (pad) {
2474 /*
2475 * FLUSH internal data buffer. pad out with random data from the front
2476 * of the mbuf chain...
2477 */
2478 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2479 EN_COUNT(sc->tailflush);
2480 EN_WRAPADD(start, stop, cur, pad);
2481 EN_DTQADD(sc, pad, chan, bcode, vtophys(l->t->m_data), 0, 0);
2482 need -= pad;
2483#ifdef EN_DEBUG
2484 printf("%s: tx%d: pad/FLUSH dma %d bytes (%d left, cur now 0x%x)\n",
2485 sc->sc_dev.dv_xname, chan, pad, need, cur);
2486#endif
2487 }
2488
2489 /* copy data */
2490 pad = need / sizeof(u_int32_t); /* round *down* */
2491 if (l->aal == MID_TBD_AAL5)
2492 pad -= 2;
2493#ifdef EN_DEBUG
2494 printf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2495 sc->sc_dev.dv_xname, chan, pad * sizeof(u_int32_t), cur);
2496#endif
2497 while (pad--) {
2498 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2499 EN_WRAPADD(start, stop, cur, 4);
2500 }
2501 if (l->aal == MID_TBD_AAL5) {
2502 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2503 EN_WRAPADD(start, stop, cur, 8);
2504 }
2505 }
2506
2507 if (addtail || dma != cur) {
2508 /* write final descritor */
2509 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2510 l->mlen, MID_DMA_END);
2511 /* dma = cur; */ /* not necessary since we are done */
2512 }
2513
2514done:
2515 /* update current pointer */
2516 sc->txslot[chan].cur = cur;
2517#ifdef EN_DEBUG
2518 printf("%s: tx%d: DONE! cur now = 0x%x\n",
2519 sc->sc_dev.dv_xname, chan, cur);
2520#endif
2521
2522 return;
2523}
2524
2525
2526/*
2527 * interrupt handler
2528 */
2529
2530EN_INTR_TYPE en_intr(arg)
2531
2532void *arg;
2533
2534{
2535 struct en_softc *sc = (struct en_softc *) arg;
2536 struct mbuf *m;
2537 struct atm_pseudohdr ah;
2538 struct ifnet *ifp;
2539 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2540 int lcv, idx, need_softserv = 0;
2541
2542 reg = EN_READ(sc, MID_INTACK);
2543
2544 if ((reg & MID_INT_ANY) == 0)
2545 EN_INTR_RET(0); /* not us */
2546
2547#ifdef EN_DEBUG
2548 printf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
2549#endif
2550
2551 /*
2552 * unexpected errors that need a reset
2553 */
2554
2555 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2556 printf("%s: unexpected interrupt=0x%b, resetting card\n",
2557 sc->sc_dev.dv_xname, reg, MID_INTBITS);
2558#ifdef EN_DEBUG
2559#ifdef DDB
2560#ifdef __FreeBSD__
2561 Debugger("en: unexpected error");
2562#else
2563 Debugger();
2564#endif
2565#endif /* DDB */
2566 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2567#else
2568 en_reset(sc);
2569 en_init(sc);
2570#endif
2571 EN_INTR_RET(1); /* for us */
2572 }
2573
2574 /*******************
2575 * xmit interrupts *
2576 ******************/
2577
2578 kick = 0; /* bitmask of channels to kick */
2579 if (reg & MID_INT_TX) { /* TX done! */
2580
2581 /*
2582 * check for tx complete, if detected then this means that some space
2583 * has come free on the card. we must account for it and arrange to
2584 * kick the channel to life (in case it is stalled waiting on the card).
2585 */
2586 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2587 if (reg & MID_TXCHAN(lcv)) {
2588 kick = kick | mask; /* want to kick later */
2589 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2590 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2591 /* convert to offset */
2592 if (val > sc->txslot[lcv].cur)
2593 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2594 else
2595 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2596#ifdef EN_DEBUG
2597 printf("%s: tx%d: trasmit done. %d bytes now free in buffer\n",
2598 sc->sc_dev.dv_xname, lcv, sc->txslot[lcv].bfree);
2599#endif
2600 }
2601 }
2602 }
2603
2604 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2605
2606 /*
2607 * check for TX DMA complete, if detected then this means that some DTQs
2608 * are now free. it also means some indma mbufs can be freed.
2609 * if we needed DTQs, kick all channels.
2610 */
2611 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2612 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2613 if (sc->need_dtqs) {
2614 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2615 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2616#ifdef EN_DEBUG
2617 printf("%s: cleared need DTQ condition\n", sc->sc_dev.dv_xname);
2618#endif
2619 }
2620 while (idx != val) {
2621 sc->dtq_free++;
2622 if ((dtq = sc->dtq[idx]) != 0) {
2623 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2624 slot = EN_DQ_SLOT(dtq);
2625 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2626 if (!m) panic("enintr: dtqsync");
2627 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2628#ifdef EN_DEBUG
2629 printf("%s: tx%d: free %d dma bytes, mbsize now %d\n",
2630 sc->sc_dev.dv_xname, slot, EN_DQ_LEN(dtq),
2631 sc->txslot[slot].mbsize);
2632#endif
2633 m_freem(m);
2634 }
2635 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2636 };
2637 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2638 }
2639
2640
2641 /*
2642 * kick xmit channels as needed
2643 */
2644
2645 if (kick) {
2646#ifdef EN_DEBUG
2647 printf("%s: tx kick mask = 0x%x\n", sc->sc_dev.dv_xname, kick);
2648#endif
2649 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2650 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2651 en_txdma(sc, lcv); /* kick it! */
2652 }
2653 } /* for each slot */
2654 } /* if kick */
2655
2656
2657 /*******************
2658 * recv interrupts *
2659 ******************/
2660
2661 /*
2662 * check for RX DMA complete, and pass the data "upstairs"
2663 */
2664
2665 if (reg & MID_INT_DMA_RX) {
2666 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2667 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2668 while (idx != val) {
2669 sc->drq_free++;
2670 if ((drq = sc->drq[idx]) != 0) {
2671 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2672 slot = EN_DQ_SLOT(drq);
2673 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2674 m = NULL;
2675 } else {
2676 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2677 if (!m)
2678 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2679 sc->sc_dev.dv_xname, slot);
2680 }
2681 /* do something with this mbuf */
2682 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2683 if (m)
2684 m_freem(m);
2685 vci = sc->rxslot[slot].atm_vci;
2686 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2687 sc->rxslot[slot].q.ifq_head == NULL &&
2688 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2689 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2690 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2691 sc->rxslot[slot].atm_vci = RX_NONE;
2692 sc->rxvc2slot[vci] = RX_NONE;
2693#ifdef EN_DEBUG
2694 printf("%s: rx%d: VCI %d now free\n", sc->sc_dev.dv_xname,
2695 slot, vci);
2696#endif
2697 }
2698 } else if (m != NULL) {
2699 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2700 ATM_PH_VPI(&ah) = 0;
2701 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2702#ifdef EN_DEBUG
2703 printf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2704 sc->sc_dev.dv_xname, slot, sc->rxslot[slot].atm_vci, m,
2705 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2706#endif
2707
2708 ifp = &sc->enif;
2709 ifp->if_ipackets++;
2710
2711#if NBPF > 0
2712 if (ifp->if_bpf)
2713 BPF_MTAP(ifp, m);
2714#endif
2715
2716 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2717 }
2718
2719 }
2720 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2721 };
2722 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2723
2724 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2725 need_softserv = 1;
2726 sc->need_drqs = 0;
2727#ifdef EN_DEBUG
2728 printf("%s: cleared need DRQ condition\n", sc->sc_dev.dv_xname);
2729#endif
2730 }
2731 }
2732
2733 /*
2734 * handle service interrupts
2735 */
2736
2737 if (reg & MID_INT_SERVICE) {
2738 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2739
2740 while (sc->hwslistp != chip) {
2741
2742 /* fetch and remove it from hardware service list */
2743 vci = EN_READ(sc, sc->hwslistp);
2744 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2745 slot = sc->rxvc2slot[vci];
2746 if (slot == RX_NONE) {
2747#ifdef EN_DEBUG
2748 printf("%s: unexpected rx interrupt on VCI %d\n",
2749 sc->sc_dev.dv_xname, vci);
2750#endif
2751 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2752 continue; /* next */
2753 }
2754 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2755 EN_COUNT(sc->hwpull);
2756
2757#ifdef EN_DEBUG
2758 printf("%s: pulled VCI %d off hwslist\n", sc->sc_dev.dv_xname, vci);
2759#endif
2760
2761 /* add it to the software service list (if needed) */
2762 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2763 EN_COUNT(sc->swadd);
2764 need_softserv = 1;
2765 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2766 sc->swslist[sc->swsl_tail] = slot;
2767 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2768 sc->swsl_size++;
2769#ifdef EN_DEBUG
2770 printf("%s: added VCI %d to swslist\n", sc->sc_dev.dv_xname, vci);
2771#endif
2772 }
2773 };
2774 }
2775
2776 /*
2777 * now service (function too big to include here)
2778 */
2779
2780 if (need_softserv)
2781 en_service(sc);
2782
2783 /*
2784 * keep our stats
2785 */
2786
2787 if (reg & MID_INT_DMA_OVR) {
2788 EN_COUNT(sc->dmaovr);
2789#ifdef EN_DEBUG
2790 printf("%s: MID_INT_DMA_OVR\n", sc->sc_dev.dv_xname);
2791#endif
2792 }
2793 reg = EN_READ(sc, MID_STAT);
2794#ifdef EN_STAT
2795 sc->otrash += MID_OTRASH(reg);
2796 sc->vtrash += MID_VTRASH(reg);
2797#endif
2798
2799 EN_INTR_RET(1); /* for us */
2800}
2801
2802
2803/*
2804 * en_service: handle a service interrupt
2805 *
2806 * Q: why do we need a software service list?
2807 *
2808 * A: if we remove a VCI from the hardware list and we find that we are
2809 * out of DRQs we must defer processing until some DRQs become free.
2810 * so we must remember to look at this RX VCI/slot later, but we can't
2811 * put it back on the hardware service list (since that isn't allowed).
2812 * so we instead save it on the software service list. it would be nice
2813 * if we could peek at the VCI on top of the hwservice list without removing
2814 * it, however this leads to a race condition: if we peek at it and
2815 * decide we are done with it new data could come in before we have a
2816 * chance to remove it from the hwslist. by the time we get it out of
2817 * the list the interrupt for the new data will be lost. oops!
2818 *
2819 */
2820
2821STATIC void en_service(sc)
2822
2823struct en_softc *sc;
2824
2825{
2826 struct mbuf *m, *tmp;
2827 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2828 u_int32_t start, stop, cnt, needalign;
2829 int slot, raw, aal5, llc, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2830
2831 aal5 = 0; /* Silence gcc */
2832next_vci:
2833 if (sc->swsl_size == 0) {
2834#ifdef EN_DEBUG
2835 printf("%s: en_service done\n", sc->sc_dev.dv_xname);
2836#endif
2837 return; /* >>> exit here if swsl now empty <<< */
2838 }
2839
2840 /*
2841 * get slot/vci to service
2842 */
2843
2844 slot = sc->swslist[sc->swsl_head];
2845 vci = sc->rxslot[slot].atm_vci;
2846#ifdef EN_DIAG
2847 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2848#endif
2849
2850 /*
2851 * determine our mode and if we've got any work to do
2852 */
2853
2854 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2855 start= sc->rxslot[slot].start;
2856 stop= sc->rxslot[slot].stop;
2857 cur = sc->rxslot[slot].cur;
2858
2859#ifdef EN_DEBUG
2860 printf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2861 sc->sc_dev.dv_xname, slot, vci, raw, start, stop, cur);
2862#endif
2863
2864same_vci:
2865 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2866 dstart = (dstart * sizeof(u_int32_t)) + start;
2867
2868 /* check to see if there is any data at all */
2869 if (dstart == cur) {
2870defer: /* defer processing */
2871 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2872 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2873 sc->swsl_size--;
2874 /* >>> remove from swslist <<< */
2875#ifdef EN_DEBUG
2876 printf("%s: rx%d: remove vci %d from swslist\n",
2877 sc->sc_dev.dv_xname, slot, vci);
2878#endif
2879 goto next_vci;
2880 }
2881
2882 /*
2883 * figure out how many bytes we need
2884 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2885 */
2886
2887 if (raw) {
2888
2889 /* raw mode (aka boodi mode) */
2890 fill = 0;
2891 if (dstart > cur)
2892 mlen = dstart - cur;
2893 else
2894 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2895
2896 if (mlen < sc->rxslot[slot].raw_threshold)
2897 goto defer; /* too little data to deal with */
2898
2899 } else {
2900
2901 /* normal mode */
2902 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2903 llc = (aal5 && (sc->rxslot[slot].atm_flags & ATM_PH_LLCSNAP)) ? 1 : 0;
2904 rbd = EN_READ(sc, cur);
2905 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2906 panic("en_service: id mismatch");
2907
2908 if (rbd & MID_RBD_T) {
2909 mlen = 0; /* we've got trash */
2910 fill = MID_RBD_SIZE;
2911 EN_COUNT(sc->ttrash);
2912#ifdef EN_DEBUG
2913 printf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2914#endif
2915 } else if (!aal5) {
2916 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2917 fill = 0;
2918 } else {
2919 struct ifnet *ifp;
2920
2921 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2922 pdu = cur + tlen - MID_PDU_SIZE;
2923 if (pdu >= stop)
2924 pdu -= (EN_RXSZ*1024);
2925 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
2926 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
2927 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
2928 static int first = 1;
2929
2930 if (first) {
2931 printf("%s: %s, dropping frame\n", sc->sc_dev.dv_xname,
2932 (rbd & MID_RBD_CRCERR) ?
2933 "CRC error" : "invalid AAL5 PDU length");
2934 printf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
2935 sc->sc_dev.dv_xname, MID_RBD_CNT(rbd),
2936 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
2937#ifndef EN_DEBUG
2938 printf("CRC error report disabled from now on!\n");
2939 first = 0;
2940#endif
2941 }
2942 fill = tlen;
2943
2944 ifp = &sc->enif;
2945 ifp->if_ierrors++;
2946
2947 }
2948 mlen = tlen - fill;
2949 }
2950
2951 }
2952
2953 /*
2954 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2955 *
2956 * notes:
2957 * 1. it is possible that we've already allocated an mbuf for this pkt
2958 * but ran out of DRQs, in which case we saved the allocated mbuf on
2959 * "q".
2960 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
2961 * of the mbuf as an identity (that we can check later), and we also
2962 * store drqneed (so we don't have to recompute it).
2963 * 3. after this block of code, if m is still NULL then we ran out of mbufs
2964 */
2965
2966 m = sc->rxslot[slot].q.ifq_head;
2967 drqneed = 1;
2968 if (m) {
2969 sav = mtod(m, u_int32_t *);
2970 if (sav[0] != cur) {
2971#ifdef EN_DEBUG
2972 printf("%s: rx%d: q'ed mbuf %p not ours\n",
2973 sc->sc_dev.dv_xname, slot, m);
2974#endif
2975 m = NULL; /* wasn't ours */
2976 EN_COUNT(sc->rxqnotus);
2977 } else {
2978 EN_COUNT(sc->rxqus);
2979 IF_DEQUEUE(&sc->rxslot[slot].q, m);
2980 drqneed = sav[1];
2981#ifdef EN_DEBUG
2982 printf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
2983 sc->sc_dev.dv_xname, slot, m, drqneed);
2984#endif
2985 }
2986 }
2987
2988 if (mlen != 0 && m == NULL) {
2989 m = en_mget(sc, mlen, &drqneed); /* allocate! */
2990 if (m == NULL) {
2991 fill += mlen;
2992 mlen = 0;
2993 EN_COUNT(sc->rxmbufout);
2994#ifdef EN_DEBUG
2995 printf("%s: rx%d: out of mbufs\n", sc->sc_dev.dv_xname, slot);
2996#endif
2997 }
2998#ifdef EN_DEBUG
2999 printf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
3000 sc->sc_dev.dv_xname, slot, m, mlen, drqneed);
3001#endif
3002 }
3003
3004#ifdef EN_DEBUG
3005 printf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
3006 sc->sc_dev.dv_xname, slot, vci, m, mlen, fill);
3007#endif
3008
3009 /*
3010 * now check to see if we've got the DRQs needed. if we are out of
3011 * DRQs we must quit (saving our mbuf, if we've got one).
3012 */
3013
3014 needfill = (fill) ? 1 : 0;
3015 if (drqneed + needfill > sc->drq_free) {
3016 sc->need_drqs = 1; /* flag condition */
3017 if (m == NULL) {
3018 EN_COUNT(sc->rxoutboth);
3019#ifdef EN_DEBUG
3020 printf("%s: rx%d: out of DRQs *and* mbufs!\n", sc->sc_dev.dv_xname, slot);
3021#endif
3022 return; /* >>> exit here if out of both mbufs and DRQs <<< */
3023 }
3024 sav = mtod(m, u_int32_t *);
3025 sav[0] = cur;
3026 sav[1] = drqneed;
3027 IF_ENQUEUE(&sc->rxslot[slot].q, m);
3028 EN_COUNT(sc->rxdrqout);
3029#ifdef EN_DEBUG
3030 printf("%s: rx%d: out of DRQs\n", sc->sc_dev.dv_xname, slot);
3031#endif
3032 return; /* >>> exit here if out of DRQs <<< */
3033 }
3034
3035 /*
3036 * at this point all resources have been allocated and we are commited
3037 * to servicing this slot.
3038 *
3039 * dma = last location we told chip about
3040 * cur = current location
3041 * mlen = space in the mbuf we want
3042 * need = bytes to xfer in (decrs to zero)
3043 * fill = how much fill we need
3044 * tlen = how much data to transfer to this mbuf
3045 * cnt/bcode/count = <same as xmit>
3046 *
3047 * 'needfill' not used after this point
3048 */
3049
3050 dma = cur; /* dma = last location we told chip about */
3051 need = roundup(mlen, sizeof(u_int32_t));
3052 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
3053
3054 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
3055 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
3056 data = mtod(tmp, u_int32_t *);
3057
3058#ifdef EN_DEBUG
3059 printf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
3060 sc->sc_dev.dv_xname, slot, tmp, tmp->m_len, tmp->m_data, tlen);
3061#endif
3062
3063 /* copy data */
3064 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
3065 datastop = (u_int32_t *)((u_char *) data + tlen);
3066 /* copy loop: preserve byte order!!! use READDAT */
3067 while (data != datastop) {
3068 *data = EN_READDAT(sc, cur);
3069 data++;
3070 EN_WRAPADD(start, stop, cur, 4);
3071 }
3072 need -= tlen;
3073#ifdef EN_DEBUG
3074 printf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
3075 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3076#endif
3077 continue;
3078 }
3079
3080 /* DMA data (check to see if we need to sync DRQ first) */
3081 if (dma != cur) {
3082 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
3083#ifdef EN_DEBUG
3084 printf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
3085 sc->sc_dev.dv_xname, slot, vci, cur);
3086#endif
3087 }
3088
3089#if !defined(MIDWAY_ENIONLY)
3090
3091 /*
3092 * the adaptec DMA engine is smart and handles everything for us.
3093 */
3094
3095 if (sc->is_adaptec) {
3096 need -= tlen;
3097 EN_WRAPADD(start, stop, cur, tlen);
3098#ifdef EN_DEBUG
3099 printf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
3100 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3101#endif
3102 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3103 EN_DRQADD(sc, tlen, vci, 0, vtophys(data), mlen, slot, end);
3104 if (end)
3105 goto done;
3106 dma = cur; /* update dma pointer */
3107 continue;
3108 }
3109#endif /* !MIDWAY_ENIONLY */
3110
3111
3112#if !defined(MIDWAY_ADPONLY)
3113
3114 /*
3115 * the ENI DMA engine is not so smart and need more help from us
3116 */
3117
3118 /* do we need to do a DMA op to align? */
3119 if (sc->alburst &&
3120 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0) {
3121 cnt = sc->bestburstlen - needalign;
3122 if (cnt > tlen) {
3123 cnt = tlen;
3124 count = cnt / sizeof(u_int32_t);
3125 bcode = MIDDMA_WORD;
3126 } else {
3127 count = cnt / sizeof(u_int32_t);
3128 bcode = en_dmaplan[count].bcode;
3129 count = cnt >> en_dmaplan[count].divshift;
3130 }
3131 need -= cnt;
3132 EN_WRAPADD(start, stop, cur, cnt);
3133#ifdef EN_DEBUG
3134 printf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
3135 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3136#endif
3137 tlen -= cnt;
3138 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3139 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3140 if (end)
3141 goto done;
3142 data = (u_int32_t *)((u_char *) data + cnt);
3143 }
3144
3145 /* do we need a max-sized burst? */
3146 if (tlen >= sc->bestburstlen) {
3147 count = tlen >> sc->bestburstshift;
3148 cnt = count << sc->bestburstshift;
3149 bcode = sc->bestburstcode;
3150 need -= cnt;
3151 EN_WRAPADD(start, stop, cur, cnt);
3152#ifdef EN_DEBUG
3153 printf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
3154 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3155#endif
3156 tlen -= cnt;
3157 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3158 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3159 if (end)
3160 goto done;
3161 data = (u_int32_t *)((u_char *) data + cnt);
3162 }
3163
3164 /* do we need to do a cleanup burst? */
3165 if (tlen) {
3166 count = tlen / sizeof(u_int32_t);
3167 bcode = en_dmaplan[count].bcode;
3168 count = tlen >> en_dmaplan[count].divshift;
3169 need -= tlen;
3170 EN_WRAPADD(start, stop, cur, tlen);
3171#ifdef EN_DEBUG
3172 printf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
3173 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3174#endif
3175 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3176 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3177 if (end)
3178 goto done;
3179 }
3180
3181 dma = cur; /* update dma pointer */
3182
3183#endif /* !MIDWAY_ADPONLY */
3184
3185 }
3186
3187 /* skip the end */
3188 if (fill || dma != cur) {
3189#ifdef EN_DEBUG
3190 if (fill)
3191 printf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
3192 sc->sc_dev.dv_xname, slot, vci, fill);
3193 else
3194 printf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
3195 sc->sc_dev.dv_xname, slot, vci, dma, cur);
3196#endif
3197 EN_WRAPADD(start, stop, cur, fill);
3198 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3199 slot, MID_DMA_END);
3200 /* dma = cur; */ /* not necessary since we are done */
3201 }
3202
3203 /*
3204 * done, remove stuff we don't want to pass up:
3205 * raw mode (boodi mode): pass everything up for later processing
3206 * aal5: remove RBD
3207 * aal0: remove RBD + cell header
3208 */
3209
3210done:
3211 if (m) {
3212 if (!raw) {
3213 cnt = MID_RBD_SIZE;
3214 if (!aal5) cnt += MID_CHDR_SIZE;
3215 m->m_len -= cnt; /* chop! */
3216 m->m_pkthdr.len -= cnt;
3217 m->m_data += cnt;
3218 }
3219 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3220 }
3221 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3222
3223#ifdef EN_DEBUG
3224 printf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3225 sc->sc_dev.dv_xname, slot, vci, cur);
3226#endif
3227
3228 goto same_vci; /* get next packet in this slot */
3229}
3230
3231
3232#ifdef EN_DDBHOOK
3233/*
3234 * functions we can call from ddb
3235 */
3236
3237/*
3238 * en_dump: dump the state
3239 */
3240
3241#define END_SWSL 0x00000040 /* swsl state */
3242#define END_DRQ 0x00000020 /* drq state */
3243#define END_DTQ 0x00000010 /* dtq state */
3244#define END_RX 0x00000008 /* rx state */
3245#define END_TX 0x00000004 /* tx state */
3246#define END_MREGS 0x00000002 /* registers */
3247#define END_STATS 0x00000001 /* dump stats */
3248
3249#define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3250
3251/* Do not staticize - meant for calling from DDB! */
3252int en_dump(unit, level)
3253
3254int unit, level;
3255
3256{
3257 struct en_softc *sc;
3258 int lcv, cnt, slot;
3259 u_int32_t ptr, reg;
3260
3261 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3262 sc = (struct en_softc *) en_cd.cd_devs[lcv];
3263 if (sc == NULL) continue;
3264 if (unit != -1 && unit != lcv)
3265 continue;
3266
3267 printf("dumping device %s at level 0x%b\n", sc->sc_dev.dv_xname, level,
3268 END_BITS);
3269
3270 if (sc->dtq_us == 0) {
3271 printf("<hasn't been en_init'd yet>\n");
3272 continue;
3273 }
3274
3275 if (level & END_STATS) {
3276 printf(" en_stats:\n");
3277 printf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3278 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3279 printf(" %d rx dma overflow interrupts\n", sc->dmaovr);
3280 printf(" %d times we ran out of TX space and stalled\n",
3281 sc->txoutspace);
3282 printf(" %d times we ran out of DTQs\n", sc->txdtqout);
3283 printf(" %d times we launched a packet\n", sc->launch);
3284 printf(" %d times we launched without on-board header\n", sc->lheader);
3285 printf(" %d times we launched without on-board tail\n", sc->ltail);
3286 printf(" %d times we pulled the hw service list\n", sc->hwpull);
3287 printf(" %d times we pushed a vci on the sw service list\n",
3288 sc->swadd);
3289 printf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3290 sc->rxqnotus);
3291 printf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3292 printf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3293 printf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3294
3295 printf(" %d trasmit packets dropped due to mbsize\n", sc->txmbovr);
3296 printf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3297 printf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3298 printf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3299 printf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
3300#ifdef NATM
3301 printf(" %d drops at natmintrq\n", natmintrq.ifq_drops);
3302#ifdef NATM_STAT
3303 printf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3304 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3305#endif
3306#endif
3307 }
3308
3309 if (level & END_MREGS) {
3310 printf("mregs:\n");
3311 printf("resid = 0x%lx\n", (u_long)EN_READ(sc, MID_RESID));
3312 printf("interrupt status = 0x%b\n",
3313 (int)EN_READ(sc, MID_INTSTAT), MID_INTBITS);
3314 printf("interrupt enable = 0x%b\n",
3315 (int)EN_READ(sc, MID_INTENA), MID_INTBITS);
3316 printf("mcsr = 0x%b\n", (int)EN_READ(sc, MID_MAST_CSR), MID_MCSRBITS);
3317 printf("serv_write = [chip=%ld] [us=%d]\n",
3318 (long)EN_READ(sc, MID_SERV_WRITE),
3319 MID_SL_A2REG(sc->hwslistp));
3320 printf("dma addr = 0x%lx\n", (u_long)EN_READ(sc, MID_DMA_ADDR));
3321 printf("DRQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3322 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3323 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)),
3324 sc->drq_chip, sc->drq_us);
3325 printf("DTQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3326 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3327 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)),
3328 sc->dtq_chip, sc->dtq_us);
3329
3330 printf(" unusal txspeeds: ");
3331 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3332 if (sc->txspeed[cnt])
3333 printf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3334 printf("\n");
3335
3336 printf(" rxvc slot mappings: ");
3337 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3338 if (sc->rxvc2slot[cnt] != RX_NONE)
3339 printf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3340 printf("\n");
3341
3342 }
3343
3344 if (level & END_TX) {
3345 printf("tx:\n");
3346 for (slot = 0 ; slot < EN_NTX; slot++) {
3347 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3348 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3349 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3350 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3351 sc->txslot[slot].bfree);
3352 printf("txhw: base_address=0x%lx, size=%ld, read=%ld, descstart=%ld\n",
3353 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3354 (u_long)MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3355 (long)EN_READ(sc, MIDX_READPTR(slot)),
3356 (long)EN_READ(sc, MIDX_DESCSTART(slot)));
3357 }
3358 }
3359
3360 if (level & END_RX) {
3361 printf(" recv slots:\n");
3362 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3363 printf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3364 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3365 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3366 printf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3367 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3368 sc->rxslot[slot].oth_flags);
3369 printf("RXHW: mode=0x%lx, DST_RP=0x%lx, WP_ST_CNT=0x%lx\n",
3370 (u_long)EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3371 (u_long)EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3372 (u_long)EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3373 }
3374 }
3375
3376 if (level & END_DTQ) {
3377 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3378 sc->need_dtqs, sc->dtq_free);
3379 ptr = sc->dtq_chip;
3380 while (ptr != sc->dtq_us) {
3381 reg = EN_READ(sc, ptr);
3382 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3383 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3384 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3385 (u_long)EN_READ(sc, ptr+4));
3386 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3387 }
3388 }
3389
3390 if (level & END_DRQ) {
3391 printf(" drq [need_drqs=%d,drq_free=%d]:\n",
3392 sc->need_drqs, sc->drq_free);
3393 ptr = sc->drq_chip;
3394 while (ptr != sc->drq_us) {
3395 reg = EN_READ(sc, ptr);
3396 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3397 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3398 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3399 (u_long)EN_READ(sc, ptr+4));
3400 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3401 }
3402 }
3403
3404 if (level & END_SWSL) {
3405 printf(" swslist [size=%d]: ", sc->swsl_size);
3406 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3407 cnt = (cnt + 1) % MID_SL_N)
3408 printf("0x%x ", sc->swslist[cnt]);
3409 printf("\n");
3410 }
3411 }
3412 return(0);
3413}
3414
3415/*
3416 * en_dumpmem: dump the memory
3417 */
3418
3419/* Do not staticize - meant for calling from DDB! */
3420int en_dumpmem(unit, addr, len)
3421
3422int unit, addr, len;
3423
3424{
3425 struct en_softc *sc;
3426 u_int32_t reg;
3427
3428 if (unit < 0 || unit > en_cd.cd_ndevs ||
3429 (sc = (struct en_softc *) en_cd.cd_devs[unit]) == NULL) {
3430 printf("invalid unit number: %d\n", unit);
3431 return(0);
3432 }
3433 addr = addr & ~3;
3434 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3435 printf("invalid addr/len number: %d, %d\n", addr, len);
3436 return(0);
3437 }
3438 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3439 while (len--) {
3440 reg = EN_READ(sc, addr);
3441 printf("mem[0x%x] = 0x%x\n", addr, reg);
3442 addr += 4;
3443 }
3444 return(0);
3445}
3446#endif