Initial import from FreeBSD RELENG_4:
[dragonfly.git] / sys / i386 / i386 / identcpu.c
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984263bc
MD
1/*
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 */
43
44#include "opt_cpu.h"
45
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/kernel.h>
49#include <sys/sysctl.h>
50
51#include <machine/asmacros.h>
52#include <machine/clock.h>
53#include <machine/cputypes.h>
54#include <machine/segments.h>
55#include <machine/specialreg.h>
56#include <machine/md_var.h>
57
58#include <i386/isa/intr_machdep.h>
59
60#define IDENTBLUE_CYRIX486 0
61#define IDENTBLUE_IBMCPU 1
62#define IDENTBLUE_CYRIXM2 2
63
64/* XXX - should be in header file: */
65void printcpuinfo(void);
66void finishidentcpu(void);
67#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
68void enable_K5_wt_alloc(void);
69void enable_K6_wt_alloc(void);
70void enable_K6_2_wt_alloc(void);
71#endif
72void panicifcpuunsupported(void);
73
74static void identifycyrix(void);
75#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
76static void print_AMD_features(void);
77#endif
78static void print_AMD_info(void);
79static void print_AMD_assoc(int i);
80static void print_transmeta_info(void);
81static void setup_tmx86_longrun(void);
82
83int cpu_class = CPUCLASS_386;
84u_int cpu_exthigh; /* Highest arg to extended CPUID */
85u_int cyrix_did; /* Device ID of Cyrix CPU */
86char machine[] = "i386";
87SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
88 machine, 0, "Machine class");
89
90static char cpu_model[128];
91SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
92 cpu_model, 0, "Machine model");
93
94static char cpu_brand[48];
95
96#define MAX_BRAND_INDEX 8
97
98static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
99 NULL, /* No brand */
100 "Intel Celeron",
101 "Intel Pentium III",
102 "Intel Pentium III Xeon",
103 NULL,
104 NULL,
105 NULL,
106 NULL,
107 "Intel Pentium 4"
108};
109
110static struct cpu_nameclass i386_cpus[] = {
111 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
112 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
113 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
114 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
115 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
116 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
117 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
118 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
119 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
120 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
121 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
122 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
123 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
124 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
125 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
126 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
127 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
128};
129
130#if defined(I586_CPU) && !defined(NO_F00F_HACK)
131int has_f00f_bug = 0; /* Initialized so that it can be patched. */
132#endif
133
134void
135printcpuinfo(void)
136{
137#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
138 u_int regs[4], i;
139#endif
140 char *brand;
141
142 cpu_class = i386_cpus[cpu].cpu_class;
143 printf("CPU: ");
144 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
145
146#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
147 /* Check for extended CPUID information and a processor name. */
148 if (cpu_high > 0 &&
149 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
150 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
151 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
152 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
153 do_cpuid(0x80000000, regs);
154 if (regs[0] >= 0x80000000) {
155 cpu_exthigh = regs[0];
156 if (cpu_exthigh >= 0x80000004) {
157 brand = cpu_brand;
158 for (i = 0x80000002; i < 0x80000005; i++) {
159 do_cpuid(i, regs);
160 memcpy(brand, regs, sizeof(regs));
161 brand += sizeof(regs);
162 }
163 }
164 }
165 }
166
167 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
168 if ((cpu_id & 0xf00) > 0x300) {
169 u_int brand_index;
170
171 cpu_model[0] = '\0';
172
173 switch (cpu_id & 0x3000) {
174 case 0x1000:
175 strcpy(cpu_model, "Overdrive ");
176 break;
177 case 0x2000:
178 strcpy(cpu_model, "Dual ");
179 break;
180 }
181
182 switch (cpu_id & 0xf00) {
183 case 0x400:
184 strcat(cpu_model, "i486 ");
185 /* Check the particular flavor of 486 */
186 switch (cpu_id & 0xf0) {
187 case 0x00:
188 case 0x10:
189 strcat(cpu_model, "DX");
190 break;
191 case 0x20:
192 strcat(cpu_model, "SX");
193 break;
194 case 0x30:
195 strcat(cpu_model, "DX2");
196 break;
197 case 0x40:
198 strcat(cpu_model, "SL");
199 break;
200 case 0x50:
201 strcat(cpu_model, "SX2");
202 break;
203 case 0x70:
204 strcat(cpu_model,
205 "DX2 Write-Back Enhanced");
206 break;
207 case 0x80:
208 strcat(cpu_model, "DX4");
209 break;
210 }
211 break;
212 case 0x500:
213 /* Check the particular flavor of 586 */
214 strcat(cpu_model, "Pentium");
215 switch (cpu_id & 0xf0) {
216 case 0x00:
217 strcat(cpu_model, " A-step");
218 break;
219 case 0x10:
220 strcat(cpu_model, "/P5");
221 break;
222 case 0x20:
223 strcat(cpu_model, "/P54C");
224 break;
225 case 0x30:
226 strcat(cpu_model, "/P54T Overdrive");
227 break;
228 case 0x40:
229 strcat(cpu_model, "/P55C");
230 break;
231 case 0x70:
232 strcat(cpu_model, "/P54C");
233 break;
234 case 0x80:
235 strcat(cpu_model, "/P55C (quarter-micron)");
236 break;
237 default:
238 /* nothing */
239 break;
240 }
241#if defined(I586_CPU) && !defined(NO_F00F_HACK)
242 /*
243 * XXX - If/when Intel fixes the bug, this
244 * should also check the version of the
245 * CPU, not just that it's a Pentium.
246 */
247 has_f00f_bug = 1;
248#endif
249 break;
250 case 0x600:
251 /* Check the particular flavor of 686 */
252 switch (cpu_id & 0xf0) {
253 case 0x00:
254 strcat(cpu_model, "Pentium Pro A-step");
255 break;
256 case 0x10:
257 strcat(cpu_model, "Pentium Pro");
258 break;
259 case 0x30:
260 case 0x50:
261 case 0x60:
262 strcat(cpu_model,
263 "Pentium II/Pentium II Xeon/Celeron");
264 cpu = CPU_PII;
265 break;
266 case 0x70:
267 case 0x80:
268 case 0xa0:
269 case 0xb0:
270 strcat(cpu_model,
271 "Pentium III/Pentium III Xeon/Celeron");
272 cpu = CPU_PIII;
273 break;
274 default:
275 strcat(cpu_model, "Unknown 80686");
276 break;
277 }
278 break;
279 case 0xf00:
280 strcat(cpu_model, "Pentium 4");
281 cpu = CPU_P4;
282 break;
283 default:
284 strcat(cpu_model, "unknown");
285 break;
286 }
287
288 /*
289 * If we didn't get a brand name from the extended
290 * CPUID, try to look it up in the brand table.
291 */
292 if (cpu_high > 0 && *cpu_brand == '\0') {
293 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
294 if (brand_index <= MAX_BRAND_INDEX &&
295 cpu_brandtable[brand_index] != NULL)
296 strcpy(cpu_brand,
297 cpu_brandtable[brand_index]);
298 }
299 }
300 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
301 /*
302 * Values taken from AMD Processor Recognition
303 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
304 * (also describes ``Features'' encodings.
305 */
306 strcpy(cpu_model, "AMD ");
307 switch (cpu_id & 0xFF0) {
308 case 0x410:
309 strcat(cpu_model, "Standard Am486DX");
310 break;
311 case 0x430:
312 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
313 break;
314 case 0x470:
315 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
316 break;
317 case 0x480:
318 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
319 break;
320 case 0x490:
321 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
322 break;
323 case 0x4E0:
324 strcat(cpu_model, "Am5x86 Write-Through");
325 break;
326 case 0x4F0:
327 strcat(cpu_model, "Am5x86 Write-Back");
328 break;
329 case 0x500:
330 strcat(cpu_model, "K5 model 0");
331 tsc_is_broken = 1;
332 break;
333 case 0x510:
334 strcat(cpu_model, "K5 model 1");
335 break;
336 case 0x520:
337 strcat(cpu_model, "K5 PR166 (model 2)");
338 break;
339 case 0x530:
340 strcat(cpu_model, "K5 PR200 (model 3)");
341 break;
342 case 0x560:
343 strcat(cpu_model, "K6");
344 break;
345 case 0x570:
346 strcat(cpu_model, "K6 266 (model 1)");
347 break;
348 case 0x580:
349 strcat(cpu_model, "K6-2");
350 break;
351 case 0x590:
352 strcat(cpu_model, "K6-III");
353 break;
354 default:
355 strcat(cpu_model, "Unknown");
356 break;
357 }
358#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
359 if ((cpu_id & 0xf00) == 0x500) {
360 if (((cpu_id & 0x0f0) > 0)
361 && ((cpu_id & 0x0f0) < 0x60)
362 && ((cpu_id & 0x00f) > 3))
363 enable_K5_wt_alloc();
364 else if (((cpu_id & 0x0f0) > 0x80)
365 || (((cpu_id & 0x0f0) == 0x80)
366 && (cpu_id & 0x00f) > 0x07))
367 enable_K6_2_wt_alloc();
368 else if ((cpu_id & 0x0f0) > 0x50)
369 enable_K6_wt_alloc();
370 }
371#endif
372 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
373 strcpy(cpu_model, "Cyrix ");
374 switch (cpu_id & 0xff0) {
375 case 0x440:
376 strcat(cpu_model, "MediaGX");
377 break;
378 case 0x520:
379 strcat(cpu_model, "6x86");
380 break;
381 case 0x540:
382 cpu_class = CPUCLASS_586;
383 strcat(cpu_model, "GXm");
384 break;
385 case 0x600:
386 strcat(cpu_model, "6x86MX");
387 break;
388 default:
389 /*
390 * Even though CPU supports the cpuid
391 * instruction, it can be disabled.
392 * Therefore, this routine supports all Cyrix
393 * CPUs.
394 */
395 switch (cyrix_did & 0xf0) {
396 case 0x00:
397 switch (cyrix_did & 0x0f) {
398 case 0x00:
399 strcat(cpu_model, "486SLC");
400 break;
401 case 0x01:
402 strcat(cpu_model, "486DLC");
403 break;
404 case 0x02:
405 strcat(cpu_model, "486SLC2");
406 break;
407 case 0x03:
408 strcat(cpu_model, "486DLC2");
409 break;
410 case 0x04:
411 strcat(cpu_model, "486SRx");
412 break;
413 case 0x05:
414 strcat(cpu_model, "486DRx");
415 break;
416 case 0x06:
417 strcat(cpu_model, "486SRx2");
418 break;
419 case 0x07:
420 strcat(cpu_model, "486DRx2");
421 break;
422 case 0x08:
423 strcat(cpu_model, "486SRu");
424 break;
425 case 0x09:
426 strcat(cpu_model, "486DRu");
427 break;
428 case 0x0a:
429 strcat(cpu_model, "486SRu2");
430 break;
431 case 0x0b:
432 strcat(cpu_model, "486DRu2");
433 break;
434 default:
435 strcat(cpu_model, "Unknown");
436 break;
437 }
438 break;
439 case 0x10:
440 switch (cyrix_did & 0x0f) {
441 case 0x00:
442 strcat(cpu_model, "486S");
443 break;
444 case 0x01:
445 strcat(cpu_model, "486S2");
446 break;
447 case 0x02:
448 strcat(cpu_model, "486Se");
449 break;
450 case 0x03:
451 strcat(cpu_model, "486S2e");
452 break;
453 case 0x0a:
454 strcat(cpu_model, "486DX");
455 break;
456 case 0x0b:
457 strcat(cpu_model, "486DX2");
458 break;
459 case 0x0f:
460 strcat(cpu_model, "486DX4");
461 break;
462 default:
463 strcat(cpu_model, "Unknown");
464 break;
465 }
466 break;
467 case 0x20:
468 if ((cyrix_did & 0x0f) < 8)
469 strcat(cpu_model, "6x86"); /* Where did you get it? */
470 else
471 strcat(cpu_model, "5x86");
472 break;
473 case 0x30:
474 strcat(cpu_model, "6x86");
475 break;
476 case 0x40:
477 if ((cyrix_did & 0xf000) == 0x3000) {
478 cpu_class = CPUCLASS_586;
479 strcat(cpu_model, "GXm");
480 } else
481 strcat(cpu_model, "MediaGX");
482 break;
483 case 0x50:
484 strcat(cpu_model, "6x86MX");
485 break;
486 case 0xf0:
487 switch (cyrix_did & 0x0f) {
488 case 0x0d:
489 strcat(cpu_model, "Overdrive CPU");
490 case 0x0e:
491 strcpy(cpu_model, "Texas Instruments 486SXL");
492 break;
493 case 0x0f:
494 strcat(cpu_model, "486SLC/DLC");
495 break;
496 default:
497 strcat(cpu_model, "Unknown");
498 break;
499 }
500 break;
501 default:
502 strcat(cpu_model, "Unknown");
503 break;
504 }
505 break;
506 }
507 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
508 strcpy(cpu_model, "Rise ");
509 switch (cpu_id & 0xff0) {
510 case 0x500:
511 strcat(cpu_model, "mP6");
512 break;
513 default:
514 strcat(cpu_model, "Unknown");
515 }
516 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
517 switch (cpu_id & 0xff0) {
518 case 0x540:
519 strcpy(cpu_model, "IDT WinChip C6");
520 tsc_is_broken = 1;
521 break;
522 case 0x580:
523 strcpy(cpu_model, "IDT WinChip 2");
524 break;
525 case 0x670:
526 strcpy(cpu_model, "VIA C3 Samuel 2");
527 break;
528 default:
529 strcpy(cpu_model, "VIA/IDT Unknown");
530 }
531 } else if (strcmp(cpu_vendor, "IBM") == 0) {
532 strcpy(cpu_model, "Blue Lightning CPU");
533 }
534
535 /*
536 * Replace cpu_model with cpu_brand minus leading spaces if
537 * we have one.
538 */
539 brand = cpu_brand;
540 while (*brand == ' ')
541 ++brand;
542 if (*brand != '\0')
543 strcpy(cpu_model, brand);
544
545#endif
546
547 printf("%s (", cpu_model);
548 switch(cpu_class) {
549 case CPUCLASS_286:
550 printf("286");
551 break;
552#if defined(I386_CPU)
553 case CPUCLASS_386:
554 printf("386");
555 break;
556#endif
557#if defined(I486_CPU)
558 case CPUCLASS_486:
559 printf("486");
560 bzero = i486_bzero;
561 break;
562#endif
563#if defined(I586_CPU)
564 case CPUCLASS_586:
565 printf("%d.%02d-MHz ",
566 (tsc_freq + 4999) / 1000000,
567 ((tsc_freq + 4999) / 10000) % 100);
568 printf("586");
569 break;
570#endif
571#if defined(I686_CPU)
572 case CPUCLASS_686:
573 printf("%d.%02d-MHz ",
574 (tsc_freq + 4999) / 1000000,
575 ((tsc_freq + 4999) / 10000) % 100);
576 printf("686");
577 break;
578#endif
579 default:
580 printf("Unknown"); /* will panic below... */
581 }
582 printf("-class CPU)\n");
583#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
584 if(*cpu_vendor)
585 printf(" Origin = \"%s\"",cpu_vendor);
586 if(cpu_id)
587 printf(" Id = 0x%x", cpu_id);
588
589 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
590 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
591 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
592 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
593 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
594 ((cpu_id & 0xf00) > 0x500))) {
595 printf(" Stepping = %u", cpu_id & 0xf);
596 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
597 printf(" DIR=0x%04x", cyrix_did);
598 if (cpu_high > 0) {
599 /*
600 * Here we should probably set up flags indicating
601 * whether or not various features are available.
602 * The interesting ones are probably VME, PSE, PAE,
603 * and PGE. The code already assumes without bothering
604 * to check that all CPUs >= Pentium have a TSC and
605 * MSRs.
606 */
607 printf("\n Features=0x%b", cpu_feature,
608 "\020"
609 "\001FPU" /* Integral FPU */
610 "\002VME" /* Extended VM86 mode support */
611 "\003DE" /* Debugging Extensions (CR4.DE) */
612 "\004PSE" /* 4MByte page tables */
613 "\005TSC" /* Timestamp counter */
614 "\006MSR" /* Machine specific registers */
615 "\007PAE" /* Physical address extension */
616 "\010MCE" /* Machine Check support */
617 "\011CX8" /* CMPEXCH8 instruction */
618 "\012APIC" /* SMP local APIC */
619 "\013oldMTRR" /* Previous implementation of MTRR */
620 "\014SEP" /* Fast System Call */
621 "\015MTRR" /* Memory Type Range Registers */
622 "\016PGE" /* PG_G (global bit) support */
623 "\017MCA" /* Machine Check Architecture */
624 "\020CMOV" /* CMOV instruction */
625 "\021PAT" /* Page attributes table */
626 "\022PSE36" /* 36 bit address space support */
627 "\023PN" /* Processor Serial number */
628 "\024CLFLUSH" /* Has the CLFLUSH instruction */
629 "\025<b20>"
630 "\026DTS" /* Debug Trace Store */
631 "\027ACPI" /* ACPI support */
632 "\030MMX" /* MMX instructions */
633 "\031FXSR" /* FXSAVE/FXRSTOR */
634 "\032SSE" /* Streaming SIMD Extensions */
635 "\033SSE2" /* Streaming SIMD Extensions #2 */
636 "\034SS" /* Self snoop */
637 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
638 "\036TM" /* Thermal Monitor clock slowdown */
639 "\037IA64" /* CPU can execute IA64 instructions */
640 "\040PBE" /* Pending Break Enable */
641 );
642
643 /*
644 * If this CPU supports hyperthreading then mention
645 * the number of logical CPU's it contains.
646 */
647 if (cpu_feature & CPUID_HTT &&
648 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
649 printf("\n Hyperthreading: %d logical CPUs",
650 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
651 }
652 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
653 cpu_exthigh >= 0x80000001)
654 print_AMD_features();
655 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
656 printf(" DIR=0x%04x", cyrix_did);
657 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
658 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
659#ifndef CYRIX_CACHE_REALLY_WORKS
660 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
661 printf("\n CPU cache: write-through mode");
662#endif
663 }
664 /* Avoid ugly blank lines: only print newline when we have to. */
665 if (*cpu_vendor || cpu_id)
666 printf("\n");
667
668#endif
669 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
670 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
671 setup_tmx86_longrun();
672 }
673
674 if (!bootverbose)
675 return;
676
677 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
678 print_AMD_info();
679 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
680 strcmp(cpu_vendor, "TransmetaCPU") == 0)
681 print_transmeta_info();
682
683#ifdef I686_CPU
684 /*
685 * XXX - Do PPro CPUID level=2 stuff here?
686 *
687 * No, but maybe in a print_Intel_info() function called from here.
688 */
689#endif
690}
691
692void
693panicifcpuunsupported(void)
694{
695
696#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
697#error This kernel is not configured for one of the supported CPUs
698#endif
699 /*
700 * Now that we have told the user what they have,
701 * let them know if that machine type isn't configured.
702 */
703 switch (cpu_class) {
704 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
705#if !defined(I386_CPU)
706 case CPUCLASS_386:
707#endif
708#if !defined(I486_CPU)
709 case CPUCLASS_486:
710#endif
711#if !defined(I586_CPU)
712 case CPUCLASS_586:
713#endif
714#if !defined(I686_CPU)
715 case CPUCLASS_686:
716#endif
717 panic("CPU class not configured");
718 default:
719 break;
720 }
721}
722
723
724static volatile u_int trap_by_rdmsr;
725
726/*
727 * Special exception 6 handler.
728 * The rdmsr instruction generates invalid opcodes fault on 486-class
729 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
730 * function identblue() when this handler is called. Stacked eip should
731 * be advanced.
732 */
733inthand_t bluetrap6;
734__asm
735("
736 .text
737 .p2align 2,0x90
738 .type " __XSTRING(CNAME(bluetrap6)) ",@function
739" __XSTRING(CNAME(bluetrap6)) ":
740 ss
741 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "
742 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
743 iret
744");
745
746/*
747 * Special exception 13 handler.
748 * Accessing non-existent MSR generates general protection fault.
749 */
750inthand_t bluetrap13;
751__asm
752("
753 .text
754 .p2align 2,0x90
755 .type " __XSTRING(CNAME(bluetrap13)) ",@function
756" __XSTRING(CNAME(bluetrap13)) ":
757 ss
758 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "
759 popl %eax # discard errorcode.
760 addl $2, (%esp) # I know rdmsr is a 2-bytes instruction.
761 iret
762");
763
764/*
765 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
766 * support cpuid instruction. This function should be called after
767 * loading interrupt descriptor table register.
768 *
769 * I don't like this method that handles fault, but I couldn't get
770 * information for any other methods. Does blue giant know?
771 */
772static int
773identblue(void)
774{
775
776 trap_by_rdmsr = 0;
777
778 /*
779 * Cyrix 486-class CPU does not support rdmsr instruction.
780 * The rdmsr instruction generates invalid opcode fault, and exception
781 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
782 * bluetrap6() set the magic number to trap_by_rdmsr.
783 */
784 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
785
786 /*
787 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
788 * In this case, rdmsr generates general protection fault, and
789 * exception will be trapped by bluetrap13().
790 */
791 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
792
793 rdmsr(0x1002); /* Cyrix CPU generates fault. */
794
795 if (trap_by_rdmsr == 0xa8c1d)
796 return IDENTBLUE_CYRIX486;
797 else if (trap_by_rdmsr == 0xa89c4)
798 return IDENTBLUE_CYRIXM2;
799 return IDENTBLUE_IBMCPU;
800}
801
802
803/*
804 * identifycyrix() set lower 16 bits of cyrix_did as follows:
805 *
806 * F E D C B A 9 8 7 6 5 4 3 2 1 0
807 * +-------+-------+---------------+
808 * | SID | RID | Device ID |
809 * | (DIR 1) | (DIR 0) |
810 * +-------+-------+---------------+
811 */
812static void
813identifycyrix(void)
814{
815 u_int eflags;
816 int ccr2_test = 0, dir_test = 0;
817 u_char ccr2, ccr3;
818
819 eflags = read_eflags();
820 disable_intr();
821
822 ccr2 = read_cyrix_reg(CCR2);
823 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
824 read_cyrix_reg(CCR2);
825 if (read_cyrix_reg(CCR2) != ccr2)
826 ccr2_test = 1;
827 write_cyrix_reg(CCR2, ccr2);
828
829 ccr3 = read_cyrix_reg(CCR3);
830 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
831 read_cyrix_reg(CCR3);
832 if (read_cyrix_reg(CCR3) != ccr3)
833 dir_test = 1; /* CPU supports DIRs. */
834 write_cyrix_reg(CCR3, ccr3);
835
836 if (dir_test) {
837 /* Device ID registers are available. */
838 cyrix_did = read_cyrix_reg(DIR1) << 8;
839 cyrix_did += read_cyrix_reg(DIR0);
840 } else if (ccr2_test)
841 cyrix_did = 0x0010; /* 486S A-step */
842 else
843 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
844
845 write_eflags(eflags);
846}
847
848/*
849 * Final stage of CPU identification. -- Should I check TI?
850 */
851void
852finishidentcpu(void)
853{
854 int isblue = 0;
855 u_char ccr3;
856 u_int regs[4];
857
858 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
859 if (cpu == CPU_486) {
860 /*
861 * These conditions are equivalent to:
862 * - CPU does not support cpuid instruction.
863 * - Cyrix/IBM CPU is detected.
864 */
865 isblue = identblue();
866 if (isblue == IDENTBLUE_IBMCPU) {
867 strcpy(cpu_vendor, "IBM");
868 cpu = CPU_BLUE;
869 return;
870 }
871 }
872 switch (cpu_id & 0xf00) {
873 case 0x600:
874 /*
875 * Cyrix's datasheet does not describe DIRs.
876 * Therefor, I assume it does not have them
877 * and use the result of the cpuid instruction.
878 * XXX they seem to have it for now at least. -Peter
879 */
880 identifycyrix();
881 cpu = CPU_M2;
882 break;
883 default:
884 identifycyrix();
885 /*
886 * This routine contains a trick.
887 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
888 */
889 switch (cyrix_did & 0x00f0) {
890 case 0x00:
891 case 0xf0:
892 cpu = CPU_486DLC;
893 break;
894 case 0x10:
895 cpu = CPU_CY486DX;
896 break;
897 case 0x20:
898 if ((cyrix_did & 0x000f) < 8)
899 cpu = CPU_M1;
900 else
901 cpu = CPU_M1SC;
902 break;
903 case 0x30:
904 cpu = CPU_M1;
905 break;
906 case 0x40:
907 /* MediaGX CPU */
908 cpu = CPU_M1SC;
909 break;
910 default:
911 /* M2 and later CPUs are treated as M2. */
912 cpu = CPU_M2;
913
914 /*
915 * enable cpuid instruction.
916 */
917 ccr3 = read_cyrix_reg(CCR3);
918 write_cyrix_reg(CCR3, CCR3_MAPEN0);
919 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
920 write_cyrix_reg(CCR3, ccr3);
921
922 do_cpuid(0, regs);
923 cpu_high = regs[0]; /* eax */
924 do_cpuid(1, regs);
925 cpu_id = regs[0]; /* eax */
926 cpu_feature = regs[3]; /* edx */
927 break;
928 }
929 }
930 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
931 /*
932 * There are BlueLightning CPUs that do not change
933 * undefined flags by dividing 5 by 2. In this case,
934 * the CPU identification routine in locore.s leaves
935 * cpu_vendor null string and puts CPU_486 into the
936 * cpu.
937 */
938 isblue = identblue();
939 if (isblue == IDENTBLUE_IBMCPU) {
940 strcpy(cpu_vendor, "IBM");
941 cpu = CPU_BLUE;
942 return;
943 }
944 }
945}
946
947static void
948print_AMD_assoc(int i)
949{
950 if (i == 255)
951 printf(", fully associative\n");
952 else
953 printf(", %d-way associative\n", i);
954}
955
956static void
957print_AMD_info(void)
958{
959 quad_t amd_whcr;
960
961 if (cpu_exthigh >= 0x80000005) {
962 u_int regs[4];
963
964 do_cpuid(0x80000005, regs);
965 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
966 print_AMD_assoc(regs[1] >> 24);
967 printf("Instruction TLB: %d entries", regs[1] & 0xff);
968 print_AMD_assoc((regs[1] >> 8) & 0xff);
969 printf("L1 data cache: %d kbytes", regs[2] >> 24);
970 printf(", %d bytes/line", regs[2] & 0xff);
971 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
972 print_AMD_assoc((regs[2] >> 16) & 0xff);
973 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
974 printf(", %d bytes/line", regs[3] & 0xff);
975 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
976 print_AMD_assoc((regs[3] >> 16) & 0xff);
977 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
978 do_cpuid(0x80000006, regs);
979 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
980 printf(", %d bytes/line", regs[2] & 0xff);
981 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
982 print_AMD_assoc((regs[2] >> 12) & 0x0f);
983 }
984 }
985 if (((cpu_id & 0xf00) == 0x500)
986 && (((cpu_id & 0x0f0) > 0x80)
987 || (((cpu_id & 0x0f0) == 0x80)
988 && (cpu_id & 0x00f) > 0x07))) {
989 /* K6-2(new core [Stepping 8-F]), K6-III or later */
990 amd_whcr = rdmsr(0xc0000082);
991 if (!(amd_whcr & (0x3ff << 22))) {
992 printf("Write Allocate Disable\n");
993 } else {
994 printf("Write Allocate Enable Limit: %dM bytes\n",
995 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
996 printf("Write Allocate 15-16M bytes: %s\n",
997 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
998 }
999 } else if (((cpu_id & 0xf00) == 0x500)
1000 && ((cpu_id & 0x0f0) > 0x50)) {
1001 /* K6, K6-2(old core) */
1002 amd_whcr = rdmsr(0xc0000082);
1003 if (!(amd_whcr & (0x7f << 1))) {
1004 printf("Write Allocate Disable\n");
1005 } else {
1006 printf("Write Allocate Enable Limit: %dM bytes\n",
1007 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1008 printf("Write Allocate 15-16M bytes: %s\n",
1009 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1010 printf("Hardware Write Allocate Control: %s\n",
1011 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1012 }
1013 }
1014}
1015
1016#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1017static void
1018print_AMD_features(void)
1019{
1020 u_int regs[4];
1021
1022 /*
1023 * Values taken from AMD Processor Recognition
1024 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1025 */
1026 do_cpuid(0x80000001, regs);
1027 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1028 "\020" /* in hex */
1029 "\001FPU" /* Integral FPU */
1030 "\002VME" /* Extended VM86 mode support */
1031 "\003DE" /* Debug extensions */
1032 "\004PSE" /* 4MByte page tables */
1033 "\005TSC" /* Timestamp counter */
1034 "\006MSR" /* Machine specific registers */
1035 "\007PAE" /* Physical address extension */
1036 "\010MCE" /* Machine Check support */
1037 "\011CX8" /* CMPEXCH8 instruction */
1038 "\012APIC" /* SMP local APIC */
1039 "\013<b10>"
1040 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1041 "\015MTRR" /* Memory Type Range Registers */
1042 "\016PGE" /* PG_G (global bit) support */
1043 "\017MCA" /* Machine Check Architecture */
1044 "\020ICMOV" /* CMOV instruction */
1045 "\021PAT" /* Page attributes table */
1046 "\022PGE36" /* 36 bit address space support */
1047 "\023RSVD" /* Reserved, unknown */
1048 "\024MP" /* Multiprocessor Capable */
1049 "\025<b20>"
1050 "\026<b21>"
1051 "\027AMIE" /* AMD MMX Instruction Extensions */
1052 "\030MMX"
1053 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1054 "\032<b25>"
1055 "\033<b26>"
1056 "\034<b27>"
1057 "\035<b28>"
1058 "\036<b29>"
1059 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1060 "\0403DNow!"
1061 );
1062}
1063#endif
1064
1065/*
1066 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1067 */
1068
1069#define MSR_TMx86_LONGRUN 0x80868010
1070#define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1071
1072#define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1073#define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1074#define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1075
1076#define LONGRUN_MODE_MINFREQUENCY 0x00
1077#define LONGRUN_MODE_ECONOMY 0x01
1078#define LONGRUN_MODE_PERFORMANCE 0x02
1079#define LONGRUN_MODE_MAXFREQUENCY 0x03
1080#define LONGRUN_MODE_UNKNOWN 0x04
1081#define LONGRUN_MODE_MAX 0x04
1082
1083union msrinfo {
1084 u_int64_t msr;
1085 u_int32_t regs[2];
1086};
1087
1088u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1089 /* MSR low, MSR high, flags bit0 */
1090 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1091 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1092 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1093 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1094};
1095
1096static u_int
1097tmx86_get_longrun_mode(void)
1098{
1099 u_long eflags;
1100 union msrinfo msrinfo;
1101 u_int low, high, flags, mode;
1102
1103 eflags = read_eflags();
1104 disable_intr();
1105
1106 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1107 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1108 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1109 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1110
1111 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1112 if (low == longrun_modes[mode][0] &&
1113 high == longrun_modes[mode][1] &&
1114 flags == longrun_modes[mode][2]) {
1115 goto out;
1116 }
1117 }
1118 mode = LONGRUN_MODE_UNKNOWN;
1119out:
1120 write_eflags(eflags);
1121 return (mode);
1122}
1123
1124static u_int
1125tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1126{
1127 u_long eflags;
1128 u_int regs[4];
1129
1130 eflags = read_eflags();
1131 disable_intr();
1132
1133 do_cpuid(0x80860007, regs);
1134 *frequency = regs[0];
1135 *voltage = regs[1];
1136 *percentage = regs[2];
1137
1138 write_eflags(eflags);
1139 return (1);
1140}
1141
1142static u_int
1143tmx86_set_longrun_mode(u_int mode)
1144{
1145 u_long eflags;
1146 union msrinfo msrinfo;
1147
1148 if (mode >= LONGRUN_MODE_UNKNOWN) {
1149 return (0);
1150 }
1151
1152 eflags = read_eflags();
1153 disable_intr();
1154
1155 /* Write LongRun mode values to Model Specific Register. */
1156 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1157 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1158 longrun_modes[mode][0]);
1159 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1160 longrun_modes[mode][1]);
1161 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1162
1163 /* Write LongRun mode flags to Model Specific Register. */
1164 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1165 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1166 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1167
1168 write_eflags(eflags);
1169 return (1);
1170}
1171
1172static u_int crusoe_longrun;
1173static u_int crusoe_frequency;
1174static u_int crusoe_voltage;
1175static u_int crusoe_percentage;
1176static struct sysctl_ctx_list crusoe_sysctl_ctx;
1177static struct sysctl_oid *crusoe_sysctl_tree;
1178
1179static int
1180tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1181{
1182 u_int mode;
1183 int error;
1184
1185 crusoe_longrun = tmx86_get_longrun_mode();
1186 mode = crusoe_longrun;
1187 error = sysctl_handle_int(oidp, &mode, 0, req);
1188 if (error || !req->newptr) {
1189 return (error);
1190 }
1191 if (mode >= LONGRUN_MODE_UNKNOWN) {
1192 error = EINVAL;
1193 return (error);
1194 }
1195 if (crusoe_longrun != mode) {
1196 crusoe_longrun = mode;
1197 tmx86_set_longrun_mode(crusoe_longrun);
1198 }
1199
1200 return (error);
1201}
1202
1203static int
1204tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1205{
1206 u_int val;
1207 int error;
1208
1209 tmx86_get_longrun_status(&crusoe_frequency,
1210 &crusoe_voltage, &crusoe_percentage);
1211 val = *(u_int *)oidp->oid_arg1;
1212 error = sysctl_handle_int(oidp, &val, 0, req);
1213 return (error);
1214}
1215
1216static void
1217setup_tmx86_longrun(void)
1218{
1219 static int done = 0;
1220
1221 if (done)
1222 return;
1223 done++;
1224
1225 sysctl_ctx_init(&crusoe_sysctl_ctx);
1226 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1227 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1228 "crusoe", CTLFLAG_RD, 0,
1229 "Transmeta Crusoe LongRun support");
1230 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1231 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1232 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1233 "LongRun mode [0-3]");
1234 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1235 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1236 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1237 "Current frequency (MHz)");
1238 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1239 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1240 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1241 "Current voltage (mV)");
1242 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1243 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1244 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1245 "Processing performance (%)");
1246}
1247
1248static void
1249print_transmeta_info()
1250{
1251 u_int regs[4], nreg = 0;
1252
1253 do_cpuid(0x80860000, regs);
1254 nreg = regs[0];
1255 if (nreg >= 0x80860001) {
1256 do_cpuid(0x80860001, regs);
1257 printf(" Processor revision %u.%u.%u.%u\n",
1258 (regs[1] >> 24) & 0xff,
1259 (regs[1] >> 16) & 0xff,
1260 (regs[1] >> 8) & 0xff,
1261 regs[1] & 0xff);
1262 }
1263 if (nreg >= 0x80860002) {
1264 do_cpuid(0x80860002, regs);
1265 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1266 (regs[1] >> 24) & 0xff,
1267 (regs[1] >> 16) & 0xff,
1268 (regs[1] >> 8) & 0xff,
1269 regs[1] & 0xff,
1270 regs[2]);
1271 }
1272 if (nreg >= 0x80860006) {
1273 char info[65];
1274 do_cpuid(0x80860003, (u_int*) &info[0]);
1275 do_cpuid(0x80860004, (u_int*) &info[16]);
1276 do_cpuid(0x80860005, (u_int*) &info[32]);
1277 do_cpuid(0x80860006, (u_int*) &info[48]);
1278 info[64] = 0;
1279 printf(" %s\n", info);
1280 }
1281
1282 crusoe_longrun = tmx86_get_longrun_mode();
1283 tmx86_get_longrun_status(&crusoe_frequency,
1284 &crusoe_voltage, &crusoe_percentage);
1285 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1286 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1287}
1288