Compensate for the frequency error that occurs at higher 'hz' settings.
[dragonfly.git] / sys / i386 / isa / clock.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
9a47427a 38 * $DragonFly: src/sys/i386/isa/Attic/clock.c,v 1.8 2004/01/07 10:59:09 dillon Exp $
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39 */
40
41/*
42 * Routines to handle clock hardware.
43 */
44
45/*
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 *
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
50 */
51
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52#include "use_apm.h"
53#include "use_mca.h"
984263bc 54#include "opt_clock.h"
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55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/time.h>
59#include <sys/kernel.h>
60#ifndef SMP
61#include <sys/lock.h>
62#endif
63#include <sys/sysctl.h>
64#include <sys/cons.h>
65
66#include <machine/clock.h>
67#ifdef CLK_CALIBRATION_LOOP
68#endif
69#include <machine/cputypes.h>
70#include <machine/frame.h>
71#include <machine/ipl.h>
72#include <machine/limits.h>
73#include <machine/md_var.h>
74#include <machine/psl.h>
75#ifdef APIC_IO
76#include <machine/segments.h>
77#endif
78#if defined(SMP) || defined(APIC_IO)
79#include <machine/smp.h>
80#endif /* SMP || APIC_IO */
81#include <machine/specialreg.h>
82
83#include <i386/isa/icu.h>
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84#include <bus/isa/i386/isa.h>
85#include <bus/isa/rtc.h>
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86#include <i386/isa/timerreg.h>
87
88#include <i386/isa/intr_machdep.h>
89
984263bc 90#if NMCA > 0
1f2de5d4 91#include <bus/mca/i386/mca_machdep.h>
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92#endif
93
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94#ifdef APIC_IO
95#include <i386/isa/intr_machdep.h>
96/* The interrupt triggered by the 8254 (timer) chip */
97int apic_8254_intr;
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98static u_long read_intr_count (int vec);
99static void setup_8254_mixed_mode (void);
984263bc 100#endif
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101
102/*
103 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
104 * can use a simple formula for leap years.
105 */
106#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
107#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
108
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109#define TIMER_DIV(x) (timer_freq / (x))
110#define FRAC_ADJUST(x) (timer_freq - ((timer_freq / (x)) * (x)))
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111
112/*
113 * Time in timer cycles that it takes for microtime() to disable interrupts
114 * and latch the count. microtime() currently uses "cli; outb ..." so it
115 * normally takes less than 2 timer cycles. Add a few for cache misses.
116 * Add a few more to allow for latency in bogus calls to microtime() with
117 * interrupts already disabled.
118 */
119#define TIMER0_LATCH_COUNT 20
120
121/*
122 * Maximum frequency that we are willing to allow for timer0. Must be
123 * low enough to guarantee that the timer interrupt handler returns
124 * before the next timer interrupt.
125 */
126#define TIMER0_MAX_FREQ 20000
127
128int adjkerntz; /* local offset from GMT in seconds */
129int clkintr_pending;
130int disable_rtc_set; /* disable resettodr() if != 0 */
131volatile u_int idelayed;
132int statclock_disable;
133u_int stat_imask = SWI_CLOCK_MASK;
134#ifndef TIMER_FREQ
135#define TIMER_FREQ 1193182
136#endif
137u_int timer_freq = TIMER_FREQ;
138int timer0_max_count;
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139int timer0_frac_adjust;
140int timer0_frac_accum; /* fractional adjustments to match frequency */
141u_int timer0_frac_freq;
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142u_int tsc_freq;
143int tsc_is_broken;
144int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
145
146static int beeping = 0;
147static u_int clk_imask = HWI_MASK | SWI_MASK;
148static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
149static u_int hardclock_max_count;
150static u_int32_t i8254_lastcount;
151static u_int32_t i8254_offset;
152static int i8254_ticked;
153/*
154 * XXX new_function and timer_func should not handle clockframes, but
155 * timer_func currently needs to hold hardclock to handle the
156 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
157 * to switch between clkintr() and a slightly different timerintr().
158 */
3ae0cd58 159static void (*new_function) (struct clockframe *frame);
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160static u_int new_rate;
161static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
162static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
163static u_int timer0_prescaler_count;
164
165/* Values for timerX_state: */
166#define RELEASED 0
167#define RELEASE_PENDING 1
168#define ACQUIRED 2
169#define ACQUIRE_PENDING 3
170
171static u_char timer0_state;
172static u_char timer2_state;
3ae0cd58 173static void (*timer_func) (struct clockframe *frame) = hardclock;
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174static u_int tsc_present;
175
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176static unsigned i8254_get_timecount (struct timecounter *tc);
177static unsigned tsc_get_timecount (struct timecounter *tc);
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178static void set_timer_freq(u_int freq, int intr_freq);
179
180static struct timecounter tsc_timecounter = {
181 tsc_get_timecount, /* get_timecount */
182 0, /* no poll_pps */
183 ~0u, /* counter_mask */
184 0, /* frequency */
185 "TSC" /* name */
186};
187
188SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
189 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
190
191static struct timecounter i8254_timecounter = {
192 i8254_get_timecount, /* get_timecount */
193 0, /* no poll_pps */
194 ~0u, /* counter_mask */
195 0, /* frequency */
196 "i8254" /* name */
197};
198
199SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
200 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
201
202static void
203clkintr(struct clockframe frame)
204{
205 if (timecounter->tc_get_timecount == i8254_get_timecount) {
8a8d5d85 206 clock_lock();
9a47427a 207 if (i8254_ticked) {
984263bc 208 i8254_ticked = 0;
9a47427a 209 } else {
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210 i8254_offset += timer0_max_count;
211 i8254_lastcount = 0;
212 }
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213 /*
214 * Lets say we are running at 100Hz. Our counter load will
215 * be 1193182 / 100 = 11931.82, which is really only 11931.
216 * The fractional code accounts for the .82 count. When it
217 * exceeds 1.00 count we adjust the reload register by + 1
218 * to compensate for the error. We must also adjust
219 * i8254_offset.
220 *
221 * If we did not do this a high frequency would cause the
222 * actual interrupt rate to seriously diverge from 'hz'.
223 */
224 timer0_frac_accum += timer0_frac_adjust;
225 if (timer0_frac_accum >= timer0_frac_freq) {
226 timer0_frac_accum -= timer0_frac_freq;
227 outb(TIMER_CNTR0, (timer0_max_count + 1) & 0xff);
228 outb(TIMER_CNTR0, (timer0_max_count + 1) >> 8);
229 ++i8254_offset;
230 } else {
231 outb(TIMER_CNTR0, timer0_max_count & 0xff);
232 outb(TIMER_CNTR0, timer0_max_count >> 8);
233 }
984263bc 234 clkintr_pending = 0;
8a8d5d85 235 clock_unlock();
984263bc 236 }
9a47427a 237
984263bc 238 timer_func(&frame);
984263bc 239
9a47427a 240 switch (timer0_state) {
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241 case RELEASED:
242 setdelayed();
243 break;
984263bc 244 case ACQUIRED:
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245 timer0_prescaler_count += timer0_max_count;
246 if (timer0_prescaler_count >= hardclock_max_count) {
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247 timer0_prescaler_count -= hardclock_max_count;
248 hardclock(&frame);
249 setdelayed();
250 }
251 break;
984263bc 252 case ACQUIRE_PENDING:
8a8d5d85 253 clock_lock();
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254 i8254_offset = i8254_get_timecount(NULL);
255 i8254_lastcount = 0;
256 timer0_max_count = TIMER_DIV(new_rate);
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257 timer0_frac_adjust = FRAC_ADJUST(new_rate);
258 timer0_frac_freq = new_rate;
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259 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
260 outb(TIMER_CNTR0, timer0_max_count & 0xff);
261 outb(TIMER_CNTR0, timer0_max_count >> 8);
8a8d5d85 262 clock_unlock();
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263 timer_func = new_function;
264 timer0_state = ACQUIRED;
265 setdelayed();
266 break;
984263bc 267 case RELEASE_PENDING:
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268 timer0_prescaler_count += timer0_max_count;
269 if (timer0_prescaler_count >= hardclock_max_count) {
8a8d5d85 270 clock_lock();
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271 i8254_offset = i8254_get_timecount(NULL);
272 i8254_lastcount = 0;
273 timer0_max_count = hardclock_max_count;
274 outb(TIMER_MODE,
275 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
276 outb(TIMER_CNTR0, timer0_max_count & 0xff);
277 outb(TIMER_CNTR0, timer0_max_count >> 8);
8a8d5d85 278 clock_unlock();
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279 timer0_prescaler_count = 0;
280 timer_func = hardclock;
281 timer0_state = RELEASED;
282 hardclock(&frame);
283 setdelayed();
284 }
285 break;
286 }
287#if NMCA > 0
288 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
289 if (MCA_system)
290 outb(0x61, inb(0x61) | 0x80);
291#endif
292}
293
294/*
295 * The acquire and release functions must be called at ipl >= splclock().
296 */
297int
3ae0cd58 298acquire_timer0(int rate, void (*function) (struct clockframe *frame))
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299{
300 static int old_rate;
301
302 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
303 return (-1);
304 switch (timer0_state) {
305
306 case RELEASED:
307 timer0_state = ACQUIRE_PENDING;
308 break;
309
310 case RELEASE_PENDING:
311 if (rate != old_rate)
312 return (-1);
313 /*
314 * The timer has been released recently, but is being
315 * re-acquired before the release completed. In this
316 * case, we simply reclaim it as if it had not been
317 * released at all.
318 */
319 timer0_state = ACQUIRED;
320 break;
321
322 default:
323 return (-1); /* busy */
324 }
325 new_function = function;
326 old_rate = new_rate = rate;
327 return (0);
328}
329
330int
331acquire_timer2(int mode)
332{
333
334 if (timer2_state != RELEASED)
335 return (-1);
336 timer2_state = ACQUIRED;
337
338 /*
339 * This access to the timer registers is as atomic as possible
340 * because it is a single instruction. We could do better if we
341 * knew the rate. Use of splclock() limits glitches to 10-100us,
342 * and this is probably good enough for timer2, so we aren't as
343 * careful with it as with timer0.
344 */
345 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
346
347 return (0);
348}
349
350int
351release_timer0()
352{
353 switch (timer0_state) {
354
355 case ACQUIRED:
356 timer0_state = RELEASE_PENDING;
357 break;
358
359 case ACQUIRE_PENDING:
360 /* Nothing happened yet, release quickly. */
361 timer0_state = RELEASED;
362 break;
363
364 default:
365 return (-1);
366 }
367 return (0);
368}
369
370int
371release_timer2()
372{
373
374 if (timer2_state != ACQUIRED)
375 return (-1);
376 timer2_state = RELEASED;
377 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
378 return (0);
379}
380
381/*
382 * This routine receives statistical clock interrupts from the RTC.
383 * As explained above, these occur at 128 interrupts per second.
384 * When profiling, we receive interrupts at a rate of 1024 Hz.
385 *
386 * This does not actually add as much overhead as it sounds, because
387 * when the statistical clock is active, the hardclock driver no longer
388 * needs to keep (inaccurate) statistics on its own. This decouples
389 * statistics gathering from scheduling interrupts.
390 *
391 * The RTC chip requires that we read status register C (RTC_INTR)
392 * to acknowledge an interrupt, before it will generate the next one.
393 * Under high interrupt load, rtcintr() can be indefinitely delayed and
394 * the clock can tick immediately after the read from RTC_INTR. In this
395 * case, the mc146818A interrupt signal will not drop for long enough
396 * to register with the 8259 PIC. If an interrupt is missed, the stat
397 * clock will halt, considerably degrading system performance. This is
398 * why we use 'while' rather than a more straightforward 'if' below.
399 * Stat clock ticks can still be lost, causing minor loss of accuracy
400 * in the statistics, but the stat clock will no longer stop.
401 */
402static void
403rtcintr(struct clockframe frame)
404{
405 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
406 statclock(&frame);
407}
408
409#include "opt_ddb.h"
410#ifdef DDB
411#include <ddb/ddb.h>
412
413DB_SHOW_COMMAND(rtc, rtc)
414{
415 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
416 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
417 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
418 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
419}
420#endif /* DDB */
421
422static int
423getit(void)
424{
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425 int high, low;
426
8a8d5d85 427 clock_lock();
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428
429 /* Select timer0 and latch counter value. */
430 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
431
432 low = inb(TIMER_CNTR0);
433 high = inb(TIMER_CNTR0);
434
8a8d5d85 435 clock_unlock();
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436 return ((high << 8) | low);
437}
438
439/*
440 * Wait "n" microseconds.
441 * Relies on timer 1 counting down from (timer_freq / hz)
442 * Note: timer had better have been programmed before this is first used!
443 */
444void
445DELAY(int n)
446{
447 int delta, prev_tick, tick, ticks_left;
448
449#ifdef DELAYDEBUG
450 int getit_calls = 1;
451 int n1;
452 static int state = 0;
453
454 if (state == 0) {
455 state = 1;
456 for (n1 = 1; n1 <= 10000000; n1 *= 10)
457 DELAY(n1);
458 state = 2;
459 }
460 if (state == 1)
461 printf("DELAY(%d)...", n);
462#endif
463 /*
464 * Guard against the timer being uninitialized if we are called
465 * early for console i/o.
466 */
467 if (timer0_max_count == 0)
468 set_timer_freq(timer_freq, hz);
469
470 /*
471 * Read the counter first, so that the rest of the setup overhead is
472 * counted. Guess the initial overhead is 20 usec (on most systems it
473 * takes about 1.5 usec for each of the i/o's in getit(). The loop
474 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
475 * multiplications and divisions to scale the count take a while).
476 */
477 prev_tick = getit();
478 n -= 0; /* XXX actually guess no initial overhead */
479 /*
480 * Calculate (n * (timer_freq / 1e6)) without using floating point
481 * and without any avoidable overflows.
482 */
483 if (n <= 0)
484 ticks_left = 0;
485 else if (n < 256)
486 /*
487 * Use fixed point to avoid a slow division by 1000000.
488 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
489 * 2^15 is the first power of 2 that gives exact results
490 * for n between 0 and 256.
491 */
492 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
493 else
494 /*
495 * Don't bother using fixed point, although gcc-2.7.2
496 * generates particularly poor code for the long long
497 * division, since even the slow way will complete long
498 * before the delay is up (unless we're interrupted).
499 */
500 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
501 / 1000000;
502
503 while (ticks_left > 0) {
504 tick = getit();
505#ifdef DELAYDEBUG
506 ++getit_calls;
507#endif
508 delta = prev_tick - tick;
509 prev_tick = tick;
510 if (delta < 0) {
511 delta += timer0_max_count;
512 /*
513 * Guard against timer0_max_count being wrong.
514 * This shouldn't happen in normal operation,
515 * but it may happen if set_timer_freq() is
516 * traced.
517 */
518 if (delta < 0)
519 delta = 0;
520 }
521 ticks_left -= delta;
522 }
523#ifdef DELAYDEBUG
524 if (state == 1)
525 printf(" %d calls to getit() at %d usec each\n",
526 getit_calls, (n + 5) / getit_calls);
527#endif
528}
529
530static void
531sysbeepstop(void *chan)
532{
533 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
534 release_timer2();
535 beeping = 0;
536}
537
538int
539sysbeep(int pitch, int period)
540{
541 int x = splclock();
542
543 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
544 if (!beeping) {
545 /* Something else owns it. */
546 splx(x);
547 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
548 }
8a8d5d85 549 clock_lock();
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550 outb(TIMER_CNTR2, pitch);
551 outb(TIMER_CNTR2, (pitch>>8));
8a8d5d85 552 clock_unlock();
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553 if (!beeping) {
554 /* enable counter2 output to speaker */
555 outb(IO_PPI, inb(IO_PPI) | 3);
556 beeping = period;
557 timeout(sysbeepstop, (void *)NULL, period);
558 }
559 splx(x);
560 return (0);
561}
562
563/*
564 * RTC support routines
565 */
566
567int
568rtcin(reg)
569 int reg;
570{
571 int s;
572 u_char val;
573
574 s = splhigh();
575 outb(IO_RTC, reg);
576 inb(0x84);
577 val = inb(IO_RTC + 1);
578 inb(0x84);
579 splx(s);
580 return (val);
581}
582
583static __inline void
584writertc(u_char reg, u_char val)
585{
586 int s;
587
588 s = splhigh();
589 inb(0x84);
590 outb(IO_RTC, reg);
591 inb(0x84);
592 outb(IO_RTC + 1, val);
593 inb(0x84); /* XXX work around wrong order in rtcin() */
594 splx(s);
595}
596
597static __inline int
598readrtc(int port)
599{
600 return(bcd2bin(rtcin(port)));
601}
602
603static u_int
604calibrate_clocks(void)
605{
606 u_int64_t old_tsc;
607 u_int count, prev_count, tot_count;
608 int sec, start_sec, timeout;
609
610 if (bootverbose)
611 printf("Calibrating clock(s) ... ");
612 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
613 goto fail;
614 timeout = 100000000;
615
616 /* Read the mc146818A seconds counter. */
617 for (;;) {
618 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
619 sec = rtcin(RTC_SEC);
620 break;
621 }
622 if (--timeout == 0)
623 goto fail;
624 }
625
626 /* Wait for the mC146818A seconds counter to change. */
627 start_sec = sec;
628 for (;;) {
629 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
630 sec = rtcin(RTC_SEC);
631 if (sec != start_sec)
632 break;
633 }
634 if (--timeout == 0)
635 goto fail;
636 }
637
638 /* Start keeping track of the i8254 counter. */
639 prev_count = getit();
640 if (prev_count == 0 || prev_count > timer0_max_count)
641 goto fail;
642 tot_count = 0;
643
644 if (tsc_present)
645 old_tsc = rdtsc();
646 else
647 old_tsc = 0; /* shut up gcc */
648
649 /*
650 * Wait for the mc146818A seconds counter to change. Read the i8254
651 * counter for each iteration since this is convenient and only
652 * costs a few usec of inaccuracy. The timing of the final reads
653 * of the counters almost matches the timing of the initial reads,
654 * so the main cause of inaccuracy is the varying latency from
655 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
656 * rtcin(RTC_SEC) that returns a changed seconds count. The
657 * maximum inaccuracy from this cause is < 10 usec on 486's.
658 */
659 start_sec = sec;
660 for (;;) {
661 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
662 sec = rtcin(RTC_SEC);
663 count = getit();
664 if (count == 0 || count > timer0_max_count)
665 goto fail;
666 if (count > prev_count)
667 tot_count += prev_count - (count - timer0_max_count);
668 else
669 tot_count += prev_count - count;
670 prev_count = count;
671 if (sec != start_sec)
672 break;
673 if (--timeout == 0)
674 goto fail;
675 }
676
677 /*
678 * Read the cpu cycle counter. The timing considerations are
679 * similar to those for the i8254 clock.
680 */
681 if (tsc_present)
682 tsc_freq = rdtsc() - old_tsc;
683
684 if (bootverbose) {
685 if (tsc_present)
686 printf("TSC clock: %u Hz, ", tsc_freq);
687 printf("i8254 clock: %u Hz\n", tot_count);
688 }
689 return (tot_count);
690
691fail:
692 if (bootverbose)
693 printf("failed, using default i8254 clock of %u Hz\n",
694 timer_freq);
695 return (timer_freq);
696}
697
698static void
699set_timer_freq(u_int freq, int intr_freq)
700{
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701 int new_timer0_max_count;
702
8a8d5d85 703 clock_lock();
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704 timer_freq = freq;
705 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
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706 timer0_frac_adjust = FRAC_ADJUST(intr_freq);
707 timer0_frac_freq = intr_freq;
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708 if (new_timer0_max_count != timer0_max_count) {
709 timer0_max_count = new_timer0_max_count;
710 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
711 outb(TIMER_CNTR0, timer0_max_count & 0xff);
712 outb(TIMER_CNTR0, timer0_max_count >> 8);
713 }
8a8d5d85 714 clock_unlock();
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715}
716
717static void
718i8254_restore(void)
719{
8a8d5d85 720 clock_lock();
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721 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
722 outb(TIMER_CNTR0, timer0_max_count & 0xff);
723 outb(TIMER_CNTR0, timer0_max_count >> 8);
8a8d5d85 724 clock_unlock();
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725}
726
727static void
728rtc_restore(void)
729{
730
731 /* Restore all of the RTC's "status" (actually, control) registers. */
732 writertc(RTC_STATUSB, RTCSB_24HR);
733 writertc(RTC_STATUSA, rtc_statusa);
734 writertc(RTC_STATUSB, rtc_statusb);
735}
736
737/*
738 * Restore all the timers non-atomically (XXX: should be atomically).
739 *
740 * This function is called from apm_default_resume() to restore all the timers.
741 * This should not be necessary, but there are broken laptops that do not
742 * restore all the timers on resume.
743 */
744void
745timer_restore(void)
746{
747
748 i8254_restore(); /* restore timer_freq and hz */
749 rtc_restore(); /* reenable RTC interrupts */
750}
751
752/*
753 * Initialize 8254 timer 0 early so that it can be used in DELAY().
754 * XXX initialization of other timers is unintentionally left blank.
755 */
756void
757startrtclock()
758{
759 u_int delta, freq;
760
761 if (cpu_feature & CPUID_TSC)
762 tsc_present = 1;
763 else
764 tsc_present = 0;
765
766 writertc(RTC_STATUSA, rtc_statusa);
767 writertc(RTC_STATUSB, RTCSB_24HR);
768
769 set_timer_freq(timer_freq, hz);
770 freq = calibrate_clocks();
771#ifdef CLK_CALIBRATION_LOOP
772 if (bootverbose) {
773 printf(
774 "Press a key on the console to abort clock calibration\n");
775 while (cncheckc() == -1)
776 calibrate_clocks();
777 }
778#endif
779
780 /*
781 * Use the calibrated i8254 frequency if it seems reasonable.
782 * Otherwise use the default, and don't use the calibrated i586
783 * frequency.
784 */
785 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
786 if (delta < timer_freq / 100) {
787#ifndef CLK_USE_I8254_CALIBRATION
788 if (bootverbose)
789 printf(
790"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
791 freq = timer_freq;
792#endif
793 timer_freq = freq;
794 } else {
795 if (bootverbose)
796 printf(
797 "%d Hz differs from default of %d Hz by more than 1%%\n",
798 freq, timer_freq);
799 tsc_freq = 0;
800 }
801
802 set_timer_freq(timer_freq, hz);
803 i8254_timecounter.tc_frequency = timer_freq;
804 init_timecounter(&i8254_timecounter);
805
806#ifndef CLK_USE_TSC_CALIBRATION
807 if (tsc_freq != 0) {
808 if (bootverbose)
809 printf(
810"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
811 tsc_freq = 0;
812 }
813#endif
814 if (tsc_present && tsc_freq == 0) {
815 /*
816 * Calibration of the i586 clock relative to the mc146818A
817 * clock failed. Do a less accurate calibration relative
818 * to the i8254 clock.
819 */
820 u_int64_t old_tsc = rdtsc();
821
822 DELAY(1000000);
823 tsc_freq = rdtsc() - old_tsc;
824#ifdef CLK_USE_TSC_CALIBRATION
825 if (bootverbose)
826 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
827#endif
828 }
829
830#if !defined(SMP)
831 /*
832 * We can not use the TSC in SMP mode, until we figure out a
833 * cheap (impossible), reliable and precise (yeah right!) way
834 * to synchronize the TSCs of all the CPUs.
835 * Curse Intel for leaving the counter out of the I/O APIC.
836 */
837
838#if NAPM > 0
839 /*
840 * We can not use the TSC if we support APM. Precise timekeeping
841 * on an APM'ed machine is at best a fools pursuit, since
842 * any and all of the time spent in various SMM code can't
843 * be reliably accounted for. Reading the RTC is your only
844 * source of reliable time info. The i8254 looses too of course
845 * but we need to have some kind of time...
846 * We don't know at this point whether APM is going to be used
847 * or not, nor when it might be activated. Play it safe.
848 */
849 return;
850#endif /* NAPM > 0 */
851
852 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
853 tsc_timecounter.tc_frequency = tsc_freq;
854 init_timecounter(&tsc_timecounter);
855 }
856
857#endif /* !defined(SMP) */
858}
859
860/*
861 * Initialize the time of day register, based on the time base which is, e.g.
862 * from a filesystem.
863 */
864void
865inittodr(time_t base)
866{
867 unsigned long sec, days;
868 int yd;
869 int year, month;
870 int y, m, s;
871 struct timespec ts;
872
873 if (base) {
874 s = splclock();
875 ts.tv_sec = base;
876 ts.tv_nsec = 0;
877 set_timecounter(&ts);
878 splx(s);
879 }
880
881 /* Look if we have a RTC present and the time is valid */
882 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
883 goto wrong_time;
884
885 /* wait for time update to complete */
886 /* If RTCSA_TUP is zero, we have at least 244us before next update */
887 s = splhigh();
888 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
889 splx(s);
890 s = splhigh();
891 }
892
893 days = 0;
894#ifdef USE_RTC_CENTURY
895 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
896#else
897 year = readrtc(RTC_YEAR) + 1900;
898 if (year < 1970)
899 year += 100;
900#endif
901 if (year < 1970) {
902 splx(s);
903 goto wrong_time;
904 }
905 month = readrtc(RTC_MONTH);
906 for (m = 1; m < month; m++)
907 days += daysinmonth[m-1];
908 if ((month > 2) && LEAPYEAR(year))
909 days ++;
910 days += readrtc(RTC_DAY) - 1;
911 yd = days;
912 for (y = 1970; y < year; y++)
913 days += DAYSPERYEAR + LEAPYEAR(y);
914 sec = ((( days * 24 +
915 readrtc(RTC_HRS)) * 60 +
916 readrtc(RTC_MIN)) * 60 +
917 readrtc(RTC_SEC));
918 /* sec now contains the number of seconds, since Jan 1 1970,
919 in the local time zone */
920
921 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
922
923 y = time_second - sec;
924 if (y <= -2 || y >= 2) {
925 /* badly off, adjust it */
926 ts.tv_sec = sec;
927 ts.tv_nsec = 0;
928 set_timecounter(&ts);
929 }
930 splx(s);
931 return;
932
933wrong_time:
934 printf("Invalid time in real time clock.\n");
935 printf("Check and reset the date immediately!\n");
936}
937
938/*
939 * Write system time back to RTC
940 */
941void
942resettodr()
943{
944 unsigned long tm;
945 int y, m, s;
946
947 if (disable_rtc_set)
948 return;
949
950 s = splclock();
951 tm = time_second;
952 splx(s);
953
954 /* Disable RTC updates and interrupts. */
955 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
956
957 /* Calculate local time to put in RTC */
958
959 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
960
961 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
962 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
963 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
964
965 /* We have now the days since 01-01-1970 in tm */
966 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
967 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
968 tm >= m;
969 y++, m = DAYSPERYEAR + LEAPYEAR(y))
970 tm -= m;
971
972 /* Now we have the years in y and the day-of-the-year in tm */
973 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
974#ifdef USE_RTC_CENTURY
975 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
976#endif
977 for (m = 0; ; m++) {
978 int ml;
979
980 ml = daysinmonth[m];
981 if (m == 1 && LEAPYEAR(y))
982 ml++;
983 if (tm < ml)
984 break;
985 tm -= ml;
986 }
987
988 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
989 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
990
991 /* Reenable RTC updates and interrupts. */
992 writertc(RTC_STATUSB, rtc_statusb);
993}
994
995
996/*
997 * Start both clocks running.
998 */
999void
1000cpu_initclocks()
1001{
1002 int diag;
1003#ifdef APIC_IO
1004 int apic_8254_trial;
1005 struct intrec *clkdesc;
1006#endif /* APIC_IO */
1007
1008 if (statclock_disable) {
1009 /*
1010 * The stat interrupt mask is different without the
1011 * statistics clock. Also, don't set the interrupt
1012 * flag which would normally cause the RTC to generate
1013 * interrupts.
1014 */
1015 stat_imask = HWI_MASK | SWI_MASK;
1016 rtc_statusb = RTCSB_24HR;
1017 } else {
1018 /* Setting stathz to nonzero early helps avoid races. */
1019 stathz = RTC_NOPROFRATE;
1020 profhz = RTC_PROFRATE;
1021 }
1022
1023 /* Finish initializing 8253 timer 0. */
1024#ifdef APIC_IO
1025
1026 apic_8254_intr = isa_apic_irq(0);
1027 apic_8254_trial = 0;
1028 if (apic_8254_intr >= 0 ) {
1029 if (apic_int_type(0, 0) == 3)
1030 apic_8254_trial = 1;
1031 } else {
1032 /* look for ExtInt on pin 0 */
1033 if (apic_int_type(0, 0) == 3) {
1034 apic_8254_intr = apic_irq(0, 0);
1035 setup_8254_mixed_mode();
1036 } else
1037 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1038 }
1039
1040 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
4b5f931b 1041 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
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1042 INTREN(1 << apic_8254_intr);
1043
1044#else /* APIC_IO */
1045
1046 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
4b5f931b 1047 INTR_EXCL | INTR_FAST);
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1048 INTREN(IRQ0);
1049
1050#endif /* APIC_IO */
1051
1052 /* Initialize RTC. */
1053 writertc(RTC_STATUSA, rtc_statusa);
1054 writertc(RTC_STATUSB, RTCSB_24HR);
1055
1056 /* Don't bother enabling the statistics clock. */
1057 if (statclock_disable)
1058 return;
1059 diag = rtcin(RTC_DIAG);
1060 if (diag != 0)
1061 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1062
1063#ifdef APIC_IO
1064 if (isa_apic_irq(8) != 8)
1065 panic("APIC RTC != 8");
1066#endif /* APIC_IO */
1067
1068 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
4b5f931b 1069 INTR_EXCL | INTR_FAST);
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1070
1071#ifdef APIC_IO
1072 INTREN(APIC_IRQ8);
1073#else
1074 INTREN(IRQ8);
1075#endif /* APIC_IO */
1076
1077 writertc(RTC_STATUSB, rtc_statusb);
1078
1079#ifdef APIC_IO
1080 if (apic_8254_trial) {
1081
1082 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1083 while (read_intr_count(8) < 6)
1084 ; /* nothing */
1085 if (read_intr_count(apic_8254_intr) < 3) {
1086 /*
1087 * The MP table is broken.
1088 * The 8254 was not connected to the specified pin
1089 * on the IO APIC.
1090 * Workaround: Limited variant of mixed mode.
1091 */
1092 INTRDIS(1 << apic_8254_intr);
1093 inthand_remove(clkdesc);
1094 printf("APIC_IO: Broken MP table detected: "
1095 "8254 is not connected to "
1096 "IOAPIC #%d intpin %d\n",
1097 int_to_apicintpin[apic_8254_intr].ioapic,
1098 int_to_apicintpin[apic_8254_intr].int_pin);
1099 /*
1100 * Revoke current ISA IRQ 0 assignment and
1101 * configure a fallback interrupt routing from
1102 * the 8254 Timer via the 8259 PIC to the
1103 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1104 * We reuse the low level interrupt handler number.
1105 */
1106 if (apic_irq(0, 0) < 0) {
1107 revoke_apic_irq(apic_8254_intr);
1108 assign_apic_irq(0, 0, apic_8254_intr);
1109 }
1110 apic_8254_intr = apic_irq(0, 0);
1111 setup_8254_mixed_mode();
1112 inthand_add("clk", apic_8254_intr,
1113 (inthand2_t *)clkintr,
4b5f931b 1114 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
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1115 INTREN(1 << apic_8254_intr);
1116 }
1117
1118 }
1119 if (apic_int_type(0, 0) != 3 ||
1120 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1121 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1122 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1123 int_to_apicintpin[apic_8254_intr].ioapic,
1124 int_to_apicintpin[apic_8254_intr].int_pin);
1125 else
1126 printf("APIC_IO: "
1127 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1128#endif
1129
1130}
1131
1132#ifdef APIC_IO
1133static u_long
1134read_intr_count(int vec)
1135{
1136 u_long *up;
1137 up = intr_countp[vec];
1138 if (up)
1139 return *up;
1140 return 0UL;
1141}
1142
1143static void
1144setup_8254_mixed_mode()
1145{
1146 /*
1147 * Allow 8254 timer to INTerrupt 8259:
1148 * re-initialize master 8259:
1149 * reset; prog 4 bytes, single ICU, edge triggered
1150 */
1151 outb(IO_ICU1, 0x13);
1152 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1153 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1154 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1155 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1156
1157 /* program IO APIC for type 3 INT on INT0 */
1158 if (ext_int_setup(0, 0) < 0)
1159 panic("8254 redirect via APIC pin0 impossible!");
1160}
1161#endif
1162
1163void
1164setstatclockrate(int newhz)
1165{
1166 if (newhz == RTC_PROFRATE)
1167 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1168 else
1169 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1170 writertc(RTC_STATUSA, rtc_statusa);
1171}
1172
1173static int
1174sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1175{
1176 int error;
1177 u_int freq;
1178
1179 /*
1180 * Use `i8254' instead of `timer' in external names because `timer'
1181 * is is too generic. Should use it everywhere.
1182 */
1183 freq = timer_freq;
1184 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1185 if (error == 0 && req->newptr != NULL) {
1186 if (timer0_state != RELEASED)
1187 return (EBUSY); /* too much trouble to handle */
1188 set_timer_freq(freq, hz);
1189 i8254_timecounter.tc_frequency = freq;
1190 update_timecounter(&i8254_timecounter);
1191 }
1192 return (error);
1193}
1194
1195SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1196 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
1197
1198static int
1199sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1200{
1201 int error;
1202 u_int freq;
1203
1204 if (tsc_timecounter.tc_frequency == 0)
1205 return (EOPNOTSUPP);
1206 freq = tsc_freq;
1207 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1208 if (error == 0 && req->newptr != NULL) {
1209 tsc_freq = freq;
1210 tsc_timecounter.tc_frequency = tsc_freq;
1211 update_timecounter(&tsc_timecounter);
1212 }
1213 return (error);
1214}
1215
1216SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1217 0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", "");
1218
1219static unsigned
1220i8254_get_timecount(struct timecounter *tc)
1221{
1222 u_int count;
1223 u_long ef;
1224 u_int high, low;
1225
1226 ef = read_eflags();
8a8d5d85 1227 clock_lock();
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1228
1229 /* Select timer0 and latch counter value. */
1230 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1231
1232 low = inb(TIMER_CNTR0);
1233 high = inb(TIMER_CNTR0);
1234 count = timer0_max_count - ((high << 8) | low);
1235 if (count < i8254_lastcount ||
1236 (!i8254_ticked && (clkintr_pending ||
1237 ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
1238#ifdef APIC_IO
1239#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1240 /* XXX this assumes that apic_8254_intr is < 24. */
1241 (lapic_irr1 & (1 << apic_8254_intr))))
1242#else
1243 (inb(IO_ICU1) & 1)))
1244#endif
1245 )) {
1246 i8254_ticked = 1;
1247 i8254_offset += timer0_max_count;
1248 }
1249 i8254_lastcount = count;
1250 count += i8254_offset;
8a8d5d85 1251 clock_unlock();
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1252 return (count);
1253}
1254
1255static unsigned
1256tsc_get_timecount(struct timecounter *tc)
1257{
1258 return (rdtsc());
1259}
1260
1261#ifdef KERN_TIMESTAMP
1262#define KERN_TIMESTAMP_SIZE 16384
1263static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1264SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1265 sizeof(tsc), "LU", "Kernel timestamps");
1266void
1267_TSTMP(u_int32_t x)
1268{
1269 static int i;
1270
1271 tsc[i] = (u_int32_t)rdtsc();
1272 tsc[i+1] = x;
1273 i = i + 2;
1274 if (i >= KERN_TIMESTAMP_SIZE)
1275 i = 0;
1276 tsc[i] = 0; /* mark last entry */
1277}
6b08710e 1278#endif /* KERN_TIMESTAMP */
984263bc 1279