x86_64: Allow UP kernel to use LAPIC timer and I/O APIC
[dragonfly.git] / sys / platform / pc64 / include / intr_machdep.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
35 * $DragonFly: src/sys/platform/pc64/isa/intr_machdep.h,v 1.1 2008/08/29 17:07:19 dillon Exp $
36 */
37
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38#ifndef _ARCH_INTR_MACHDEP_H_
39#define _ARCH_INTR_MACHDEP_H_
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40
41#ifndef LOCORE
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42#ifndef _SYS_TYPES_H_
43#include <sys/types.h>
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44#endif
45#endif
46
47/*
48 * Low level interrupt code.
49 */
50
51#ifdef _KERNEL
52
617a6d43 53#define IDT_OFFSET 0x20
9caf58d7 54#define IDT_OFFSET_SYSCALL 0x80
617a6d43 55#define IDT_OFFSET_IPI 0xe0
c8fe38ae 56
c8fe38ae 57/*
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58 * Local APIC TPR priority vector levels:
59 *
60 * 0xff (255) +-------------+
61 * | | 15 (IPIs: Xcpustop, Xspuriousint)
62 * 0xf0 (240) +-------------+
63 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
64 * 0xe0 (224) +-------------+
65 * | | 13
66 * 0xd0 (208) +-------------+
67 * | | 12
68 * 0xc0 (192) +-------------+
69 * | | 11
70 * 0xb0 (176) +-------------+
71 * | | 10
72 * 0xa0 (160) +-------------+
73 * | | 9
74 * 0x90 (144) +-------------+
75 * | | 8 (syscall at 0x80)
76 * 0x80 (128) +-------------+
77 * | | 7
78 * 0x70 (112) +-------------+
79 * | | 6
80 * 0x60 (96) +-------------+
81 * | | 5
82 * 0x50 (80) +-------------+
83 * | | 4
84 * 0x40 (64) +-------------+
85 * | | 3
86 * 0x30 (48) +-------------+
87 * | | 2 (hardware INTs)
88 * 0x20 (32) +-------------+
89 * | | 1 (exceptions, traps, etc.)
90 * 0x10 (16) +-------------+
91 * | | 0 (exceptions, traps, etc.)
92 * 0x00 (0) +-------------+
c8fe38ae 93 */
617a6d43 94#define TPR_STEP 0x10
c8fe38ae 95
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96/* Local APIC Task Priority Register */
97#define TPR_IPI (IDT_OFFSET_IPI - 1)
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98
99
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100/*
101 * IPI group1
102 */
103#define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
c8fe38ae 104
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105/* TLB shootdowns */
106#define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
c8fe38ae 107
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108/* IPI group1 1: unused (was inter-cpu clock handling) */
109/* IPI group1 2: unused (was inter-cpu rendezvous) */
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110
111/* IPIQ rendezvous */
617a6d43 112#define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
c8fe38ae 113
46d4e165 114/* TIMER rendezvous */
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115#define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
116
117/* IPI group1 5 ~ 15: unused */
46d4e165 118
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119
120/*
617a6d43 121 * IPI group2
c8fe38ae 122 */
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123#define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
124
125/* IPI to signal CPUs to stop and wait for another CPU to restart them */
126#define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
127
128/* IPI group2 1 ~ 14: unused */
129
130/* NOTE: this vector MUST be xxxx1111 */
131#define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
c8fe38ae 132
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133#ifndef LOCORE
134
135/*
136 * Type of the first (asm) part of an interrupt handler.
137 */
138#ifndef JG_defined_inthand_t
139#define JG_defined_inthand_t
140typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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141#endif
142
143#define IDTVEC(name) __CONCAT(X,name)
144
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145inthand_t
146 Xspuriousint, /* handle APIC "spurious INTs" */
147 Xtimer; /* handle LAPIC timer INT */
148
149#ifdef SMP
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150inthand_t
151 Xinvltlb, /* TLB shootdowns */
c8fe38ae 152 Xcpustop, /* CPU stops & waits for another CPU to restart it */
c8fe38ae 153 Xipiq; /* handle lwkt_send_ipiq() requests */
9a4bd8f3 154#endif
c8fe38ae 155
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156#endif /* LOCORE */
157
158#endif /* _KERNEL */
159
57a9c56b 160#endif /* !_ARCH_INTR_MACHDEP_H_ */