jme: Put TX related stuffs into struct jme_txdata
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
CommitLineData
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1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
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28 */
29
8a0620e4 30#include "opt_ifpoll.h"
93bfe1b8 31#include "opt_jme.h"
9de40864 32
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33#include <sys/param.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/interrupt.h>
38#include <sys/malloc.h>
39#include <sys/proc.h>
40#include <sys/rman.h>
41#include <sys/serialize.h>
31f0d5a2 42#include <sys/serialize2.h>
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43#include <sys/socket.h>
44#include <sys/sockio.h>
45#include <sys/sysctl.h>
46
47#include <net/ethernet.h>
48#include <net/if.h>
49#include <net/bpf.h>
50#include <net/if_arp.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
8a0620e4 53#include <net/if_poll.h>
76fbb0b9 54#include <net/ifq_var.h>
24dd1705 55#include <net/toeplitz.h>
a6acc6e2 56#include <net/toeplitz2.h>
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57#include <net/vlan/if_vlan_var.h>
58#include <net/vlan/if_vlan_ether.h>
59
1bedd927
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60#include <netinet/ip.h>
61#include <netinet/tcp.h>
a6acc6e2 62
76fbb0b9 63#include <dev/netif/mii_layer/miivar.h>
dbe37f03 64#include <dev/netif/mii_layer/jmphyreg.h>
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65
66#include <bus/pci/pcireg.h>
67#include <bus/pci/pcivar.h>
68#include <bus/pci/pcidevs.h>
69
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70#include <dev/netif/jme/if_jmereg.h>
71#include <dev/netif/jme/if_jmevar.h>
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72
73#include "miibus_if.h"
74
29890f78
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75#define JME_TX_SERIALIZE 1
76#define JME_RX_SERIALIZE 2
77
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78#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
79
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80#ifdef JME_RSS_DEBUG
81#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
82do { \
66f75939 83 if ((sc)->jme_rss_debug >= (lvl)) \
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84 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
85} while (0)
86#else /* !JME_RSS_DEBUG */
87#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
88#endif /* JME_RSS_DEBUG */
89
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90static int jme_probe(device_t);
91static int jme_attach(device_t);
92static int jme_detach(device_t);
93static int jme_shutdown(device_t);
94static int jme_suspend(device_t);
95static int jme_resume(device_t);
96
97static int jme_miibus_readreg(device_t, int, int);
98static int jme_miibus_writereg(device_t, int, int, int);
99static void jme_miibus_statchg(device_t);
100
101static void jme_init(void *);
102static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
103static void jme_start(struct ifnet *);
104static void jme_watchdog(struct ifnet *);
105static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
106static int jme_mediachange(struct ifnet *);
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107#ifdef IFPOLL_ENABLE
108static void jme_npoll(struct ifnet *, struct ifpoll_info *);
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109static void jme_npoll_status(struct ifnet *, int);
110static void jme_npoll_rx(struct ifnet *, void *, int);
111static void jme_npoll_tx(struct ifnet *, void *, int);
9de40864 112#endif
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113static void jme_serialize(struct ifnet *, enum ifnet_serialize);
114static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
115static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
116#ifdef INVARIANTS
117static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
118 boolean_t);
119#endif
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120
121static void jme_intr(void *);
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122static void jme_msix_tx(void *);
123static void jme_msix_rx(void *);
e0009afb 124static void jme_msix_status(void *);
9b99c84f 125static void jme_txeof(struct jme_txdata *);
dea2452a 126static void jme_rxeof(struct jme_rxdata *, int);
4447c752 127static void jme_rx_intr(struct jme_softc *, uint32_t);
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128static void jme_enable_intr(struct jme_softc *);
129static void jme_disable_intr(struct jme_softc *);
de437f82 130static void jme_rx_restart(struct jme_softc *, uint32_t);
76fbb0b9 131
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132static int jme_msix_setup(device_t);
133static void jme_msix_teardown(device_t, int);
134static int jme_intr_setup(device_t);
135static void jme_intr_teardown(device_t);
136static void jme_msix_try_alloc(device_t);
137static void jme_msix_free(device_t);
138static int jme_intr_alloc(device_t);
139static void jme_intr_free(device_t);
76fbb0b9 140static int jme_dma_alloc(struct jme_softc *);
0b3414d9 141static void jme_dma_free(struct jme_softc *);
dea2452a 142static int jme_init_rx_ring(struct jme_rxdata *);
9b99c84f 143static void jme_init_tx_ring(struct jme_txdata *);
76fbb0b9 144static void jme_init_ssb(struct jme_softc *);
dea2452a 145static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
9b99c84f 146static int jme_encap(struct jme_txdata *, struct mbuf **);
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147static void jme_rxpkt(struct jme_rxdata *);
148static int jme_rxring_dma_alloc(struct jme_rxdata *);
149static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
064b75ed 150static int jme_rxbuf_dma_filter(void *, bus_addr_t);
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151
152static void jme_tick(void *);
153static void jme_stop(struct jme_softc *);
154static void jme_reset(struct jme_softc *);
58880b0d 155static void jme_set_msinum(struct jme_softc *);
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156static void jme_set_vlan(struct jme_softc *);
157static void jme_set_filter(struct jme_softc *);
158static void jme_stop_tx(struct jme_softc *);
159static void jme_stop_rx(struct jme_softc *);
160static void jme_mac_config(struct jme_softc *);
161static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
162static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
163static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
164#ifdef notyet
165static void jme_setwol(struct jme_softc *);
166static void jme_setlinkspeed(struct jme_softc *);
167#endif
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168static void jme_set_tx_coal(struct jme_softc *);
169static void jme_set_rx_coal(struct jme_softc *);
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170static void jme_enable_rss(struct jme_softc *);
171static void jme_disable_rss(struct jme_softc *);
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172static void jme_serialize_skipmain(struct jme_softc *);
173static void jme_deserialize_skipmain(struct jme_softc *);
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174
175static void jme_sysctl_node(struct jme_softc *);
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176static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
177static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
178static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
179static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
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180#ifdef IFPOLL_ENABLE
181static int jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
182static int jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
183#endif
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184
185/*
186 * Devices supported by this driver.
187 */
188static const struct jme_dev {
189 uint16_t jme_vendorid;
190 uint16_t jme_deviceid;
3a5f3f36 191 uint32_t jme_caps;
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192 const char *jme_name;
193} jme_devs[] = {
44e8c66c 194 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
3a5f3f36 195 JME_CAP_JUMBO,
76fbb0b9 196 "JMicron Inc, JMC250 Gigabit Ethernet" },
44e8c66c 197 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
3a5f3f36 198 JME_CAP_FASTETH,
76fbb0b9 199 "JMicron Inc, JMC260 Fast Ethernet" },
3a5f3f36 200 { 0, 0, 0, NULL }
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201};
202
203static device_method_t jme_methods[] = {
204 /* Device interface. */
205 DEVMETHOD(device_probe, jme_probe),
206 DEVMETHOD(device_attach, jme_attach),
207 DEVMETHOD(device_detach, jme_detach),
208 DEVMETHOD(device_shutdown, jme_shutdown),
209 DEVMETHOD(device_suspend, jme_suspend),
210 DEVMETHOD(device_resume, jme_resume),
211
212 /* Bus interface. */
213 DEVMETHOD(bus_print_child, bus_generic_print_child),
214 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215
216 /* MII interface. */
217 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
218 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
219 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
220
221 { NULL, NULL }
222};
223
224static driver_t jme_driver = {
225 "jme",
226 jme_methods,
227 sizeof(struct jme_softc)
228};
229
230static devclass_t jme_devclass;
231
232DECLARE_DUMMY_MODULE(if_jme);
233MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
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234DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
235DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
76fbb0b9 236
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237static const struct {
238 uint32_t jme_coal;
239 uint32_t jme_comp;
58880b0d 240 uint32_t jme_empty;
4447c752 241} jme_rx_status[JME_NRXRING_MAX] = {
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242 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
243 INTR_RXQ0_DESC_EMPTY },
244 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
245 INTR_RXQ1_DESC_EMPTY },
246 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
247 INTR_RXQ2_DESC_EMPTY },
248 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
249 INTR_RXQ3_DESC_EMPTY }
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250};
251
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252static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
253static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
6afef6ab 254static int jme_rx_ring_count = 0;
3eba890a 255static int jme_msi_enable = 1;
58880b0d 256static int jme_msix_enable = 1;
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257
258TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
259TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
413d06bb 260TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
3eba890a 261TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
58880b0d 262TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
83b03786 263
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264static __inline void
265jme_setup_rxdesc(struct jme_rxdesc *rxd)
266{
267 struct jme_desc *desc;
268
269 desc = rxd->rx_desc;
270 desc->buflen = htole32(MCLBYTES);
271 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
272 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
273 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
274}
275
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276/*
277 * Read a PHY register on the MII of the JMC250.
278 */
279static int
280jme_miibus_readreg(device_t dev, int phy, int reg)
281{
282 struct jme_softc *sc = device_get_softc(dev);
283 uint32_t val;
284 int i;
285
286 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 287 if (sc->jme_caps & JME_CAP_FPGA) {
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288 if (phy == 0)
289 return (0);
290 } else {
291 if (sc->jme_phyaddr != phy)
292 return (0);
293 }
294
295 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
296 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
297
298 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
299 DELAY(1);
300 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
301 break;
302 }
303 if (i == 0) {
304 device_printf(sc->jme_dev, "phy read timeout: "
305 "phy %d, reg %d\n", phy, reg);
306 return (0);
307 }
308
309 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
310}
311
312/*
313 * Write a PHY register on the MII of the JMC250.
314 */
315static int
316jme_miibus_writereg(device_t dev, int phy, int reg, int val)
317{
318 struct jme_softc *sc = device_get_softc(dev);
319 int i;
320
321 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 322 if (sc->jme_caps & JME_CAP_FPGA) {
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323 if (phy == 0)
324 return (0);
325 } else {
326 if (sc->jme_phyaddr != phy)
327 return (0);
328 }
329
330 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
331 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
332 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
333
334 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
335 DELAY(1);
336 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
337 break;
338 }
339 if (i == 0) {
340 device_printf(sc->jme_dev, "phy write timeout: "
341 "phy %d, reg %d\n", phy, reg);
342 }
343
344 return (0);
345}
346
347/*
348 * Callback from MII layer when media changes.
349 */
350static void
351jme_miibus_statchg(device_t dev)
352{
353 struct jme_softc *sc = device_get_softc(dev);
354 struct ifnet *ifp = &sc->arpcom.ac_if;
9b99c84f 355 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
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356 struct mii_data *mii;
357 struct jme_txdesc *txd;
358 bus_addr_t paddr;
4447c752 359 int i, r;
76fbb0b9 360
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361 if (sc->jme_in_tick)
362 jme_serialize_skipmain(sc);
31f0d5a2 363 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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364
365 if ((ifp->if_flags & IFF_RUNNING) == 0)
cccc3955 366 goto done;
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367
368 mii = device_get_softc(sc->jme_miibus);
369
cccc3955 370 sc->jme_has_link = FALSE;
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371 if ((mii->mii_media_status & IFM_AVALID) != 0) {
372 switch (IFM_SUBTYPE(mii->mii_media_active)) {
373 case IFM_10_T:
374 case IFM_100_TX:
cccc3955 375 sc->jme_has_link = TRUE;
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376 break;
377 case IFM_1000_T:
ec7e787b 378 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 379 break;
cccc3955 380 sc->jme_has_link = TRUE;
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381 break;
382 default:
383 break;
384 }
385 }
386
387 /*
388 * Disabling Rx/Tx MACs have a side-effect of resetting
389 * JME_TXNDA/JME_RXNDA register to the first address of
390 * Tx/Rx descriptor address. So driver should reset its
391 * internal procucer/consumer pointer and reclaim any
392 * allocated resources. Note, just saving the value of
393 * JME_TXNDA and JME_RXNDA registers before stopping MAC
394 * and restoring JME_TXNDA/JME_RXNDA register is not
395 * sufficient to make sure correct MAC state because
396 * stopping MAC operation can take a while and hardware
397 * might have updated JME_TXNDA/JME_RXNDA registers
398 * during the stop operation.
399 */
400
401 /* Disable interrupts */
402 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
403
404 /* Stop driver */
405 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
406 ifp->if_timer = 0;
407 callout_stop(&sc->jme_tick_ch);
408
409 /* Stop receiver/transmitter. */
410 jme_stop_rx(sc);
411 jme_stop_tx(sc);
412
7b040092 413 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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414 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
415
dea2452a 416 jme_rxeof(rdata, -1);
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417 if (rdata->jme_rxhead != NULL)
418 m_freem(rdata->jme_rxhead);
dea2452a 419 JME_RXCHAIN_RESET(rdata);
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420
421 /*
422 * Reuse configured Rx descriptors and reset
423 * procuder/consumer index.
424 */
425 rdata->jme_rx_cons = 0;
426 }
6afef6ab 427 if (JME_ENABLE_HWRSS(sc))
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428 jme_enable_rss(sc);
429 else
430 jme_disable_rss(sc);
76fbb0b9 431
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432 jme_txeof(tdata);
433 if (tdata->jme_tx_cnt != 0) {
76fbb0b9 434 /* Remove queued packets for transmit. */
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435 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
436 txd = &tdata->jme_txdesc[i];
76fbb0b9 437 if (txd->tx_m != NULL) {
9b99c84f 438 bus_dmamap_unload( tdata->jme_tx_tag,
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439 txd->tx_dmamap);
440 m_freem(txd->tx_m);
441 txd->tx_m = NULL;
442 txd->tx_ndesc = 0;
443 ifp->if_oerrors++;
444 }
445 }
446 }
9b99c84f 447 jme_init_tx_ring(tdata);
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448
449 /* Initialize shadow status block. */
450 jme_init_ssb(sc);
451
452 /* Program MAC with resolved speed/duplex/flow-control. */
cccc3955 453 if (sc->jme_has_link) {
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454 jme_mac_config(sc);
455
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456 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
457
458 /* Set Tx ring address to the hardware. */
9b99c84f 459 paddr = tdata->jme_tx_ring_paddr;
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460 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
461 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
462
7b040092 463 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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464 CSR_WRITE_4(sc, JME_RXCSR,
465 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
466
467 /* Set Rx ring address to the hardware. */
468 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
469 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
470 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
471 }
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472
473 /* Restart receiver/transmitter. */
474 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
475 RXCSR_RXQ_START);
476 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
477 }
478
479 ifp->if_flags |= IFF_RUNNING;
480 ifp->if_flags &= ~IFF_OACTIVE;
481 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
482
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483#ifdef IFPOLL_ENABLE
484 if (!(ifp->if_flags & IFF_NPOLLING))
9de40864 485#endif
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486 /* Reenable interrupts. */
487 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
cccc3955
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488
489done:
490 if (sc->jme_in_tick)
491 jme_deserialize_skipmain(sc);
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492}
493
494/*
495 * Get the current interface media status.
496 */
497static void
498jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
499{
500 struct jme_softc *sc = ifp->if_softc;
501 struct mii_data *mii = device_get_softc(sc->jme_miibus);
502
31f0d5a2 503 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
504
505 mii_pollstat(mii);
506 ifmr->ifm_status = mii->mii_media_status;
507 ifmr->ifm_active = mii->mii_media_active;
508}
509
510/*
511 * Set hardware to newly-selected media.
512 */
513static int
514jme_mediachange(struct ifnet *ifp)
515{
516 struct jme_softc *sc = ifp->if_softc;
517 struct mii_data *mii = device_get_softc(sc->jme_miibus);
518 int error;
519
31f0d5a2 520 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
521
522 if (mii->mii_instance != 0) {
523 struct mii_softc *miisc;
524
525 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
526 mii_phy_reset(miisc);
527 }
528 error = mii_mediachg(mii);
529
530 return (error);
531}
532
533static int
534jme_probe(device_t dev)
535{
536 const struct jme_dev *sp;
537 uint16_t vid, did;
538
539 vid = pci_get_vendor(dev);
540 did = pci_get_device(dev);
541 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
542 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
3a5f3f36
SZ
543 struct jme_softc *sc = device_get_softc(dev);
544
545 sc->jme_caps = sp->jme_caps;
76fbb0b9 546 device_set_desc(dev, sp->jme_name);
76fbb0b9
SZ
547 return (0);
548 }
549 }
550 return (ENXIO);
551}
552
553static int
554jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
555{
556 uint32_t reg;
557 int i;
558
559 *val = 0;
560 for (i = JME_TIMEOUT; i > 0; i--) {
561 reg = CSR_READ_4(sc, JME_SMBCSR);
562 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
563 break;
564 DELAY(1);
565 }
566
567 if (i == 0) {
568 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
569 return (ETIMEDOUT);
570 }
571
572 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
573 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
574 for (i = JME_TIMEOUT; i > 0; i--) {
575 DELAY(1);
576 reg = CSR_READ_4(sc, JME_SMBINTF);
577 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
578 break;
579 }
580
581 if (i == 0) {
582 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
583 return (ETIMEDOUT);
584 }
585
586 reg = CSR_READ_4(sc, JME_SMBINTF);
587 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
588
589 return (0);
590}
591
592static int
593jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
594{
595 uint8_t fup, reg, val;
596 uint32_t offset;
597 int match;
598
599 offset = 0;
600 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
601 fup != JME_EEPROM_SIG0)
602 return (ENOENT);
603 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
604 fup != JME_EEPROM_SIG1)
605 return (ENOENT);
606 match = 0;
607 do {
608 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
609 break;
09927fe6
SZ
610 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
611 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
76fbb0b9
SZ
612 if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
613 break;
614 if (reg >= JME_PAR0 &&
615 reg < JME_PAR0 + ETHER_ADDR_LEN) {
616 if (jme_eeprom_read_byte(sc, offset + 2,
617 &val) != 0)
618 break;
619 eaddr[reg - JME_PAR0] = val;
620 match++;
621 }
622 }
09927fe6
SZ
623 /* Check for the end of EEPROM descriptor. */
624 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
625 break;
76fbb0b9
SZ
626 /* Try next eeprom descriptor. */
627 offset += JME_EEPROM_DESC_BYTES;
628 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
629
630 if (match == ETHER_ADDR_LEN)
631 return (0);
632
633 return (ENOENT);
634}
635
636static void
637jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
638{
639 uint32_t par0, par1;
640
641 /* Read station address. */
642 par0 = CSR_READ_4(sc, JME_PAR0);
643 par1 = CSR_READ_4(sc, JME_PAR1);
644 par1 &= 0xFFFF;
645 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
646 device_printf(sc->jme_dev,
647 "generating fake ethernet address.\n");
648 par0 = karc4random();
649 /* Set OUI to JMicron. */
650 eaddr[0] = 0x00;
651 eaddr[1] = 0x1B;
652 eaddr[2] = 0x8C;
653 eaddr[3] = (par0 >> 16) & 0xff;
654 eaddr[4] = (par0 >> 8) & 0xff;
655 eaddr[5] = par0 & 0xff;
656 } else {
657 eaddr[0] = (par0 >> 0) & 0xFF;
658 eaddr[1] = (par0 >> 8) & 0xFF;
659 eaddr[2] = (par0 >> 16) & 0xFF;
660 eaddr[3] = (par0 >> 24) & 0xFF;
661 eaddr[4] = (par1 >> 0) & 0xFF;
662 eaddr[5] = (par1 >> 8) & 0xFF;
663 }
664}
665
666static int
667jme_attach(device_t dev)
668{
669 struct jme_softc *sc = device_get_softc(dev);
670 struct ifnet *ifp = &sc->arpcom.ac_if;
671 uint32_t reg;
b249905b
SZ
672 uint16_t did;
673 uint8_t pcie_ptr, rev;
a3fede62 674 int error = 0, i, j, rx_desc_cnt, coal_max;
76fbb0b9 675 uint8_t eaddr[ETHER_ADDR_LEN];
8a0620e4
SZ
676#ifdef IFPOLL_ENABLE
677 int offset, offset_def;
678#endif
76fbb0b9 679
9b99c84f
SZ
680 /*
681 * Initialize serializers
682 */
31f0d5a2 683 lwkt_serialize_init(&sc->jme_serialize);
9b99c84f 684 lwkt_serialize_init(&sc->jme_cdata.jme_tx_data.jme_tx_serialize);
31f0d5a2
SZ
685 for (i = 0; i < JME_NRXRING_MAX; ++i) {
686 lwkt_serialize_init(
687 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
688 }
689
9b99c84f
SZ
690 /*
691 * Get # of RX ring descriptors
692 */
7b040092 693 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
1cc217a9 694 jme_rx_desc_count);
7b040092
SZ
695 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
696 if (rx_desc_cnt > JME_NDESC_MAX)
697 rx_desc_cnt = JME_NDESC_MAX;
69325526 698
9b99c84f
SZ
699 /*
700 * Get # of TX ring descriptors
701 */
702 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt =
703 device_getenv_int(dev, "tx_desc_count", jme_tx_desc_count);
704 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt =
705 roundup(sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, JME_NDESC_ALIGN);
706 if (sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt > JME_NDESC_MAX)
707 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = JME_NDESC_MAX;
83b03786 708
9389fe19 709 /*
9b99c84f 710 * Get # of RX rings
9389fe19 711 */
7b040092 712 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
1cc217a9 713 jme_rx_ring_count);
7b040092
SZ
714 sc->jme_cdata.jme_rx_ring_cnt =
715 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
4447c752 716
9b99c84f
SZ
717 /*
718 * Initialize serializer array
719 */
31f0d5a2
SZ
720 i = 0;
721 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
29890f78
SZ
722
723 KKASSERT(i == JME_TX_SERIALIZE);
9b99c84f
SZ
724 sc->jme_serialize_arr[i++] =
725 &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
29890f78
SZ
726
727 KKASSERT(i == JME_RX_SERIALIZE);
7b040092 728 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
31f0d5a2
SZ
729 sc->jme_serialize_arr[i++] =
730 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
731 }
732 KKASSERT(i <= JME_NSERIALIZE);
733 sc->jme_serialize_cnt = i;
734
9b99c84f
SZ
735 /*
736 * Setup TX ring specific data
737 */
738 sc->jme_cdata.jme_tx_data.jme_sc = sc;
739
740 /*
741 * Setup RX rings specific data
742 */
7b040092 743 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
58880b0d
SZ
744 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
745
746 rdata->jme_sc = sc;
747 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
748 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
749 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
750 rdata->jme_rx_idx = i;
7b040092 751 rdata->jme_rx_desc_cnt = rx_desc_cnt;
58880b0d
SZ
752 }
753
76fbb0b9 754 sc->jme_dev = dev;
b249905b
SZ
755 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
756
76fbb0b9
SZ
757 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
758
759 callout_init(&sc->jme_tick_ch);
760
761#ifndef BURN_BRIDGES
762 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
763 uint32_t irq, mem;
764
765 irq = pci_read_config(dev, PCIR_INTLINE, 4);
766 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
767
768 device_printf(dev, "chip is in D%d power mode "
769 "-- setting to D0\n", pci_get_powerstate(dev));
770
771 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
772
773 pci_write_config(dev, PCIR_INTLINE, irq, 4);
774 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
775 }
776#endif /* !BURN_BRIDGE */
777
778 /* Enable bus mastering */
779 pci_enable_busmaster(dev);
780
781 /*
782 * Allocate IO memory
783 *
784 * JMC250 supports both memory mapped and I/O register space
785 * access. Because I/O register access should use different
786 * BARs to access registers it's waste of time to use I/O
787 * register spce access. JMC250 uses 16K to map entire memory
788 * space.
789 */
790 sc->jme_mem_rid = JME_PCIR_BAR;
791 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
792 &sc->jme_mem_rid, RF_ACTIVE);
793 if (sc->jme_mem_res == NULL) {
794 device_printf(dev, "can't allocate IO memory\n");
795 return ENXIO;
796 }
797 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
798 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
799
800 /*
801 * Allocate IRQ
802 */
58880b0d
SZ
803 error = jme_intr_alloc(dev);
804 if (error)
76fbb0b9 805 goto fail;
76fbb0b9
SZ
806
807 /*
b249905b 808 * Extract revisions
76fbb0b9
SZ
809 */
810 reg = CSR_READ_4(sc, JME_CHIPMODE);
811 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
812 CHIPMODE_NOT_FPGA) {
ec7e787b 813 sc->jme_caps |= JME_CAP_FPGA;
76fbb0b9 814 if (bootverbose) {
b249905b 815 device_printf(dev, "FPGA revision: 0x%04x\n",
76fbb0b9
SZ
816 (reg & CHIPMODE_FPGA_REV_MASK) >>
817 CHIPMODE_FPGA_REV_SHIFT);
818 }
819 }
820
b249905b
SZ
821 /* NOTE: FM revision is put in the upper 4 bits */
822 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
823 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
824 if (bootverbose)
825 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
826
827 did = pci_get_device(dev);
828 switch (did) {
829 case PCI_PRODUCT_JMICRON_JMC250:
830 if (rev == JME_REV1_A2)
831 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
832 break;
833
834 case PCI_PRODUCT_JMICRON_JMC260:
835 if (rev == JME_REV2)
836 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
837 break;
838
839 default:
ed20d0e3 840 panic("unknown device id 0x%04x", did);
b249905b
SZ
841 }
842 if (rev >= JME_REV2) {
843 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
844 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
845 GHC_TXMAC_CLKSRC_1000;
846 }
847
76fbb0b9
SZ
848 /* Reset the ethernet controller. */
849 jme_reset(sc);
850
58880b0d
SZ
851 /* Map MSI/MSI-X vectors */
852 jme_set_msinum(sc);
853
76fbb0b9
SZ
854 /* Get station address. */
855 reg = CSR_READ_4(sc, JME_SMBCSR);
856 if (reg & SMBCSR_EEPROM_PRESENT)
857 error = jme_eeprom_macaddr(sc, eaddr);
858 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
859 if (error != 0 && (bootverbose)) {
860 device_printf(dev, "ethernet hardware address "
861 "not found in EEPROM.\n");
862 }
863 jme_reg_macaddr(sc, eaddr);
864 }
865
866 /*
867 * Save PHY address.
868 * Integrated JR0211 has fixed PHY address whereas FPGA version
869 * requires PHY probing to get correct PHY address.
870 */
ec7e787b 871 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
76fbb0b9
SZ
872 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
873 GPREG0_PHY_ADDR_MASK;
874 if (bootverbose) {
875 device_printf(dev, "PHY is at address %d.\n",
876 sc->jme_phyaddr);
877 }
878 } else {
879 sc->jme_phyaddr = 0;
880 }
881
882 /* Set max allowable DMA size. */
883 pcie_ptr = pci_get_pciecap_ptr(dev);
884 if (pcie_ptr != 0) {
885 uint16_t ctrl;
886
ec7e787b 887 sc->jme_caps |= JME_CAP_PCIE;
76fbb0b9
SZ
888 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
889 if (bootverbose) {
890 device_printf(dev, "Read request size : %d bytes.\n",
891 128 << ((ctrl >> 12) & 0x07));
892 device_printf(dev, "TLP payload size : %d bytes.\n",
893 128 << ((ctrl >> 5) & 0x07));
894 }
895 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
896 case PCIEM_DEVCTL_MAX_READRQ_128:
897 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
898 break;
899 case PCIEM_DEVCTL_MAX_READRQ_256:
900 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
901 break;
902 default:
903 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
904 break;
905 }
906 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
907 } else {
908 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
909 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
910 }
911
912#ifdef notyet
913 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
ec7e787b 914 sc->jme_caps |= JME_CAP_PMCAP;
76fbb0b9
SZ
915#endif
916
8a0620e4
SZ
917#ifdef IFPOLL_ENABLE
918 /*
919 * NPOLLING RX CPU offset
920 */
921 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
922 offset = 0;
923 } else {
924 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
925 device_get_unit(dev)) % ncpus2;
926 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
927 if (offset >= ncpus2 ||
928 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
929 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
930 offset, offset_def);
931 offset = offset_def;
932 }
933 }
934 sc->jme_npoll_rxoff = offset;
935
936 /*
937 * NPOLLING TX CPU offset
938 */
939 offset_def = sc->jme_npoll_rxoff;
940 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
941 if (offset >= ncpus2) {
942 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
943 offset, offset_def);
944 offset = offset_def;
945 }
946 sc->jme_npoll_txoff = offset;
947#endif
948
76fbb0b9 949 /*
a3fede62
SZ
950 * Set default coalesce valves
951 */
952 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
953 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
954 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
955 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
956
957 /*
958 * Adjust coalesce valves, in case that the number of TX/RX
959 * descs are set to small values by users.
960 *
961 * NOTE: coal_max will not be zero, since number of descs
962 * must aligned by JME_NDESC_ALIGN (16 currently)
963 */
9b99c84f 964 coal_max = sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt / 2;
a3fede62
SZ
965 if (coal_max < sc->jme_tx_coal_pkt)
966 sc->jme_tx_coal_pkt = coal_max;
967
968 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2;
969 if (coal_max < sc->jme_rx_coal_pkt)
970 sc->jme_rx_coal_pkt = coal_max;
971
972 /*
76fbb0b9
SZ
973 * Create sysctl tree
974 */
975 jme_sysctl_node(sc);
976
977 /* Allocate DMA stuffs */
978 error = jme_dma_alloc(sc);
979 if (error)
980 goto fail;
981
982 ifp->if_softc = sc;
983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
984 ifp->if_init = jme_init;
985 ifp->if_ioctl = jme_ioctl;
986 ifp->if_start = jme_start;
8a0620e4
SZ
987#ifdef IFPOLL_ENABLE
988 ifp->if_npoll = jme_npoll;
9de40864 989#endif
76fbb0b9 990 ifp->if_watchdog = jme_watchdog;
31f0d5a2
SZ
991 ifp->if_serialize = jme_serialize;
992 ifp->if_deserialize = jme_deserialize;
993 ifp->if_tryserialize = jme_tryserialize;
994#ifdef INVARIANTS
995 ifp->if_serialize_assert = jme_serialize_assert;
996#endif
b020bb10 997 ifq_set_maxlen(&ifp->if_snd,
9b99c84f 998 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt - JME_TXD_RSVD);
76fbb0b9
SZ
999 ifq_set_ready(&ifp->if_snd);
1000
1001 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
1002 ifp->if_capabilities = IFCAP_HWCSUM |
1bedd927 1003 IFCAP_TSO |
76fbb0b9
SZ
1004 IFCAP_VLAN_MTU |
1005 IFCAP_VLAN_HWTAGGING;
7b040092 1006 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
d585233c 1007 ifp->if_capabilities |= IFCAP_RSS;
76fbb0b9
SZ
1008 ifp->if_capenable = ifp->if_capabilities;
1009
3d2aeb15
SZ
1010 /*
1011 * Disable TXCSUM by default to improve bulk data
1012 * transmit performance (+20Mbps improvement).
1013 */
1014 ifp->if_capenable &= ~IFCAP_TXCSUM;
1015
1016 if (ifp->if_capenable & IFCAP_TXCSUM)
1bedd927
SZ
1017 ifp->if_hwassist |= JME_CSUM_FEATURES;
1018 ifp->if_hwassist |= CSUM_TSO;
3d2aeb15 1019
76fbb0b9
SZ
1020 /* Set up MII bus. */
1021 error = mii_phy_probe(dev, &sc->jme_miibus,
1022 jme_mediachange, jme_mediastatus);
1023 if (error) {
1024 device_printf(dev, "no PHY found!\n");
1025 goto fail;
1026 }
1027
1028 /*
1029 * Save PHYADDR for FPGA mode PHY.
1030 */
ec7e787b 1031 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ
1032 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1033
1034 if (mii->mii_instance != 0) {
1035 struct mii_softc *miisc;
1036
1037 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1038 if (miisc->mii_phy != 0) {
1039 sc->jme_phyaddr = miisc->mii_phy;
1040 break;
1041 }
1042 }
1043 if (sc->jme_phyaddr != 0) {
1044 device_printf(sc->jme_dev,
1045 "FPGA PHY is at %d\n", sc->jme_phyaddr);
1046 /* vendor magic. */
dbe37f03
SZ
1047 jme_miibus_writereg(dev, sc->jme_phyaddr,
1048 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
1049
ad22907f 1050 /* XXX should we clear JME_WA_EXTFIFO */
76fbb0b9
SZ
1051 }
1052 }
1053 }
1054
1055 ether_ifattach(ifp, eaddr, NULL);
1056
1057 /* Tell the upper layer(s) we support long frames. */
1058 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1059
58880b0d 1060 error = jme_intr_setup(dev);
76fbb0b9 1061 if (error) {
76fbb0b9
SZ
1062 ether_ifdetach(ifp);
1063 goto fail;
1064 }
1065
76fbb0b9
SZ
1066 return 0;
1067fail:
1068 jme_detach(dev);
1069 return (error);
1070}
1071
1072static int
1073jme_detach(device_t dev)
1074{
1075 struct jme_softc *sc = device_get_softc(dev);
1076
1077 if (device_is_attached(dev)) {
1078 struct ifnet *ifp = &sc->arpcom.ac_if;
1079
31f0d5a2 1080 ifnet_serialize_all(ifp);
76fbb0b9 1081 jme_stop(sc);
58880b0d 1082 jme_intr_teardown(dev);
31f0d5a2 1083 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
1084
1085 ether_ifdetach(ifp);
1086 }
1087
1088 if (sc->jme_sysctl_tree != NULL)
1089 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1090
1091 if (sc->jme_miibus != NULL)
1092 device_delete_child(dev, sc->jme_miibus);
1093 bus_generic_detach(dev);
1094
58880b0d 1095 jme_intr_free(dev);
76fbb0b9
SZ
1096
1097 if (sc->jme_mem_res != NULL) {
1098 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1099 sc->jme_mem_res);
1100 }
1101
0b3414d9 1102 jme_dma_free(sc);
76fbb0b9
SZ
1103
1104 return (0);
1105}
1106
1107static void
1108jme_sysctl_node(struct jme_softc *sc)
1109{
760c056c 1110#ifdef JME_RSS_DEBUG
760c056c
SZ
1111 int r;
1112#endif
83b03786 1113
76fbb0b9
SZ
1114 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1115 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1116 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1117 device_get_nameunit(sc->jme_dev),
1118 CTLFLAG_RD, 0, "");
1119 if (sc->jme_sysctl_tree == NULL) {
1120 device_printf(sc->jme_dev, "can't add sysctl node\n");
1121 return;
1122 }
1123
1124 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1125 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1126 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1127 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
76fbb0b9
SZ
1128
1129 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1130 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1131 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1132 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
76fbb0b9
SZ
1133
1134 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1135 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1136 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1137 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
76fbb0b9
SZ
1138
1139 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1140 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1141 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1142 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
76fbb0b9 1143
83b03786
SZ
1144 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1145 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ
1146 "rx_desc_count", CTLFLAG_RD,
1147 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
83b03786
SZ
1148 0, "RX desc count");
1149 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1150 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
b020bb10 1151 "tx_desc_count", CTLFLAG_RD,
9b99c84f 1152 &sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt,
83b03786 1153 0, "TX desc count");
760c056c
SZ
1154 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1155 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ
1156 "rx_ring_count", CTLFLAG_RD,
1157 &sc->jme_cdata.jme_rx_ring_cnt,
760c056c 1158 0, "RX ring count");
8a0620e4 1159
760c056c
SZ
1160#ifdef JME_RSS_DEBUG
1161 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1162 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
24dd1705 1163 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
760c056c 1164 0, "RSS debug level");
7b040092 1165 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
955f266e 1166 char rx_ring_desc[32];
7b040092 1167
955f266e
SZ
1168 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1169 "rx_ring%d_pkt", r);
7b040092
SZ
1170 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1171 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
955f266e 1172 rx_ring_desc, CTLFLAG_RW,
7b040092 1173 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
955f266e
SZ
1174
1175 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1176 "rx_ring%d_emp", r);
1177 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1178 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1179 rx_ring_desc, CTLFLAG_RW,
1180 &sc->jme_cdata.jme_rx_data[r].jme_rx_emp,
1181 "# of time RX ring empty");
760c056c
SZ
1182 }
1183#endif
83b03786 1184
8a0620e4
SZ
1185#ifdef IFPOLL_ENABLE
1186 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1187 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1188 "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
1189 jme_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1190 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1191 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1192 "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
1193 jme_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1194#endif
76fbb0b9
SZ
1195}
1196
76fbb0b9
SZ
1197static int
1198jme_dma_alloc(struct jme_softc *sc)
1199{
9b99c84f 1200 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9 1201 struct jme_txdesc *txd;
1128a202 1202 bus_dmamem_t dmem;
ff7f3632 1203 int error, i, asize;
76fbb0b9 1204
9b99c84f
SZ
1205 tdata->jme_txdesc =
1206 kmalloc(tdata->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
83b03786 1207 M_DEVBUF, M_WAITOK | M_ZERO);
7b040092
SZ
1208 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1209 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1210
1211 rdata->jme_rxdesc =
1212 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
4447c752
SZ
1213 M_DEVBUF, M_WAITOK | M_ZERO);
1214 }
83b03786 1215
76fbb0b9
SZ
1216 /* Create parent ring tag. */
1217 error = bus_dma_tag_create(NULL,/* parent */
a7547dad
SZ
1218 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1219 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ
1220 BUS_SPACE_MAXADDR, /* highaddr */
1221 NULL, NULL, /* filter, filterarg */
1222 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1223 0, /* nsegments */
1224 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1225 0, /* flags */
1226 &sc->jme_cdata.jme_ring_tag);
1227 if (error) {
1228 device_printf(sc->jme_dev,
1229 "could not create parent ring DMA tag.\n");
1230 return error;
1231 }
1232
1233 /*
1234 * Create DMA stuffs for TX ring
1235 */
9b99c84f 1236 asize = roundup2(JME_TX_RING_SIZE(tdata), JME_TX_RING_ALIGN);
1128a202
SZ
1237 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1238 JME_TX_RING_ALIGN, 0,
0eb220ec 1239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1240 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9 1241 if (error) {
1128a202 1242 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
76fbb0b9
SZ
1243 return error;
1244 }
9b99c84f
SZ
1245 tdata->jme_tx_ring_tag = dmem.dmem_tag;
1246 tdata->jme_tx_ring_map = dmem.dmem_map;
1247 tdata->jme_tx_ring = dmem.dmem_addr;
1248 tdata->jme_tx_ring_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ
1249
1250 /*
1128a202 1251 * Create DMA stuffs for RX rings
76fbb0b9 1252 */
7b040092 1253 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1254 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752
SZ
1255 if (error)
1256 return error;
76fbb0b9 1257 }
76fbb0b9 1258
76fbb0b9
SZ
1259 /* Create parent buffer tag. */
1260 error = bus_dma_tag_create(NULL,/* parent */
1261 1, 0, /* algnmnt, boundary */
b249905b 1262 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ
1263 BUS_SPACE_MAXADDR, /* highaddr */
1264 NULL, NULL, /* filter, filterarg */
1265 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1266 0, /* nsegments */
1267 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1268 0, /* flags */
1269 &sc->jme_cdata.jme_buffer_tag);
1270 if (error) {
1271 device_printf(sc->jme_dev,
1272 "could not create parent buffer DMA tag.\n");
1273 return error;
1274 }
1275
1276 /*
1277 * Create DMA stuffs for shadow status block
1278 */
ff7f3632 1279 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1128a202 1280 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
0eb220ec 1281 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 1282 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9
SZ
1283 if (error) {
1284 device_printf(sc->jme_dev,
1128a202 1285 "could not create shadow status block.\n");
76fbb0b9
SZ
1286 return error;
1287 }
1128a202
SZ
1288 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1289 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1290 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1291 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ
1292
1293 /*
1294 * Create DMA stuffs for TX buffers
1295 */
1296
1297 /* Create tag for Tx buffers. */
1298 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1299 1, 0, /* algnmnt, boundary */
0eb220ec 1300 BUS_SPACE_MAXADDR, /* lowaddr */
76fbb0b9
SZ
1301 BUS_SPACE_MAXADDR, /* highaddr */
1302 NULL, NULL, /* filter, filterarg */
1bedd927 1303 JME_TSO_MAXSIZE, /* maxsize */
76fbb0b9 1304 JME_MAXTXSEGS, /* nsegments */
9d424cee
SZ
1305 JME_MAXSEGSIZE, /* maxsegsize */
1306 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
9b99c84f 1307 &tdata->jme_tx_tag);
76fbb0b9
SZ
1308 if (error != 0) {
1309 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1310 return error;
1311 }
1312
1313 /* Create DMA maps for Tx buffers. */
9b99c84f
SZ
1314 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
1315 txd = &tdata->jme_txdesc[i];
1316 error = bus_dmamap_create(tdata->jme_tx_tag,
9d424cee
SZ
1317 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1318 &txd->tx_dmamap);
76fbb0b9
SZ
1319 if (error) {
1320 int j;
1321
1322 device_printf(sc->jme_dev,
1323 "could not create %dth Tx dmamap.\n", i);
1324
1325 for (j = 0; j < i; ++j) {
9b99c84f
SZ
1326 txd = &tdata->jme_txdesc[j];
1327 bus_dmamap_destroy(tdata->jme_tx_tag,
76fbb0b9
SZ
1328 txd->tx_dmamap);
1329 }
9b99c84f
SZ
1330 bus_dma_tag_destroy(tdata->jme_tx_tag);
1331 tdata->jme_tx_tag = NULL;
76fbb0b9
SZ
1332 return error;
1333 }
1334 }
1335
1336 /*
1337 * Create DMA stuffs for RX buffers
1338 */
7b040092 1339 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1340 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752 1341 if (error)
76fbb0b9 1342 return error;
76fbb0b9
SZ
1343 }
1344 return 0;
1345}
1346
1347static void
0b3414d9 1348jme_dma_free(struct jme_softc *sc)
76fbb0b9 1349{
9b99c84f 1350 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ
1351 struct jme_txdesc *txd;
1352 struct jme_rxdesc *rxd;
4447c752
SZ
1353 struct jme_rxdata *rdata;
1354 int i, r;
76fbb0b9
SZ
1355
1356 /* Tx ring */
9b99c84f
SZ
1357 if (tdata->jme_tx_ring_tag != NULL) {
1358 bus_dmamap_unload(tdata->jme_tx_ring_tag,
1359 tdata->jme_tx_ring_map);
1360 bus_dmamem_free(tdata->jme_tx_ring_tag,
1361 tdata->jme_tx_ring, tdata->jme_tx_ring_map);
1362 bus_dma_tag_destroy(tdata->jme_tx_ring_tag);
1363 tdata->jme_tx_ring_tag = NULL;
76fbb0b9
SZ
1364 }
1365
1366 /* Rx ring */
7b040092 1367 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
1368 rdata = &sc->jme_cdata.jme_rx_data[r];
1369 if (rdata->jme_rx_ring_tag != NULL) {
1370 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1371 rdata->jme_rx_ring_map);
1372 bus_dmamem_free(rdata->jme_rx_ring_tag,
1373 rdata->jme_rx_ring,
1374 rdata->jme_rx_ring_map);
1375 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1376 rdata->jme_rx_ring_tag = NULL;
1377 }
76fbb0b9
SZ
1378 }
1379
1380 /* Tx buffers */
9b99c84f
SZ
1381 if (tdata->jme_tx_tag != NULL) {
1382 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
1383 txd = &tdata->jme_txdesc[i];
1384 bus_dmamap_destroy(tdata->jme_tx_tag, txd->tx_dmamap);
76fbb0b9 1385 }
9b99c84f
SZ
1386 bus_dma_tag_destroy(tdata->jme_tx_tag);
1387 tdata->jme_tx_tag = NULL;
76fbb0b9
SZ
1388 }
1389
1390 /* Rx buffers */
7b040092 1391 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
1392 rdata = &sc->jme_cdata.jme_rx_data[r];
1393 if (rdata->jme_rx_tag != NULL) {
7b040092 1394 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
1395 rxd = &rdata->jme_rxdesc[i];
1396 bus_dmamap_destroy(rdata->jme_rx_tag,
1397 rxd->rx_dmamap);
1398 }
1399 bus_dmamap_destroy(rdata->jme_rx_tag,
1400 rdata->jme_rx_sparemap);
1401 bus_dma_tag_destroy(rdata->jme_rx_tag);
1402 rdata->jme_rx_tag = NULL;
76fbb0b9 1403 }
76fbb0b9
SZ
1404 }
1405
1406 /* Shadow status block. */
1407 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1408 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1409 sc->jme_cdata.jme_ssb_map);
1410 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
560616bf 1411 sc->jme_cdata.jme_ssb_block,
76fbb0b9
SZ
1412 sc->jme_cdata.jme_ssb_map);
1413 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1414 sc->jme_cdata.jme_ssb_tag = NULL;
1415 }
1416
1417 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1418 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1419 sc->jme_cdata.jme_buffer_tag = NULL;
1420 }
1421 if (sc->jme_cdata.jme_ring_tag != NULL) {
1422 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1423 sc->jme_cdata.jme_ring_tag = NULL;
1424 }
83b03786 1425
9b99c84f
SZ
1426 if (tdata->jme_txdesc != NULL) {
1427 kfree(tdata->jme_txdesc, M_DEVBUF);
1428 tdata->jme_txdesc = NULL;
0b3414d9 1429 }
7b040092 1430 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
0b3414d9
SZ
1431 rdata = &sc->jme_cdata.jme_rx_data[r];
1432 if (rdata->jme_rxdesc != NULL) {
1433 kfree(rdata->jme_rxdesc, M_DEVBUF);
1434 rdata->jme_rxdesc = NULL;
83b03786
SZ
1435 }
1436 }
76fbb0b9
SZ
1437}
1438
1439/*
1440 * Make sure the interface is stopped at reboot time.
1441 */
1442static int
1443jme_shutdown(device_t dev)
1444{
1445 return jme_suspend(dev);
1446}
1447
1448#ifdef notyet
1449/*
1450 * Unlike other ethernet controllers, JMC250 requires
1451 * explicit resetting link speed to 10/100Mbps as gigabit
1452 * link will cunsume more power than 375mA.
1453 * Note, we reset the link speed to 10/100Mbps with
1454 * auto-negotiation but we don't know whether that operation
1455 * would succeed or not as we have no control after powering
1456 * off. If the renegotiation fail WOL may not work. Running
1457 * at 1Gbps draws more power than 375mA at 3.3V which is
1458 * specified in PCI specification and that would result in
1459 * complete shutdowning power to ethernet controller.
1460 *
1461 * TODO
1462 * Save current negotiated media speed/duplex/flow-control
1463 * to softc and restore the same link again after resuming.
1464 * PHY handling such as power down/resetting to 100Mbps
1465 * may be better handled in suspend method in phy driver.
1466 */
1467static void
1468jme_setlinkspeed(struct jme_softc *sc)
1469{
1470 struct mii_data *mii;
1471 int aneg, i;
1472
1473 JME_LOCK_ASSERT(sc);
1474
1475 mii = device_get_softc(sc->jme_miibus);
1476 mii_pollstat(mii);
1477 aneg = 0;
1478 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1479 switch IFM_SUBTYPE(mii->mii_media_active) {
1480 case IFM_10_T:
1481 case IFM_100_TX:
1482 return;
1483 case IFM_1000_T:
1484 aneg++;
1485 default:
1486 break;
1487 }
1488 }
1489 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1490 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1491 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1492 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1493 BMCR_AUTOEN | BMCR_STARTNEG);
1494 DELAY(1000);
1495 if (aneg != 0) {
1496 /* Poll link state until jme(4) get a 10/100 link. */
1497 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1498 mii_pollstat(mii);
1499 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1500 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1501 case IFM_10_T:
1502 case IFM_100_TX:
1503 jme_mac_config(sc);
1504 return;
1505 default:
1506 break;
1507 }
1508 }
1509 JME_UNLOCK(sc);
1510 pause("jmelnk", hz);
1511 JME_LOCK(sc);
1512 }
1513 if (i == MII_ANEGTICKS_GIGE)
1514 device_printf(sc->jme_dev, "establishing link failed, "
1515 "WOL may not work!");
1516 }
1517 /*
1518 * No link, force MAC to have 100Mbps, full-duplex link.
1519 * This is the last resort and may/may not work.
1520 */
1521 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1522 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1523 jme_mac_config(sc);
1524}
1525
1526static void
1527jme_setwol(struct jme_softc *sc)
1528{
1529 struct ifnet *ifp = &sc->arpcom.ac_if;
1530 uint32_t gpr, pmcs;
1531 uint16_t pmstat;
1532 int pmc;
1533
1534 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1535 /* No PME capability, PHY power down. */
1536 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1537 MII_BMCR, BMCR_PDOWN);
1538 return;
1539 }
1540
1541 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1542 pmcs = CSR_READ_4(sc, JME_PMCS);
1543 pmcs &= ~PMCS_WOL_ENB_MASK;
1544 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1545 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1546 /* Enable PME message. */
1547 gpr |= GPREG0_PME_ENB;
1548 /* For gigabit controllers, reset link speed to 10/100. */
ec7e787b 1549 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
76fbb0b9
SZ
1550 jme_setlinkspeed(sc);
1551 }
1552
1553 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1554 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1555
1556 /* Request PME. */
1557 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1558 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1559 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1560 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1561 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1562 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1563 /* No WOL, PHY power down. */
1564 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1565 MII_BMCR, BMCR_PDOWN);
1566 }
1567}
1568#endif
1569
1570static int
1571jme_suspend(device_t dev)
1572{
1573 struct jme_softc *sc = device_get_softc(dev);
1574 struct ifnet *ifp = &sc->arpcom.ac_if;
1575
31f0d5a2 1576 ifnet_serialize_all(ifp);
76fbb0b9
SZ
1577 jme_stop(sc);
1578#ifdef notyet
1579 jme_setwol(sc);
1580#endif
31f0d5a2 1581 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
1582
1583 return (0);
1584}
1585
1586static int
1587jme_resume(device_t dev)
1588{
1589 struct jme_softc *sc = device_get_softc(dev);
1590 struct ifnet *ifp = &sc->arpcom.ac_if;
1591#ifdef notyet
1592 int pmc;
1593#endif
1594
31f0d5a2 1595 ifnet_serialize_all(ifp);
76fbb0b9
SZ
1596
1597#ifdef notyet
1598 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1599 uint16_t pmstat;
1600
1601 pmstat = pci_read_config(sc->jme_dev,
1602 pmc + PCIR_POWER_STATUS, 2);
1603 /* Disable PME clear PME status. */
1604 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1605 pci_write_config(sc->jme_dev,
1606 pmc + PCIR_POWER_STATUS, pmstat, 2);
1607 }
1608#endif
1609
1610 if (ifp->if_flags & IFF_UP)
1611 jme_init(sc);
1612
31f0d5a2 1613 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
1614
1615 return (0);
1616}
1617
1bedd927
SZ
1618static __inline int
1619jme_tso_pullup(struct mbuf **mp)
1620{
1621 int hoff, iphlen, thoff;
1622 struct mbuf *m;
1623
1624 m = *mp;
1625 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1626
1627 iphlen = m->m_pkthdr.csum_iphlen;
1628 thoff = m->m_pkthdr.csum_thlen;
1629 hoff = m->m_pkthdr.csum_lhlen;
1630
1631 KASSERT(iphlen > 0, ("invalid ip hlen"));
1632 KASSERT(thoff > 0, ("invalid tcp hlen"));
1633 KASSERT(hoff > 0, ("invalid ether hlen"));
1634
1635 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1636 m = m_pullup(m, hoff + iphlen + thoff);
1637 if (m == NULL) {
1638 *mp = NULL;
1639 return ENOBUFS;
1640 }
1641 *mp = m;
1642 }
1643 return 0;
1644}
1645
76fbb0b9 1646static int
9b99c84f 1647jme_encap(struct jme_txdata *tdata, struct mbuf **m_head)
76fbb0b9
SZ
1648{
1649 struct jme_txdesc *txd;
1650 struct jme_desc *desc;
1651 struct mbuf *m;
76fbb0b9 1652 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
b0ba1747 1653 int maxsegs, nsegs;
9b3ee148 1654 int error, i, prod, symbol_desc;
1bedd927 1655 uint32_t cflags, flag64, mss;
76fbb0b9
SZ
1656
1657 M_ASSERTPKTHDR((*m_head));
1658
1bedd927
SZ
1659 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) {
1660 /* XXX Is this necessary? */
1661 error = jme_tso_pullup(m_head);
1662 if (error)
1663 return error;
1664 }
1665
9b99c84f
SZ
1666 prod = tdata->jme_tx_prod;
1667 txd = &tdata->jme_txdesc[prod];
76fbb0b9 1668
9b99c84f 1669 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
9b3ee148
SZ
1670 symbol_desc = 1;
1671 else
1672 symbol_desc = 0;
1673
9b99c84f 1674 maxsegs = (tdata->jme_tx_desc_cnt - tdata->jme_tx_cnt) -
9b3ee148 1675 (JME_TXD_RSVD + symbol_desc);
76fbb0b9
SZ
1676 if (maxsegs > JME_MAXTXSEGS)
1677 maxsegs = JME_MAXTXSEGS;
1bedd927 1678 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc),
ed20d0e3 1679 ("not enough segments %d", maxsegs));
76fbb0b9 1680
9b99c84f 1681 error = bus_dmamap_load_mbuf_defrag(tdata->jme_tx_tag,
b0ba1747
SZ
1682 txd->tx_dmamap, m_head,
1683 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1684 if (error)
ecc6de9e 1685 goto fail;
76fbb0b9 1686
9b99c84f 1687 bus_dmamap_sync(tdata->jme_tx_tag, txd->tx_dmamap,
4458ee95
SZ
1688 BUS_DMASYNC_PREWRITE);
1689
76fbb0b9
SZ
1690 m = *m_head;
1691 cflags = 0;
1bedd927 1692 mss = 0;
76fbb0b9
SZ
1693
1694 /* Configure checksum offload. */
1bedd927
SZ
1695 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1696 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT;
1697 cflags |= JME_TD_TSO;
1698 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) {
1699 if (m->m_pkthdr.csum_flags & CSUM_IP)
1700 cflags |= JME_TD_IPCSUM;
1701 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1702 cflags |= JME_TD_TCPCSUM;
1703 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1704 cflags |= JME_TD_UDPCSUM;
1705 }
76fbb0b9
SZ
1706
1707 /* Configure VLAN. */
1708 if (m->m_flags & M_VLANTAG) {
1709 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1710 cflags |= JME_TD_VLAN_TAG;
1711 }
1712
9b99c84f 1713 desc = &tdata->jme_tx_ring[prod];
76fbb0b9 1714 desc->flags = htole32(cflags);
76fbb0b9 1715 desc->addr_hi = htole32(m->m_pkthdr.len);
9b99c84f 1716 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
7228f061
SZ
1717 /*
1718 * Use 64bits TX desc chain format.
1719 *
1720 * The first TX desc of the chain, which is setup here,
1721 * is just a symbol TX desc carrying no payload.
1722 */
1723 flag64 = JME_TD_64BIT;
1bedd927 1724 desc->buflen = htole32(mss);
7228f061
SZ
1725 desc->addr_lo = 0;
1726
1727 /* No effective TX desc is consumed */
1728 i = 0;
1729 } else {
1730 /*
1731 * Use 32bits TX desc chain format.
1732 *
1733 * The first TX desc of the chain, which is setup here,
1734 * is an effective TX desc carrying the first segment of
1735 * the mbuf chain.
1736 */
1737 flag64 = 0;
1bedd927 1738 desc->buflen = htole32(mss | txsegs[0].ds_len);
7228f061
SZ
1739 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1740
1741 /* One effective TX desc is consumed */
1742 i = 1;
1743 }
9b99c84f
SZ
1744 tdata->jme_tx_cnt++;
1745 KKASSERT(tdata->jme_tx_cnt - i < tdata->jme_tx_desc_cnt - JME_TXD_RSVD);
1746 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt);
7228f061
SZ
1747
1748 txd->tx_ndesc = 1 - i;
b0ba1747 1749 for (; i < nsegs; i++) {
9b99c84f 1750 desc = &tdata->jme_tx_ring[prod];
76fbb0b9
SZ
1751 desc->buflen = htole32(txsegs[i].ds_len);
1752 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1753 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
a54bd021 1754 desc->flags = htole32(JME_TD_OWN | flag64);
76fbb0b9 1755
9b99c84f
SZ
1756 tdata->jme_tx_cnt++;
1757 KKASSERT(tdata->jme_tx_cnt <=
1758 tdata->jme_tx_desc_cnt - JME_TXD_RSVD);
1759 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt);
76fbb0b9
SZ
1760 }
1761
1762 /* Update producer index. */
9b99c84f 1763 tdata->jme_tx_prod = prod;
76fbb0b9
SZ
1764 /*
1765 * Finally request interrupt and give the first descriptor
1766 * owenership to hardware.
1767 */
1768 desc = txd->tx_desc;
1769 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1770
1771 txd->tx_m = m;
b0ba1747 1772 txd->tx_ndesc += nsegs;
76fbb0b9 1773
ecc6de9e
SZ
1774 return 0;
1775fail:
1776 m_freem(*m_head);
1777 *m_head = NULL;
1778 return error;
76fbb0b9
SZ
1779}
1780
1781static void
1782jme_start(struct ifnet *ifp)
1783{
1784 struct jme_softc *sc = ifp->if_softc;
9b99c84f 1785 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ
1786 struct mbuf *m_head;
1787 int enq = 0;
1788
9b99c84f 1789 ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
76fbb0b9 1790
cccc3955 1791 if (!sc->jme_has_link) {
76fbb0b9
SZ
1792 ifq_purge(&ifp->if_snd);
1793 return;
1794 }
1795
1796 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1797 return;
1798
9b99c84f
SZ
1799 if (tdata->jme_tx_cnt >= JME_TX_DESC_HIWAT(tdata))
1800 jme_txeof(tdata);
76fbb0b9
SZ
1801
1802 while (!ifq_is_empty(&ifp->if_snd)) {
1803 /*
1804 * Check number of available TX descs, always
1805 * leave JME_TXD_RSVD free TX descs.
1806 */
9b99c84f
SZ
1807 if (tdata->jme_tx_cnt + JME_TXD_SPARE >
1808 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) {
76fbb0b9
SZ
1809 ifp->if_flags |= IFF_OACTIVE;
1810 break;
1811 }
1812
1813 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1814 if (m_head == NULL)
1815 break;
1816
1817 /*
1818 * Pack the data into the transmit ring. If we
1819 * don't have room, set the OACTIVE flag and wait
1820 * for the NIC to drain the ring.
1821 */
9b99c84f 1822 if (jme_encap(tdata, &m_head)) {
ecc6de9e
SZ
1823 KKASSERT(m_head == NULL);
1824 ifp->if_oerrors++;
76fbb0b9
SZ
1825 ifp->if_flags |= IFF_OACTIVE;
1826 break;
1827 }
1828 enq++;
1829
1830 /*
1831 * If there's a BPF listener, bounce a copy of this frame
1832 * to him.
1833 */
1834 ETHER_BPF_MTAP(ifp, m_head);
1835 }
1836
1837 if (enq > 0) {
1838 /*
1839 * Reading TXCSR takes very long time under heavy load
1840 * so cache TXCSR value and writes the ORed value with
1841 * the kick command to the TXCSR. This saves one register
1842 * access cycle.
1843 */
1844 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1845 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1846 /* Set a timeout in case the chip goes out to lunch. */
1847 ifp->if_timer = JME_TX_TIMEOUT;
1848 }
1849}
1850
1851static void
1852jme_watchdog(struct ifnet *ifp)
1853{
1854 struct jme_softc *sc = ifp->if_softc;
9b99c84f 1855 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9 1856
31f0d5a2 1857 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9 1858
cccc3955 1859 if (!sc->jme_has_link) {
76fbb0b9
SZ
1860 if_printf(ifp, "watchdog timeout (missed link)\n");
1861 ifp->if_oerrors++;
1862 jme_init(sc);
1863 return;
1864 }
1865
9b99c84f
SZ
1866 jme_txeof(tdata);
1867 if (tdata->jme_tx_cnt == 0) {
76fbb0b9
SZ
1868 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1869 "-- recovering\n");
1870 if (!ifq_is_empty(&ifp->if_snd))
1871 if_devstart(ifp);
1872 return;
1873 }
1874
1875 if_printf(ifp, "watchdog timeout\n");
1876 ifp->if_oerrors++;
1877 jme_init(sc);
1878 if (!ifq_is_empty(&ifp->if_snd))
1879 if_devstart(ifp);
1880}
1881
1882static int
1883jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1884{
1885 struct jme_softc *sc = ifp->if_softc;
1886 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1887 struct ifreq *ifr = (struct ifreq *)data;
1888 int error = 0, mask;
1889
31f0d5a2 1890 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
1891
1892 switch (cmd) {
1893 case SIOCSIFMTU:
1894 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
3a5f3f36 1895 (!(sc->jme_caps & JME_CAP_JUMBO) &&
76fbb0b9
SZ
1896 ifr->ifr_mtu > JME_MAX_MTU)) {
1897 error = EINVAL;
1898 break;
1899 }
1900
1901 if (ifp->if_mtu != ifr->ifr_mtu) {
1902 /*
1903 * No special configuration is required when interface
1904 * MTU is changed but availability of Tx checksum
1905 * offload should be chcked against new MTU size as
1906 * FIFO size is just 2K.
1907 */
1908 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1bedd927
SZ
1909 ifp->if_capenable &=
1910 ~(IFCAP_TXCSUM | IFCAP_TSO);
1911 ifp->if_hwassist &=
1912 ~(JME_CSUM_FEATURES | CSUM_TSO);
76fbb0b9
SZ
1913 }
1914 ifp->if_mtu = ifr->ifr_mtu;
1915 if (ifp->if_flags & IFF_RUNNING)
1916 jme_init(sc);
1917 }
1918 break;
1919
1920 case SIOCSIFFLAGS:
1921 if (ifp->if_flags & IFF_UP) {
1922 if (ifp->if_flags & IFF_RUNNING) {
1923 if ((ifp->if_flags ^ sc->jme_if_flags) &
1924 (IFF_PROMISC | IFF_ALLMULTI))
1925 jme_set_filter(sc);
1926 } else {
1927 jme_init(sc);
1928 }
1929 } else {
1930 if (ifp->if_flags & IFF_RUNNING)
1931 jme_stop(sc);
1932 }
1933 sc->jme_if_flags = ifp->if_flags;
1934 break;
1935
1936 case SIOCADDMULTI:
1937 case SIOCDELMULTI:
1938 if (ifp->if_flags & IFF_RUNNING)
1939 jme_set_filter(sc);
1940 break;
1941
1942 case SIOCSIFMEDIA:
1943 case SIOCGIFMEDIA:
1944 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1945 break;
1946
1947 case SIOCSIFCAP:
1948 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1949
1950 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
e4616e94 1951 ifp->if_capenable ^= IFCAP_TXCSUM;
1bedd927 1952 if (ifp->if_capenable & IFCAP_TXCSUM)
e4616e94
SZ
1953 ifp->if_hwassist |= JME_CSUM_FEATURES;
1954 else
1955 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
76fbb0b9 1956 }
e4616e94 1957 if (mask & IFCAP_RXCSUM) {
76fbb0b9
SZ
1958 uint32_t reg;
1959
1960 ifp->if_capenable ^= IFCAP_RXCSUM;
1961 reg = CSR_READ_4(sc, JME_RXMAC);
1962 reg &= ~RXMAC_CSUM_ENB;
1963 if (ifp->if_capenable & IFCAP_RXCSUM)
1964 reg |= RXMAC_CSUM_ENB;
1965 CSR_WRITE_4(sc, JME_RXMAC, reg);
1966 }
1967
e4616e94 1968 if (mask & IFCAP_VLAN_HWTAGGING) {
76fbb0b9
SZ
1969 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1970 jme_set_vlan(sc);
1971 }
e4616e94 1972
1bedd927
SZ
1973 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1974 ifp->if_capenable ^= IFCAP_TSO;
1975 if (ifp->if_capenable & IFCAP_TSO)
1976 ifp->if_hwassist |= CSUM_TSO;
1977 else
1978 ifp->if_hwassist &= ~CSUM_TSO;
1979 }
1980
9f20b7b3 1981 if (mask & IFCAP_RSS)
d585233c 1982 ifp->if_capenable ^= IFCAP_RSS;
76fbb0b9
SZ
1983 break;
1984
1985 default:
1986 error = ether_ioctl(ifp, cmd, data);
1987 break;
1988 }
1989 return (error);
1990}
1991
1992static void
1993jme_mac_config(struct jme_softc *sc)
1994{
1995 struct mii_data *mii;
3b3da110
SZ
1996 uint32_t ghc, rxmac, txmac, txpause, gp1;
1997 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
76fbb0b9
SZ
1998
1999 mii = device_get_softc(sc->jme_miibus);
2000
2001 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2002 DELAY(10);
2003 CSR_WRITE_4(sc, JME_GHC, 0);
2004 ghc = 0;
2005 rxmac = CSR_READ_4(sc, JME_RXMAC);
2006 rxmac &= ~RXMAC_FC_ENB;
2007 txmac = CSR_READ_4(sc, JME_TXMAC);
2008 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2009 txpause = CSR_READ_4(sc, JME_TXPFC);
2010 txpause &= ~TXPFC_PAUSE_ENB;
2011 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2012 ghc |= GHC_FULL_DUPLEX;
2013 rxmac &= ~RXMAC_COLL_DET_ENB;
2014 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2015 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2016 TXMAC_FRAME_BURST);
2017#ifdef notyet
2018 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2019 txpause |= TXPFC_PAUSE_ENB;
2020 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2021 rxmac |= RXMAC_FC_ENB;
2022#endif
2023 /* Disable retry transmit timer/retry limit. */
2024 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2025 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2026 } else {
2027 rxmac |= RXMAC_COLL_DET_ENB;
2028 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2029 /* Enable retry transmit timer/retry limit. */
2030 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2031 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2032 }
2033
3b3da110
SZ
2034 /*
2035 * Reprogram Tx/Rx MACs with resolved speed/duplex.
2036 */
2037 gp1 = CSR_READ_4(sc, JME_GPREG1);
2038 gp1 &= ~GPREG1_WA_HDX;
2039
2040 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2041 hdx = 1;
2042
76fbb0b9
SZ
2043 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2044 case IFM_10_T:
b249905b 2045 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
3b3da110
SZ
2046 if (hdx)
2047 gp1 |= GPREG1_WA_HDX;
76fbb0b9 2048 break;
dbe37f03 2049
76fbb0b9 2050 case IFM_100_TX:
b249905b 2051 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
3b3da110
SZ
2052 if (hdx)
2053 gp1 |= GPREG1_WA_HDX;
dbe37f03
SZ
2054
2055 /*
2056 * Use extended FIFO depth to workaround CRC errors
2057 * emitted by chips before JMC250B
2058 */
2059 phyconf = JMPHY_CONF_EXTFIFO;
76fbb0b9 2060 break;
dbe37f03 2061
76fbb0b9 2062 case IFM_1000_T:
ec7e787b 2063 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 2064 break;
dbe37f03 2065
b249905b 2066 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
3b3da110 2067 if (hdx)
76fbb0b9
SZ
2068 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2069 break;
dbe37f03 2070
76fbb0b9
SZ
2071 default:
2072 break;
2073 }
2074 CSR_WRITE_4(sc, JME_GHC, ghc);
2075 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2076 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2077 CSR_WRITE_4(sc, JME_TXPFC, txpause);
dbe37f03 2078
ad22907f 2079 if (sc->jme_workaround & JME_WA_EXTFIFO) {
dbe37f03
SZ
2080 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2081 JMPHY_CONF, phyconf);
2082 }
3b3da110
SZ
2083 if (sc->jme_workaround & JME_WA_HDX)
2084 CSR_WRITE_4(sc, JME_GPREG1, gp1);
76fbb0b9
SZ
2085}
2086
2087static void
2088jme_intr(void *xsc)
2089{
2090 struct jme_softc *sc = xsc;
2091 struct ifnet *ifp = &sc->arpcom.ac_if;
2092 uint32_t status;
4447c752 2093 int r;
76fbb0b9 2094
31f0d5a2 2095 ASSERT_SERIALIZED(&sc->jme_serialize);
76fbb0b9
SZ
2096
2097 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2098 if (status == 0 || status == 0xFFFFFFFF)
2099 return;
2100
2101 /* Disable interrupts. */
2102 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2103
2104 status = CSR_READ_4(sc, JME_INTR_STATUS);
2105 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2106 goto back;
2107
2108 /* Reset PCC counter/timer and Ack interrupts. */
2109 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
4447c752 2110
76fbb0b9
SZ
2111 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2112 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
4447c752 2113
7b040092 2114 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
2115 if (status & jme_rx_status[r].jme_coal) {
2116 status |= jme_rx_status[r].jme_coal |
2117 jme_rx_status[r].jme_comp;
2118 }
2119 }
2120
76fbb0b9
SZ
2121 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2122
2123 if (ifp->if_flags & IFF_RUNNING) {
9b99c84f
SZ
2124 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
2125
76fbb0b9 2126 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
4447c752 2127 jme_rx_intr(sc, status);
76fbb0b9
SZ
2128
2129 if (status & INTR_RXQ_DESC_EMPTY) {
2130 /*
2131 * Notify hardware availability of new Rx buffers.
2132 * Reading RXCSR takes very long time under heavy
2133 * load so cache RXCSR value and writes the ORed
2134 * value with the kick command to the RXCSR. This
2135 * saves one register access cycle.
2136 */
2137 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2138 RXCSR_RX_ENB | RXCSR_RXQ_START);
2139 }
2140
2141 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
9b99c84f
SZ
2142 lwkt_serialize_enter(&tdata->jme_tx_serialize);
2143 jme_txeof(tdata);
76fbb0b9
SZ
2144 if (!ifq_is_empty(&ifp->if_snd))
2145 if_devstart(ifp);
9b99c84f 2146 lwkt_serialize_exit(&tdata->jme_tx_serialize);
76fbb0b9
SZ
2147 }
2148 }
2149back:
2150 /* Reenable interrupts. */
2151 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2152}
2153
2154static void
9b99c84f 2155jme_txeof(struct jme_txdata *tdata)
76fbb0b9 2156{
9b99c84f 2157 struct ifnet *ifp = &tdata->jme_sc->arpcom.ac_if;
6960d7d2 2158 int cons;
76fbb0b9 2159
9b99c84f
SZ
2160 cons = tdata->jme_tx_cons;
2161 if (cons == tdata->jme_tx_prod)
76fbb0b9
SZ
2162 return;
2163
76fbb0b9
SZ
2164 /*
2165 * Go through our Tx list and free mbufs for those
2166 * frames which have been transmitted.
2167 */
9b99c84f 2168 while (cons != tdata->jme_tx_prod) {
6960d7d2
SZ
2169 struct jme_txdesc *txd, *next_txd;
2170 uint32_t status, next_status;
2171 int next_cons, nsegs;
2172
9b99c84f 2173 txd = &tdata->jme_txdesc[cons];
76fbb0b9 2174 KASSERT(txd->tx_m != NULL,
ed20d0e3 2175 ("%s: freeing NULL mbuf!", __func__));
76fbb0b9
SZ
2176
2177 status = le32toh(txd->tx_desc->flags);
2178 if ((status & JME_TD_OWN) == JME_TD_OWN)
2179 break;
2180
6960d7d2
SZ
2181 /*
2182 * NOTE:
2183 * This chip will always update the TX descriptor's
2184 * buflen field and this updating always happens
2185 * after clearing the OWN bit, so even if the OWN
2186 * bit is cleared by the chip, we still don't sure
2187 * about whether the buflen field has been updated
2188 * by the chip or not. To avoid this race, we wait
2189 * for the next TX descriptor's OWN bit to be cleared
2190 * by the chip before reusing this TX descriptor.
2191 */
2192 next_cons = cons;
9b99c84f
SZ
2193 JME_DESC_ADD(next_cons, txd->tx_ndesc, tdata->jme_tx_desc_cnt);
2194 next_txd = &tdata->jme_txdesc[next_cons];
6960d7d2
SZ
2195 if (next_txd->tx_m == NULL)
2196 break;
2197 next_status = le32toh(next_txd->tx_desc->flags);
2198 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2199 break;
2200
76fbb0b9
SZ
2201 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2202 ifp->if_oerrors++;
2203 } else {
2204 ifp->if_opackets++;
2205 if (status & JME_TD_COLLISION) {
2206 ifp->if_collisions +=
2207 le32toh(txd->tx_desc->buflen) &
2208 JME_TD_BUF_LEN_MASK;
2209 }
2210 }
2211
2212 /*
2213 * Only the first descriptor of multi-descriptor
2214 * transmission is updated so driver have to skip entire
2215 * chained buffers for the transmiited frame. In other
2216 * words, JME_TD_OWN bit is valid only at the first
2217 * descriptor of a multi-descriptor transmission.
2218 */
2219 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
9b99c84f
SZ
2220 tdata->jme_tx_ring[cons].flags = 0;
2221 JME_DESC_INC(cons, tdata->jme_tx_desc_cnt);
76fbb0b9
SZ
2222 }
2223
2224 /* Reclaim transferred mbufs. */
9b99c84f 2225 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap);
76fbb0b9
SZ
2226 m_freem(txd->tx_m);
2227 txd->tx_m = NULL;
9b99c84f
SZ
2228 tdata->jme_tx_cnt -= txd->tx_ndesc;
2229 KASSERT(tdata->jme_tx_cnt >= 0,
ed20d0e3 2230 ("%s: Active Tx desc counter was garbled", __func__));
76fbb0b9
SZ
2231 txd->tx_ndesc = 0;
2232 }
9b99c84f 2233 tdata->jme_tx_cons = cons;
76fbb0b9 2234
1bedd927 2235 /* 1 for symbol TX descriptor */
9b99c84f 2236 if (tdata->jme_tx_cnt <= JME_MAXTXSEGS + 1)
76fbb0b9
SZ
2237 ifp->if_timer = 0;
2238
9b99c84f
SZ
2239 if (tdata->jme_tx_cnt + JME_TXD_SPARE <=
2240 tdata->jme_tx_desc_cnt - JME_TXD_RSVD)
76fbb0b9 2241 ifp->if_flags &= ~IFF_OACTIVE;
76fbb0b9
SZ
2242}
2243
2244static __inline void
dea2452a 2245jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
76fbb0b9
SZ
2246{
2247 int i;
2248
2249 for (i = 0; i < count; ++i) {
fd2a6d2c 2250 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
7b040092 2251 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
76fbb0b9
SZ
2252 }
2253}
2254
a6acc6e2
SZ
2255static __inline struct pktinfo *
2256jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2257{
2258 if (flags & JME_RD_IPV4)
2259 pi->pi_netisr = NETISR_IP;
2260 else if (flags & JME_RD_IPV6)
2261 pi->pi_netisr = NETISR_IPV6;
2262 else
2263 return NULL;
2264
2265 pi->pi_flags = 0;
2266 pi->pi_l3proto = IPPROTO_UNKNOWN;
2267
2268 if (flags & JME_RD_MORE_FRAG)
2269 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2270 else if (flags & JME_RD_TCP)
2271 pi->pi_l3proto = IPPROTO_TCP;
2272 else if (flags & JME_RD_UDP)
2273 pi->pi_l3proto = IPPROTO_UDP;
7345eb80
SZ
2274 else
2275 pi = NULL;
a6acc6e2
SZ
2276 return pi;
2277}
2278
76fbb0b9
SZ
2279/* Receive a frame. */
2280static void
dea2452a 2281jme_rxpkt(struct jme_rxdata *rdata)
76fbb0b9 2282{
dea2452a 2283 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
76fbb0b9
SZ
2284 struct jme_desc *desc;
2285 struct jme_rxdesc *rxd;
2286 struct mbuf *mp, *m;
a6acc6e2 2287 uint32_t flags, status, hash, hashinfo;
76fbb0b9
SZ
2288 int cons, count, nsegs;
2289
4447c752
SZ
2290 cons = rdata->jme_rx_cons;
2291 desc = &rdata->jme_rx_ring[cons];
9d4f763d 2292
76fbb0b9
SZ
2293 flags = le32toh(desc->flags);
2294 status = le32toh(desc->buflen);
a6acc6e2
SZ
2295 hash = le32toh(desc->addr_hi);
2296 hashinfo = le32toh(desc->addr_lo);
76fbb0b9
SZ
2297 nsegs = JME_RX_NSEGS(status);
2298
9d4f763d
SZ
2299 if (nsegs > 1) {
2300 /* Skip the first descriptor. */
2301 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2302
2303 /*
2304 * Clear the OWN bit of the following RX descriptors;
2305 * hardware will not clear the OWN bit except the first
2306 * RX descriptor.
2307 *
2308 * Since the first RX descriptor is setup, i.e. OWN bit
2309 * on, before its followins RX descriptors, leaving the
2310 * OWN bit on the following RX descriptors will trick
2311 * the hardware into thinking that the following RX
2312 * descriptors are ready to be used too.
2313 */
2314 for (count = 1; count < nsegs; count++,
2315 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2316 rdata->jme_rx_ring[cons].flags = 0;
2317
2318 cons = rdata->jme_rx_cons;
2319 }
2320
7b040092 2321 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
a6acc6e2 2322 "hash 0x%08x, hash info 0x%08x\n",
7b040092 2323 rdata->jme_rx_idx, flags, hash, hashinfo);
760c056c 2324
76fbb0b9
SZ
2325 if (status & JME_RX_ERR_STAT) {
2326 ifp->if_ierrors++;
dea2452a 2327 jme_discard_rxbufs(rdata, cons, nsegs);
76fbb0b9 2328#ifdef JME_SHOW_ERRORS
7b040092 2329 if_printf(ifp, "%s : receive error = 0x%b\n",
76fbb0b9
SZ
2330 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2331#endif
4447c752 2332 rdata->jme_rx_cons += nsegs;
7b040092 2333 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ
2334 return;
2335 }
2336
4447c752 2337 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
76fbb0b9 2338 for (count = 0; count < nsegs; count++,
7b040092 2339 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
4447c752 2340 rxd = &rdata->jme_rxdesc[cons];
76fbb0b9
SZ
2341 mp = rxd->rx_m;
2342
2343 /* Add a new receive buffer to the ring. */
dea2452a 2344 if (jme_newbuf(rdata, rxd, 0) != 0) {
76fbb0b9
SZ
2345 ifp->if_iqdrops++;
2346 /* Reuse buffer. */
dea2452a 2347 jme_discard_rxbufs(rdata, cons, nsegs - count);
4447c752
SZ
2348 if (rdata->jme_rxhead != NULL) {
2349 m_freem(rdata->jme_rxhead);
dea2452a 2350 JME_RXCHAIN_RESET(rdata);
76fbb0b9
SZ
2351 }
2352 break;
2353 }
2354
2355 /*
2356 * Assume we've received a full sized frame.
2357 * Actual size is fixed when we encounter the end of
2358 * multi-segmented frame.
2359 */
2360 mp->m_len = MCLBYTES;
2361
2362 /* Chain received mbufs. */
4447c752
SZ
2363 if (rdata->jme_rxhead == NULL) {
2364 rdata->jme_rxhead = mp;
2365 rdata->jme_rxtail = mp;
76fbb0b9
SZ
2366 } else {
2367 /*
2368 * Receive processor can receive a maximum frame
2369 * size of 65535 bytes.
2370 */
4447c752
SZ
2371 rdata->jme_rxtail->m_next = mp;
2372 rdata->jme_rxtail = mp;
76fbb0b9
SZ
2373 }
2374
2375 if (count == nsegs - 1) {
a6acc6e2
SZ
2376 struct pktinfo pi0, *pi;
2377
76fbb0b9 2378 /* Last desc. for this frame. */
4447c752 2379 m = rdata->jme_rxhead;
4447c752 2380 m->m_pkthdr.len = rdata->jme_rxlen;
76fbb0b9
SZ
2381 if (nsegs > 1) {
2382 /* Set first mbuf size. */
2383 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2384 /* Set last mbuf size. */
4447c752 2385 mp->m_len = rdata->jme_rxlen -
76fbb0b9
SZ
2386 ((MCLBYTES - JME_RX_PAD_BYTES) +
2387 (MCLBYTES * (nsegs - 2)));
2388 } else {
4447c752 2389 m->m_len = rdata->jme_rxlen;
76fbb0b9
SZ
2390 }
2391 m->m_pkthdr.rcvif = ifp;
2392
2393 /*
2394 * Account for 10bytes auto padding which is used
2395 * to align IP header on 32bit boundary. Also note,
2396 * CRC bytes is automatically removed by the
2397 * hardware.
2398 */
2399 m->m_data += JME_RX_PAD_BYTES;
2400
2401 /* Set checksum information. */
2402 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2403 (flags & JME_RD_IPV4)) {
2404 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2405 if (flags & JME_RD_IPCSUM)
2406 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2407 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2408 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2409 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2410 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2411 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2412 m->m_pkthdr.csum_flags |=
2413 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2414 m->m_pkthdr.csum_data = 0xffff;
2415 }
2416 }
2417
2418 /* Check for VLAN tagged packets. */
2419 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2420 (flags & JME_RD_VLAN_TAG)) {
2421 m->m_pkthdr.ether_vlantag =
2422 flags & JME_RD_VLAN_MASK;
2423 m->m_flags |= M_VLANTAG;
2424 }
2425
2426 ifp->if_ipackets++;
a6acc6e2
SZ
2427
2428 if (ifp->if_capenable & IFCAP_RSS)
2429 pi = jme_pktinfo(&pi0, flags);
2430 else
2431 pi = NULL;
2432
2433 if (pi != NULL &&
055b7997
SZ
2434 (hashinfo & JME_RD_HASH_FN_MASK) ==
2435 JME_RD_HASH_FN_TOEPLITZ) {
2436 m->m_flags |= (M_HASH | M_CKHASH);
a6acc6e2
SZ
2437 m->m_pkthdr.hash = toeplitz_hash(hash);
2438 }
2439
2440#ifdef JME_RSS_DEBUG
2441 if (pi != NULL) {
7b040092 2442 JME_RSS_DPRINTF(rdata->jme_sc, 10,
a6acc6e2
SZ
2443 "isr %d flags %08x, l3 %d %s\n",
2444 pi->pi_netisr, pi->pi_flags,
2445 pi->pi_l3proto,
2446 (m->m_flags & M_HASH) ? "hash" : "");
2447 }
2448#endif
2449
76fbb0b9 2450 /* Pass it on. */
eda7db08 2451 ether_input_pkt(ifp, m, pi);
76fbb0b9
SZ
2452
2453 /* Reset mbuf chains. */
dea2452a 2454 JME_RXCHAIN_RESET(rdata);
760c056c 2455#ifdef JME_RSS_DEBUG
7b040092 2456 rdata->jme_rx_pkt++;
760c056c 2457#endif
76fbb0b9
SZ
2458 }
2459 }
2460
4447c752 2461 rdata->jme_rx_cons += nsegs;
7b040092 2462 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ
2463}
2464
eda7db08 2465static void
dea2452a 2466jme_rxeof(struct jme_rxdata *rdata, int count)
76fbb0b9
SZ
2467{
2468 struct jme_desc *desc;
eda7db08 2469 int nsegs, pktlen;
76fbb0b9 2470
76fbb0b9 2471 for (;;) {
8a0620e4 2472#ifdef IFPOLL_ENABLE
3fa06afc
SZ
2473 if (count >= 0 && count-- == 0)
2474 break;
2475#endif
4447c752 2476 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
76fbb0b9
SZ
2477 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2478 break;
2479 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2480 break;
2481
2482 /*
2483 * Check number of segments against received bytes.
2484 * Non-matching value would indicate that hardware
2485 * is still trying to update Rx descriptors. I'm not
2486 * sure whether this check is needed.
2487 */
2488 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2489 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2490 if (nsegs != howmany(pktlen, MCLBYTES)) {
dea2452a
SZ
2491 if_printf(&rdata->jme_sc->arpcom.ac_if,
2492 "RX fragment count(%d) and "
2493 "packet size(%d) mismach\n", nsegs, pktlen);
76fbb0b9
SZ
2494 break;
2495 }
2496
6afef6ab
SZ
2497 /*
2498 * NOTE:
2499 * RSS hash and hash information may _not_ be set by the
2500 * hardware even if the OWN bit is cleared and VALID bit
2501 * is set.
2502 *
2503 * If the RSS information is not delivered by the hardware
2504 * yet, we MUST NOT accept this packet, let alone reusing
2505 * its RX descriptor. If this packet was accepted and its
2506 * RX descriptor was reused before hardware delivering the
2507 * RSS information, the RX buffer's address would be trashed
2508 * by the RSS information delivered by the hardware.
2509 */
2510 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2511 struct jme_rxdesc *rxd;
2512 uint32_t hashinfo;
2513
2514 hashinfo = le32toh(desc->addr_lo);
2515 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2516
2517 /*
2518 * This test should be enough to detect the pending
2519 * RSS information delivery, given:
2520 * - If RSS hash is not calculated, the hashinfo
064b75ed
SZ
2521 * will be 0. Howvever, the lower 32bits of RX
2522 * buffers' physical address will never be 0.
2523 * (see jme_rxbuf_dma_filter)
6afef6ab
SZ
2524 * - If RSS hash is calculated, the lowest 4 bits
2525 * of hashinfo will be set, while the RX buffers
2526 * are at least 2K aligned.
2527 */
2528 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2529#ifdef JME_SHOW_RSSWB
2530 if_printf(&rdata->jme_sc->arpcom.ac_if,
2531 "RSS is not written back yet\n");
2532#endif
2533 break;
2534 }
2535 }
2536
76fbb0b9 2537 /* Received a frame. */
dea2452a 2538 jme_rxpkt(rdata);
76fbb0b9 2539 }
76fbb0b9
SZ
2540}
2541
2542static void
2543jme_tick(void *xsc)
2544{
2545 struct jme_softc *sc = xsc;
76fbb0b9
SZ
2546 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2547
cccc3955 2548 lwkt_serialize_enter(&sc->jme_serialize);
76fbb0b9 2549
cccc3955 2550 sc->jme_in_tick = TRUE;
76fbb0b9 2551 mii_tick(mii);
cccc3955
SZ
2552 sc->jme_in_tick = FALSE;
2553
76fbb0b9
SZ
2554 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2555
cccc3955 2556 lwkt_serialize_exit(&sc->jme_serialize);
76fbb0b9
SZ
2557}
2558
2559static void
2560jme_reset(struct jme_softc *sc)
2561{
409fe405
SZ
2562 uint32_t val;
2563
2564 /* Make sure that TX and RX are stopped */
76fbb0b9 2565 jme_stop_tx(sc);
409fe405
SZ
2566 jme_stop_rx(sc);
2567
2568 /* Start reset */
76fbb0b9 2569 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
409fe405
SZ
2570 DELAY(20);
2571
2572 /*
2573 * Hold reset bit before stop reset
2574 */
2575
2576 /* Disable TXMAC and TXOFL clock sources */
2577 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2578 /* Disable RXMAC clock source */
2579 val = CSR_READ_4(sc, JME_GPREG1);
2580 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2581 /* Flush */
2582 CSR_READ_4(sc, JME_GHC);
2583
2584 /* Stop reset */
2585 CSR_WRITE_4(sc, JME_GHC, 0);
2586 /* Flush */
2587 CSR_READ_4(sc, JME_GHC);
2588
2589 /*
2590 * Clear reset bit after stop reset
2591 */
2592
2593 /* Enable TXMAC and TXOFL clock sources */
2594 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2595 /* Enable RXMAC clock source */
2596 val = CSR_READ_4(sc, JME_GPREG1);
2597 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2598 /* Flush */
2599 CSR_READ_4(sc, JME_GHC);
2600
2601 /* Disable TXMAC and TXOFL clock sources */
76fbb0b9 2602 CSR_WRITE_4(sc, JME_GHC, 0);
409fe405
SZ
2603 /* Disable RXMAC clock source */
2604 val = CSR_READ_4(sc, JME_GPREG1);
2605 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2606 /* Flush */
2607 CSR_READ_4(sc, JME_GHC);
2608
2609 /* Enable TX and RX */
2610 val = CSR_READ_4(sc, JME_TXCSR);
2611 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2612 val = CSR_READ_4(sc, JME_RXCSR);
2613 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2614 /* Flush */
2615 CSR_READ_4(sc, JME_TXCSR);
2616 CSR_READ_4(sc, JME_RXCSR);
2617
2618 /* Enable TXMAC and TXOFL clock sources */
2619 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2620 /* Eisable RXMAC clock source */
2621 val = CSR_READ_4(sc, JME_GPREG1);
2622 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2623 /* Flush */
2624 CSR_READ_4(sc, JME_GHC);
2625
2626 /* Stop TX and RX */
2627 jme_stop_tx(sc);
2628 jme_stop_rx(sc);
76fbb0b9
SZ
2629}
2630
2631static void
2632jme_init(void *xsc)
2633{
2634 struct jme_softc *sc = xsc;
2635 struct ifnet *ifp = &sc->arpcom.ac_if;
2636 struct mii_data *mii;
2637 uint8_t eaddr[ETHER_ADDR_LEN];
2638 bus_addr_t paddr;
2639 uint32_t reg;
4447c752 2640 int error, r;
76fbb0b9 2641
31f0d5a2 2642 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2643
2644 /*
2645 * Cancel any pending I/O.
2646 */
2647 jme_stop(sc);
2648
2649 /*
2650 * Reset the chip to a known state.
2651 */
2652 jme_reset(sc);
2653
58880b0d
SZ
2654 /*
2655 * Setup MSI/MSI-X vectors to interrupts mapping
2656 */
2657 jme_set_msinum(sc);
2658
6afef6ab 2659 if (JME_ENABLE_HWRSS(sc))
760c056c
SZ
2660 jme_enable_rss(sc);
2661 else
2662 jme_disable_rss(sc);
4447c752
SZ
2663
2664 /* Init RX descriptors */
7b040092 2665 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
dea2452a 2666 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
4447c752
SZ
2667 if (error) {
2668 if_printf(ifp, "initialization failed: "
2669 "no memory for %dth RX ring.\n", r);
2670 jme_stop(sc);
2671 return;
2672 }
2673 }
2674
2675 /* Init TX descriptors */
9b99c84f 2676 jme_init_tx_ring(&sc->jme_cdata.jme_tx_data);
76fbb0b9
SZ
2677
2678 /* Initialize shadow status block. */
2679 jme_init_ssb(sc);
2680
2681 /* Reprogram the station address. */
2682 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2683 CSR_WRITE_4(sc, JME_PAR0,
2684 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2685 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2686
2687 /*
2688 * Configure Tx queue.
2689 * Tx priority queue weight value : 0
2690 * Tx FIFO threshold for processing next packet : 16QW
2691 * Maximum Tx DMA length : 512
2692 * Allow Tx DMA burst.
2693 */
2694 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2695 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2696 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2697 sc->jme_txcsr |= sc->jme_tx_dma_size;
2698 sc->jme_txcsr |= TXCSR_DMA_BURST;
2699 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2700
2701 /* Set Tx descriptor counter. */
9b99c84f 2702 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt);
76fbb0b9
SZ
2703
2704 /* Set Tx ring address to the hardware. */
9b99c84f 2705 paddr = sc->jme_cdata.jme_tx_data.jme_tx_ring_paddr;
76fbb0b9
SZ
2706 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2707 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2708
2709 /* Configure TxMAC parameters. */
2710 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2711 reg |= TXMAC_THRESH_1_PKT;
2712 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2713 CSR_WRITE_4(sc, JME_TXMAC, reg);
2714
2715 /*
2716 * Configure Rx queue.
2717 * FIFO full threshold for transmitting Tx pause packet : 128T
2718 * FIFO threshold for processing next packet : 128QW
2719 * Rx queue 0 select
2720 * Max Rx DMA length : 128
2721 * Rx descriptor retry : 32
2722 * Rx descriptor retry time gap : 256ns
2723 * Don't receive runt/bad frame.
2724 */
2725 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
223cfc2f 2726#if 0
76fbb0b9
SZ
2727 /*
2728 * Since Rx FIFO size is 4K bytes, receiving frames larger
2729 * than 4K bytes will suffer from Rx FIFO overruns. So
2730 * decrease FIFO threshold to reduce the FIFO overruns for
2731 * frames larger than 4000 bytes.
2732 * For best performance of standard MTU sized frames use
2733 * maximum allowable FIFO threshold, 128QW.
2734 */
2735 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2736 JME_RX_FIFO_SIZE)
2737 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2738 else
2739 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
223cfc2f
SZ
2740#else
2741 /* Improve PCI Express compatibility */
2742 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2743#endif
2744 sc->jme_rxcsr |= sc->jme_rx_dma_size;
76fbb0b9
SZ
2745 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2746 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2747 /* XXX TODO DROP_BAD */
76fbb0b9 2748
7b040092
SZ
2749 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2750 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2751
4447c752
SZ
2752 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2753
2754 /* Set Rx descriptor counter. */
7b040092 2755 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
76fbb0b9 2756
4447c752 2757 /* Set Rx ring address to the hardware. */
7b040092 2758 paddr = rdata->jme_rx_ring_paddr;
4447c752
SZ
2759 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2760 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2761 }
76fbb0b9
SZ
2762
2763 /* Clear receive filter. */
2764 CSR_WRITE_4(sc, JME_RXMAC, 0);
2765
2766 /* Set up the receive filter. */
2767 jme_set_filter(sc);
2768 jme_set_vlan(sc);
2769
2770 /*
2771 * Disable all WOL bits as WOL can interfere normal Rx
2772 * operation. Also clear WOL detection status bits.
2773 */
2774 reg = CSR_READ_4(sc, JME_PMCS);
2775 reg &= ~PMCS_WOL_ENB_MASK;
2776 CSR_WRITE_4(sc, JME_PMCS, reg);
2777
2778 /*
2779 * Pad 10bytes right before received frame. This will greatly
2780 * help Rx performance on strict-alignment architectures as
2781 * it does not need to copy the frame to align the payload.
2782 */
2783 reg = CSR_READ_4(sc, JME_RXMAC);
2784 reg |= RXMAC_PAD_10BYTES;
2785
2786 if (ifp->if_capenable & IFCAP_RXCSUM)
2787 reg |= RXMAC_CSUM_ENB;
2788 CSR_WRITE_4(sc, JME_RXMAC, reg);
2789
2790 /* Configure general purpose reg0 */
2791 reg = CSR_READ_4(sc, JME_GPREG0);
2792 reg &= ~GPREG0_PCC_UNIT_MASK;
2793 /* Set PCC timer resolution to micro-seconds unit. */
2794 reg |= GPREG0_PCC_UNIT_US;
2795 /*
2796 * Disable all shadow register posting as we have to read
2797 * JME_INTR_STATUS register in jme_intr. Also it seems
2798 * that it's hard to synchronize interrupt status between
2799 * hardware and software with shadow posting due to
2800 * requirements of bus_dmamap_sync(9).
2801 */
2802 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2803 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2804 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2805 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2806 /* Disable posting of DW0. */
2807 reg &= ~GPREG0_POST_DW0_ENB;
2808 /* Clear PME message. */
2809 reg &= ~GPREG0_PME_ENB;
2810 /* Set PHY address. */
2811 reg &= ~GPREG0_PHY_ADDR_MASK;
2812 reg |= sc->jme_phyaddr;
2813 CSR_WRITE_4(sc, JME_GPREG0, reg);
2814
2815 /* Configure Tx queue 0 packet completion coalescing. */
2870abc4 2816 jme_set_tx_coal(sc);
76fbb0b9 2817
dea2452a 2818 /* Configure Rx queues packet completion coalescing. */
2870abc4 2819 jme_set_rx_coal(sc);
76fbb0b9
SZ
2820
2821 /* Configure shadow status block but don't enable posting. */
560616bf 2822 paddr = sc->jme_cdata.jme_ssb_block_paddr;
76fbb0b9
SZ
2823 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2824 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2825
2826 /* Disable Timer 1 and Timer 2. */
2827 CSR_WRITE_4(sc, JME_TIMER1, 0);
2828 CSR_WRITE_4(sc, JME_TIMER2, 0);
2829
2830 /* Configure retry transmit period, retry limit value. */
2831 CSR_WRITE_4(sc, JME_TXTRHD,
2832 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2833 TXTRHD_RT_PERIOD_MASK) |
2834 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2835 TXTRHD_RT_LIMIT_SHIFT));
2836
8a0620e4
SZ
2837#ifdef IFPOLL_ENABLE
2838 if (!(ifp->if_flags & IFF_NPOLLING))
9de40864 2839#endif
76fbb0b9 2840 /* Initialize the interrupt mask. */
8a0620e4 2841 jme_enable_intr(sc);
76fbb0b9
SZ
2842 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2843
2844 /*
2845 * Enabling Tx/Rx DMA engines and Rx queue processing is
2846 * done after detection of valid link in jme_miibus_statchg.
2847 */
cccc3955 2848 sc->jme_has_link = FALSE;
76fbb0b9
SZ
2849
2850 /* Set the current media. */
2851 mii = device_get_softc(sc->jme_miibus);
2852 mii_mediachg(mii);
2853
2854 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2855
2856 ifp->if_flags |= IFF_RUNNING;
2857 ifp->if_flags &= ~IFF_OACTIVE;
2858}
2859
2860static void
2861jme_stop(struct jme_softc *sc)
2862{
2863 struct ifnet *ifp = &sc->arpcom.ac_if;
9b99c84f 2864 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data;
76fbb0b9
SZ
2865 struct jme_txdesc *txd;
2866 struct jme_rxdesc *rxd;
4447c752
SZ
2867 struct jme_rxdata *rdata;
2868 int i, r;
76fbb0b9 2869
31f0d5a2 2870 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2871
2872 /*
2873 * Mark the interface down and cancel the watchdog timer.
2874 */
2875 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2876 ifp->if_timer = 0;
2877
2878 callout_stop(&sc->jme_tick_ch);
cccc3955 2879 sc->jme_has_link = FALSE;
76fbb0b9
SZ
2880
2881 /*
2882 * Disable interrupts.
2883 */
8a0620e4 2884 jme_disable_intr(sc);
76fbb0b9
SZ
2885 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2886
2887 /* Disable updating shadow status block. */
2888 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2889 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2890
2891 /* Stop receiver, transmitter. */
2892 jme_stop_rx(sc);
2893 jme_stop_tx(sc);
2894
76fbb0b9
SZ
2895 /*
2896 * Free partial finished RX segments
2897 */
7b040092 2898 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
2899 rdata = &sc->jme_cdata.jme_rx_data[r];
2900 if (rdata->jme_rxhead != NULL)
2901 m_freem(rdata->jme_rxhead);
dea2452a 2902 JME_RXCHAIN_RESET(rdata);
4447c752 2903 }
76fbb0b9
SZ
2904
2905 /*
2906 * Free RX and TX mbufs still in the queues.
2907 */
7b040092 2908 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752 2909 rdata = &sc->jme_cdata.jme_rx_data[r];
7b040092 2910 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
2911 rxd = &rdata->jme_rxdesc[i];
2912 if (rxd->rx_m != NULL) {
2913 bus_dmamap_unload(rdata->jme_rx_tag,
2914 rxd->rx_dmamap);
2915 m_freem(rxd->rx_m);
2916 rxd->rx_m = NULL;
2917 }
76fbb0b9 2918 }
4447c752 2919 }
9b99c84f
SZ
2920 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
2921 txd = &tdata->jme_txdesc[i];
76fbb0b9 2922 if (txd->tx_m != NULL) {
9b99c84f 2923 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap);
76fbb0b9
SZ
2924 m_freem(txd->tx_m);
2925 txd->tx_m = NULL;
2926 txd->tx_ndesc = 0;
2927 }
2928 }
2929}
2930
2931static void
2932jme_stop_tx(struct jme_softc *sc)
2933{
2934 uint32_t reg;
2935 int i;
2936
2937 reg = CSR_READ_4(sc, JME_TXCSR);
2938 if ((reg & TXCSR_TX_ENB) == 0)
2939 return;
2940 reg &= ~TXCSR_TX_ENB;
2941 CSR_WRITE_4(sc, JME_TXCSR, reg);
2942 for (i = JME_TIMEOUT; i > 0; i--) {
2943 DELAY(1);
2944 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2945 break;
2946 }
2947 if (i == 0)
2948 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2949}
2950
2951static void
2952jme_stop_rx(struct jme_softc *sc)
2953{
2954 uint32_t reg;
2955 int i;
2956
2957 reg = CSR_READ_4(sc, JME_RXCSR);
2958 if ((reg & RXCSR_RX_ENB) == 0)
2959 return;
2960 reg &= ~RXCSR_RX_ENB;
2961 CSR_WRITE_4(sc, JME_RXCSR, reg);
2962 for (i = JME_TIMEOUT; i > 0; i--) {
2963 DELAY(1);
2964 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2965 break;
2966 }
2967 if (i == 0)
2968 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2969}
2970
2971static void
9b99c84f 2972jme_init_tx_ring(struct jme_txdata *tdata)
76fbb0b9 2973{
76fbb0b9
SZ
2974 struct jme_txdesc *txd;
2975 int i;
2976
9b99c84f
SZ
2977 tdata->jme_tx_prod = 0;
2978 tdata->jme_tx_cons = 0;
2979 tdata->jme_tx_cnt = 0;
76fbb0b9 2980
9b99c84f
SZ
2981 bzero(tdata->jme_tx_ring, JME_TX_RING_SIZE(tdata));
2982 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) {
2983 txd = &tdata->jme_txdesc[i];
76fbb0b9 2984 txd->tx_m = NULL;
9b99c84f 2985 txd->tx_desc = &tdata->jme_tx_ring[i];
76fbb0b9
SZ
2986 txd->tx_ndesc = 0;
2987 }
76fbb0b9
SZ
2988}
2989
2990static void
2991jme_init_ssb(struct jme_softc *sc)
2992{
560616bf 2993 struct jme_chain_data *cd;
76fbb0b9 2994
560616bf
SZ
2995 cd = &sc->jme_cdata;
2996 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
76fbb0b9
SZ
2997}
2998
2999static int
dea2452a 3000jme_init_rx_ring(struct jme_rxdata *rdata)
76fbb0b9 3001{
76fbb0b9
SZ
3002 struct jme_rxdesc *rxd;
3003 int i;
3004
4447c752
SZ
3005 KKASSERT(rdata->jme_rxhead == NULL &&
3006 rdata->jme_rxtail == NULL &&
3007 rdata->jme_rxlen == 0);
3008 rdata->jme_rx_cons = 0;
76fbb0b9 3009
7b040092
SZ
3010 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
3011 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
76fbb0b9
SZ
3012 int error;
3013
4447c752 3014 rxd = &rdata->jme_rxdesc[i];
76fbb0b9 3015 rxd->rx_m = NULL;
4447c752 3016 rxd->rx_desc = &rdata->jme_rx_ring[i];
dea2452a 3017 error = jme_newbuf(rdata, rxd, 1);
76fbb0b9 3018 if (error)
4447c752 3019 return error;
76fbb0b9 3020 }
4447c752 3021 return 0;
76fbb0b9
SZ
3022}
3023
3024static int
dea2452a 3025jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
76fbb0b9 3026{
76fbb0b9 3027 struct mbuf *m;
76fbb0b9
SZ
3028 bus_dma_segment_t segs;
3029 bus_dmamap_t map;
b0ba1747 3030 int error, nsegs;
76fbb0b9
SZ
3031
3032 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3033 if (m == NULL)
4447c752 3034 return ENOBUFS;
76fbb0b9
SZ
3035 /*
3036 * JMC250 has 64bit boundary alignment limitation so jme(4)
3037 * takes advantage of 10 bytes padding feature of hardware
3038 * in order not to copy entire frame to align IP header on
3039 * 32bit boundary.
3040 */
3041 m->m_len = m->m_pkthdr.len = MCLBYTES;
3042
b0ba1747
SZ
3043 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
3044 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
3045 BUS_DMA_NOWAIT);
3046 if (error) {
76fbb0b9 3047 m_freem(m);
dea2452a
SZ
3048 if (init) {
3049 if_printf(&rdata->jme_sc->arpcom.ac_if,
3050 "can't load RX mbuf\n");
3051 }
4447c752 3052 return error;
76fbb0b9
SZ
3053 }
3054
3055 if (rxd->rx_m != NULL) {
4447c752 3056 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
76fbb0b9 3057 BUS_DMASYNC_POSTREAD);
4447c752 3058 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
76fbb0b9
SZ
3059 }
3060 map = rxd->rx_dmamap;
4447c752
SZ
3061 rxd->rx_dmamap = rdata->jme_rx_sparemap;
3062 rdata->jme_rx_sparemap = map;
76fbb0b9 3063 rxd->rx_m = m;
fd2a6d2c 3064 rxd->rx_paddr = segs.ds_addr;
76fbb0b9 3065
fd2a6d2c 3066 jme_setup_rxdesc(rxd);
4447c752 3067 return 0;
76fbb0b9
SZ
3068}
3069
3070static void
3071jme_set_vlan(struct jme_softc *sc)
3072{
3073 struct ifnet *ifp = &sc->arpcom.ac_if;
3074 uint32_t reg;
3075
31f0d5a2 3076 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
3077
3078 reg = CSR_READ_4(sc, JME_RXMAC);
3079 reg &= ~RXMAC_VLAN_ENB;
3080 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
3081 reg |= RXMAC_VLAN_ENB;
3082 CSR_WRITE_4(sc, JME_RXMAC, reg);
3083}
3084
3085static void
3086jme_set_filter(struct jme_softc *sc)
3087{
3088 struct ifnet *ifp = &sc->arpcom.ac_if;
3089 struct ifmultiaddr *ifma;
3090 uint32_t crc;
3091 uint32_t mchash[2];
3092 uint32_t rxcfg;
3093
31f0d5a2 3094 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
3095
3096 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3097 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3098 RXMAC_ALLMULTI);
3099
3100 /*
3101 * Always accept frames destined to our station address.
3102 * Always accept broadcast frames.
3103 */
3104 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
3105
3106 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
3107 if (ifp->if_flags & IFF_PROMISC)
3108 rxcfg |= RXMAC_PROMISC;
3109 if (ifp->if_flags & IFF_ALLMULTI)
3110 rxcfg |= RXMAC_ALLMULTI;
3111 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3112 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3113 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3114 return;
3115 }
3116
3117 /*
3118 * Set up the multicast address filter by passing all multicast
3119 * addresses through a CRC generator, and then using the low-order
3120 * 6 bits as an index into the 64 bit multicast hash table. The
3121 * high order bits select the register, while the rest of the bits
3122 * select the bit within the register.
3123 */
3124 rxcfg |= RXMAC_MULTICAST;
3125 bzero(mchash, sizeof(mchash));
3126
441d34b2 3127 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
76fbb0b9
SZ
3128 if (ifma->ifma_addr->sa_family != AF_LINK)
3129 continue;
3130 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3131 ifma->ifma_addr), ETHER_ADDR_LEN);
3132
3133 /* Just want the 6 least significant bits. */
3134 crc &= 0x3f;
3135
3136 /* Set the corresponding bit in the hash table. */
3137 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3138 }
3139
3140 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3141 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3142 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3143}
3144
3145static int
2870abc4 3146jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3147{
2870abc4
SZ
3148 struct jme_softc *sc = arg1;
3149 struct ifnet *ifp = &sc->arpcom.ac_if;
3150 int error, v;
3151
31f0d5a2 3152 ifnet_serialize_all(ifp);
2870abc4
SZ
3153
3154 v = sc->jme_tx_coal_to;
3155 error = sysctl_handle_int(oidp, &v, 0, req);
3156 if (error || req->newptr == NULL)
3157 goto back;
3158
3159 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3160 error = EINVAL;
3161 goto back;
3162 }
3163
3164 if (v != sc->jme_tx_coal_to) {
3165 sc->jme_tx_coal_to = v;
3166 if (ifp->if_flags & IFF_RUNNING)
3167 jme_set_tx_coal(sc);
3168 }
3169back:
31f0d5a2 3170 ifnet_deserialize_all(ifp);
2870abc4 3171 return error;
76fbb0b9
SZ
3172}
3173
3174static int
2870abc4 3175jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
76fbb0b9 3176{
2870abc4
SZ
3177 struct jme_softc *sc = arg1;
3178 struct ifnet *ifp = &sc->arpcom.ac_if;
3179 int error, v;
3180
31f0d5a2 3181 ifnet_serialize_all(ifp);
2870abc4
SZ
3182
3183 v = sc->jme_tx_coal_pkt;
3184 error = sysctl_handle_int(oidp, &v, 0, req);
3185 if (error || req->newptr == NULL)
3186 goto back;
3187
3188 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3189 error = EINVAL;
3190 goto back;
3191 }
3192
3193 if (v != sc->jme_tx_coal_pkt) {
3194 sc->jme_tx_coal_pkt = v;
3195 if (ifp->if_flags & IFF_RUNNING)
3196 jme_set_tx_coal(sc);
3197 }
3198back:
31f0d5a2 3199 ifnet_deserialize_all(ifp);
2870abc4 3200 return error;
76fbb0b9
SZ
3201}
3202
3203static int
2870abc4 3204jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 3205{
2870abc4
SZ
3206 struct jme_softc *sc = arg1;
3207 struct ifnet *ifp = &sc->arpcom.ac_if;
3208 int error, v;
3209
31f0d5a2 3210 ifnet_serialize_all(ifp);
2870abc4
SZ
3211
3212 v = sc->jme_rx_coal_to;
3213 error = sysctl_handle_int(oidp, &v, 0, req);
3214 if (error || req->newptr == NULL)
3215 goto back;
3216
3217 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3218 error = EINVAL;
3219 goto back;
3220 }
3221
3222 if (v != sc->jme_rx_coal_to) {
3223 sc->jme_rx_coal_to = v;
3224 if (ifp->if_flags & IFF_RUNNING)
3225 jme_set_rx_coal(sc);
3226 }
3227back:
31f0d5a2 3228 ifnet_deserialize_all(ifp);
2870abc4 3229 return error;
76fbb0b9
SZ
3230}
3231
3232static int
2870abc4
SZ
3233jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3234{
3235 struct jme_softc *sc = arg1;
3236 struct ifnet *ifp = &sc->arpcom.ac_if;
3237 int error, v;
3238
31f0d5a2 3239 ifnet_serialize_all(ifp);
2870abc4
SZ
3240
3241 v = sc->jme_rx_coal_pkt;
3242 error = sysctl_handle_int(oidp, &v, 0, req);
3243 if (error || req->newptr == NULL)
3244 goto back;
3245
3246 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3247 error = EINVAL;
3248 goto back;
3249 }
3250
3251 if (v != sc->jme_rx_coal_pkt) {
3252 sc->jme_rx_coal_pkt = v;
3253 if (ifp->if_flags & IFF_RUNNING)
3254 jme_set_rx_coal(sc);
3255 }
3256back:
31f0d5a2 3257 ifnet_deserialize_all(ifp);
2870abc4
SZ
3258 return error;
3259}
3260
3261static void
3262jme_set_tx_coal(struct jme_softc *sc)
3263{
3264 uint32_t reg;
3265
3266 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3267 PCCTX_COAL_TO_MASK;
3268 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3269 PCCTX_COAL_PKT_MASK;
3270 reg |= PCCTX_COAL_TXQ0;
3271 CSR_WRITE_4(sc, JME_PCCTX, reg);
3272}
3273
3274static void
3275jme_set_rx_coal(struct jme_softc *sc)
76fbb0b9 3276{
2870abc4 3277 uint32_t reg;
4447c752 3278 int r;
2870abc4
SZ
3279
3280 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3281 PCCRX_COAL_TO_MASK;
3282 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3283 PCCRX_COAL_PKT_MASK;
7b040092 3284 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
9f20b7b3 3285 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
76fbb0b9 3286}
9de40864 3287
8a0620e4 3288#ifdef IFPOLL_ENABLE
9de40864
SZ
3289
3290static void
8a0620e4 3291jme_npoll_status(struct ifnet *ifp, int pollhz __unused)
9de40864
SZ
3292{
3293 struct jme_softc *sc = ifp->if_softc;
3294 uint32_t status;
3295
31f0d5a2 3296 ASSERT_SERIALIZED(&sc->jme_serialize);
9de40864 3297
8a0620e4
SZ
3298 status = CSR_READ_4(sc, JME_INTR_STATUS);
3299 if (status & INTR_RXQ_DESC_EMPTY) {
41d0e8e7 3300 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY);
de437f82 3301 jme_rx_restart(sc, status);
8a0620e4
SZ
3302 }
3303}
0e7f1e6f 3304
8a0620e4
SZ
3305static void
3306jme_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3307{
3308 struct jme_rxdata *rdata = arg;
3309
3310 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3311
3312 jme_rxeof(rdata, cycle);
3313}
3314
3315static void
9b99c84f 3316jme_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
8a0620e4 3317{
9b99c84f 3318 struct jme_txdata *tdata = arg;
8a0620e4 3319
9b99c84f 3320 ASSERT_SERIALIZED(&tdata->jme_tx_serialize);
8a0620e4 3321
9b99c84f 3322 jme_txeof(tdata);
8a0620e4
SZ
3323 if (!ifq_is_empty(&ifp->if_snd))
3324 if_devstart(ifp);
3325}
3326
3327static void
3328jme_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3329{
3330 struct jme_softc *sc = ifp->if_softc;
3331
3332 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3333
3334 if (info) {
3335 int i, off;
3336
3337 info->ifpi_status.status_func = jme_npoll_status;
3338 info->ifpi_status.serializer = &sc->jme_serialize;
3339
3340 off = sc->jme_npoll_txoff;
3341 KKASSERT(off <= ncpus2);
3342 info->ifpi_tx[off].poll_func = jme_npoll_tx;
9b99c84f
SZ
3343 info->ifpi_tx[off].arg = &sc->jme_cdata.jme_tx_data;
3344 info->ifpi_tx[off].serializer =
3345 &sc->jme_cdata.jme_tx_data.jme_tx_serialize;
8a0620e4
SZ
3346
3347 off = sc->jme_npoll_rxoff;
3348 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
31f0d5a2 3349 struct jme_rxdata *rdata =
8a0620e4
SZ
3350 &sc->jme_cdata.jme_rx_data[i];
3351 int idx = i + off;
31f0d5a2 3352
8a0620e4
SZ
3353 info->ifpi_rx[idx].poll_func = jme_npoll_rx;
3354 info->ifpi_rx[idx].arg = rdata;
3355 info->ifpi_rx[idx].serializer =
3356 &rdata->jme_rx_serialize;
31f0d5a2 3357 }
9de40864 3358
8a0620e4
SZ
3359 if (ifp->if_flags & IFF_RUNNING)
3360 jme_disable_intr(sc);
3361 ifp->if_npoll_cpuid = sc->jme_npoll_txoff;
3362 } else {
3363 if (ifp->if_flags & IFF_RUNNING)
3364 jme_enable_intr(sc);
3365 ifp->if_npoll_cpuid = -1;
3366 }
3367}
9de40864 3368
8a0620e4
SZ
3369static int
3370jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3371{
3372 struct jme_softc *sc = (void *)arg1;
3373 struct ifnet *ifp = &sc->arpcom.ac_if;
3374 int error, off;
3375
3376 off = sc->jme_npoll_rxoff;
3377 error = sysctl_handle_int(oidp, &off, 0, req);
3378 if (error || req->newptr == NULL)
3379 return error;
3380 if (off < 0)
3381 return EINVAL;
3382
3383 ifnet_serialize_all(ifp);
3384 if (off >= ncpus2 || off % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3385 error = EINVAL;
3386 } else {
3387 error = 0;
3388 sc->jme_npoll_rxoff = off;
3389 }
3390 ifnet_deserialize_all(ifp);
3391
3392 return error;
3393}
3394
3395static int
3396jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3397{
3398 struct jme_softc *sc = (void *)arg1;
3399 struct ifnet *ifp = &sc->arpcom.ac_if;
3400 int error, off;
3401
3402 off = sc->jme_npoll_txoff;
3403 error = sysctl_handle_int(oidp, &off, 0, req);
3404 if (error || req->newptr == NULL)
3405 return error;
3406 if (off < 0)
3407 return EINVAL;
3408
3409 ifnet_serialize_all(ifp);
3410 if (off >= ncpus2) {
3411 error = EINVAL;
3412 } else {
3413 error = 0;
3414 sc->jme_npoll_txoff = off;
9de40864 3415 }
8a0620e4
SZ
3416 ifnet_deserialize_all(ifp);
3417
3418 return error;
9de40864
SZ
3419}
3420
8a0620e4 3421#endif /* IFPOLL_ENABLE */
4447c752
SZ
3422
3423static int
dea2452a 3424jme_rxring_dma_alloc(struct jme_rxdata *rdata)
4447c752 3425{
1128a202 3426 bus_dmamem_t dmem;
ff7f3632 3427 int error, asize;
4447c752 3428
ff7f3632 3429 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
dea2452a 3430 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
1128a202 3431 JME_RX_RING_ALIGN, 0,
0eb220ec 3432 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ff7f3632 3433 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4447c752 3434 if (error) {
dea2452a
SZ
3435 device_printf(rdata->jme_sc->jme_dev,
3436 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
4447c752
SZ
3437 return error;
3438 }
1128a202
SZ
3439 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3440 rdata->jme_rx_ring_map = dmem.dmem_map;
3441 rdata->jme_rx_ring = dmem.dmem_addr;
3442 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
4447c752
SZ
3443
3444 return 0;
3445}
3446
3447static int
064b75ed
SZ
3448jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3449{
3450 if ((paddr & 0xffffffff) == 0) {
3451 /*
3452 * Don't allow lower 32bits of the RX buffer's
3453 * physical address to be 0, else it will break
3454 * hardware pending RSS information delivery
3455 * detection on RX path.
3456 */
3457 return 1;
3458 }
3459 return 0;
3460}
3461
3462static int
dea2452a 3463jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
4447c752 3464{
064b75ed 3465 bus_addr_t lowaddr;
4447c752
SZ
3466 int i, error;
3467
064b75ed
SZ
3468 lowaddr = BUS_SPACE_MAXADDR;
3469 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3470 /* jme_rxbuf_dma_filter will be called */
3471 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3472 }
3473
4447c752 3474 /* Create tag for Rx buffers. */
dea2452a
SZ
3475 error = bus_dma_tag_create(
3476 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
4447c752 3477 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
064b75ed 3478 lowaddr, /* lowaddr */
4447c752 3479 BUS_SPACE_MAXADDR, /* highaddr */
064b75ed 3480 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
4447c752
SZ
3481 MCLBYTES, /* maxsize */
3482 1, /* nsegments */
3483 MCLBYTES, /* maxsegsize */
9d424cee 3484 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
4447c752
SZ
3485 &rdata->jme_rx_tag);
3486 if (error) {
dea2452a
SZ
3487 device_printf(rdata->jme_sc->jme_dev,
3488 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
4447c752
SZ
3489 return error;
3490 }
3491
3492 /* Create DMA maps for Rx buffers. */
9d424cee 3493 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ
3494 &rdata->jme_rx_sparemap);
3495 if (error) {
dea2452a
SZ
3496 device_printf(rdata->jme_sc->jme_dev,
3497 "could not create %dth spare Rx dmamap.\n",
3498 rdata->jme_rx_idx);
4447c752
SZ
3499 bus_dma_tag_destroy(rdata->jme_rx_tag);
3500 rdata->jme_rx_tag = NULL;
3501 return error;
3502 }
7b040092 3503 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
3504 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3505
9d424cee 3506 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ
3507 &rxd->rx_dmamap);
3508 if (error) {
3509 int j;
3510
dea2452a 3511 device_printf(rdata->jme_sc->jme_dev,
4447c752 3512 "could not create %dth Rx dmamap "
dea2452a 3513 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
4447c752
SZ
3514
3515 for (j = 0; j < i; ++j) {
3516 rxd = &rdata->jme_rxdesc[j];
3517 bus_dmamap_destroy(rdata->jme_rx_tag,
3518 rxd->rx_dmamap);
3519 }
3520 bus_dmamap_destroy(rdata->jme_rx_tag,
3521 rdata->jme_rx_sparemap);
3522 bus_dma_tag_destroy(rdata->jme_rx_tag);
3523 rdata->jme_rx_tag = NULL;
3524 return error;
3525 }
3526 }
3527 return 0;
3528}
3529
3530static void
3531jme_rx_intr(struct jme_softc *sc, uint32_t status)
3532{
eda7db08 3533 int r;
4447c752 3534
7b040092 3535 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31810fb8 3536 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
31f0d5a2 3537
31810fb8 3538 if (status & rdata->jme_rx_coal) {
31f0d5a2 3539 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3540 jme_rxeof(rdata, -1);
31f0d5a2
SZ
3541 lwkt_serialize