[dragonfly.git] / sys / dev / netif / igb / if_igb.h

/*
 * Copyright (c) 2001-2011, Intel Corporation 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
 * modification, are permitted provided that the following conditions are met:
 * 
 *  1. Redistributions of source code must retain the above copyright notice, 
 *     this list of conditions and the following disclaimer.
 * 
 *  2. Redistributions in binary form must reproduce the above copyright 
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 * 
 *  3. Neither the name of the Intel Corporation nor the names of its 
 *     contributors may be used to endorse or promote products derived from 
 *     this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _IF_IGB_H_
#define _IF_IGB_H_

/* Tunables */

/*
 * Max ring count
 */
#define IGB_MAX_RING_82575	4
#define IGB_MAX_RING_I350	8
#define IGB_MAX_RING_82580	8
#define IGB_MAX_RING_82576	16
#define IGB_MIN_RING		1
#define IGB_MIN_RING_RSS	2

/*
 * Max TX/RX interrupt bits
 */
#define IGB_MAX_TXRXINT_82575	4	/* XXX not used */
#define IGB_MAX_TXRXINT_I350	8
#define IGB_MAX_TXRXINT_82580	8
#define IGB_MAX_TXRXINT_82576	16
#define IGB_MIN_TXRXINT		2	/* XXX VF? */

/*
 * Max IVAR count
 */
#define IGB_MAX_IVAR_I350	4
#define IGB_MAX_IVAR_82580	4
#define IGB_MAX_IVAR_82576	8
#define IGB_MAX_IVAR_VF		1

/*
 * IGB_TXD: Maximum number of Transmit Descriptors
 *
 *   This value is the number of transmit descriptors allocated by the driver.
 *   Increasing this value allows the driver to queue more transmits. Each
 *   descriptor is 16 bytes.
 *   Since TDLEN should be multiple of 128bytes, the number of transmit
 *   desscriptors should meet the following condition.
 *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
 */
#define IGB_MIN_TXD		256
#define IGB_DEFAULT_TXD		1024
#define IGB_MAX_TXD		4096

/*
 * IGB_RXD: Maximum number of Transmit Descriptors
 *
 *   This value is the number of receive descriptors allocated by the driver.
 *   Increasing this value allows the driver to buffer more incoming packets.
 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
 *   descriptor. The maximum MTU size is 16110.
 *   Since TDLEN should be multiple of 128bytes, the number of transmit
 *   desscriptors should meet the following condition.
 *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
 */
#define IGB_MIN_RXD		256
#define IGB_DEFAULT_RXD		1024
#define IGB_MAX_RXD		4096

/*
 * This parameter controls when the driver calls the routine to reclaim
 * transmit descriptors. Cleaning earlier seems a win.
 */
#define IGB_TX_CLEANUP_THRESHOLD(sc)	((sc)->num_tx_desc / 2)

/*
 * This parameter controls whether or not autonegotation is enabled.
 *              0 - Disable autonegotiation
 *              1 - Enable  autonegotiation
 */
#define DO_AUTO_NEG		1

/*
 * This parameter control whether or not the driver will wait for
 * autonegotiation to complete.
 *              1 - Wait for autonegotiation to complete
 *              0 - Don't wait for autonegotiation to complete
 */
#define WAIT_FOR_AUTO_NEG_DEFAULT	0

/* Tunables -- End */

#define AUTONEG_ADV_DEFAULT	(ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
				 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
				 ADVERTISE_1000_FULL)

#define AUTO_ALL_MODES			0

/* PHY master/slave setting */
#define IGB_MASTER_SLAVE		e1000_ms_hw_default

/*
 * Micellaneous constants
 */
#define IGB_VENDOR_ID			0x8086

#define IGB_JUMBO_PBA			0x00000028
#define IGB_DEFAULT_PBA			0x00000030
#define IGB_SMARTSPEED_DOWNSHIFT	3
#define IGB_SMARTSPEED_MAX		15
#define IGB_MAX_LOOP			10

#define IGB_RX_PTHRESH			(hw->mac.type <= e1000_82576 ? 16 : 8)
#define IGB_RX_HTHRESH			8
#define IGB_RX_WTHRESH			1

#define IGB_TX_PTHRESH			8
#define IGB_TX_HTHRESH			1
#define IGB_TX_WTHRESH			16

#define MAX_NUM_MULTICAST_ADDRESSES	128
#define IGB_FC_PAUSE_TIME		0x0680

#define IGB_INTR_RATE			10000
#define IGB_MSIX_RX_RATE		6000
#define IGB_MSIX_TX_RATE		4000

/*
 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
 * also optimize cache line size effect. H/W supports up to cache line size 128.
 */
#define IGB_DBA_ALIGN			128

/* PCI Config defines */
#define IGB_MSIX_BAR			3

#define IGB_MAX_SCATTER			64
#define IGB_VFTA_SIZE			128
#define IGB_TSO_SIZE			(65535 + \
					 sizeof(struct ether_vlan_header))
#define IGB_TSO_SEG_SIZE		4096	/* Max dma segment size */
#define IGB_HDR_BUF			128
#define IGB_PKTTYPE_MASK		0x0000FFF0

#define IGB_CSUM_FEATURES		(CSUM_IP | CSUM_TCP | CSUM_UDP)
#define IGB_IPVHL_SIZE			1 /* sizeof(ip.ip_vhl) */
#define IGB_TXCSUM_MINHL		(ETHER_HDR_LEN + EVL_ENCAPLEN + \
					 IGB_IPVHL_SIZE)

/* One for TX csum offloading desc, the other 2 are reserved */
#define IGB_TX_RESERVED			3

/* Large enough for 64K TSO */
#define IGB_TX_SPARE			32

#define IGB_TX_OACTIVE_MAX		64

/* main + 16x RX + 16x TX */
#define IGB_NSERIALIZE			33

#define IGB_NRSSRK			10
#define IGB_RSSRK_SIZE			4
#define IGB_RSSRK_VAL(key, i)		(key[(i) * IGB_RSSRK_SIZE] | \
					 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \
					 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \
					 key[(i) * IGB_RSSRK_SIZE + 3] << 24)

#define IGB_NRETA			32
#define IGB_RETA_SIZE			4
#define IGB_RETA_SHIFT			0
#define IGB_RETA_SHIFT_82575		6

struct igb_softc;

/*
 * Bus dma information structure
 */
struct igb_dma {
	bus_addr_t		dma_paddr;
	void			*dma_vaddr;
	bus_dma_tag_t		dma_tag;
	bus_dmamap_t		dma_map;
};

/*
 * Transmit ring: one per queue
 */
struct igb_tx_ring {
	struct lwkt_serialize	tx_serialize;
	struct igb_softc	*sc;
	uint32_t		me;
	struct igb_dma		txdma;
	bus_dma_tag_t		tx_hdr_dtag;
	bus_dmamap_t		tx_hdr_dmap;
	bus_addr_t		tx_hdr_paddr;
	struct e1000_tx_desc	*tx_base;
	int			num_tx_desc;
	uint32_t		next_avail_desc;
	uint32_t		next_to_clean;
	uint32_t		*tx_hdr;
	int			tx_avail;
	struct igb_tx_buf	*tx_buf;
	bus_dma_tag_t		tx_tag;
	int			tx_nsegs;
	int			spare_desc;
	int			oact_lo_desc;
	int			oact_hi_desc;
	int			intr_nsegs;
	int			tx_intr_bit;
	uint32_t		tx_intr_mask;

	u_long			no_desc_avail;
	u_long			tx_packets;

	u_long			ctx_try_pullup;
	u_long			ctx_drop1;
	u_long			ctx_drop2;
	u_long			ctx_pullup1;
	u_long			ctx_pullup1_failed;
	u_long			ctx_pullup2;
	u_long			ctx_pullup2_failed;
};

/*
 * Receive ring: one per queue
 */
struct igb_rx_ring {
	struct lwkt_serialize	rx_serialize;
	struct igb_softc	*sc;
	uint32_t		me;
	struct igb_dma		rxdma;
	union e1000_adv_rx_desc	*rx_base;
	boolean_t		discard;
	int			num_rx_desc;
	uint32_t		next_to_check;
	struct igb_rx_buf	*rx_buf;
	bus_dma_tag_t		rx_tag;
	bus_dmamap_t		rx_sparemap;
	int			rx_intr_bit;
	uint32_t		rx_intr_mask;

	/*
	 * First/last mbuf pointers, for
	 * collecting multisegment RX packets.
	 */
	struct mbuf		*fmp;
	struct mbuf		*lmp;

	/* Soft stats */
	u_long			rx_packets;
};

struct igb_msix_data {
	struct lwkt_serialize	*msix_serialize;
	struct lwkt_serialize	msix_serialize0;
	struct igb_softc	*msix_sc;
	uint32_t		msix_mask;
	struct igb_rx_ring	*msix_rx;
	struct igb_tx_ring	*msix_tx;

	driver_intr_t		*msix_func;
	void			*msix_arg;

	int			msix_cpuid;
	char			msix_desc[32];
	int			msix_rid;
	struct resource		*msix_res;
	void			*msix_handle;
	u_int			msix_vector;
	int			msix_rate;
	char			msix_rate_desc[32];
};

struct igb_softc {
	struct arpcom		arpcom;
	struct e1000_hw		hw;

	struct e1000_osdep	osdep;
	device_t		dev;
	uint32_t		flags;
#define IGB_FLAG_SHARED_INTR	0x1
#define IGB_FLAG_HAS_MGMT	0x2

	bus_dma_tag_t		parent_tag;

	int			mem_rid;
	struct resource 	*mem_res;

	struct ifmedia		media;
	struct callout		timer;

	int			intr_type;
	int			intr_rid;
	struct resource		*intr_res;
	void			*intr_tag;

	int			if_flags;
	int			max_frame_size;
	int			pause_frames;
	uint16_t		vf_ifp;	/* a VF interface */

	/* Management and WOL features */
	int			wol;

	/* Info about the interface */
	uint8_t			link_active;
	uint16_t		link_speed;
	uint16_t		link_duplex;
	uint32_t		smartspeed;
	uint32_t		dma_coalesce;

	/* Multicast array pointer */
	uint8_t			*mta;

	int			serialize_cnt;
	int			tx_serialize;
	int			rx_serialize;
	struct lwkt_serialize	*serializes[IGB_NSERIALIZE];
	struct lwkt_serialize	main_serialize;

	int			intr_rate;
	uint32_t		intr_mask;
	int			sts_intr_bit;
	uint32_t		sts_intr_mask;

	/*
	 * Transmit rings
	 */
	int			tx_ring_cnt;
	struct igb_tx_ring	*tx_rings;

	/*
	 * Receive rings
	 */
	int			rss_debug;
	int			rx_ring_cnt;
	int			rx_ring_msix;
	int			rx_ring_inuse;
	struct igb_rx_ring	*rx_rings;

	/* Misc stats maintained by the driver */
	u_long			dropped_pkts;
	u_long			mbuf_defrag_failed;
	u_long			no_tx_dma_setup;
	u_long			watchdog_events;
	u_long			rx_overruns;
	u_long			device_control;
	u_long			rx_control;
	u_long			int_mask;
	u_long			eint_mask;
	u_long			packet_buf_alloc_rx;
	u_long			packet_buf_alloc_tx;

	/* sysctl tree glue */
	struct sysctl_ctx_list	sysctl_ctx;
	struct sysctl_oid	*sysctl_tree;

	void 			*stats;

	int			msix_tx_cpuid;
	int			msix_mem_rid;
	struct resource 	*msix_mem_res;
	int			msix_cnt;
	struct igb_msix_data	*msix_data;
};

#define IGB_ENABLE_HWRSS(sc)	((sc)->rx_ring_cnt > 1)

struct igb_tx_buf {
	struct mbuf	*m_head;
	bus_dmamap_t	map;		/* bus_dma map for packet */
};

struct igb_rx_buf {
	struct mbuf	*m_head;
	bus_dmamap_t	map;	/* bus_dma map for packet */
	bus_addr_t	paddr;
};

#define UPDATE_VF_REG(reg, last, cur)		\
{						\
	uint32_t new = E1000_READ_REG(hw, reg);	\
	if (new < last)				\
		cur += 0x100000000LL;		\
	last = new;				\
	cur &= 0xFFFFFFFF00000000LL;		\
	cur |= new;				\
}

#define IGB_IS_OACTIVE(txr)	((txr)->tx_avail < (txr)->oact_lo_desc)
#define IGB_IS_NOT_OACTIVE(txr)	((txr)->tx_avail >= (txr)->oact_hi_desc)

#endif /* _IF_IGB_H_ */
Commit	Line	Data
1f7e3916 SZ	1	/*
	2	* Copyright (c) 2001-2011, Intel Corporation
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	*
	8	* 1. Redistributions of source code must retain the above copyright notice,
	9	* this list of conditions and the following disclaimer.
	10	*
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	*
	15	* 3. Neither the name of the Intel Corporation nor the names of its
	16	* contributors may be used to endorse or promote products derived from
	17	* this software without specific prior written permission.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	* POSSIBILITY OF SUCH DAMAGE.
	30	*/
	31
	32	#ifndef _IF_IGB_H_
	33	#define _IF_IGB_H_
	34
	35	/* Tunables */
	36
	37	/*
8d6600da SZ	38	* Max ring count
	39	*/
	40	#define IGB_MAX_RING_82575 4
	41	#define IGB_MAX_RING_I350 8
	42	#define IGB_MAX_RING_82580 8
	43	#define IGB_MAX_RING_82576 16
	44	#define IGB_MIN_RING 1
be922da6	45	#define IGB_MIN_RING_RSS 2
8d6600da SZ	46
	47	/*
	48	* Max TX/RX interrupt bits
	49	*/
	50	#define IGB_MAX_TXRXINT_82575 4 /* XXX not used */
	51	#define IGB_MAX_TXRXINT_I350 8
	52	#define IGB_MAX_TXRXINT_82580 8
	53	#define IGB_MAX_TXRXINT_82576 16
	54	#define IGB_MIN_TXRXINT 2 /* XXX VF? */
	55
	56	/*
9c0ecdcc SZ	57	* Max IVAR count
	58	*/
	59	#define IGB_MAX_IVAR_I350 4
	60	#define IGB_MAX_IVAR_82580 4
	61	#define IGB_MAX_IVAR_82576 8
	62	#define IGB_MAX_IVAR_VF 1
	63
	64	/*
1f7e3916 SZ	65	* IGB_TXD: Maximum number of Transmit Descriptors
	66	*
	67	* This value is the number of transmit descriptors allocated by the driver.
	68	* Increasing this value allows the driver to queue more transmits. Each
	69	* descriptor is 16 bytes.
	70	* Since TDLEN should be multiple of 128bytes, the number of transmit
	71	* desscriptors should meet the following condition.
	72	* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
	73	*/
	74	#define IGB_MIN_TXD 256
	75	#define IGB_DEFAULT_TXD 1024
	76	#define IGB_MAX_TXD 4096
	77
	78	/*
	79	* IGB_RXD: Maximum number of Transmit Descriptors
	80	*
	81	* This value is the number of receive descriptors allocated by the driver.
	82	* Increasing this value allows the driver to buffer more incoming packets.
	83	* Each descriptor is 16 bytes. A receive buffer is also allocated for each
	84	* descriptor. The maximum MTU size is 16110.
	85	* Since TDLEN should be multiple of 128bytes, the number of transmit
	86	* desscriptors should meet the following condition.
	87	* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
	88	*/
	89	#define IGB_MIN_RXD 256
	90	#define IGB_DEFAULT_RXD 1024
	91	#define IGB_MAX_RXD 4096
	92
	93	/*
	94	* This parameter controls when the driver calls the routine to reclaim
	95	* transmit descriptors. Cleaning earlier seems a win.
	96	*/
	97	#define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
	98
	99	/*
	100	* This parameter controls whether or not autonegotation is enabled.
	101	* 0 - Disable autonegotiation
	102	* 1 - Enable autonegotiation
	103	*/
	104	#define DO_AUTO_NEG 1
	105
	106	/*
	107	* This parameter control whether or not the driver will wait for
	108	* autonegotiation to complete.
	109	* 1 - Wait for autonegotiation to complete
	110	* 0 - Don't wait for autonegotiation to complete
	111	*/
	112	#define WAIT_FOR_AUTO_NEG_DEFAULT 0
	113
	114	/* Tunables -- End */
	115
	116	#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF \| ADVERTISE_10_FULL \| \
	117	ADVERTISE_100_HALF \| ADVERTISE_100_FULL \| \
	118	ADVERTISE_1000_FULL)
	119
	120	#define AUTO_ALL_MODES 0
	121
	122	/* PHY master/slave setting */
	123	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	124
	125	/*
	126	* Micellaneous constants
	127	*/
	128	#define IGB_VENDOR_ID 0x8086
129
130	#define IGB_JUMBO_PBA 0x00000028
131	#define IGB_DEFAULT_PBA 0x00000030
132	#define IGB_SMARTSPEED_DOWNSHIFT 3
133	#define IGB_SMARTSPEED_MAX 15
134	#define IGB_MAX_LOOP 10
135
136	#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
137	#define IGB_RX_HTHRESH 8
138	#define IGB_RX_WTHRESH 1
139
140	#define IGB_TX_PTHRESH 8
141	#define IGB_TX_HTHRESH 1
396b7048	142	#define IGB_TX_WTHRESH 16
1f7e3916 SZ	143
	144	#define MAX_NUM_MULTICAST_ADDRESSES 128
	145	#define IGB_FC_PAUSE_TIME 0x0680
	146
	147	#define IGB_INTR_RATE 10000
9c0ecdcc SZ	148	#define IGB_MSIX_RX_RATE 6000
9c0ecdcc SZ	149	#define IGB_MSIX_TX_RATE 4000
1f7e3916 SZ	150
	151	/*
	152	* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
	153	* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
	154	* also optimize cache line size effect. H/W supports up to cache line size 128.
	155	*/
	156	#define IGB_DBA_ALIGN 128
	157
	158	/* PCI Config defines */
	159	#define IGB_MSIX_BAR 3
	160
	161	#define IGB_MAX_SCATTER 64
	162	#define IGB_VFTA_SIZE 128
	163	#define IGB_TSO_SIZE (65535 + \
	164	sizeof(struct ether_vlan_header))
	165	#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
	166	#define IGB_HDR_BUF 128
	167	#define IGB_PKTTYPE_MASK 0x0000FFF0
	168
	169	#define IGB_CSUM_FEATURES (CSUM_IP \| CSUM_TCP \| CSUM_UDP)
	170	#define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
	171	#define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
	172	IGB_IPVHL_SIZE)
	173
b6220144 SZ	174	/* One for TX csum offloading desc, the other 2 are reserved */
	175	#define IGB_TX_RESERVED 3
	176
	177	/* Large enough for 64K TSO */
	178	#define IGB_TX_SPARE 32
	179
	180	#define IGB_TX_OACTIVE_MAX 64
	181
7d235eb5 SZ	182	/* main + 16x RX + 16x TX */
	183	#define IGB_NSERIALIZE 33
	184
8d6600da SZ	185	#define IGB_NRSSRK 10
	186	#define IGB_RSSRK_SIZE 4
	187	#define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] \| \
	188	key[(i) * IGB_RSSRK_SIZE + 1] << 8 \| \
	189	key[(i) * IGB_RSSRK_SIZE + 2] << 16 \| \
	190	key[(i) * IGB_RSSRK_SIZE + 3] << 24)
	191
	192	#define IGB_NRETA 32
	193	#define IGB_RETA_SIZE 4
	194	#define IGB_RETA_SHIFT 0
	195	#define IGB_RETA_SHIFT_82575 6
	196
1f7e3916 SZ	197	struct igb_softc;
	198
	199	/*
	200	* Bus dma information structure
	201	*/
	202	struct igb_dma {
	203	bus_addr_t dma_paddr;
	204	void *dma_vaddr;
	205	bus_dma_tag_t dma_tag;
	206	bus_dmamap_t dma_map;
	207	};
	208
	209	/*
1f7e3916 SZ	210	* Transmit ring: one per queue
	211	*/
	212	struct igb_tx_ring {
7d235eb5	213	struct lwkt_serialize tx_serialize;
1f7e3916 SZ	214	struct igb_softc *sc;
	215	uint32_t me;
	216	struct igb_dma txdma;
b6220144 SZ	217	bus_dma_tag_t tx_hdr_dtag;
	218	bus_dmamap_t tx_hdr_dmap;
	219	bus_addr_t tx_hdr_paddr;
1f7e3916	220	struct e1000_tx_desc *tx_base;
91b8700a	221	int num_tx_desc;
1f7e3916 SZ	222	uint32_t next_avail_desc;
1f7e3916 SZ	223	uint32_t next_to_clean;
b6220144 SZ	224	uint32_t *tx_hdr;
b6220144 SZ	225	int tx_avail;
1f7e3916 SZ	226	struct igb_tx_buf *tx_buf;
1f7e3916 SZ	227	bus_dma_tag_t tx_tag;
b6220144 SZ	228	int tx_nsegs;
	229	int spare_desc;
	230	int oact_lo_desc;
	231	int oact_hi_desc;
	232	int intr_nsegs;
f6167a56 SZ	233	int tx_intr_bit;
f6167a56 SZ	234	uint32_t tx_intr_mask;
1f7e3916 SZ	235
	236	u_long no_desc_avail;
	237	u_long tx_packets;
	238
	239	u_long ctx_try_pullup;
	240	u_long ctx_drop1;
	241	u_long ctx_drop2;
	242	u_long ctx_pullup1;
	243	u_long ctx_pullup1_failed;
	244	u_long ctx_pullup2;
	245	u_long ctx_pullup2_failed;
	246	};
	247
	248	/*
	249	* Receive ring: one per queue
	250	*/
	251	struct igb_rx_ring {
7d235eb5	252	struct lwkt_serialize rx_serialize;
1f7e3916 SZ	253	struct igb_softc *sc;
	254	uint32_t me;
	255	struct igb_dma rxdma;
	256	union e1000_adv_rx_desc *rx_base;
	257	boolean_t discard;
91b8700a	258	int num_rx_desc;
1f7e3916 SZ	259	uint32_t next_to_check;
	260	struct igb_rx_buf *rx_buf;
	261	bus_dma_tag_t rx_tag;
	262	bus_dmamap_t rx_sparemap;
f6167a56 SZ	263	int rx_intr_bit;
f6167a56 SZ	264	uint32_t rx_intr_mask;
1f7e3916 SZ	265
	266	/*
	267	* First/last mbuf pointers, for
	268	* collecting multisegment RX packets.
	269	*/
	270	struct mbuf *fmp;
	271	struct mbuf *lmp;
	272
	273	/* Soft stats */
	274	u_long rx_packets;
	275	};
	276
9c0ecdcc SZ	277	struct igb_msix_data {
	278	struct lwkt_serialize *msix_serialize;
	279	struct lwkt_serialize msix_serialize0;
	280	struct igb_softc *msix_sc;
	281	uint32_t msix_mask;
	282	struct igb_rx_ring *msix_rx;
	283	struct igb_tx_ring *msix_tx;
	284
	285	driver_intr_t *msix_func;
	286	void *msix_arg;
	287
	288	int msix_cpuid;
	289	char msix_desc[32];
	290	int msix_rid;
	291	struct resource *msix_res;
	292	void *msix_handle;
	293	u_int msix_vector;
	294	int msix_rate;
	295	char msix_rate_desc[32];
	296	};
	297
1f7e3916 SZ	298	struct igb_softc {
	299	struct arpcom arpcom;
	300	struct e1000_hw hw;
	301
	302	struct e1000_osdep osdep;
	303	device_t dev;
f6167a56 SZ	304	uint32_t flags;
f6167a56 SZ	305	#define IGB_FLAG_SHARED_INTR 0x1
396b7048	306	#define IGB_FLAG_HAS_MGMT 0x2
1f7e3916 SZ	307
	308	bus_dma_tag_t parent_tag;
	309
	310	int mem_rid;
	311	struct resource *mem_res;
	312
1f7e3916 SZ	313	struct ifmedia media;
	314	struct callout timer;
	315
1f7e3916 SZ	316	int intr_type;
	317	int intr_rid;
	318	struct resource *intr_res;
	319	void *intr_tag;
	320
	321	int if_flags;
	322	int max_frame_size;
1f7e3916	323	int pause_frames;
1f7e3916 SZ	324	uint16_t vf_ifp; /* a VF interface */
	325
	326	/* Management and WOL features */
	327	int wol;
1f7e3916 SZ	328
	329	/* Info about the interface */
	330	uint8_t link_active;
	331	uint16_t link_speed;
	332	uint16_t link_duplex;
	333	uint32_t smartspeed;
	334	uint32_t dma_coalesce;
	335
396b7048 SZ	336	/* Multicast array pointer */
	337	uint8_t *mta;
	338
7d235eb5 SZ	339	int serialize_cnt;
	340	int tx_serialize;
	341	int rx_serialize;
	342	struct lwkt_serialize *serializes[IGB_NSERIALIZE];
	343	struct lwkt_serialize main_serialize;
	344
1f7e3916	345	int intr_rate;
f6167a56	346	uint32_t intr_mask;
9c0ecdcc SZ	347	int sts_intr_bit;
9c0ecdcc SZ	348	uint32_t sts_intr_mask;
1f7e3916 SZ	349
	350	/*
	351	* Transmit rings
	352	*/
27866bf1	353	int tx_ring_cnt;
1f7e3916	354	struct igb_tx_ring *tx_rings;
1f7e3916	355
396b7048	356	/*
1f7e3916 SZ	357	* Receive rings
1f7e3916 SZ	358	*/
8d6600da	359	int rss_debug;
27866bf1	360	int rx_ring_cnt;
9c0ecdcc	361	int rx_ring_msix;
be922da6	362	int rx_ring_inuse;
1f7e3916	363	struct igb_rx_ring *rx_rings;
1f7e3916 SZ	364
	365	/* Misc stats maintained by the driver */
	366	u_long dropped_pkts;
	367	u_long mbuf_defrag_failed;
	368	u_long no_tx_dma_setup;
	369	u_long watchdog_events;
	370	u_long rx_overruns;
	371	u_long device_control;
	372	u_long rx_control;
	373	u_long int_mask;
	374	u_long eint_mask;
	375	u_long packet_buf_alloc_rx;
	376	u_long packet_buf_alloc_tx;
	377
	378	/* sysctl tree glue */
	379	struct sysctl_ctx_list sysctl_ctx;
	380	struct sysctl_oid *sysctl_tree;
	381
	382	void *stats;
9c0ecdcc SZ	383
	384	int msix_tx_cpuid;
	385	int msix_mem_rid;
	386	struct resource *msix_mem_res;
	387	int msix_cnt;
	388	struct igb_msix_data *msix_data;
1f7e3916 SZ	389	};
1f7e3916 SZ	390
8d6600da SZ	391	#define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
8d6600da SZ	392
1f7e3916	393	struct igb_tx_buf {
1f7e3916 SZ	394	struct mbuf *m_head;
	395	bus_dmamap_t map; /* bus_dma map for packet */
	396	};
	397
	398	struct igb_rx_buf {
	399	struct mbuf *m_head;
	400	bus_dmamap_t map; /* bus_dma map for packet */
	401	bus_addr_t paddr;
	402	};
	403
	404	#define UPDATE_VF_REG(reg, last, cur) \
	405	{ \
	406	uint32_t new = E1000_READ_REG(hw, reg); \
	407	if (new < last) \
	408	cur += 0x100000000LL; \
	409	last = new; \
	410	cur &= 0xFFFFFFFF00000000LL; \
	411	cur \|= new; \
	412	}
	413
b6220144 SZ	414	#define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
	415	#define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
	416
1f7e3916	417	#endif /* _IF_IGB_H_ */