kernel - Fix floating point save state structure and minor npx issues
[dragonfly.git] / sys / platform / pc64 / x86_64 / npx.c
CommitLineData
d7f50089 1/*
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2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
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4 * Copyright (c) 2006 The DragonFly Project.
5 * Copyright (c) 2006 Matthew Dillon.
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6 * All rights reserved.
7 *
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8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
17 * distribution.
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
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37 */
38
39#include "opt_debug_npx.h"
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/bus.h>
44#include <sys/kernel.h>
45#include <sys/malloc.h>
46#include <sys/module.h>
47#include <sys/sysctl.h>
48#include <sys/proc.h>
49#include <sys/rman.h>
50#ifdef NPX_DEBUG
51#include <sys/syslog.h>
52#endif
53#include <sys/signalvar.h>
684a93c4 54
d7f50089 55#include <sys/thread2.h>
684a93c4 56#include <sys/mplock2.h>
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57
58#ifndef SMP
59#include <machine/asmacros.h>
60#endif
61#include <machine/cputypes.h>
62#include <machine/frame.h>
63#include <machine/md_var.h>
64#include <machine/pcb.h>
65#include <machine/psl.h>
66#ifndef SMP
67#include <machine/clock.h>
68#endif
69#include <machine/specialreg.h>
70#include <machine/segments.h>
71#include <machine/globaldata.h>
72
73#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
74#define fnclex() __asm("fnclex")
75#define fninit() __asm("fninit")
76#define fnop() __asm("fnop")
77#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
78#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
79#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
80#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
81#ifndef CPU_DISABLE_SSE
82#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
83#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
84#endif
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85#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
86 : : "n" (CR0_TS) : "ax")
87#define stop_emulating() __asm("clts")
d7f50089 88
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89typedef u_char bool_t;
90#ifndef CPU_DISABLE_SSE
91static void fpu_clean_state(void);
92#endif
93
c8fe38ae 94static struct krate badfprate = { 1 };
d7f50089 95
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96static void fpusave (union savefpu *);
97static void fpurstor (union savefpu *);
98
d7f50089 99/*
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100 * Initialize the floating point unit.
101 */
102void
103npxinit(u_short control)
104{
1b251f0a 105 static union savefpu dummy __aligned(16);
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106
107 /*
108 * fninit has the same h/w bugs as fnsave. Use the detoxified
109 * fnsave to throw away any junk in the fpu. npxsave() initializes
110 * the fpu and sets npxthread = NULL as important side effects.
111 */
112 npxsave(&dummy);
113 crit_enter();
c8fe38ae 114 stop_emulating();
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115 fldcw(&control);
116 fpusave(curthread->td_savefpu);
117 mdcpu->gd_npxthread = NULL;
c8fe38ae 118 start_emulating();
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119 crit_exit();
120}
121
122/*
123 * Free coprocessor (if we have it).
124 */
125void
126npxexit(void)
127{
128 if (curthread == mdcpu->gd_npxthread)
129 npxsave(curthread->td_savefpu);
130}
131
bfc09ba0 132#if 0
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133/*
134 * The following mechanism is used to ensure that the FPE_... value
135 * that is passed as a trapcode to the signal handler of the user
136 * process does not have more than one bit set.
137 *
138 * Multiple bits may be set if the user process modifies the control
139 * word while a status word bit is already set. While this is a sign
140 * of bad coding, we have no choise than to narrow them down to one
141 * bit, since we must not send a trapcode that is not exactly one of
142 * the FPE_ macros.
143 *
144 * The mechanism has a static table with 127 entries. Each combination
145 * of the 7 FPU status word exception bits directly translates to a
146 * position in this table, where a single FPE_... value is stored.
147 * This FPE_... value stored there is considered the "most important"
148 * of the exception bits and will be sent as the signal code. The
149 * precedence of the bits is based upon Intel Document "Numerical
150 * Applications", Chapter "Special Computational Situations".
151 *
152 * The macro to choose one of these values does these steps: 1) Throw
153 * away status word bits that cannot be masked. 2) Throw away the bits
154 * currently masked in the control word, assuming the user isn't
155 * interested in them anymore. 3) Reinsert status word bit 7 (stack
156 * fault) if it is set, which cannot be masked but must be presered.
157 * 4) Use the remaining bits to point into the trapcode table.
158 *
159 * The 6 maskable bits in order of their preference, as stated in the
160 * above referenced Intel manual:
161 * 1 Invalid operation (FP_X_INV)
162 * 1a Stack underflow
163 * 1b Stack overflow
164 * 1c Operand of unsupported format
165 * 1d SNaN operand.
166 * 2 QNaN operand (not an exception, irrelavant here)
167 * 3 Any other invalid-operation not mentioned above or zero divide
168 * (FP_X_INV, FP_X_DZ)
169 * 4 Denormal operand (FP_X_DNML)
170 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
171 * 6 Inexact result (FP_X_IMP)
172 */
173static char fpetable[128] = {
174 0,
175 FPE_FLTINV, /* 1 - INV */
176 FPE_FLTUND, /* 2 - DNML */
177 FPE_FLTINV, /* 3 - INV | DNML */
178 FPE_FLTDIV, /* 4 - DZ */
179 FPE_FLTINV, /* 5 - INV | DZ */
180 FPE_FLTDIV, /* 6 - DNML | DZ */
181 FPE_FLTINV, /* 7 - INV | DNML | DZ */
182 FPE_FLTOVF, /* 8 - OFL */
183 FPE_FLTINV, /* 9 - INV | OFL */
184 FPE_FLTUND, /* A - DNML | OFL */
185 FPE_FLTINV, /* B - INV | DNML | OFL */
186 FPE_FLTDIV, /* C - DZ | OFL */
187 FPE_FLTINV, /* D - INV | DZ | OFL */
188 FPE_FLTDIV, /* E - DNML | DZ | OFL */
189 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
190 FPE_FLTUND, /* 10 - UFL */
191 FPE_FLTINV, /* 11 - INV | UFL */
192 FPE_FLTUND, /* 12 - DNML | UFL */
193 FPE_FLTINV, /* 13 - INV | DNML | UFL */
194 FPE_FLTDIV, /* 14 - DZ | UFL */
195 FPE_FLTINV, /* 15 - INV | DZ | UFL */
196 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
197 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
198 FPE_FLTOVF, /* 18 - OFL | UFL */
199 FPE_FLTINV, /* 19 - INV | OFL | UFL */
200 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
201 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
202 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
203 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
204 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
205 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
206 FPE_FLTRES, /* 20 - IMP */
207 FPE_FLTINV, /* 21 - INV | IMP */
208 FPE_FLTUND, /* 22 - DNML | IMP */
209 FPE_FLTINV, /* 23 - INV | DNML | IMP */
210 FPE_FLTDIV, /* 24 - DZ | IMP */
211 FPE_FLTINV, /* 25 - INV | DZ | IMP */
212 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
213 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
214 FPE_FLTOVF, /* 28 - OFL | IMP */
215 FPE_FLTINV, /* 29 - INV | OFL | IMP */
216 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
217 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
218 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
219 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
220 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
221 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
222 FPE_FLTUND, /* 30 - UFL | IMP */
223 FPE_FLTINV, /* 31 - INV | UFL | IMP */
224 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
225 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
226 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
227 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
228 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
229 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
230 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
231 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
232 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
233 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
234 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
235 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
236 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
237 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
238 FPE_FLTSUB, /* 40 - STK */
239 FPE_FLTSUB, /* 41 - INV | STK */
240 FPE_FLTUND, /* 42 - DNML | STK */
241 FPE_FLTSUB, /* 43 - INV | DNML | STK */
242 FPE_FLTDIV, /* 44 - DZ | STK */
243 FPE_FLTSUB, /* 45 - INV | DZ | STK */
244 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
245 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
246 FPE_FLTOVF, /* 48 - OFL | STK */
247 FPE_FLTSUB, /* 49 - INV | OFL | STK */
248 FPE_FLTUND, /* 4A - DNML | OFL | STK */
249 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
250 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
251 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
252 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
253 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
254 FPE_FLTUND, /* 50 - UFL | STK */
255 FPE_FLTSUB, /* 51 - INV | UFL | STK */
256 FPE_FLTUND, /* 52 - DNML | UFL | STK */
257 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
258 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
259 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
260 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
261 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
262 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
263 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
264 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
265 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
266 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
267 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
268 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
269 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
270 FPE_FLTRES, /* 60 - IMP | STK */
271 FPE_FLTSUB, /* 61 - INV | IMP | STK */
272 FPE_FLTUND, /* 62 - DNML | IMP | STK */
273 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
274 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
275 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
276 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
277 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
278 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
279 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
280 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
281 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
282 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
283 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
284 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
285 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
286 FPE_FLTUND, /* 70 - UFL | IMP | STK */
287 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
288 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
289 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
290 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
291 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
292 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
293 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
294 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
295 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
296 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
297 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
298 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
299 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
300 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
301 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
302};
303
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304#endif
305
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306/*
307 * Implement the device not available (DNA) exception. gd_npxthread had
308 * better be NULL. Restore the current thread's FP state and set gd_npxthread
309 * to curthread.
310 *
311 * Interrupts are enabled and preemption can occur. Enter a critical
312 * section to stabilize the FP state.
313 */
314int
c8fe38ae 315npxdna(void)
d7f50089 316{
c8fe38ae 317 thread_t td = curthread;
c8fe38ae 318 int didinit = 0;
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319
320 if (mdcpu->gd_npxthread != NULL) {
321 kprintf("npxdna: npxthread = %p, curthread = %p\n",
322 mdcpu->gd_npxthread, curthread);
323 panic("npxdna");
324 }
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325
326 /*
327 * Setup the initial saved state if the thread has never before
328 * used the FP unit. This also occurs when a thread pushes a
329 * signal handler and uses FP in the handler.
330 */
9e6e869e 331 crit_enter();
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332 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) {
333 td->td_flags |= TDF_USINGFP;
1b251f0a 334 npxinit(__INITIAL_NPXCW__);
c8fe38ae 335 didinit = 1;
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336 }
337
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338 /*
339 * The setting of gd_npxthread and the call to fpurstor() must not
340 * be preempted by an interrupt thread or we will take an npxdna
341 * trap and potentially save our current fpstate (which is garbage)
342 * and then restore the garbage rather then the originally saved
343 * fpstate.
344 */
c8fe38ae 345 stop_emulating();
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346 /*
347 * Record new context early in case frstor causes an IRQ13.
348 */
c8fe38ae 349 mdcpu->gd_npxthread = td;
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350 /*
351 * The following frstor may cause an IRQ13 when the state being
352 * restored has a pending error. The error will appear to have been
353 * triggered by the current (npx) user instruction even when that
354 * instruction is a no-wait instruction that should not trigger an
355 * error (e.g., fnclex). On at least one 486 system all of the
356 * no-wait instructions are broken the same as frstor, so our
357 * treatment does not amplify the breakage. On at least one
358 * 386/Cyrix 387 system, fnclex works correctly while frstor and
359 * fnsave are broken, so our treatment breaks fnclex if it is the
360 * first FPU instruction after a context switch.
361 */
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362 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
363#ifndef CPU_DISABLE_SSE
364 && cpu_fxsr
365#endif
366 ) {
367 krateprintf(&badfprate,
368 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
369 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
370 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
371 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
372 }
373 fpurstor(td->td_savefpu);
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374 crit_exit();
375
376 return (1);
377}
378
379/*
380 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
381 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
382 * any IRQ13 to be handled immediately, and then ignore it. This routine is
383 * often called at splhigh so it must not use many system services. In
384 * particular, it's much easier to install a special handler than to
385 * guarantee that it's safe to use npxintr() and its supporting code.
386 *
387 * WARNING! This call is made during a switch and the MP lock will be
388 * setup for the new target thread rather then the current thread, so we
389 * cannot do anything here that depends on the *_mplock() functions as
390 * we may trip over their assertions.
391 *
392 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
393 * kernel will always assume that the FP state is 'safe' (will not cause
394 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
395 * setup a custom save area before actually using the FP unit, but it will
396 * not bother calling fninit. This greatly improves kernel performance when
397 * it wishes to use the FP unit.
398 */
399void
400npxsave(union savefpu *addr)
401{
402 crit_enter();
c8fe38ae 403 stop_emulating();
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404 fpusave(addr);
405 mdcpu->gd_npxthread = NULL;
406 fninit();
c8fe38ae 407 start_emulating();
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408 crit_exit();
409}
410
411static void
412fpusave(union savefpu *addr)
413{
c8fe38ae 414#ifndef CPU_DISABLE_SSE
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415 if (cpu_fxsr)
416 fxsave(addr);
417 else
c8fe38ae 418#endif
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419 fnsave(addr);
420}
421
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422/*
423 * Save the FP state to the mcontext structure.
424 *
425 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
426 * then it MUST be 16-byte aligned. Currently this is not guarenteed.
427 */
428void
429npxpush(mcontext_t *mctx)
430{
431 thread_t td = curthread;
432
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433 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
434
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435 if (td->td_flags & TDF_USINGFP) {
436 if (mdcpu->gd_npxthread == td) {
437 /*
438 * XXX Note: This is a bit inefficient if the signal
439 * handler uses floating point, extra faults will
440 * occur.
441 */
442 mctx->mc_ownedfp = _MC_FPOWNED_FPU;
443 npxsave(td->td_savefpu);
444 } else {
445 mctx->mc_ownedfp = _MC_FPOWNED_PCB;
446 }
447 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
448 td->td_flags &= ~TDF_USINGFP;
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449 mctx->mc_fpformat =
450#ifndef CPU_DISABLE_SSE
451 (cpu_fxsr) ? _MC_FPFMT_XMM :
452#endif
453 _MC_FPFMT_387;
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454 } else {
455 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
c8fe38ae 456 mctx->mc_fpformat = _MC_FPFMT_NODEV;
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457 }
458}
459
460/*
461 * Restore the FP state from the mcontext structure.
462 */
463void
464npxpop(mcontext_t *mctx)
465{
466 thread_t td = curthread;
467
468 switch(mctx->mc_ownedfp) {
469 case _MC_FPOWNED_NONE:
470 /*
471 * If the signal handler used the FP unit but the interrupted
472 * code did not, release the FP unit. Clear TDF_USINGFP will
473 * force the FP unit to reinit so the interrupted code sees
474 * a clean slate.
475 */
476 if (td->td_flags & TDF_USINGFP) {
477 if (td == mdcpu->gd_npxthread)
478 npxsave(td->td_savefpu);
479 td->td_flags &= ~TDF_USINGFP;
480 }
481 break;
482 case _MC_FPOWNED_FPU:
483 case _MC_FPOWNED_PCB:
484 /*
485 * Clear ownership of the FP unit and restore our saved state.
486 *
487 * NOTE: The signal handler may have set-up some FP state and
488 * enabled the FP unit, so we have to restore no matter what.
489 *
490 * XXX: This is bit inefficient, if the code being returned
491 * to is actively using the FP this results in multiple
492 * kernel faults.
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493 *
494 * WARNING: The saved state was exposed to userland and may
495 * have to be sanitized to avoid a GP fault in the kernel.
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496 */
497 if (td == mdcpu->gd_npxthread)
498 npxsave(td->td_savefpu);
499 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
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MD
500 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
501#ifndef CPU_DISABLE_SSE
502 && cpu_fxsr
503#endif
504 ) {
505 krateprintf(&badfprate,
506 "pid %d (%s) signal return from user: "
507 "illegal FP MXCSR %08x\n",
508 td->td_proc->p_pid,
509 td->td_proc->p_comm,
510 td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
511 }
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MD
512 td->td_flags |= TDF_USINGFP;
513 break;
514 }
515}
516
517
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YY
518#ifndef CPU_DISABLE_SSE
519/*
520 * On AuthenticAMD processors, the fxrstor instruction does not restore
521 * the x87's stored last instruction pointer, last data pointer, and last
522 * opcode values, except in the rare case in which the exception summary
523 * (ES) bit in the x87 status word is set to 1.
524 *
525 * In order to avoid leaking this information across processes, we clean
526 * these values by performing a dummy load before executing fxrstor().
527 */
528static double dummy_variable = 0.0;
529static void
530fpu_clean_state(void)
531{
532 u_short status;
533
534 /*
535 * Clear the ES bit in the x87 status word if it is currently
536 * set, in order to avoid causing a fault in the upcoming load.
537 */
538 fnstsw(&status);
539 if (status & 0x80)
540 fnclex();
541
542 /*
543 * Load the dummy variable into the x87 stack. This mangles
544 * the x87 stack, but we don't care since we're about to call
545 * fxrstor() anyway.
546 */
6fb07b8b 547 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
d7f50089
YY
548}
549#endif /* CPU_DISABLE_SSE */
550
551static void
552fpurstor(union savefpu *addr)
553{
554#ifndef CPU_DISABLE_SSE
555 if (cpu_fxsr) {
556 fpu_clean_state();
557 fxrstor(addr);
558 } else {
559 frstor(addr);
560 }
561#else
562 frstor(addr);
563#endif
564}
565