if: Move IFF_OACTIVE bit into ifaltq; prepare multiple TX queues support
[dragonfly.git] / sys / dev / netif / ral / rt2661.c
CommitLineData
feb94d24
RP
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $ */
2
3/*-
5fdff524
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4 * Copyright (c) 2006
5 * Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
feb94d24 19 * $FreeBSD: head/sys/dev/ral/rt2661.c 195618 2009-07-11 15:02:45Z rpaulo $
5fdff524
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20 */
21
feb94d24 22/*-
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23 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
24 * http://www.ralinktech.com/
25 */
26
27#include <sys/param.h>
feb94d24
RP
28#include <sys/sysctl.h>
29#include <sys/sockio.h>
30#include <sys/mbuf.h>
5fdff524 31#include <sys/kernel.h>
feb94d24
RP
32#include <sys/socket.h>
33#include <sys/systm.h>
5fdff524 34#include <sys/malloc.h>
feb94d24
RP
35#include <sys/lock.h>
36#include <sys/mutex.h>
9dd87f8a 37#include <sys/module.h>
feb94d24
RP
38#include <sys/bus.h>
39#include <sys/endian.h>
d83c779a 40#include <sys/firmware.h>
1f7ab7c9 41#include <sys/rman.h>
5fdff524
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42
43#include <net/bpf.h>
44#include <net/if.h>
45#include <net/if_arp.h>
46#include <net/ethernet.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
feb94d24 49#include <net/if_types.h>
5fdff524
SZ
50#include <net/ifq_var.h>
51
52#include <netproto/802_11/ieee80211_var.h>
53#include <netproto/802_11/ieee80211_radiotap.h>
feb94d24
RP
54#include <netproto/802_11/ieee80211_regdomain.h>
55#include <netproto/802_11/ieee80211_ratectl.h>
56
57#include <netinet/in.h>
58#include <netinet/in_systm.h>
59#include <netinet/in_var.h>
60#include <netinet/ip.h>
61#include <netinet/if_ether.h>
5fdff524 62
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SZ
63#include <dev/netif/ral/rt2661reg.h>
64#include <dev/netif/ral/rt2661var.h>
5fdff524 65
feb94d24 66#define RAL_DEBUG
5fdff524 67#ifdef RAL_DEBUG
feb94d24
RP
68#define DPRINTF(sc, fmt, ...) do { \
69 if (sc->sc_debug > 0) \
70 kprintf(fmt, __VA_ARGS__); \
71} while (0)
72#define DPRINTFN(sc, n, fmt, ...) do { \
73 if (sc->sc_debug >= (n)) \
74 kprintf(fmt, __VA_ARGS__); \
75} while (0)
5fdff524 76#else
feb94d24
RP
77#define DPRINTF(sc, fmt, ...)
78#define DPRINTFN(sc, n, fmt, ...)
5fdff524
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79#endif
80
feb94d24
RP
81static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *,
82 const char name[IFNAMSIZ], int unit, int opmode,
83 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
84 const uint8_t mac[IEEE80211_ADDR_LEN]);
85static void rt2661_vap_delete(struct ieee80211vap *);
5fdff524
SZ
86static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
87 int);
5fdff524
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88static int rt2661_alloc_tx_ring(struct rt2661_softc *,
89 struct rt2661_tx_ring *, int);
90static void rt2661_reset_tx_ring(struct rt2661_softc *,
91 struct rt2661_tx_ring *);
92static void rt2661_free_tx_ring(struct rt2661_softc *,
93 struct rt2661_tx_ring *);
94static int rt2661_alloc_rx_ring(struct rt2661_softc *,
95 struct rt2661_rx_ring *, int);
96static void rt2661_reset_rx_ring(struct rt2661_softc *,
97 struct rt2661_rx_ring *);
98static void rt2661_free_rx_ring(struct rt2661_softc *,
99 struct rt2661_rx_ring *);
5c379f0f 100static void rt2661_newassoc(struct ieee80211_node *, int);
feb94d24 101static int rt2661_newstate(struct ieee80211vap *,
5fdff524
SZ
102 enum ieee80211_state, int);
103static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
104static void rt2661_rx_intr(struct rt2661_softc *);
105static void rt2661_tx_intr(struct rt2661_softc *);
106static void rt2661_tx_dma_intr(struct rt2661_softc *,
107 struct rt2661_tx_ring *);
108static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
109static void rt2661_mcu_wakeup(struct rt2661_softc *);
110static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
feb94d24
RP
111static void rt2661_scan_start(struct ieee80211com *);
112static void rt2661_scan_end(struct ieee80211com *);
113static void rt2661_set_channel(struct ieee80211com *);
5fdff524
SZ
114static void rt2661_setup_tx_desc(struct rt2661_softc *,
115 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
feb94d24 116 int, const bus_dma_segment_t *, int, int);
5fdff524
SZ
117static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
118 struct ieee80211_node *, int);
119static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
120 struct ieee80211_node *);
feb94d24 121static void rt2661_start_locked(struct ifnet *);
5fdff524 122static void rt2661_start(struct ifnet *);
feb94d24
RP
123static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *,
124 const struct ieee80211_bpf_params *);
d8235d53 125static void rt2661_watchdog_callout(void *);
5fdff524 126static int rt2661_ioctl(struct ifnet *, u_long, caddr_t,
feb94d24 127 struct ucred *);
5fdff524
SZ
128static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
129 uint8_t);
130static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
131static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
132 uint32_t);
133static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
134 uint16_t);
135static void rt2661_select_antenna(struct rt2661_softc *);
136static void rt2661_enable_mrr(struct rt2661_softc *);
137static void rt2661_set_txpreamble(struct rt2661_softc *);
feb94d24 138static void rt2661_set_basicrates(struct rt2661_softc *,
5fdff524
SZ
139 const struct ieee80211_rateset *);
140static void rt2661_select_band(struct rt2661_softc *,
141 struct ieee80211_channel *);
142static void rt2661_set_chan(struct rt2661_softc *,
143 struct ieee80211_channel *);
144static void rt2661_set_bssid(struct rt2661_softc *,
145 const uint8_t *);
146static void rt2661_set_macaddr(struct rt2661_softc *,
147 const uint8_t *);
feb94d24 148static void rt2661_update_promisc(struct ifnet *);
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SZ
149static int rt2661_wme_update(struct ieee80211com *) __unused;
150static void rt2661_update_slot(struct ifnet *);
151static const char *rt2661_get_rf(int);
feb94d24
RP
152static void rt2661_read_eeprom(struct rt2661_softc *,
153 uint8_t macaddr[IEEE80211_ADDR_LEN]);
5fdff524 154static int rt2661_bbp_init(struct rt2661_softc *);
feb94d24 155static void rt2661_init_locked(struct rt2661_softc *);
5fdff524 156static void rt2661_init(void *);
feb94d24 157static void rt2661_stop_locked(struct rt2661_softc *);
5fdff524 158static void rt2661_stop(void *);
feb94d24
RP
159static int rt2661_load_microcode(struct rt2661_softc *);
160#ifdef notyet
161static void rt2661_rx_tune(struct rt2661_softc *);
162static void rt2661_radar_start(struct rt2661_softc *);
163static int rt2661_radar_stop(struct rt2661_softc *);
164#endif
165static int rt2661_prepare_beacon(struct rt2661_softc *,
166 struct ieee80211vap *);
5fdff524 167static void rt2661_enable_tsf_sync(struct rt2661_softc *);
feb94d24
RP
168static void rt2661_enable_tsf(struct rt2661_softc *);
169static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
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170
171static const struct {
172 uint32_t reg;
173 uint32_t val;
174} rt2661_def_mac[] = {
175 RT2661_DEF_MAC
176};
177
178static const struct {
179 uint8_t reg;
180 uint8_t val;
181} rt2661_def_bbp[] = {
182 RT2661_DEF_BBP
183};
184
feb94d24
RP
185static const struct rfprog {
186 uint8_t chan;
187 uint32_t r1, r2, r3, r4;
188} rt2661_rf5225_1[] = {
189 RT2661_RF5225_1
190}, rt2661_rf5225_2[] = {
191 RT2661_RF5225_2
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SZ
192};
193
194int
195rt2661_attach(device_t dev, int id)
196{
197 struct rt2661_softc *sc = device_get_softc(dev);
feb94d24
RP
198 struct ieee80211com *ic;
199 struct ifnet *ifp;
200 uint32_t val;
201 int error, ac, ntries;
202 uint8_t bands;
203 uint8_t macaddr[IEEE80211_ADDR_LEN];
204 struct sysctl_ctx_list *ctx;
205 struct sysctl_oid *tree;
206
207 sc->sc_id = id;
208 sc->sc_dev = dev;
5fdff524 209
feb94d24
RP
210 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
211 if (ifp == NULL) {
212 device_printf(sc->sc_dev, "can not if_alloc()\n");
213 return ENOMEM;
5fdff524 214 }
feb94d24
RP
215 ic = ifp->if_l2com;
216
feb94d24 217 callout_init(&sc->watchdog_ch);
5fdff524
SZ
218
219 /* wait for NIC to initialize */
220 for (ntries = 0; ntries < 1000; ntries++) {
221 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
222 break;
223 DELAY(1000);
224 }
225 if (ntries == 1000) {
226 device_printf(sc->sc_dev,
227 "timeout waiting for NIC to initialize\n");
228 error = EIO;
feb94d24 229 goto fail1;
5fdff524
SZ
230 }
231
232 /* retrieve RF rev. no and various other things from EEPROM */
feb94d24 233 rt2661_read_eeprom(sc, macaddr);
5fdff524 234
feb94d24 235 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
5fdff524
SZ
236 rt2661_get_rf(sc->rf_rev));
237
5fdff524
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238 /*
239 * Allocate Tx and Rx rings.
240 */
241 for (ac = 0; ac < 4; ac++) {
242 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
243 RT2661_TX_RING_COUNT);
244 if (error != 0) {
245 device_printf(sc->sc_dev,
246 "could not allocate Tx ring %d\n", ac);
feb94d24 247 goto fail2;
5fdff524
SZ
248 }
249 }
250
251 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
252 if (error != 0) {
253 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
feb94d24 254 goto fail2;
5fdff524
SZ
255 }
256
257 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
258 if (error != 0) {
259 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
feb94d24 260 goto fail3;
5fdff524
SZ
261 }
262
263 ifp->if_softc = sc;
264 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
266 ifp->if_init = rt2661_init;
267 ifp->if_ioctl = rt2661_ioctl;
268 ifp->if_start = rt2661_start;
5fdff524
SZ
269 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
270 ifq_set_ready(&ifp->if_snd);
271
feb94d24
RP
272 ic->ic_ifp = ifp;
273 ic->ic_opmode = IEEE80211_M_STA;
5fdff524 274 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
e3ab8063 275
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SZ
276 /* set device capabilities */
277 ic->ic_caps =
feb94d24
RP
278 IEEE80211_C_STA /* station mode */
279 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
280 | IEEE80211_C_HOSTAP /* hostap mode */
281 | IEEE80211_C_MONITOR /* monitor mode */
282 | IEEE80211_C_AHDEMO /* adhoc demo mode */
283 | IEEE80211_C_WDS /* 4-address traffic works */
284 | IEEE80211_C_MBSS /* mesh point link mode */
285 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
286 | IEEE80211_C_SHSLOT /* short slot time supported */
287 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
288 | IEEE80211_C_BGSCAN /* capable of bg scanning */
5fdff524 289#ifdef notyet
feb94d24
RP
290 | IEEE80211_C_TXFRAG /* handle tx frags */
291 | IEEE80211_C_WME /* 802.11e */
5fdff524 292#endif
feb94d24
RP
293 ;
294
295 bands = 0;
296 setbit(&bands, IEEE80211_MODE_11B);
297 setbit(&bands, IEEE80211_MODE_11G);
298 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325)
299 setbit(&bands, IEEE80211_MODE_11A);
300 ieee80211_init_channels(ic, NULL, &bands);
301
302 ieee80211_ifattach(ic, macaddr);
5c379f0f 303 ic->ic_newassoc = rt2661_newassoc;
feb94d24
RP
304#if 0
305 ic->ic_wme.wme_update = rt2661_wme_update;
306#endif
307 ic->ic_scan_start = rt2661_scan_start;
308 ic->ic_scan_end = rt2661_scan_end;
309 ic->ic_set_channel = rt2661_set_channel;
5fdff524 310 ic->ic_updateslot = rt2661_update_slot;
feb94d24
RP
311 ic->ic_update_promisc = rt2661_update_promisc;
312 ic->ic_raw_xmit = rt2661_raw_xmit;
313
314 ic->ic_vap_create = rt2661_vap_create;
315 ic->ic_vap_delete = rt2661_vap_delete;
316
317 ieee80211_radiotap_attach(ic,
318 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
319 RT2661_TX_RADIOTAP_PRESENT,
320 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
321 RT2661_RX_RADIOTAP_PRESENT);
322
323 ctx = &sc->sc_sysctl_ctx;
324 sysctl_ctx_init(ctx);
325 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw),
326 OID_AUTO,
327 device_get_nameunit(sc->sc_dev),
328 CTLFLAG_RD, 0, "");
329 if (tree == NULL) {
330 device_printf(sc->sc_dev, "can't add sysctl node\n");
331 return 0;
332 }
cb3c6fae 333#ifdef RAL_DEBUG
feb94d24
RP
334 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
335 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
cb3c6fae 336#endif
5fdff524
SZ
337 if (bootverbose)
338 ieee80211_announce(ic);
feb94d24 339
5fdff524 340 return 0;
feb94d24
RP
341
342fail3: rt2661_free_tx_ring(sc, &sc->mgtq);
343fail2: while (--ac >= 0)
344 rt2661_free_tx_ring(sc, &sc->txq[ac]);
d8235d53 345fail1:
feb94d24 346 if_free(ifp);
5fdff524
SZ
347 return error;
348}
349
350int
351rt2661_detach(void *xsc)
352{
353 struct rt2661_softc *sc = xsc;
feb94d24
RP
354 struct ifnet *ifp = sc->sc_ifp;
355 struct ieee80211com *ic = ifp->if_l2com;
356
feb94d24 357 rt2661_stop_locked(sc);
5fdff524 358
feb94d24 359 ieee80211_ifdetach(ic);
5fdff524
SZ
360
361 rt2661_free_tx_ring(sc, &sc->txq[0]);
362 rt2661_free_tx_ring(sc, &sc->txq[1]);
363 rt2661_free_tx_ring(sc, &sc->txq[2]);
364 rt2661_free_tx_ring(sc, &sc->txq[3]);
365 rt2661_free_tx_ring(sc, &sc->mgtq);
366 rt2661_free_rx_ring(sc, &sc->rxq);
367
feb94d24 368 if_free(ifp);
5fdff524 369
5fdff524
SZ
370 return 0;
371}
372
feb94d24
RP
373static struct ieee80211vap *
374rt2661_vap_create(struct ieee80211com *ic,
375 const char name[IFNAMSIZ], int unit, int opmode, int flags,
376 const uint8_t bssid[IEEE80211_ADDR_LEN],
377 const uint8_t mac[IEEE80211_ADDR_LEN])
378{
379 struct ifnet *ifp = ic->ic_ifp;
380 struct rt2661_vap *rvp;
381 struct ieee80211vap *vap;
382
383 switch (opmode) {
384 case IEEE80211_M_STA:
385 case IEEE80211_M_IBSS:
386 case IEEE80211_M_AHDEMO:
387 case IEEE80211_M_MONITOR:
388 case IEEE80211_M_HOSTAP:
389 case IEEE80211_M_MBSS:
390 /* XXXRP: TBD */
391 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
392 if_printf(ifp, "only 1 vap supported\n");
393 return NULL;
394 }
395 if (opmode == IEEE80211_M_STA)
396 flags |= IEEE80211_CLONE_NOBEACONS;
397 break;
398 case IEEE80211_M_WDS:
399 if (TAILQ_EMPTY(&ic->ic_vaps) ||
400 ic->ic_opmode != IEEE80211_M_HOSTAP) {
401 if_printf(ifp, "wds only supported in ap mode\n");
402 return NULL;
403 }
404 /*
405 * Silently remove any request for a unique
406 * bssid; WDS vap's always share the local
407 * mac address.
408 */
409 flags &= ~IEEE80211_CLONE_BSSID;
410 break;
411 default:
412 if_printf(ifp, "unknown opmode %d\n", opmode);
413 return NULL;
414 }
415 rvp = (struct rt2661_vap *) kmalloc(sizeof(struct rt2661_vap),
57d5bd0d 416 M_80211_VAP, M_INTWAIT | M_ZERO);
feb94d24
RP
417 if (rvp == NULL)
418 return NULL;
419 vap = &rvp->ral_vap;
420 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
421
422 /* override state transition machine */
423 rvp->ral_newstate = vap->iv_newstate;
424 vap->iv_newstate = rt2661_newstate;
425#if 0
426 vap->iv_update_beacon = rt2661_beacon_update;
427#endif
428
429 ieee80211_ratectl_init(vap);
430 /* complete setup */
431 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status);
432 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
433 ic->ic_opmode = opmode;
434 return vap;
435}
436
437static void
438rt2661_vap_delete(struct ieee80211vap *vap)
439{
440 struct rt2661_vap *rvp = RT2661_VAP(vap);
441
442 ieee80211_ratectl_deinit(vap);
443 ieee80211_vap_detach(vap);
444 kfree(rvp, M_80211_VAP);
445}
446
5fdff524
SZ
447void
448rt2661_shutdown(void *xsc)
449{
450 struct rt2661_softc *sc = xsc;
5fdff524 451
5fdff524 452 rt2661_stop(sc);
5fdff524
SZ
453}
454
455void
456rt2661_suspend(void *xsc)
457{
458 struct rt2661_softc *sc = xsc;
5fdff524 459
5fdff524 460 rt2661_stop(sc);
5fdff524
SZ
461}
462
463void
464rt2661_resume(void *xsc)
465{
466 struct rt2661_softc *sc = xsc;
feb94d24 467 struct ifnet *ifp = sc->sc_ifp;
5fdff524 468
feb94d24
RP
469 if (ifp->if_flags & IFF_UP)
470 rt2661_init(sc);
5fdff524
SZ
471}
472
473static void
474rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
475{
476 if (error != 0)
477 return;
478
479 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
480
481 *(bus_addr_t *)arg = segs[0].ds_addr;
482}
483
484static int
485rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
486 int count)
487{
488 int i, error;
489
490 ring->count = count;
491 ring->queued = 0;
feb94d24 492 ring->cur = ring->next = ring->stat = 0;
5fdff524 493
feb94d24
RP
494 error = bus_dma_tag_create(ring->desc_dmat, 4, 0,
495 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
496 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE,
497 0, &ring->desc_dmat);
5fdff524
SZ
498 if (error != 0) {
499 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
500 goto fail;
501 }
502
503 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
feb94d24 504 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
5fdff524
SZ
505 if (error != 0) {
506 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
507 goto fail;
508 }
509
510 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
511 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
512 0);
513 if (error != 0) {
514 device_printf(sc->sc_dev, "could not load desc DMA map\n");
5fdff524
SZ
515 goto fail;
516 }
517
feb94d24 518 ring->data = kmalloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF,
57d5bd0d 519 M_INTWAIT | M_ZERO);
feb94d24
RP
520 if (ring->data == NULL) {
521 device_printf(sc->sc_dev, "could not allocate soft data\n");
522 error = ENOMEM;
523 goto fail;
524 }
5fdff524 525
feb94d24
RP
526 error = bus_dma_tag_create(ring->data_dmat, 1, 0,
527 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
0ed377c9 528 RT2661_MAX_SCATTER, MCLBYTES, 0, &ring->data_dmat);
5fdff524
SZ
529 if (error != 0) {
530 device_printf(sc->sc_dev, "could not create data DMA tag\n");
531 goto fail;
532 }
533
534 for (i = 0; i < count; i++) {
535 error = bus_dmamap_create(ring->data_dmat, 0,
536 &ring->data[i].map);
537 if (error != 0) {
538 device_printf(sc->sc_dev, "could not create DMA map\n");
539 goto fail;
540 }
541 }
feb94d24 542
5fdff524
SZ
543 return 0;
544
545fail: rt2661_free_tx_ring(sc, ring);
546 return error;
547}
548
549static void
550rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
551{
552 struct rt2661_tx_desc *desc;
feb94d24 553 struct rt2661_tx_data *data;
5fdff524
SZ
554 int i;
555
556 for (i = 0; i < ring->count; i++) {
557 desc = &ring->desc[i];
558 data = &ring->data[i];
559
560 if (data->m != NULL) {
561 bus_dmamap_sync(ring->data_dmat, data->map,
562 BUS_DMASYNC_POSTWRITE);
563 bus_dmamap_unload(ring->data_dmat, data->map);
564 m_freem(data->m);
565 data->m = NULL;
566 }
567
feb94d24
RP
568 if (data->ni != NULL) {
569 ieee80211_free_node(data->ni);
570 data->ni = NULL;
571 }
572
5fdff524
SZ
573 desc->flags = 0;
574 }
575
576 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
577
578 ring->queued = 0;
feb94d24 579 ring->cur = ring->next = ring->stat = 0;
5fdff524
SZ
580}
581
582static void
583rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
584{
feb94d24 585 struct rt2661_tx_data *data;
5fdff524
SZ
586 int i;
587
588 if (ring->desc != NULL) {
589 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
590 BUS_DMASYNC_POSTWRITE);
591 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
592 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
5fdff524
SZ
593 }
594
feb94d24 595 if (ring->desc_dmat != NULL)
5fdff524 596 bus_dma_tag_destroy(ring->desc_dmat);
5fdff524
SZ
597
598 if (ring->data != NULL) {
599 for (i = 0; i < ring->count; i++) {
600 data = &ring->data[i];
601
602 if (data->m != NULL) {
603 bus_dmamap_sync(ring->data_dmat, data->map,
604 BUS_DMASYNC_POSTWRITE);
605 bus_dmamap_unload(ring->data_dmat, data->map);
606 m_freem(data->m);
5fdff524
SZ
607 }
608
feb94d24
RP
609 if (data->ni != NULL)
610 ieee80211_free_node(data->ni);
611
612 if (data->map != NULL)
5fdff524 613 bus_dmamap_destroy(ring->data_dmat, data->map);
5fdff524
SZ
614 }
615
efda3bd0 616 kfree(ring->data, M_DEVBUF);
5fdff524
SZ
617 }
618
feb94d24 619 if (ring->data_dmat != NULL)
5fdff524 620 bus_dma_tag_destroy(ring->data_dmat);
5fdff524
SZ
621}
622
623static int
624rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
625 int count)
626{
627 struct rt2661_rx_desc *desc;
feb94d24 628 struct rt2661_rx_data *data;
5fdff524
SZ
629 bus_addr_t physaddr;
630 int i, error;
631
632 ring->count = count;
633 ring->cur = ring->next = 0;
634
feb94d24
RP
635 error = bus_dma_tag_create(ring->desc_dmat, 4, 0,
636 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
637 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE,
638 0, &ring->desc_dmat);
5fdff524
SZ
639 if (error != 0) {
640 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
641 goto fail;
642 }
643
644 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
feb94d24 645 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
5fdff524
SZ
646 if (error != 0) {
647 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
648 goto fail;
649 }
650
651 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
652 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
653 0);
654 if (error != 0) {
655 device_printf(sc->sc_dev, "could not load desc DMA map\n");
5fdff524
SZ
656 goto fail;
657 }
658
feb94d24 659 ring->data = kmalloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF,
57d5bd0d 660 M_INTWAIT | M_ZERO);
feb94d24
RP
661 if (ring->data == NULL) {
662 device_printf(sc->sc_dev, "could not allocate soft data\n");
663 error = ENOMEM;
664 goto fail;
665 }
5fdff524
SZ
666
667 /*
668 * Pre-allocate Rx buffers and populate Rx ring.
669 */
feb94d24
RP
670 error = bus_dma_tag_create(ring->data_dmat, 1, 0,
671 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
672 1, MCLBYTES, 0, &ring->data_dmat);
5fdff524
SZ
673 if (error != 0) {
674 device_printf(sc->sc_dev, "could not create data DMA tag\n");
675 goto fail;
676 }
677
678 for (i = 0; i < count; i++) {
679 desc = &sc->rxq.desc[i];
680 data = &sc->rxq.data[i];
681
682 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
683 if (error != 0) {
684 device_printf(sc->sc_dev, "could not create DMA map\n");
685 goto fail;
686 }
687
688 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
689 if (data->m == NULL) {
690 device_printf(sc->sc_dev,
691 "could not allocate rx mbuf\n");
692 error = ENOMEM;
693 goto fail;
694 }
695
696 error = bus_dmamap_load(ring->data_dmat, data->map,
697 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
698 &physaddr, 0);
699 if (error != 0) {
700 device_printf(sc->sc_dev,
701 "could not load rx buf DMA map");
5fdff524
SZ
702 goto fail;
703 }
704
705 desc->flags = htole32(RT2661_RX_BUSY);
706 desc->physaddr = htole32(physaddr);
707 }
708
709 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
710
711 return 0;
712
713fail: rt2661_free_rx_ring(sc, ring);
714 return error;
715}
716
717static void
718rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
719{
720 int i;
721
722 for (i = 0; i < ring->count; i++)
723 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
724
725 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
726
727 ring->cur = ring->next = 0;
728}
729
730static void
731rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
732{
feb94d24 733 struct rt2661_rx_data *data;
5fdff524
SZ
734 int i;
735
736 if (ring->desc != NULL) {
737 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
738 BUS_DMASYNC_POSTWRITE);
739 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
740 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
5fdff524
SZ
741 }
742
feb94d24 743 if (ring->desc_dmat != NULL)
5fdff524 744 bus_dma_tag_destroy(ring->desc_dmat);
5fdff524
SZ
745
746 if (ring->data != NULL) {
747 for (i = 0; i < ring->count; i++) {
748 data = &ring->data[i];
749
750 if (data->m != NULL) {
751 bus_dmamap_sync(ring->data_dmat, data->map,
752 BUS_DMASYNC_POSTREAD);
753 bus_dmamap_unload(ring->data_dmat, data->map);
754 m_freem(data->m);
5fdff524
SZ
755 }
756
feb94d24 757 if (data->map != NULL)
5fdff524 758 bus_dmamap_destroy(ring->data_dmat, data->map);
5fdff524
SZ
759 }
760
efda3bd0 761 kfree(ring->data, M_DEVBUF);
5fdff524
SZ
762 }
763
feb94d24 764 if (ring->data_dmat != NULL)
5fdff524 765 bus_dma_tag_destroy(ring->data_dmat);
5fdff524
SZ
766}
767
5c379f0f
JT
768static void
769rt2661_newassoc(struct ieee80211_node *ni, int isnew)
770{
771 ieee80211_ratectl_node_deinit(ni);
772 ieee80211_ratectl_node_init(ni);
773}
774
5fdff524 775static int
feb94d24 776rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5fdff524 777{
feb94d24
RP
778 struct rt2661_vap *rvp = RT2661_VAP(vap);
779 struct ieee80211com *ic = vap->iv_ic;
5fdff524 780 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
feb94d24 781 int error;
5fdff524 782
feb94d24
RP
783 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
784 uint32_t tmp;
5fdff524 785
feb94d24
RP
786 /* abort TSF synchronization */
787 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
788 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
789 }
110dc487 790
feb94d24 791 error = rvp->ral_newstate(vap, nstate, arg);
5fdff524 792
feb94d24
RP
793 if (error == 0 && nstate == IEEE80211_S_RUN) {
794 struct ieee80211_node *ni = vap->iv_bss;
5fdff524 795
feb94d24 796 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
5fdff524
SZ
797 rt2661_enable_mrr(sc);
798 rt2661_set_txpreamble(sc);
feb94d24 799 rt2661_set_basicrates(sc, &ni->ni_rates);
5fdff524
SZ
800 rt2661_set_bssid(sc, ni->ni_bssid);
801 }
802
feb94d24
RP
803 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
804 vap->iv_opmode == IEEE80211_M_IBSS ||
805 vap->iv_opmode == IEEE80211_M_MBSS) {
806 error = rt2661_prepare_beacon(sc, vap);
807 if (error != 0)
808 return error;
5fdff524 809 }
feb94d24 810 if (vap->iv_opmode != IEEE80211_M_MONITOR)
5fdff524 811 rt2661_enable_tsf_sync(sc);
feb94d24
RP
812 else
813 rt2661_enable_tsf(sc);
814 }
815 return error;
5fdff524
SZ
816}
817
818/*
819 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
820 * 93C66).
821 */
822static uint16_t
823rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
824{
825 uint32_t tmp;
826 uint16_t val;
827 int n;
828
829 /* clock C once before the first command */
830 RT2661_EEPROM_CTL(sc, 0);
831
832 RT2661_EEPROM_CTL(sc, RT2661_S);
833 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
834 RT2661_EEPROM_CTL(sc, RT2661_S);
835
836 /* write start bit (1) */
837 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
838 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
839
840 /* write READ opcode (10) */
841 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
842 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
843 RT2661_EEPROM_CTL(sc, RT2661_S);
844 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
845
846 /* write address (A5-A0 or A7-A0) */
847 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
848 for (; n >= 0; n--) {
849 RT2661_EEPROM_CTL(sc, RT2661_S |
850 (((addr >> n) & 1) << RT2661_SHIFT_D));
851 RT2661_EEPROM_CTL(sc, RT2661_S |
852 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
853 }
854
855 RT2661_EEPROM_CTL(sc, RT2661_S);
856
857 /* read data Q15-Q0 */
858 val = 0;
859 for (n = 15; n >= 0; n--) {
860 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
861 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
862 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
863 RT2661_EEPROM_CTL(sc, RT2661_S);
864 }
865
866 RT2661_EEPROM_CTL(sc, 0);
867
868 /* clear Chip Select and clock C */
869 RT2661_EEPROM_CTL(sc, RT2661_S);
870 RT2661_EEPROM_CTL(sc, 0);
871 RT2661_EEPROM_CTL(sc, RT2661_C);
872
873 return val;
874}
875
876static void
877rt2661_tx_intr(struct rt2661_softc *sc)
878{
feb94d24
RP
879 struct ifnet *ifp = sc->sc_ifp;
880 struct rt2661_tx_ring *txq;
881 struct rt2661_tx_data *data;
882 uint32_t val;
883 int qid, retrycnt;
884 struct ieee80211vap *vap;
5fdff524
SZ
885
886 for (;;) {
feb94d24
RP
887 struct ieee80211_node *ni;
888 struct mbuf *m;
e3ab8063 889
5fdff524
SZ
890 val = RAL_READ(sc, RT2661_STA_CSR4);
891 if (!(val & RT2661_TX_STAT_VALID))
892 break;
893
feb94d24
RP
894 /* retrieve the queue in which this frame was sent */
895 qid = RT2661_TX_QID(val);
896 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
5fdff524
SZ
897
898 /* retrieve rate control algorithm context */
feb94d24
RP
899 data = &txq->data[txq->stat];
900 m = data->m;
901 data->m = NULL;
051377a2 902
feb94d24
RP
903 ni = data->ni;
904 data->ni = NULL;
feb94d24
RP
905
906 /* if no frame has been sent, ignore */
907 if (ni == NULL)
9dd87f8a 908 continue;
9dd87f8a 909
051377a2
JT
910 vap = ni->ni_vap;
911
feb94d24 912 switch (RT2661_TX_RESULT(val)) {
5fdff524
SZ
913 case RT2661_TX_SUCCESS:
914 retrycnt = RT2661_TX_RETRYCNT(val);
feb94d24
RP
915
916 DPRINTFN(sc, 10, "data frame sent successfully after "
917 "%d retries\n", retrycnt);
918 if (data->rix != IEEE80211_FIXED_RATE_NONE)
919 ieee80211_ratectl_tx_complete(vap, ni,
920 IEEE80211_RATECTL_TX_SUCCESS,
921 &retrycnt, NULL);
922 ifp->if_opackets++;
5fdff524
SZ
923 break;
924
925 case RT2661_TX_RETRY_FAIL:
feb94d24
RP
926 retrycnt = RT2661_TX_RETRYCNT(val);
927
928 DPRINTFN(sc, 9, "%s\n",
929 "sending data frame failed (too much retries)");
930 if (data->rix != IEEE80211_FIXED_RATE_NONE)
931 ieee80211_ratectl_tx_complete(vap, ni,
932 IEEE80211_RATECTL_TX_FAILURE,
933 &retrycnt, NULL);
934 ifp->if_oerrors++;
5fdff524
SZ
935 break;
936
937 default:
938 /* other failure */
939 device_printf(sc->sc_dev,
940 "sending data frame failed 0x%08x\n", val);
feb94d24 941 ifp->if_oerrors++;
5fdff524
SZ
942 }
943
feb94d24
RP
944 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
945
946 txq->queued--;
947 if (++txq->stat >= txq->count) /* faster than % count */
948 txq->stat = 0;
e3ab8063 949
feb94d24
RP
950 if (m->m_flags & M_TXCB)
951 ieee80211_process_callback(ni, m,
952 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS);
953 m_freem(m);
954 ieee80211_free_node(ni);
5fdff524 955 }
feb94d24
RP
956
957 sc->sc_tx_timer = 0;
9ed293e0 958 ifq_clr_oactive(&ifp->if_snd);
feb94d24
RP
959
960 rt2661_start_locked(ifp);
5fdff524
SZ
961}
962
963static void
964rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
965{
966 struct rt2661_tx_desc *desc;
feb94d24 967 struct rt2661_tx_data *data;
5fdff524
SZ
968
969 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
970
971 for (;;) {
972 desc = &txq->desc[txq->next];
973 data = &txq->data[txq->next];
974
975 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
976 !(le32toh(desc->flags) & RT2661_TX_VALID))
977 break;
978
979 bus_dmamap_sync(txq->data_dmat, data->map,
980 BUS_DMASYNC_POSTWRITE);
981 bus_dmamap_unload(txq->data_dmat, data->map);
5fdff524
SZ
982
983 /* descriptor is no longer valid */
984 desc->flags &= ~htole32(RT2661_TX_VALID);
985
feb94d24 986 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
5fdff524
SZ
987
988 if (++txq->next >= txq->count) /* faster than % count */
989 txq->next = 0;
990 }
991
992 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
993}
994
995static void
996rt2661_rx_intr(struct rt2661_softc *sc)
997{
feb94d24
RP
998 struct ifnet *ifp = sc->sc_ifp;
999 struct ieee80211com *ic = ifp->if_l2com;
5fdff524 1000 struct rt2661_rx_desc *desc;
feb94d24 1001 struct rt2661_rx_data *data;
5fdff524 1002 bus_addr_t physaddr;
feb94d24 1003 struct ieee80211_frame *wh;
5fdff524 1004 struct ieee80211_node *ni;
5fdff524
SZ
1005 struct mbuf *mnew, *m;
1006 int error;
1007
1008 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1009 BUS_DMASYNC_POSTREAD);
1010
1011 for (;;) {
feb94d24 1012 int8_t rssi, nf;
a6b13394 1013
5fdff524
SZ
1014 desc = &sc->rxq.desc[sc->rxq.cur];
1015 data = &sc->rxq.data[sc->rxq.cur];
1016
feb94d24 1017 if (le32toh(desc->flags) & RT2661_RX_BUSY)
5fdff524
SZ
1018 break;
1019
feb94d24
RP
1020 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
1021 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
5fdff524
SZ
1022 /*
1023 * This should not happen since we did not request
1024 * to receive those frames when we filled TXRX_CSR0.
1025 */
feb94d24
RP
1026 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n",
1027 le32toh(desc->flags));
5fdff524
SZ
1028 ifp->if_ierrors++;
1029 goto skip;
1030 }
1031
feb94d24 1032 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
5fdff524
SZ
1033 ifp->if_ierrors++;
1034 goto skip;
1035 }
1036
1037 /*
1038 * Try to allocate a new mbuf for this ring element and load it
1039 * before processing the current mbuf. If the ring element
1040 * cannot be loaded, drop the received packet and reuse the old
1041 * mbuf. In the unlikely case that the old mbuf can't be
1042 * reloaded either, explicitly panic.
1043 */
1044 mnew = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1045 if (mnew == NULL) {
1046 ifp->if_ierrors++;
1047 goto skip;
1048 }
1049
1050 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1051 BUS_DMASYNC_POSTREAD);
1052 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1053
1054 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1055 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1056 &physaddr, 0);
1057 if (error != 0) {
1058 m_freem(mnew);
1059
1060 /* try to reload the old mbuf */
1061 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1062 mtod(data->m, void *), MCLBYTES,
1063 rt2661_dma_map_addr, &physaddr, 0);
1064 if (error != 0) {
1065 /* very unlikely that it will fail... */
1066 panic("%s: could not load old rx mbuf",
1067 device_get_name(sc->sc_dev));
1068 }
1069 ifp->if_ierrors++;
1070 goto skip;
1071 }
1072
1073 /*
1074 * New mbuf successfully loaded, update Rx ring and continue
1075 * processing.
1076 */
1077 m = data->m;
1078 data->m = mnew;
1079 desc->physaddr = htole32(physaddr);
1080
1081 /* finalize mbuf */
1082 m->m_pkthdr.rcvif = ifp;
feb94d24
RP
1083 m->m_pkthdr.len = m->m_len =
1084 (le32toh(desc->flags) >> 16) & 0xfff;
d2eb9874 1085
feb94d24 1086 rssi = rt2661_get_rssi(sc, desc->rssi);
d2eb9874
SZ
1087 /* Error happened during RSSI conversion. */
1088 if (rssi < 0)
feb94d24
RP
1089 rssi = -30; /* XXX ignored by net80211 */
1090 nf = RT2661_NOISE_FLOOR;
d2eb9874 1091
feb94d24 1092 if (ieee80211_radiotap_active(ic)) {
5fdff524
SZ
1093 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1094 uint32_t tsf_lo, tsf_hi;
1095
1096 /* get timestamp (low and high 32 bits) */
1097 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1098 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1099
1100 tap->wr_tsf =
1101 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1102 tap->wr_flags = 0;
feb94d24
RP
1103 tap->wr_rate = ieee80211_plcp2rate(desc->rate,
1104 (desc->flags & htole32(RT2661_RX_OFDM)) ?
1105 IEEE80211_T_OFDM : IEEE80211_T_CCK);
1106 tap->wr_antsignal = nf + rssi;
1107 tap->wr_antnoise = nf;
5fdff524 1108 }
feb94d24 1109 sc->sc_flags |= RAL_INPUT_RUNNING;
feb94d24 1110 wh = mtod(m, struct ieee80211_frame *);
5fdff524 1111
5fdff524 1112 /* send the frame to the 802.11 layer */
feb94d24
RP
1113 ni = ieee80211_find_rxnode(ic,
1114 (struct ieee80211_frame_min *)wh);
1115 if (ni != NULL) {
1116 (void) ieee80211_input(ni, m, rssi, nf);
1117 ieee80211_free_node(ni);
1118 } else
1119 (void) ieee80211_input_all(ic, m, rssi, nf);
5717dc1a 1120
feb94d24 1121 sc->sc_flags &= ~RAL_INPUT_RUNNING;
5fdff524
SZ
1122
1123skip: desc->flags |= htole32(RT2661_RX_BUSY);
1124
feb94d24 1125 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur);
5fdff524
SZ
1126
1127 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1128 }
1129
1130 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1131 BUS_DMASYNC_PREWRITE);
1132}
1133
1134/* ARGSUSED */
1135static void
1136rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1137{
1138 /* do nothing */
1139}
1140
1141static void
1142rt2661_mcu_wakeup(struct rt2661_softc *sc)
1143{
1144 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1145
1146 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1147 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1148 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1149
1150 /* send wakeup command to MCU */
1151 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1152}
1153
1154static void
1155rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1156{
1157 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1158 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1159}
1160
feb94d24 1161void
5fdff524
SZ
1162rt2661_intr(void *arg)
1163{
1164 struct rt2661_softc *sc = arg;
feb94d24 1165 struct ifnet *ifp = sc->sc_ifp;
5fdff524
SZ
1166 uint32_t r1, r2;
1167
1168 /* disable MAC and MCU interrupts */
1169 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1170 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1171
1172 /* don't re-enable interrupts if we're shutting down */
feb94d24 1173 if (!(ifp->if_flags & IFF_RUNNING)) {
5fdff524 1174 return;
feb94d24 1175 }
5fdff524
SZ
1176
1177 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1178 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1179
1180 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1181 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1182
1183 if (r1 & RT2661_MGT_DONE)
1184 rt2661_tx_dma_intr(sc, &sc->mgtq);
1185
1186 if (r1 & RT2661_RX_DONE)
1187 rt2661_rx_intr(sc);
1188
1189 if (r1 & RT2661_TX0_DMA_DONE)
1190 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1191
1192 if (r1 & RT2661_TX1_DMA_DONE)
1193 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1194
1195 if (r1 & RT2661_TX2_DMA_DONE)
1196 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1197
1198 if (r1 & RT2661_TX3_DMA_DONE)
1199 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1200
1201 if (r1 & RT2661_TX_DONE)
1202 rt2661_tx_intr(sc);
1203
1204 if (r2 & RT2661_MCU_CMD_DONE)
1205 rt2661_mcu_cmd_intr(sc);
1206
1207 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1208 rt2661_mcu_beacon_expire(sc);
1209
1210 if (r2 & RT2661_MCU_WAKEUP)
1211 rt2661_mcu_wakeup(sc);
1212
1213 /* re-enable MAC and MCU interrupts */
1214 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1215 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
5fdff524 1216
feb94d24 1217}
5fdff524 1218
5fdff524
SZ
1219static uint8_t
1220rt2661_plcp_signal(int rate)
1221{
1222 switch (rate) {
5fdff524
SZ
1223 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1224 case 12: return 0xb;
1225 case 18: return 0xf;
1226 case 24: return 0xa;
1227 case 36: return 0xe;
1228 case 48: return 0x9;
1229 case 72: return 0xd;
1230 case 96: return 0x8;
1231 case 108: return 0xc;
1232
feb94d24
RP
1233 /* CCK rates (NB: not IEEE std, device-specific) */
1234 case 2: return 0x0;
1235 case 4: return 0x1;
1236 case 11: return 0x2;
1237 case 22: return 0x3;
5fdff524 1238 }
feb94d24 1239 return 0xff; /* XXX unsupported/unknown rate */
5fdff524
SZ
1240}
1241
1242static void
1243rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1244 uint32_t flags, uint16_t xflags, int len, int rate,
feb94d24 1245 const bus_dma_segment_t *segs, int nsegs, int ac)
5fdff524 1246{
feb94d24
RP
1247 struct ifnet *ifp = sc->sc_ifp;
1248 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1249 uint16_t plcp_length;
1250 int i, remainder;
1251
1252 desc->flags = htole32(flags);
1253 desc->flags |= htole32(len << 16);
feb94d24 1254 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID);
5fdff524
SZ
1255
1256 desc->xflags = htole16(xflags);
1257 desc->xflags |= htole16(nsegs << 13);
1258
1259 desc->wme = htole16(
1260 RT2661_QID(ac) |
1261 RT2661_AIFSN(2) |
1262 RT2661_LOGCWMIN(4) |
1263 RT2661_LOGCWMAX(10));
1264
1265 /*
feb94d24
RP
1266 * Remember in which queue this frame was sent. This field is driver
1267 * private data only. It will be made available by the NIC in STA_CSR4
1268 * on Tx interrupts.
5fdff524 1269 */
feb94d24 1270 desc->qid = ac;
5fdff524
SZ
1271
1272 /* setup PLCP fields */
1273 desc->plcp_signal = rt2661_plcp_signal(rate);
1274 desc->plcp_service = 4;
1275
1276 len += IEEE80211_CRC_LEN;
feb94d24 1277 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) {
5fdff524
SZ
1278 desc->flags |= htole32(RT2661_TX_OFDM);
1279
1280 plcp_length = len & 0xfff;
1281 desc->plcp_length_hi = plcp_length >> 6;
1282 desc->plcp_length_lo = plcp_length & 0x3f;
1283 } else {
1284 plcp_length = (16 * len + rate - 1) / rate;
1285 if (rate == 22) {
1286 remainder = (16 * len) % 22;
1287 if (remainder != 0 && remainder < 7)
1288 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1289 }
1290 desc->plcp_length_hi = plcp_length >> 8;
1291 desc->plcp_length_lo = plcp_length & 0xff;
1292
1293 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1294 desc->plcp_signal |= 0x08;
1295 }
1296
1297 /* RT2x61 supports scatter with up to 5 segments */
1298 for (i = 0; i < nsegs; i++) {
1299 desc->addr[i] = htole32(segs[i].ds_addr);
1300 desc->len [i] = htole16(segs[i].ds_len);
1301 }
1302}
1303
1304static int
1305rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1306 struct ieee80211_node *ni)
1307{
feb94d24
RP
1308 struct ieee80211vap *vap = ni->ni_vap;
1309 struct ieee80211com *ic = ni->ni_ic;
5fdff524 1310 struct rt2661_tx_desc *desc;
feb94d24 1311 struct rt2661_tx_data *data;
5fdff524 1312 struct ieee80211_frame *wh;
feb94d24
RP
1313 struct ieee80211_key *k;
1314 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
5fdff524
SZ
1315 uint16_t dur;
1316 uint32_t flags = 0; /* XXX HWSEQ */
feb94d24 1317 int nsegs, rate, error;
5fdff524
SZ
1318
1319 desc = &sc->mgtq.desc[sc->mgtq.cur];
1320 data = &sc->mgtq.data[sc->mgtq.cur];
1321
feb94d24
RP
1322 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate;
1323
1324 wh = mtod(m0, struct ieee80211_frame *);
1325
1326 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1327 k = ieee80211_crypto_encap(ni, m0);
1328 if (k == NULL) {
1329 m_freem(m0);
1330 return ENOBUFS;
1331 }
1332 }
5fdff524 1333
feb94d24 1334 error = bus_dmamap_load_mbuf_segment(sc->mgtq.data_dmat, data->map, m0,
47383cff 1335 segs, 1, &nsegs, BUS_DMA_NOWAIT);
5fdff524
SZ
1336 if (error != 0) {
1337 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1338 error);
1339 m_freem(m0);
1340 return error;
1341 }
1342
feb94d24 1343 if (ieee80211_radiotap_active_vap(vap)) {
5fdff524
SZ
1344 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1345
1346 tap->wt_flags = 0;
1347 tap->wt_rate = rate;
5fdff524 1348
feb94d24 1349 ieee80211_radiotap_tx(vap, m0);
5fdff524
SZ
1350 }
1351
1352 data->m = m0;
feb94d24
RP
1353 data->ni = ni;
1354 /* management frames are not taken into account for amrr */
1355 data->rix = IEEE80211_FIXED_RATE_NONE;
5fdff524
SZ
1356
1357 wh = mtod(m0, struct ieee80211_frame *);
1358
1359 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1360 flags |= RT2661_TX_NEED_ACK;
1361
feb94d24
RP
1362 dur = ieee80211_ack_duration(ic->ic_rt,
1363 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
5fdff524
SZ
1364 *(uint16_t *)wh->i_dur = htole16(dur);
1365
1366 /* tell hardware to add timestamp in probe responses */
1367 if ((wh->i_fc[0] &
1368 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1369 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1370 flags |= RT2661_TX_TIMESTAMP;
1371 }
1372
1373 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
feb94d24 1374 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT);
5fdff524
SZ
1375
1376 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1377 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1378 BUS_DMASYNC_PREWRITE);
1379
feb94d24
RP
1380 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n",
1381 m0->m_pkthdr.len, sc->mgtq.cur, rate);
5fdff524
SZ
1382
1383 /* kick mgt */
1384 sc->mgtq.queued++;
1385 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1386 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1387
1388 return 0;
1389}
1390
feb94d24
RP
1391static int
1392rt2661_sendprot(struct rt2661_softc *sc, int ac,
1393 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
5fdff524 1394{
feb94d24
RP
1395 struct ieee80211com *ic = ni->ni_ic;
1396 struct rt2661_tx_ring *txq = &sc->txq[ac];
1397 const struct ieee80211_frame *wh;
1398 struct rt2661_tx_desc *desc;
1399 struct rt2661_tx_data *data;
1400 struct mbuf *mprot;
1401 int protrate, ackrate, pktlen, flags, isshort, error;
1402 uint16_t dur;
1403 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1404 int nsegs;
5fdff524 1405
feb94d24
RP
1406 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY,
1407 ("protection %d", prot));
1408
1409 wh = mtod(m, const struct ieee80211_frame *);
1410 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
1411
1412 protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
1413 ackrate = ieee80211_ack_rate(ic->ic_rt, rate);
1414
1415 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
1416 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort)
1417 + ieee80211_ack_duration(ic->ic_rt, rate, isshort);
1418 flags = RT2661_TX_MORE_FRAG;
1419 if (prot == IEEE80211_PROT_RTSCTS) {
1420 /* NB: CTS is the same size as an ACK */
1421 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort);
1422 flags |= RT2661_TX_NEED_ACK;
1423 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur);
1424 } else {
1425 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur);
1426 }
1427 if (mprot == NULL) {
1428 /* XXX stat + msg */
1429 return ENOBUFS;
1430 }
1431
1432 data = &txq->data[txq->cur];
1433 desc = &txq->desc[txq->cur];
1434
1435 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, mprot, segs,
47383cff 1436 1, &nsegs, BUS_DMA_NOWAIT);
feb94d24
RP
1437 if (error != 0) {
1438 device_printf(sc->sc_dev,
1439 "could not map mbuf (error %d)\n", error);
1440 m_freem(mprot);
1441 return error;
5fdff524
SZ
1442 }
1443
feb94d24
RP
1444 data->m = mprot;
1445 data->ni = ieee80211_ref_node(ni);
1446 /* ctl frames are not taken into account for amrr */
1447 data->rix = IEEE80211_FIXED_RATE_NONE;
1448
1449 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len,
1450 protrate, segs, 1, ac);
5fdff524 1451
feb94d24
RP
1452 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1453 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
5fdff524 1454
feb94d24
RP
1455 txq->queued++;
1456 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
5fdff524 1457
feb94d24 1458 return 0;
5fdff524
SZ
1459}
1460
1461static int
1462rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1463 struct ieee80211_node *ni, int ac)
1464{
feb94d24
RP
1465 struct ieee80211vap *vap = ni->ni_vap;
1466 struct ifnet *ifp = sc->sc_ifp;
1467 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1468 struct rt2661_tx_ring *txq = &sc->txq[ac];
1469 struct rt2661_tx_desc *desc;
feb94d24 1470 struct rt2661_tx_data *data;
5fdff524 1471 struct ieee80211_frame *wh;
feb94d24
RP
1472 const struct ieee80211_txparam *tp;
1473 struct ieee80211_key *k;
5fdff524
SZ
1474 const struct chanAccParams *cap;
1475 struct mbuf *mnew;
feb94d24 1476 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
5fdff524 1477 uint16_t dur;
feb94d24
RP
1478 uint32_t flags;
1479 int error, nsegs, rate, noack = 0;
5fdff524
SZ
1480
1481 wh = mtod(m0, struct ieee80211_frame *);
feb94d24
RP
1482
1483 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1484 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1485 rate = tp->mcastrate;
1486 } else if (m0->m_flags & M_EAPOL) {
1487 rate = tp->mgmtrate;
1488 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1489 rate = tp->ucastrate;
1490 } else {
051377a2 1491 ieee80211_ratectl_rate(ni, NULL, 0);
feb94d24
RP
1492 rate = ni->ni_txrate;
1493 }
1494 rate &= IEEE80211_RATE_VAL;
1495
5fdff524
SZ
1496 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
1497 cap = &ic->ic_wme.wme_chanParams;
1498 noack = cap->cap_wmeParams[ac].wmep_noackPolicy;
1499 }
1500
1501 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
feb94d24 1502 k = ieee80211_crypto_encap(ni, m0);
5fdff524
SZ
1503 if (k == NULL) {
1504 m_freem(m0);
1505 return ENOBUFS;
1506 }
1507
1508 /* packet header may have moved, reset our local pointer */
1509 wh = mtod(m0, struct ieee80211_frame *);
1510 }
1511
feb94d24
RP
1512 flags = 0;
1513 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1514 int prot = IEEE80211_PROT_NONE;
1515 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1516 prot = IEEE80211_PROT_RTSCTS;
1517 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1518 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM)
1519 prot = ic->ic_protmode;
1520 if (prot != IEEE80211_PROT_NONE) {
1521 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate);
1522 if (error) {
1523 m_freem(m0);
1524 return error;
1525 }
1526 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
5fdff524 1527 }
5fdff524
SZ
1528 }
1529
1530 data = &txq->data[txq->cur];
1531 desc = &txq->desc[txq->cur];
1532
feb94d24 1533 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0, segs,
47383cff 1534 1, &nsegs, BUS_DMA_NOWAIT);
5fdff524
SZ
1535 if (error != 0 && error != EFBIG) {
1536 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1537 error);
1538 m_freem(m0);
1539 return error;
1540 }
1541 if (error != 0) {
1542 mnew = m_defrag(m0, MB_DONTWAIT);
1543 if (mnew == NULL) {
1544 device_printf(sc->sc_dev,
1545 "could not defragment mbuf\n");
1546 m_freem(m0);
1547 return ENOBUFS;
1548 }
1549 m0 = mnew;
1550
feb94d24 1551 error = bus_dmamap_load_mbuf_segment(txq->data_dmat, data->map, m0,
47383cff 1552 segs, 1, &nsegs, BUS_DMA_NOWAIT);
5fdff524
SZ
1553 if (error != 0) {
1554 device_printf(sc->sc_dev,
1555 "could not map mbuf (error %d)\n", error);
1556 m_freem(m0);
1557 return error;
1558 }
1559
1560 /* packet header have moved, reset our local pointer */
1561 wh = mtod(m0, struct ieee80211_frame *);
1562 }
1563
feb94d24 1564 if (ieee80211_radiotap_active_vap(vap)) {
5fdff524
SZ
1565 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1566
1567 tap->wt_flags = 0;
1568 tap->wt_rate = rate;
5fdff524 1569
feb94d24 1570 ieee80211_radiotap_tx(vap, m0);
5fdff524
SZ
1571 }
1572
1573 data->m = m0;
feb94d24 1574 data->ni = ni;
9dd87f8a 1575
feb94d24
RP
1576 /* remember link conditions for rate adaptation algorithm */
1577 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) {
1578 data->rix = ni->ni_txrate;
1579 /* XXX probably need last rssi value and not avg */
1580 data->rssi = ic->ic_node_getrssi(ni);
1581 } else
1582 data->rix = IEEE80211_FIXED_RATE_NONE;
5fdff524
SZ
1583
1584 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1585 flags |= RT2661_TX_NEED_ACK;
1586
feb94d24
RP
1587 dur = ieee80211_ack_duration(ic->ic_rt,
1588 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
5fdff524
SZ
1589 *(uint16_t *)wh->i_dur = htole16(dur);
1590 }
1591
feb94d24
RP
1592 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs,
1593 nsegs, ac);
5fdff524
SZ
1594
1595 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1596 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1597
feb94d24
RP
1598 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n",
1599 m0->m_pkthdr.len, txq->cur, rate);
5fdff524
SZ
1600
1601 /* kick Tx */
1602 txq->queued++;
1603 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1604 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1605
1606 return 0;
1607}
1608
1609static void
feb94d24 1610rt2661_start_locked(struct ifnet *ifp)
5fdff524
SZ
1611{
1612 struct rt2661_softc *sc = ifp->if_softc;
feb94d24 1613 struct mbuf *m;
5fdff524
SZ
1614 struct ieee80211_node *ni;
1615 int ac;
1616
1617 /* prevent management frames from being sent if we're not ready */
feb94d24 1618 if (!(ifp->if_flags & IFF_RUNNING) || sc->sc_invalid)
5fdff524
SZ
1619 return;
1620
1621 for (;;) {
feb94d24
RP
1622 IF_DEQUEUE(&ifp->if_snd, m);
1623 if (m == NULL)
1624 break;
5fdff524 1625
feb94d24
RP
1626 ac = M_WME_GETAC(m);
1627 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1628 /* there is no place left in this ring */
1629 IF_PREPEND(&ifp->if_snd, m);
9ed293e0 1630 ifq_set_oactive(&ifp->if_snd);
feb94d24
RP
1631 break;
1632 }
1633 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1634 if (rt2661_tx_data(sc, m, ni, ac) != 0) {
1635 ieee80211_free_node(ni);
1636 ifp->if_oerrors++;
1637 break;
5fdff524
SZ
1638 }
1639
1640 sc->sc_tx_timer = 5;
5fdff524
SZ
1641 }
1642}
1643
1644static void
feb94d24 1645rt2661_start(struct ifnet *ifp)
5fdff524 1646{
feb94d24 1647 rt2661_start_locked(ifp);
5fdff524
SZ
1648}
1649
5fdff524 1650static int
feb94d24
RP
1651rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1652 const struct ieee80211_bpf_params *params)
5fdff524 1653{
feb94d24
RP
1654 struct ieee80211com *ic = ni->ni_ic;
1655 struct ifnet *ifp = ic->ic_ifp;
5fdff524 1656 struct rt2661_softc *sc = ifp->if_softc;
5fdff524 1657
feb94d24
RP
1658 /* prevent management frames from being sent if we're not ready */
1659 if (!(ifp->if_flags & IFF_RUNNING)) {
feb94d24
RP
1660 m_freem(m);
1661 ieee80211_free_node(ni);
1662 return ENETDOWN;
1663 }
1664 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
9ed293e0 1665 ifq_set_oactive(&ifp->if_snd);
feb94d24
RP
1666 m_freem(m);
1667 ieee80211_free_node(ni);
1668 return ENOBUFS; /* XXX */
1669 }
1670
1671 ifp->if_opackets++;
1672
1673 /*
1674 * Legacy path; interpret frame contents to decide
1675 * precisely how to send the frame.
1676 * XXX raw path
1677 */
1678 if (rt2661_tx_mgt(sc, m, ni) != 0)
1679 goto bad;
1680 sc->sc_tx_timer = 5;
1681
5fdff524 1682 return 0;
feb94d24
RP
1683bad:
1684 ifp->if_oerrors++;
1685 ieee80211_free_node(ni);
feb94d24
RP
1686 return EIO; /* XXX */
1687}
1688
1689static void
d8235d53 1690rt2661_watchdog_callout(void *arg)
feb94d24
RP
1691{
1692 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1693 struct ifnet *ifp = sc->sc_ifp;
1694
feb94d24
RP
1695 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running"));
1696
1697 if (sc->sc_invalid) /* card ejected */
1698 return;
1699
1700 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1701 if_printf(ifp, "device timeout\n");
1702 rt2661_init_locked(sc);
1703 ifp->if_oerrors++;
1704 /* NB: callout is reset in rt2661_init() */
1705 return;
1706 }
d8235d53 1707 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog_callout, sc);
feb94d24 1708
5fdff524
SZ
1709}
1710
1711static int
feb94d24 1712rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred)
5fdff524
SZ
1713{
1714 struct rt2661_softc *sc = ifp->if_softc;
feb94d24
RP
1715 struct ieee80211com *ic = ifp->if_l2com;
1716 struct ifreq *ifr = (struct ifreq *) data;
1717 int error = 0, startall = 0;
5fdff524
SZ
1718
1719 switch (cmd) {
1720 case SIOCSIFFLAGS:
1721 if (ifp->if_flags & IFF_UP) {
feb94d24
RP
1722 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1723 rt2661_init_locked(sc);
1724 startall = 1;
1725 } else
1726 rt2661_update_promisc(ifp);
5fdff524
SZ
1727 } else {
1728 if (ifp->if_flags & IFF_RUNNING)
feb94d24 1729 rt2661_stop_locked(sc);
5fdff524 1730 }
feb94d24
RP
1731 if (startall)
1732 ieee80211_start_all(ic);
1733 break;
1734 case SIOCGIFMEDIA:
1735 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1736 break;
1737 case SIOCGIFADDR:
1738 error = ether_ioctl(ifp, cmd, data);
5fdff524 1739 break;
5fdff524 1740 default:
feb94d24
RP
1741 error = EINVAL;
1742 break;
5fdff524
SZ
1743 }
1744 return error;
1745}
1746
1747static void
1748rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
1749{
1750 uint32_t tmp;
1751 int ntries;
1752
1753 for (ntries = 0; ntries < 100; ntries++) {
1754 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1755 break;
1756 DELAY(1);
1757 }
1758 if (ntries == 100) {
1759 device_printf(sc->sc_dev, "could not write to BBP\n");
1760 return;
1761 }
1762
1763 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1764 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
1765
feb94d24 1766 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
5fdff524
SZ
1767}
1768
1769static uint8_t
1770rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
1771{
1772 uint32_t val;
1773 int ntries;
1774
1775 for (ntries = 0; ntries < 100; ntries++) {
1776 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1777 break;
1778 DELAY(1);
1779 }
1780 if (ntries == 100) {
1781 device_printf(sc->sc_dev, "could not read from BBP\n");
1782 return 0;
1783 }
1784
1785 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1786 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
1787
1788 for (ntries = 0; ntries < 100; ntries++) {
1789 val = RAL_READ(sc, RT2661_PHY_CSR3);
1790 if (!(val & RT2661_BBP_BUSY))
1791 return val & 0xff;
1792 DELAY(1);
1793 }
1794
1795 device_printf(sc->sc_dev, "could not read from BBP\n");
1796 return 0;
1797}
1798
1799static void
1800rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
1801{
1802 uint32_t tmp;
1803 int ntries;
1804
1805 for (ntries = 0; ntries < 100; ntries++) {
1806 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
1807 break;
1808 DELAY(1);
1809 }
1810 if (ntries == 100) {
1811 device_printf(sc->sc_dev, "could not write to RF\n");
1812 return;
1813 }
1814
1815 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
1816 (reg & 3);
1817 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
1818
1819 /* remember last written value in sc */
1820 sc->rf_regs[reg] = val;
1821
feb94d24 1822 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
5fdff524
SZ
1823}
1824
1825static int
1826rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1827{
1828 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1829 return EIO; /* there is already a command pending */
1830
1831 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1832 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1833
1834 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1835
1836 return 0;
1837}
1838
1839static void
1840rt2661_select_antenna(struct rt2661_softc *sc)
1841{
1842 uint8_t bbp4, bbp77;
1843 uint32_t tmp;
1844
1845 bbp4 = rt2661_bbp_read(sc, 4);
1846 bbp77 = rt2661_bbp_read(sc, 77);
1847
1848 /* TBD */
1849
1850 /* make sure Rx is disabled before switching antenna */
1851 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
1852 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
1853
1854 rt2661_bbp_write(sc, 4, bbp4);
1855 rt2661_bbp_write(sc, 77, bbp77);
1856
1857 /* restore Rx filter */
1858 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1859}
1860
1861/*
1862 * Enable multi-rate retries for frames sent at OFDM rates.
1863 * In 802.11b/g mode, allow fallback to CCK rates.
1864 */
1865static void
1866rt2661_enable_mrr(struct rt2661_softc *sc)
1867{
feb94d24
RP
1868 struct ifnet *ifp = sc->sc_ifp;
1869 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1870 uint32_t tmp;
1871
1872 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1873
1874 tmp &= ~RT2661_MRR_CCK_FALLBACK;
feb94d24 1875 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan))
5fdff524
SZ
1876 tmp |= RT2661_MRR_CCK_FALLBACK;
1877 tmp |= RT2661_MRR_ENABLED;
1878
1879 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1880}
1881
1882static void
1883rt2661_set_txpreamble(struct rt2661_softc *sc)
1884{
feb94d24
RP
1885 struct ifnet *ifp = sc->sc_ifp;
1886 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1887 uint32_t tmp;
1888
1889 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1890
1891 tmp &= ~RT2661_SHORT_PREAMBLE;
feb94d24 1892 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5fdff524
SZ
1893 tmp |= RT2661_SHORT_PREAMBLE;
1894
1895 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1896}
1897
1898static void
feb94d24
RP
1899rt2661_set_basicrates(struct rt2661_softc *sc,
1900 const struct ieee80211_rateset *rs)
5fdff524
SZ
1901{
1902#define RV(r) ((r) & IEEE80211_RATE_VAL)
feb94d24
RP
1903 struct ifnet *ifp = sc->sc_ifp;
1904 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
1905 uint32_t mask = 0;
1906 uint8_t rate;
1907 int i, j;
1908
1909 for (i = 0; i < rs->rs_nrates; i++) {
1910 rate = rs->rs_rates[i];
1911
1912 if (!(rate & IEEE80211_RATE_BASIC))
1913 continue;
1914
1915 /*
1916 * Find h/w rate index. We know it exists because the rate
1917 * set has already been negotiated.
1918 */
feb94d24 1919 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++);
5fdff524
SZ
1920
1921 mask |= 1 << j;
1922 }
1923
1924 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
1925
feb94d24 1926 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask);
5fdff524
SZ
1927#undef RV
1928}
1929
1930/*
1931 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
1932 * driver.
1933 */
1934static void
1935rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
1936{
1937 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
1938 uint32_t tmp;
1939
1940 /* update all BBP registers that depend on the band */
1941 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
1942 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
1943 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1944 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
1945 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
1946 }
1947 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1948 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1949 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
1950 }
1951
1952 rt2661_bbp_write(sc, 17, bbp17);
1953 rt2661_bbp_write(sc, 96, bbp96);
1954 rt2661_bbp_write(sc, 104, bbp104);
1955
1956 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1957 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1958 rt2661_bbp_write(sc, 75, 0x80);
1959 rt2661_bbp_write(sc, 86, 0x80);
1960 rt2661_bbp_write(sc, 88, 0x80);
1961 }
1962
1963 rt2661_bbp_write(sc, 35, bbp35);
1964 rt2661_bbp_write(sc, 97, bbp97);
1965 rt2661_bbp_write(sc, 98, bbp98);
1966
1967 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
1968 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
1969 if (IEEE80211_IS_CHAN_2GHZ(c))
1970 tmp |= RT2661_PA_PE_2GHZ;
1971 else
1972 tmp |= RT2661_PA_PE_5GHZ;
1973 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
1974}
1975
1976static void
1977rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
1978{
feb94d24
RP
1979 struct ifnet *ifp = sc->sc_ifp;
1980 struct ieee80211com *ic = ifp->if_l2com;
1981 const struct rfprog *rfprog;
5fdff524
SZ
1982 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
1983 int8_t power;
1984 u_int i, chan;
1985
1986 chan = ieee80211_chan2ieee(ic, c);
feb94d24
RP
1987 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan));
1988
1989 /* select the appropriate RF settings based on what EEPROM says */
1990 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
5fdff524 1991
5fdff524 1992 /* find the settings for this channel (we know it exists) */
feb94d24 1993 for (i = 0; rfprog[i].chan != chan; i++);
5fdff524
SZ
1994
1995 power = sc->txpow[i];
1996 if (power < 0) {
1997 bbp94 += power;
1998 power = 0;
1999 } else if (power > 31) {
2000 bbp94 += power - 31;
2001 power = 31;
2002 }
2003
2004 /*
2005 * If we are switching from the 2GHz band to the 5GHz band or
2006 * vice-versa, BBP registers need to be reprogrammed.
2007 */
2008 if (c->ic_flags != sc->sc_curchan->ic_flags) {
2009 rt2661_select_band(sc, c);
2010 rt2661_select_antenna(sc);
2011 }
2012 sc->sc_curchan = c;
2013
feb94d24
RP
2014 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2015 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2016 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2017 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2018
2019 DELAY(200);
2020
2021 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2022 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2023 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
2024 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2025
2026 DELAY(200);
2027
2028 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2029 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2030 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2031 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
5fdff524
SZ
2032
2033 /* enable smart mode for MIMO-capable RFs */
2034 bbp3 = rt2661_bbp_read(sc, 3);
2035
2036 bbp3 &= ~RT2661_SMART_MODE;
2037 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2038 bbp3 |= RT2661_SMART_MODE;
2039
2040 rt2661_bbp_write(sc, 3, bbp3);
2041
2042 if (bbp94 != RT2661_BBPR94_DEFAULT)
2043 rt2661_bbp_write(sc, 94, bbp94);
2044
2045 /* 5GHz radio needs a 1ms delay here */
2046 if (IEEE80211_IS_CHAN_5GHZ(c))
2047 DELAY(1000);
2048}
2049
2050static void
2051rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
2052{
2053 uint32_t tmp;
2054
2055 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
2056 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2057
2058 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
2059 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2060}
2061
2062static void
2063rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2064{
2065 uint32_t tmp;
2066
2067 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2068 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2069
2070 tmp = addr[4] | addr[5] << 8;
2071 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2072}
2073
2074static void
feb94d24 2075rt2661_update_promisc(struct ifnet *ifp)
5fdff524 2076{
feb94d24 2077 struct rt2661_softc *sc = ifp->if_softc;
5fdff524
SZ
2078 uint32_t tmp;
2079
2080 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2081
2082 tmp &= ~RT2661_DROP_NOT_TO_ME;
2083 if (!(ifp->if_flags & IFF_PROMISC))
2084 tmp |= RT2661_DROP_NOT_TO_ME;
2085
2086 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2087
feb94d24
RP
2088 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ?
2089 "entering" : "leaving");
5fdff524
SZ
2090}
2091
2092/*
2093 * Update QoS (802.11e) settings for each h/w Tx ring.
2094 */
2095static int
2096rt2661_wme_update(struct ieee80211com *ic)
2097{
2098 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
2099 const struct wmeParams *wmep;
2100
2101 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
2102
2103 /* XXX: not sure about shifts. */
2104 /* XXX: the reference driver plays with AC_VI settings too. */
2105
2106 /* update TxOp */
2107 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2108 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2109 wmep[WME_AC_BK].wmep_txopLimit);
2110 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2111 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2112 wmep[WME_AC_VO].wmep_txopLimit);
2113
2114 /* update CWmin */
2115 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2116 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2117 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2118 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2119 wmep[WME_AC_VO].wmep_logcwmin);
2120
2121 /* update CWmax */
2122 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2123 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2124 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2125 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2126 wmep[WME_AC_VO].wmep_logcwmax);
2127
2128 /* update Aifsn */
2129 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2130 wmep[WME_AC_BE].wmep_aifsn << 12 |
2131 wmep[WME_AC_BK].wmep_aifsn << 8 |
2132 wmep[WME_AC_VI].wmep_aifsn << 4 |
2133 wmep[WME_AC_VO].wmep_aifsn);
2134
2135 return 0;
2136}
2137
2138static void
2139rt2661_update_slot(struct ifnet *ifp)
2140{
2141 struct rt2661_softc *sc = ifp->if_softc;
feb94d24 2142 struct ieee80211com *ic = ifp->if_l2com;
5fdff524
SZ
2143 uint8_t slottime;
2144 uint32_t tmp;
2145
2146 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2147
2148 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2149 tmp = (tmp & ~0xff) | slottime;
2150 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2151}
2152
2153static const char *
2154rt2661_get_rf(int rev)
2155{
2156 switch (rev) {
2157 case RT2661_RF_5225: return "RT5225";
2158 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2159 case RT2661_RF_2527: return "RT2527";
2160 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2161 default: return "unknown";
2162 }
2163}
2164
2165static void
feb94d24 2166rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
5fdff524 2167{
5fdff524 2168 uint16_t val;
feb94d24 2169 int i;
5fdff524
SZ
2170
2171 /* read MAC address */
2172 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
feb94d24
RP
2173 macaddr[0] = val & 0xff;
2174 macaddr[1] = val >> 8;
5fdff524
SZ
2175
2176 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
feb94d24
RP
2177 macaddr[2] = val & 0xff;
2178 macaddr[3] = val >> 8;
5fdff524
SZ
2179
2180 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
feb94d24
RP
2181 macaddr[4] = val & 0xff;
2182 macaddr[5] = val >> 8;
5fdff524
SZ
2183
2184 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2185 /* XXX: test if different from 0xffff? */
2186 sc->rf_rev = (val >> 11) & 0x1f;
2187 sc->hw_radio = (val >> 10) & 0x1;
2188 sc->rx_ant = (val >> 4) & 0x3;
2189 sc->tx_ant = (val >> 2) & 0x3;
2190 sc->nb_ant = val & 0x3;
2191
feb94d24 2192 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev);
5fdff524
SZ
2193
2194 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2195 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2196 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2197
feb94d24
RP
2198 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2199 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
99fda2c4 2200
5fdff524 2201 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
feb94d24
RP
2202 if ((val & 0xff) != 0xff)
2203 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
5fdff524 2204
7f742cc9 2205 /* Only [-10, 10] is valid */
feb94d24
RP
2206 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10)
2207 sc->rssi_2ghz_corr = 0;
7f742cc9 2208
5fdff524
SZ
2209 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2210 if ((val & 0xff) != 0xff)
2211 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2212
7f742cc9
SZ
2213 /* Only [-10, 10] is valid */
2214 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10)
2215 sc->rssi_5ghz_corr = 0;
2216
5fdff524 2217 /* adjust RSSI correction for external low-noise amplifier */
feb94d24
RP
2218 if (sc->ext_2ghz_lna)
2219 sc->rssi_2ghz_corr -= 14;
5fdff524
SZ
2220 if (sc->ext_5ghz_lna)
2221 sc->rssi_5ghz_corr -= 14;
2222
feb94d24
RP
2223 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2224 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
5fdff524
SZ
2225
2226 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2227 if ((val >> 8) != 0xff)
feb94d24 2228 sc->rfprog = (val >> 8) & 0x3;
5fdff524
SZ
2229 if ((val & 0xff) != 0xff)
2230 sc->rffreq = val & 0xff;
2231
feb94d24 2232 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
5fdff524 2233
feb94d24
RP
2234 /* read Tx power for all a/b/g channels */
2235 for (i = 0; i < 19; i++) {
2236 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2237 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2238 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2239 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
2240 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2241 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2242 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
2243 }
5fdff524
SZ
2244
2245 /* read vendor-specific BBP values */
2246 for (i = 0; i < 16; i++) {
2247 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2248 if (val == 0 || val == 0xffff)
2249 continue; /* skip invalid entries */
2250 sc->bbp_prom[i].reg = val >> 8;
2251 sc->bbp_prom[i].val = val & 0xff;
feb94d24
RP
2252 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2253 sc->bbp_prom[i].val);
5fdff524
SZ
2254 }
2255}
2256
2257static int
2258rt2661_bbp_init(struct rt2661_softc *sc)
2259{
2260#define N(a) (sizeof (a) / sizeof ((a)[0]))
2261 int i, ntries;
2262 uint8_t val;
2263
2264 /* wait for BBP to be ready */
2265 for (ntries = 0; ntries < 100; ntries++) {
2266 val = rt2661_bbp_read(sc, 0);
2267 if (val != 0 && val != 0xff)
2268 break;
2269 DELAY(100);
2270 }
2271 if (ntries == 100) {
2272 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2273 return EIO;
2274 }
2275
2276 /* initialize BBP registers to default values */
2277 for (i = 0; i < N(rt2661_def_bbp); i++) {
2278 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2279 rt2661_def_bbp[i].val);
2280 }
2281
2282 /* write vendor-specific BBP values (from EEPROM) */
2283 for (i = 0; i < 16; i++) {
2284 if (sc->bbp_prom[i].reg == 0)
2285 continue;
2286 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2287 }
2288
2289 return 0;
2290#undef N
2291}
2292
2293static void
feb94d24 2294rt2661_init_locked(struct rt2661_softc *sc)
5fdff524
SZ
2295{
2296#define N(a) (sizeof (a) / sizeof ((a)[0]))
feb94d24
RP
2297 struct ifnet *ifp = sc->sc_ifp;
2298 struct ieee80211com *ic = ifp->if_l2com;
5fdff524 2299 uint32_t tmp, sta[3];
feb94d24 2300 int i, error, ntries;
5fdff524 2301
feb94d24
RP
2302 if ((sc->sc_flags & RAL_FW_LOADED) == 0) {
2303 error = rt2661_load_microcode(sc);
2304 if (error != 0) {
2305 if_printf(ifp,
2306 "%s: could not load 8051 microcode, error %d\n",
2307 __func__, error);
2308 return;
2309 }
2310 sc->sc_flags |= RAL_FW_LOADED;
2311 }
2312
2313 rt2661_stop_locked(sc);
5fdff524
SZ
2314
2315 /* initialize Tx rings */
2316 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2317 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2318 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2319 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2320
2321 /* initialize Mgt ring */
2322 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2323
2324 /* initialize Rx ring */
2325 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2326
2327 /* initialize Tx rings sizes */
2328 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2329 RT2661_TX_RING_COUNT << 24 |
2330 RT2661_TX_RING_COUNT << 16 |
2331 RT2661_TX_RING_COUNT << 8 |
2332 RT2661_TX_RING_COUNT);
2333
2334 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2335 RT2661_TX_DESC_WSIZE << 16 |
2336 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2337 RT2661_MGT_RING_COUNT);
2338
2339 /* initialize Rx rings */
2340 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2341 RT2661_RX_DESC_BACK << 16 |
2342 RT2661_RX_DESC_WSIZE << 8 |
2343 RT2661_RX_RING_COUNT);
2344
2345 /* XXX: some magic here */
2346 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2347
2348 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2349 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2350
2351 /* load base address of Rx ring */
2352 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2353
2354 /* initialize MAC registers to default values */
2355 for (i = 0; i < N(rt2661_def_mac); i++)
2356 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2357
feb94d24 2358 rt2661_set_macaddr(sc, IF_LLADDR(ifp));
5fdff524
SZ
2359
2360 /* set host ready */
2361 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2362 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2363
2364 /* wait for BBP/RF to wakeup */
2365 for (ntries = 0; ntries < 1000; ntries++) {
2366 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2367 break;
2368 DELAY(1000);
2369 }
2370 if (ntries == 1000) {
e3869ec7 2371 kprintf("timeout waiting for BBP/RF to wakeup\n");
feb94d24 2372 rt2661_stop_locked(sc);
5fdff524
SZ
2373 return;
2374 }
2375
2376 if (rt2661_bbp_init(sc) != 0) {
feb94d24 2377 rt2661_stop_locked(sc);
5fdff524
SZ
2378 return;
2379 }
2380
2381 /* select default channel */
2382 sc->sc_curchan = ic->ic_curchan;
2383 rt2661_select_band(sc, sc->sc_curchan);
2384 rt2661_select_antenna(sc);
2385 rt2661_set_chan(sc, sc->sc_curchan);
2386
2387 /* update Rx filter */
2388 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2389
2390 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2391 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2392 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2393 RT2661_DROP_ACKCTS;
feb94d24
RP
2394 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
2395 ic->ic_opmode != IEEE80211_M_MBSS)
5fdff524
SZ
2396 tmp |= RT2661_DROP_TODS;
2397 if (!(ifp->if_flags & IFF_PROMISC))
2398 tmp |= RT2661_DROP_NOT_TO_ME;
2399 }
2400
2401 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2402
2403 /* clear STA registers */
2404 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta));
2405
2406 /* initialize ASIC */
2407 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2408
2409 /* clear any pending interrupt */
2410 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2411
2412 /* enable interrupts */
2413 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2414 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2415
2416 /* kick Rx */
2417 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2418
9ed293e0 2419 ifq_clr_oactive(&ifp->if_snd);
5fdff524
SZ
2420 ifp->if_flags |= IFF_RUNNING;
2421
d8235d53 2422 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog_callout, sc);
feb94d24
RP
2423#undef N
2424}
5717dc1a 2425
feb94d24
RP
2426static void
2427rt2661_init(void *priv)
2428{
2429 struct rt2661_softc *sc = priv;
2430 struct ifnet *ifp = sc->sc_ifp;
2431 struct ieee80211com *ic = ifp->if_l2com;
5717dc1a 2432
feb94d24 2433 rt2661_init_locked(sc);
110dc487 2434
feb94d24
RP
2435 if (ifp->if_flags & IFF_RUNNING)
2436 ieee80211_start_all(ic); /* start all vap's */
5fdff524
SZ
2437}
2438
2439void
feb94d24 2440rt2661_stop_locked(struct rt2661_softc *sc)
5fdff524 2441{
feb94d24 2442 struct ifnet *ifp = sc->sc_ifp;
5fdff524 2443 uint32_t tmp;
feb94d24 2444 volatile int *flags = &sc->sc_flags;
5fdff524 2445
feb94d24 2446 while (*flags & RAL_INPUT_RUNNING)
d8235d53 2447 zsleep(sc, &wlan_global_serializer, 0, "ralrunning", hz/10);
31358101 2448
feb94d24 2449 callout_stop(&sc->watchdog_ch);
5fdff524 2450 sc->sc_tx_timer = 0;
5fdff524 2451
feb94d24 2452 if (ifp->if_flags & IFF_RUNNING) {
9ed293e0
SZ
2453 ifp->if_flags &= ~IFF_RUNNING;
2454 ifq_clr_oactive(&ifp->if_snd);
feb94d24
RP
2455
2456 /* abort Tx (for all 5 Tx rings) */
2457 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2458
2459 /* disable Rx (value remains after reset!) */
2460 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2461 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2462
2463 /* reset ASIC */
2464 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2465 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2466
2467 /* disable interrupts */
2468 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2469 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2470
2471 /* clear any pending interrupt */
2472 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2473 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2474
2475 /* reset Tx and Rx rings */
2476 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2477 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2478 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2479 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2480 rt2661_reset_tx_ring(sc, &sc->mgtq);
2481 rt2661_reset_rx_ring(sc, &sc->rxq);
9dd87f8a 2482 }
feb94d24 2483}
9dd87f8a 2484
feb94d24
RP
2485void
2486rt2661_stop(void *priv)
2487{
2488 struct rt2661_softc *sc = priv;
5717dc1a 2489
feb94d24 2490 rt2661_stop_locked(sc);
5fdff524
SZ
2491}
2492
2493static int
feb94d24 2494rt2661_load_microcode(struct rt2661_softc *sc)
5fdff524 2495{
feb94d24
RP
2496 struct ifnet *ifp = sc->sc_ifp;
2497 const struct firmware *fp;
2498 const char *imagename;
2499 int ntries, error;
5fdff524 2500
feb94d24
RP
2501 switch (sc->sc_id) {
2502 case 0x0301: imagename = "rt2561sfw"; break;
2503 case 0x0302: imagename = "rt2561fw"; break;
2504 case 0x0401: imagename = "rt2661fw"; break;
2505 default:
2506 if_printf(ifp, "%s: unexpected pci device id 0x%x, "
2507 "don't know how to retrieve firmware\n",
2508 __func__, sc->sc_id);
2509 return EINVAL;
2510 }
feb94d24 2511 fp = firmware_get(imagename);
feb94d24
RP
2512 if (fp == NULL) {
2513 if_printf(ifp, "%s: unable to retrieve firmware image %s\n",
2514 __func__, imagename);
2515 return EINVAL;
2516 }
2517
2518 /*
2519 * Load 8051 microcode into NIC.
2520 */
5fdff524
SZ
2521 /* reset 8051 */
2522 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2523
2524 /* cancel any pending Host to MCU command */
2525 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2526 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2527 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2528
2529 /* write 8051's microcode */
2530 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
feb94d24 2531 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize);
5fdff524
SZ
2532 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2533
2534 /* kick 8051's ass */
2535 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2536
2537 /* wait for 8051 to initialize */
2538 for (ntries = 0; ntries < 500; ntries++) {
2539 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2540 break;
2541 DELAY(100);
2542 }
2543 if (ntries == 500) {
feb94d24
RP
2544 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n",
2545 __func__);
2546 error = EIO;
2547 } else
2548 error = 0;
2549
2550 firmware_put(fp, FIRMWARE_UNLOAD);
2551 return error;
2552}
2553
2554#ifdef notyet
2555/*
2556 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2557 * false CCA count. This function is called periodically (every seconds) when
2558 * in the RUN state. Values taken from the reference driver.
2559 */
2560static void
2561rt2661_rx_tune(struct rt2661_softc *sc)
2562{
2563 uint8_t bbp17;
2564 uint16_t cca;
2565 int lo, hi, dbm;
2566
2567 /*
2568 * Tuning range depends on operating band and on the presence of an
2569 * external low-noise amplifier.
2570 */
2571 lo = 0x20;
2572 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2573 lo += 0x08;
2574 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2575 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2576 lo += 0x10;
2577 hi = lo + 0x20;
2578
2579 /* retrieve false CCA count since last call (clear on read) */
2580 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2581
2582 if (dbm >= -35) {
2583 bbp17 = 0x60;
2584 } else if (dbm >= -58) {
2585 bbp17 = hi;
2586 } else if (dbm >= -66) {
2587 bbp17 = lo + 0x10;
2588 } else if (dbm >= -74) {
2589 bbp17 = lo + 0x08;
2590 } else {
2591 /* RSSI < -74dBm, tune using false CCA count */
2592
2593 bbp17 = sc->bbp17; /* current value */
2594
2595 hi -= 2 * (-74 - dbm);
2596 if (hi < lo)
2597 hi = lo;
2598
2599 if (bbp17 > hi) {
2600 bbp17 = hi;
2601
2602 } else if (cca > 512) {
2603 if (++bbp17 > hi)
2604 bbp17 = hi;
2605 } else if (cca < 100) {
2606 if (--bbp17 < lo)
2607 bbp17 = lo;
2608 }
5fdff524 2609 }
feb94d24
RP
2610
2611 if (bbp17 != sc->bbp17) {
2612 rt2661_bbp_write(sc, 17, bbp17);
2613 sc->bbp17 = bbp17;
2614 }
2615}
2616
2617/*
2618 * Enter/Leave radar detection mode.
2619 * This is for 802.11h additional regulatory domains.
2620 */
2621static void
2622rt2661_radar_start(struct rt2661_softc *sc)
2623{
2624 uint32_t tmp;
2625
2626 /* disable Rx */
2627 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2628 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2629
2630 rt2661_bbp_write(sc, 82, 0x20);
2631 rt2661_bbp_write(sc, 83, 0x00);
2632 rt2661_bbp_write(sc, 84, 0x40);
2633
2634 /* save current BBP registers values */
2635 sc->bbp18 = rt2661_bbp_read(sc, 18);
2636 sc->bbp21 = rt2661_bbp_read(sc, 21);
2637 sc->bbp22 = rt2661_bbp_read(sc, 22);
2638 sc->bbp16 = rt2661_bbp_read(sc, 16);
2639 sc->bbp17 = rt2661_bbp_read(sc, 17);
2640 sc->bbp64 = rt2661_bbp_read(sc, 64);
2641
2642 rt2661_bbp_write(sc, 18, 0xff);
2643 rt2661_bbp_write(sc, 21, 0x3f);
2644 rt2661_bbp_write(sc, 22, 0x3f);
2645 rt2661_bbp_write(sc, 16, 0xbd);
2646 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2647 rt2661_bbp_write(sc, 64, 0x21);
2648
2649 /* restore Rx filter */
2650 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
5fdff524
SZ
2651}
2652
5fdff524 2653static int
feb94d24 2654rt2661_radar_stop(struct rt2661_softc *sc)
5fdff524 2655{
feb94d24
RP
2656 uint8_t bbp66;
2657
2658 /* read radar detection result */
2659 bbp66 = rt2661_bbp_read(sc, 66);
2660
2661 /* restore BBP registers values */
2662 rt2661_bbp_write(sc, 16, sc->bbp16);
2663 rt2661_bbp_write(sc, 17, sc->bbp17);
2664 rt2661_bbp_write(sc, 18, sc->bbp18);
2665 rt2661_bbp_write(sc, 21, sc->bbp21);
2666 rt2661_bbp_write(sc, 22, sc->bbp22);
2667 rt2661_bbp_write(sc, 64, sc->bbp64);
2668
2669 return bbp66 == 1;
2670}
2671#endif
2672
2673static int
2674rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap)
2675{
2676 struct ieee80211com *ic = vap->iv_ic;
5fdff524
SZ
2677 struct ieee80211_beacon_offsets bo;
2678 struct rt2661_tx_desc desc;
2679 struct mbuf *m0;
2680 int rate;
2681
feb94d24 2682 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo);
5fdff524
SZ
2683 if (m0 == NULL) {
2684 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2685 return ENOBUFS;
2686 }
2687
2688 /* send beacons at the lowest available rate */
feb94d24 2689 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2;
5fdff524
SZ
2690
2691 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
feb94d24 2692 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT);
5fdff524
SZ
2693
2694 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2695 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2696
2697 /* copy beacon header and payload into NIC memory */
2698 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2699 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2700
2701 m_freem(m0);
feb94d24 2702
5fdff524
SZ
2703 return 0;
2704}
2705
2706/*
2707 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2708 * and HostAP operating modes.
2709 */
2710static void
2711rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2712{
feb94d24
RP
2713 struct ifnet *ifp = sc->sc_ifp;
2714 struct ieee80211com *ic = ifp->if_l2com;
2715 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
5fdff524
SZ
2716 uint32_t tmp;
2717
feb94d24 2718 if (vap->iv_opmode != IEEE80211_M_STA) {
5fdff524
SZ
2719 /*
2720 * Change default 16ms TBTT adjustment to 8ms.
2721 * Must be done before enabling beacon generation.
2722 */
2723 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2724 }
2725
2726 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2727
2728 /* set beacon interval (in 1/16ms unit) */
feb94d24 2729 tmp |= vap->iv_bss->ni_intval * 16;
5fdff524
SZ
2730
2731 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
feb94d24 2732 if (vap->iv_opmode == IEEE80211_M_STA)
5fdff524
SZ
2733 tmp |= RT2661_TSF_MODE(1);
2734 else
2735 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2736
2737 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2738}
2739
feb94d24
RP
2740static void
2741rt2661_enable_tsf(struct rt2661_softc *sc)
2742{
2743 RAL_WRITE(sc, RT2661_TXRX_CSR9,
2744 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000)
2745 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2));
2746}
2747
5fdff524
SZ
2748/*
2749 * Retrieve the "Received Signal Strength Indicator" from the raw values
2750 * contained in Rx descriptors. The computation depends on which band the
2751 * frame was received. Correction values taken from the reference driver.
2752 */
2753static int
feb94d24 2754rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
5fdff524
SZ
2755{
2756 int lna, agc, rssi;
2757
2758 lna = (raw >> 5) & 0x3;
2759 agc = raw & 0x1f;
2760
d2eb9874
SZ
2761 if (lna == 0) {
2762 /*
feb94d24 2763 * No mapping available.
d2eb9874
SZ
2764 *
2765 * NB: Since RSSI is relative to noise floor, -1 is
2766 * adequate for caller to know error happened.
2767 */
2768 return -1;
2769 }
2770
a6b13394 2771 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
5fdff524
SZ
2772
2773 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
feb94d24 2774 rssi += sc->rssi_2ghz_corr;
5fdff524
SZ
2775
2776 if (lna == 1)
2777 rssi -= 64;
2778 else if (lna == 2)
2779 rssi -= 74;
2780 else if (lna == 3)
2781 rssi -= 90;
2782 } else {
2783 rssi += sc->rssi_5ghz_corr;
2784
2785 if (lna == 1)
2786 rssi -= 64;
2787 else if (lna == 2)
2788 rssi -= 86;
2789 else if (lna == 3)
2790 rssi -= 100;
2791 }
2792 return rssi;
2793}
2794
2795static void
feb94d24 2796rt2661_scan_start(struct ieee80211com *ic)
6c40999e 2797{
feb94d24
RP
2798 struct ifnet *ifp = ic->ic_ifp;
2799 struct rt2661_softc *sc = ifp->if_softc;
2800 uint32_t tmp;
99fda2c4 2801
feb94d24
RP
2802 /* abort TSF synchronization */
2803 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
2804 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff);
2805 rt2661_set_bssid(sc, ifp->if_broadcastaddr);
99fda2c4
SZ
2806}
2807
2808static void
feb94d24 2809rt2661_scan_end(struct ieee80211com *ic)
99fda2c4 2810{
feb94d24
RP
2811 struct ifnet *ifp = ic->ic_ifp;
2812 struct rt2661_softc *sc = ifp->if_softc;
2813 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
411892e8 2814
feb94d24
RP
2815 rt2661_enable_tsf_sync(sc);
2816 /* XXX keep local copy */
2817 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid);
99fda2c4
SZ
2818}
2819
2820static void
feb94d24 2821rt2661_set_channel(struct ieee80211com *ic)
99fda2c4 2822{
feb94d24
RP
2823 struct ifnet *ifp = ic->ic_ifp;
2824 struct rt2661_softc *sc = ifp->if_softc;
99fda2c4 2825
feb94d24 2826 rt2661_set_chan(sc, ic->ic_curchan);
99fda2c4 2827}