if: Move IFF_OACTIVE bit into ifaltq; prepare multiple TX queues support
[dragonfly.git] / sys / dev / netif / sis / if_sis.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 */
34
35/*
36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
37 * available from http://www.sis.com.tw.
38 *
39 * This driver also supports the NatSemi DP83815. Datasheets are
40 * available from http://www.national.com.
41 *
42 * Written by Bill Paul <wpaul@ee.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
49 * simple TX and RX descriptors of 3 longwords in size. The receiver
50 * has a single perfect filter entry for the station address and a
51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
52 * transceiver while the 7016 requires an external transceiver chip.
53 * Both chips offer the standard bit-bang MII interface as well as
54 * an enchanced PHY interface which simplifies accessing MII registers.
55 *
56 * The only downside to this chipset is that RX descriptors must be
57 * longword aligned.
58 */
59
3bcfba15 60#include "opt_ifpoll.h"
2b71c8f1 61
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62#include <sys/param.h>
63#include <sys/systm.h>
64#include <sys/sockio.h>
65#include <sys/mbuf.h>
66#include <sys/malloc.h>
67#include <sys/kernel.h>
68#include <sys/socket.h>
69#include <sys/sysctl.h>
78195a76 70#include <sys/serialize.h>
3b7f6d2b 71#include <sys/thread2.h>
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72#include <sys/bus.h>
73#include <sys/rman.h>
9db4b353 74#include <sys/interrupt.h>
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75
76#include <net/if.h>
e25db1f0 77#include <net/ifq_var.h>
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78#include <net/if_arp.h>
79#include <net/ethernet.h>
80#include <net/if_dl.h>
81#include <net/if_media.h>
3bcfba15 82#include <net/if_poll.h>
984263bc 83#include <net/if_types.h>
1f2de5d4 84#include <net/vlan/if_vlan_var.h>
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85
86#include <net/bpf.h>
87
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88#include <dev/netif/mii_layer/mii.h>
89#include <dev/netif/mii_layer/miivar.h>
984263bc 90
94b23fe3 91#include <bus/pci/pcidevs.h>
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92#include <bus/pci/pcireg.h>
93#include <bus/pci/pcivar.h>
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94
95#define SIS_USEIOSPACE
96
1f2de5d4 97#include "if_sisreg.h"
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98
99/* "controller miibus0" required. See GENERIC if you get errors here. */
100#include "miibus_if.h"
101
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102/*
103 * Various supported device vendors/types and their names.
104 */
105static struct sis_type sis_devs[] = {
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106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
107 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
108 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
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109 { 0, 0, NULL }
110};
111
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112static int sis_probe(device_t);
113static int sis_attach(device_t);
114static int sis_detach(device_t);
115
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116static int sis_newbuf(struct sis_softc *, int, int);
117static void sis_setup_rxdesc(struct sis_softc *, int);
118static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *);
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119static void sis_rxeof(struct sis_softc *);
120static void sis_rxeoc(struct sis_softc *);
121static void sis_txeof(struct sis_softc *);
122static void sis_intr(void *);
123static void sis_tick(void *);
124static void sis_start(struct ifnet *);
bd4539cc 125static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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126static void sis_init(void *);
127static void sis_stop(struct sis_softc *);
128static void sis_watchdog(struct ifnet *);
129static void sis_shutdown(device_t);
130static int sis_ifmedia_upd(struct ifnet *);
131static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
132
133static uint16_t sis_reverse(uint16_t);
134static void sis_delay(struct sis_softc *);
135static void sis_eeprom_idle(struct sis_softc *);
136static void sis_eeprom_putbyte(struct sis_softc *, int);
137static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
138static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
984263bc 139#ifdef __i386__
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140static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
141static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
142static device_t sis_find_bridge(device_t);
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143#endif
144
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145static void sis_mii_sync(struct sis_softc *);
146static void sis_mii_send(struct sis_softc *, uint32_t, int);
147static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
148static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
149static int sis_miibus_readreg(device_t, int, int);
150static int sis_miibus_writereg(device_t, int, int, int);
151static void sis_miibus_statchg(device_t);
152
153static void sis_setmulti_sis(struct sis_softc *);
154static void sis_setmulti_ns(struct sis_softc *);
155static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
156static void sis_reset(struct sis_softc *);
157static int sis_list_rx_init(struct sis_softc *);
158static int sis_list_tx_init(struct sis_softc *);
4ddeda6c 159
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160static int sis_dma_alloc(device_t dev);
161static void sis_dma_free(device_t dev);
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162#ifdef IFPOLL_ENABLE
163static void sis_npoll(struct ifnet *, struct ifpoll_info *);
164static void sis_npoll_compat(struct ifnet *, void *, int);
9c095379 165#endif
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166#ifdef SIS_USEIOSPACE
167#define SIS_RES SYS_RES_IOPORT
168#define SIS_RID SIS_PCI_LOIO
169#else
170#define SIS_RES SYS_RES_MEMORY
171#define SIS_RID SIS_PCI_LOMEM
172#endif
173
174static device_method_t sis_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, sis_probe),
177 DEVMETHOD(device_attach, sis_attach),
178 DEVMETHOD(device_detach, sis_detach),
179 DEVMETHOD(device_shutdown, sis_shutdown),
180
181 /* bus interface */
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
187 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
188 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
189
190 { 0, 0 }
191};
192
193static driver_t sis_driver = {
194 "sis",
195 sis_methods,
196 sizeof(struct sis_softc)
197};
198
199static devclass_t sis_devclass;
200
32832096 201DECLARE_DUMMY_MODULE(if_sis);
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202DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, NULL, NULL);
203DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, NULL, NULL);
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204
205#define SIS_SETBIT(sc, reg, x) \
49eef4c6 206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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207
208#define SIS_CLRBIT(sc, reg, x) \
49eef4c6 209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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210
211#define SIO_SET(x) \
212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
213
214#define SIO_CLR(x) \
215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
216
217/*
218 * Routine to reverse the bits in a word. Stolen almost
219 * verbatim from /usr/games/fortune.
220 */
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221static uint16_t
222sis_reverse(uint16_t n)
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223{
224 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
225 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
226 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
227 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
228
229 return(n);
230}
231
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232static void
233sis_delay(struct sis_softc *sc)
984263bc 234{
49eef4c6 235 int idx;
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236
237 for (idx = (300 / 33) + 1; idx > 0; idx--)
238 CSR_READ_4(sc, SIS_CSR);
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239}
240
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241static void
242sis_eeprom_idle(struct sis_softc *sc)
984263bc 243{
49eef4c6 244 int i;
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245
246 SIO_SET(SIS_EECTL_CSEL);
247 sis_delay(sc);
248 SIO_SET(SIS_EECTL_CLK);
249 sis_delay(sc);
250
251 for (i = 0; i < 25; i++) {
252 SIO_CLR(SIS_EECTL_CLK);
253 sis_delay(sc);
254 SIO_SET(SIS_EECTL_CLK);
255 sis_delay(sc);
256 }
257
258 SIO_CLR(SIS_EECTL_CLK);
259 sis_delay(sc);
260 SIO_CLR(SIS_EECTL_CSEL);
261 sis_delay(sc);
262 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
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263}
264
265/*
266 * Send a read command and address to the EEPROM, check for ACK.
267 */
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268static void
269sis_eeprom_putbyte(struct sis_softc *sc, int addr)
984263bc 270{
49eef4c6 271 int d, i;
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272
273 d = addr | SIS_EECMD_READ;
274
275 /*
276 * Feed in each bit and stobe the clock.
277 */
278 for (i = 0x400; i; i >>= 1) {
49eef4c6 279 if (d & i)
984263bc 280 SIO_SET(SIS_EECTL_DIN);
49eef4c6 281 else
984263bc 282 SIO_CLR(SIS_EECTL_DIN);
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283 sis_delay(sc);
284 SIO_SET(SIS_EECTL_CLK);
285 sis_delay(sc);
286 SIO_CLR(SIS_EECTL_CLK);
287 sis_delay(sc);
288 }
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289}
290
291/*
292 * Read a word of data stored in the EEPROM at address 'addr.'
293 */
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294static void
295sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
984263bc 296{
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297 int i;
298 uint16_t word = 0;
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299
300 /* Force EEPROM to idle state. */
301 sis_eeprom_idle(sc);
302
303 /* Enter EEPROM access mode. */
304 sis_delay(sc);
305 SIO_CLR(SIS_EECTL_CLK);
306 sis_delay(sc);
307 SIO_SET(SIS_EECTL_CSEL);
308 sis_delay(sc);
309
310 /*
311 * Send address of word we want to read.
312 */
313 sis_eeprom_putbyte(sc, addr);
314
315 /*
316 * Start reading bits from EEPROM.
317 */
318 for (i = 0x8000; i; i >>= 1) {
319 SIO_SET(SIS_EECTL_CLK);
320 sis_delay(sc);
321 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
322 word |= i;
323 sis_delay(sc);
324 SIO_CLR(SIS_EECTL_CLK);
325 sis_delay(sc);
326 }
327
328 /* Turn off EEPROM access mode. */
329 sis_eeprom_idle(sc);
330
331 *dest = word;
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332}
333
334/*
335 * Read a sequence of words from the EEPROM.
336 */
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337static void
338sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc 339{
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340 int i;
341 uint16_t word = 0, *ptr;
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342
343 for (i = 0; i < cnt; i++) {
344 sis_eeprom_getword(sc, off + i, &word);
49eef4c6 345 ptr = (uint16_t *)(dest + (i * 2));
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346 if (swap)
347 *ptr = ntohs(word);
348 else
349 *ptr = word;
350 }
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351}
352
353#ifdef __i386__
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354static device_t
355sis_find_bridge(device_t dev)
984263bc 356{
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357 devclass_t pci_devclass;
358 device_t *pci_devices;
359 int pci_count = 0;
360 device_t *pci_children;
361 int pci_childcount = 0;
362 device_t *busp, *childp;
363 device_t child = NULL;
364 int i, j;
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365
366 if ((pci_devclass = devclass_find("pci")) == NULL)
367 return(NULL);
368
369 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
370
371 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
372 pci_childcount = 0;
373 device_get_children(*busp, &pci_children, &pci_childcount);
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374 for (j = 0, childp = pci_children; j < pci_childcount;
375 j++, childp++) {
94b23fe3 376 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
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377 pci_get_device(*childp) == 0x0008) {
378 child = *childp;
379 goto done;
380 }
381 }
382 }
383
384done:
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385 kfree(pci_devices, M_TEMP);
386 kfree(pci_children, M_TEMP);
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387 return(child);
388}
389
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390static void
391sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
392 int cnt)
984263bc 393{
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394 device_t bridge;
395 uint8_t reg;
396 int i;
397 bus_space_tag_t btag;
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398
399 bridge = sis_find_bridge(dev);
400 if (bridge == NULL)
401 return;
402 reg = pci_read_config(bridge, 0x48, 1);
403 pci_write_config(bridge, 0x48, reg|0x40, 1);
404
405 /* XXX */
406 btag = I386_BUS_SPACE_IO;
407
408 for (i = 0; i < cnt; i++) {
409 bus_space_write_1(btag, 0x0, 0x70, i + off);
410 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
411 }
412
413 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
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414}
415
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416static void
417sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
984263bc 418{
49eef4c6 419 uint32_t filtsave, csrsave;
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420
421 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
422 csrsave = CSR_READ_4(sc, SIS_CSR);
423
424 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
425 CSR_WRITE_4(sc, SIS_CSR, 0);
426
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
428
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
49eef4c6 430 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc 431 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
49eef4c6 432 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
984263bc 433 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
49eef4c6 434 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
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435
436 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
437 CSR_WRITE_4(sc, SIS_CSR, csrsave);
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438}
439#endif
440
441/*
442 * Sync the PHYs by setting data bit and strobing the clock 32 times.
443 */
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444static void
445sis_mii_sync(struct sis_softc *sc)
984263bc 446{
49eef4c6 447 int i;
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448
449 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
450
451 for (i = 0; i < 32; i++) {
452 SIO_SET(SIS_MII_CLK);
453 DELAY(1);
454 SIO_CLR(SIS_MII_CLK);
455 DELAY(1);
456 }
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457}
458
459/*
460 * Clock a series of bits through the MII.
461 */
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462static void
463sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
984263bc 464{
49eef4c6 465 int i;
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466
467 SIO_CLR(SIS_MII_CLK);
468
469 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
49eef4c6 470 if (bits & i)
984263bc 471 SIO_SET(SIS_MII_DATA);
49eef4c6 472 else
984263bc 473 SIO_CLR(SIS_MII_DATA);
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474 DELAY(1);
475 SIO_CLR(SIS_MII_CLK);
476 DELAY(1);
477 SIO_SET(SIS_MII_CLK);
478 }
479}
480
481/*
482 * Read an PHY register through the MII.
483 */
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484static int
485sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
984263bc 486{
3b7f6d2b 487 int i, ack;
984263bc 488
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489 /*
490 * Set up frame for RX.
491 */
492 frame->mii_stdelim = SIS_MII_STARTDELIM;
493 frame->mii_opcode = SIS_MII_READOP;
494 frame->mii_turnaround = 0;
495 frame->mii_data = 0;
496
497 /*
498 * Turn on data xmit.
499 */
500 SIO_SET(SIS_MII_DIR);
501
502 sis_mii_sync(sc);
503
504 /*
505 * Send command/address info.
506 */
507 sis_mii_send(sc, frame->mii_stdelim, 2);
508 sis_mii_send(sc, frame->mii_opcode, 2);
509 sis_mii_send(sc, frame->mii_phyaddr, 5);
510 sis_mii_send(sc, frame->mii_regaddr, 5);
511
512 /* Idle bit */
513 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
514 DELAY(1);
515 SIO_SET(SIS_MII_CLK);
516 DELAY(1);
517
518 /* Turn off xmit. */
519 SIO_CLR(SIS_MII_DIR);
520
521 /* Check for ack */
522 SIO_CLR(SIS_MII_CLK);
523 DELAY(1);
524 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
525 SIO_SET(SIS_MII_CLK);
526 DELAY(1);
527
528 /*
529 * Now try reading data bits. If the ack failed, we still
530 * need to clock through 16 cycles to keep the PHY(s) in sync.
531 */
532 if (ack) {
533 for(i = 0; i < 16; i++) {
534 SIO_CLR(SIS_MII_CLK);
535 DELAY(1);
536 SIO_SET(SIS_MII_CLK);
537 DELAY(1);
538 }
539 goto fail;
540 }
541
542 for (i = 0x8000; i; i >>= 1) {
543 SIO_CLR(SIS_MII_CLK);
544 DELAY(1);
545 if (!ack) {
546 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
547 frame->mii_data |= i;
548 DELAY(1);
549 }
550 SIO_SET(SIS_MII_CLK);
551 DELAY(1);
552 }
553
554fail:
555
556 SIO_CLR(SIS_MII_CLK);
557 DELAY(1);
558 SIO_SET(SIS_MII_CLK);
559 DELAY(1);
560
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561 if (ack)
562 return(1);
563 return(0);
564}
565
566/*
567 * Write to a PHY register through the MII.
568 */
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569static int
570sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
984263bc 571{
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572 /*
573 * Set up frame for TX.
574 */
575
576 frame->mii_stdelim = SIS_MII_STARTDELIM;
577 frame->mii_opcode = SIS_MII_WRITEOP;
578 frame->mii_turnaround = SIS_MII_TURNAROUND;
49eef4c6 579
984263bc 580 /*
49eef4c6 581 * Turn on data output.
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582 */
583 SIO_SET(SIS_MII_DIR);
584
585 sis_mii_sync(sc);
586
587 sis_mii_send(sc, frame->mii_stdelim, 2);
588 sis_mii_send(sc, frame->mii_opcode, 2);
589 sis_mii_send(sc, frame->mii_phyaddr, 5);
590 sis_mii_send(sc, frame->mii_regaddr, 5);
591 sis_mii_send(sc, frame->mii_turnaround, 2);
592 sis_mii_send(sc, frame->mii_data, 16);
593
594 /* Idle bit. */
595 SIO_SET(SIS_MII_CLK);
596 DELAY(1);
597 SIO_CLR(SIS_MII_CLK);
598 DELAY(1);
599
600 /*
601 * Turn off xmit.
602 */
603 SIO_CLR(SIS_MII_DIR);
604
984263bc
MD
605 return(0);
606}
607
49eef4c6
JS
608static int
609sis_miibus_readreg(device_t dev, int phy, int reg)
984263bc 610{
49eef4c6
JS
611 struct sis_softc *sc;
612 struct sis_mii_frame frame;
984263bc
MD
613
614 sc = device_get_softc(dev);
615
616 if (sc->sis_type == SIS_TYPE_83815) {
617 if (phy != 0)
618 return(0);
619 /*
620 * The NatSemi chip can take a while after
621 * a reset to come ready, during which the BMSR
622 * returns a value of 0. This is *never* supposed
623 * to happen: some of the BMSR bits are meant to
624 * be hardwired in the on position, and this can
625 * confuse the miibus code a bit during the probe
626 * and attach phase. So we make an effort to check
627 * for this condition and wait for it to clear.
628 */
629 if (!CSR_READ_4(sc, NS_BMSR))
630 DELAY(1000);
631 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
632 }
633 /*
49eef4c6
JS
634 * Chipsets < SIS_635 seem not to be able to read/write
635 * through mdio. Use the enhanced PHY access register
636 * again for them.
637 */
984263bc
MD
638 if (sc->sis_type == SIS_TYPE_900 &&
639 sc->sis_rev < SIS_REV_635) {
49eef4c6 640 int i, val = 0;
984263bc
MD
641
642 if (phy != 0)
643 return(0);
644
645 CSR_WRITE_4(sc, SIS_PHYCTL,
646 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
647 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
648
649 for (i = 0; i < SIS_TIMEOUT; i++) {
650 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
651 break;
652 }
653
654 if (i == SIS_TIMEOUT) {
10c5bfa0 655 device_printf(dev, "PHY failed to come ready\n");
984263bc
MD
656 return(0);
657 }
658
659 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
660
661 if (val == 0xFFFF)
662 return(0);
663
664 return(val);
665 } else {
666 bzero((char *)&frame, sizeof(frame));
49eef4c6 667
984263bc
MD
668 frame.mii_phyaddr = phy;
669 frame.mii_regaddr = reg;
670 sis_mii_readreg(sc, &frame);
49eef4c6 671
984263bc
MD
672 return(frame.mii_data);
673 }
674}
675
49eef4c6
JS
676static int
677sis_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 678{
49eef4c6
JS
679 struct sis_softc *sc;
680 struct sis_mii_frame frame;
984263bc
MD
681
682 sc = device_get_softc(dev);
683
684 if (sc->sis_type == SIS_TYPE_83815) {
685 if (phy != 0)
686 return(0);
687 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
688 return(0);
689 }
690
691 if (sc->sis_type == SIS_TYPE_900 &&
692 sc->sis_rev < SIS_REV_635) {
49eef4c6 693 int i;
984263bc
MD
694
695 if (phy != 0)
696 return(0);
49eef4c6 697
984263bc
MD
698 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
699 (reg << 6) | SIS_PHYOP_WRITE);
700 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
701
702 for (i = 0; i < SIS_TIMEOUT; i++) {
703 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
704 break;
705 }
49eef4c6 706
984263bc 707 if (i == SIS_TIMEOUT)
10c5bfa0 708 device_printf(dev, "PHY failed to come ready\n");
984263bc
MD
709 } else {
710 bzero((char *)&frame, sizeof(frame));
49eef4c6 711
984263bc
MD
712 frame.mii_phyaddr = phy;
713 frame.mii_regaddr = reg;
714 frame.mii_data = data;
715 sis_mii_writereg(sc, &frame);
716 }
717 return(0);
718}
719
7b9f668c
SW
720static void
721sis_miibus_statchg(device_t dev)
984263bc 722{
49eef4c6 723 struct sis_softc *sc;
984263bc
MD
724
725 sc = device_get_softc(dev);
726 sis_init(sc);
984263bc
MD
727}
728
49eef4c6
JS
729static uint32_t
730sis_mchash(struct sis_softc *sc, const uint8_t *addr)
984263bc 731{
49eef4c6
JS
732 uint32_t crc, carry;
733 int i, j;
734 uint8_t c;
984263bc
MD
735
736 /* Compute CRC for the address value. */
737 crc = 0xFFFFFFFF; /* initial value */
738
739 for (i = 0; i < 6; i++) {
740 c = *(addr + i);
741 for (j = 0; j < 8; j++) {
742 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
743 crc <<= 1;
744 c >>= 1;
745 if (carry)
746 crc = (crc ^ 0x04c11db6) | carry;
747 }
748 }
749
750 /*
751 * return the filter bit position
752 *
753 * The NatSemi chip has a 512-bit filter, which is
754 * different than the SiS, so we special-case it.
755 */
756 if (sc->sis_type == SIS_TYPE_83815)
757 return (crc >> 23);
49eef4c6 758 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
984263bc
MD
759 return (crc >> 24);
760 else
761 return (crc >> 25);
762}
763
49eef4c6
JS
764static void
765sis_setmulti_ns(struct sis_softc *sc)
984263bc 766{
49eef4c6
JS
767 struct ifnet *ifp;
768 struct ifmultiaddr *ifma;
769 uint32_t h = 0, i, filtsave;
770 int bit, index;
984263bc
MD
771
772 ifp = &sc->arpcom.ac_if;
773
774 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
775 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
776 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
777 return;
778 }
779
780 /*
781 * We have to explicitly enable the multicast hash table
782 * on the NatSemi chip if we want to use it, which we do.
783 */
784 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
785 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
786
787 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
788
789 /* first, zot all the existing hash bits */
790 for (i = 0; i < 32; i++) {
791 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
792 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
793 }
794
441d34b2 795 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
796 if (ifma->ifma_addr->sa_family != AF_LINK)
797 continue;
49eef4c6
JS
798 h = sis_mchash(sc,
799 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
984263bc
MD
800 index = h >> 3;
801 bit = h & 0x1F;
802 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
803 if (bit > 0xF)
804 bit -= 0x10;
805 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
806 }
807
808 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
984263bc
MD
809}
810
49eef4c6
JS
811static void
812sis_setmulti_sis(struct sis_softc *sc)
984263bc 813{
49eef4c6
JS
814 struct ifnet *ifp;
815 struct ifmultiaddr *ifma;
816 uint32_t h, i, n, ctl;
817 uint16_t hashes[16];
984263bc
MD
818
819 ifp = &sc->arpcom.ac_if;
820
821 /* hash table size */
49eef4c6 822 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
984263bc
MD
823 n = 16;
824 else
825 n = 8;
826
827 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
828
829 if (ifp->if_flags & IFF_BROADCAST)
830 ctl |= SIS_RXFILTCTL_BROAD;
831
832 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
833 ctl |= SIS_RXFILTCTL_ALLMULTI;
834 if (ifp->if_flags & IFF_PROMISC)
835 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
836 for (i = 0; i < n; i++)
837 hashes[i] = ~0;
838 } else {
839 for (i = 0; i < n; i++)
840 hashes[i] = 0;
841 i = 0;
441d34b2 842 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
843 if (ifma->ifma_addr->sa_family != AF_LINK)
844 continue;
49eef4c6 845 h = sis_mchash(sc,
984263bc
MD
846 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
847 hashes[h >> 4] |= 1 << (h & 0xf);
848 i++;
849 }
850 if (i > n) {
851 ctl |= SIS_RXFILTCTL_ALLMULTI;
852 for (i = 0; i < n; i++)
853 hashes[i] = ~0;
854 }
855 }
856
857 for (i = 0; i < n; i++) {
858 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
859 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
860 }
861
862 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
863}
864
49eef4c6
JS
865static void
866sis_reset(struct sis_softc *sc)
984263bc 867{
10c5bfa0 868 struct ifnet *ifp = &sc->arpcom.ac_if;
49eef4c6 869 int i;
984263bc
MD
870
871 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
872
873 for (i = 0; i < SIS_TIMEOUT; i++) {
874 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
875 break;
876 }
877
878 if (i == SIS_TIMEOUT)
10c5bfa0 879 if_printf(ifp, "reset never completed\n");
984263bc
MD
880
881 /* Wait a little while for the chip to get its brains in order. */
882 DELAY(1000);
883
884 /*
885 * If this is a NetSemi chip, make sure to clear
886 * PME mode.
887 */
888 if (sc->sis_type == SIS_TYPE_83815) {
889 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
890 CSR_WRITE_4(sc, NS_CLKRUN, 0);
891 }
984263bc
MD
892}
893
894/*
895 * Probe for an SiS chip. Check the PCI vendor and device
896 * IDs against our list and return a device name if we find a match.
897 */
49eef4c6
JS
898static int
899sis_probe(device_t dev)
984263bc 900{
49eef4c6 901 struct sis_type *t;
984263bc
MD
902
903 t = sis_devs;
904
905 while(t->sis_name != NULL) {
906 if ((pci_get_vendor(dev) == t->sis_vid) &&
907 (pci_get_device(dev) == t->sis_did)) {
908 device_set_desc(dev, t->sis_name);
909 return(0);
910 }
911 t++;
912 }
913
914 return(ENXIO);
915}
916
917/*
918 * Attach the interface. Allocate softc structures, do ifmedia
919 * setup and ethernet/BPF attach.
920 */
49eef4c6
JS
921static int
922sis_attach(device_t dev)
984263bc 923{
49eef4c6
JS
924 uint8_t eaddr[ETHER_ADDR_LEN];
925 uint32_t command;
926 struct sis_softc *sc;
927 struct ifnet *ifp;
10c5bfa0 928 int error, rid, waittime;
984263bc 929
984263bc
MD
930 error = waittime = 0;
931 sc = device_get_softc(dev);
984263bc 932
94b23fe3 933 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
984263bc 934 sc->sis_type = SIS_TYPE_900;
94b23fe3 935 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
984263bc 936 sc->sis_type = SIS_TYPE_7016;
94b23fe3 937 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
984263bc
MD
938 sc->sis_type = SIS_TYPE_83815;
939
940 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
941
942 /*
943 * Handle power management nonsense.
944 */
945
946 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
947 if (command == 0x01) {
948
949 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
950 if (command & SIS_PSTATE_MASK) {
49eef4c6 951 uint32_t iobase, membase, irq;
984263bc
MD
952
953 /* Save important PCI config data. */
954 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
955 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
956 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
957
958 /* Reset the power state. */
10c5bfa0
JS
959 device_printf(dev, "chip is in D%d power mode "
960 "-- setting to D0\n", command & SIS_PSTATE_MASK);
984263bc
MD
961 command &= 0xFFFFFFFC;
962 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
963
964 /* Restore PCI config data. */
965 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
966 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
967 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
968 }
969 }
970
971 /*
972 * Map control/status registers.
973 */
974 command = pci_read_config(dev, PCIR_COMMAND, 4);
975 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
976 pci_write_config(dev, PCIR_COMMAND, command, 4);
977 command = pci_read_config(dev, PCIR_COMMAND, 4);
978
979#ifdef SIS_USEIOSPACE
980 if (!(command & PCIM_CMD_PORTEN)) {
10c5bfa0 981 device_printf(dev, "failed to enable I/O ports!\n");
fc6d0222 982 error = ENXIO;
984263bc
MD
983 goto fail;
984 }
985#else
986 if (!(command & PCIM_CMD_MEMEN)) {
10c5bfa0 987 device_printf(dev, "failed to enable memory mapping!\n");
fc6d0222 988 error = ENXIO;
984263bc
MD
989 goto fail;
990 }
991#endif
992
993 rid = SIS_RID;
4e6d744d 994 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
984263bc
MD
995
996 if (sc->sis_res == NULL) {
10c5bfa0 997 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
998 error = ENXIO;
999 goto fail;
1000 }
1001
1002 sc->sis_btag = rman_get_bustag(sc->sis_res);
1003 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1004
1005 /* Allocate interrupt */
1006 rid = 0;
4e6d744d 1007 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
1008 RF_SHAREABLE | RF_ACTIVE);
1009
1010 if (sc->sis_irq == NULL) {
10c5bfa0 1011 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
1012 error = ENXIO;
1013 goto fail;
1014 }
1015
984263bc
MD
1016 /* Reset the adapter. */
1017 sis_reset(sc);
1018
1019 if (sc->sis_type == SIS_TYPE_900 &&
1020 (sc->sis_rev == SIS_REV_635 ||
1021 sc->sis_rev == SIS_REV_900B)) {
1022 SIO_SET(SIS_CFG_RND_CNT);
1023 SIO_SET(SIS_CFG_PERR_DETECT);
1024 }
1025
1026 /*
1027 * Get station address from the EEPROM.
1028 */
1029 switch (pci_get_vendor(dev)) {
94b23fe3 1030 case PCI_VENDOR_NS:
984263bc
MD
1031 /*
1032 * Reading the MAC address out of the EEPROM on
1033 * the NatSemi chip takes a bit more work than
1034 * you'd expect. The address spans 4 16-bit words,
1035 * with the first word containing only a single bit.
1036 * You have to shift everything over one bit to
1037 * get it aligned properly. Also, the bits are
1038 * stored backwards (the LSB is really the MSB,
1039 * and so on) so you have to reverse them in order
1040 * to get the MAC address into the form we want.
1041 * Why? Who the hell knows.
1042 */
1043 {
49eef4c6 1044 uint16_t tmp[4];
984263bc
MD
1045
1046 sis_read_eeprom(sc, (caddr_t)&tmp,
1047 NS_EE_NODEADDR, 4, 0);
1048
1049 /* Shift everything over one bit. */
1050 tmp[3] = tmp[3] >> 1;
1051 tmp[3] |= tmp[2] << 15;
1052 tmp[2] = tmp[2] >> 1;
1053 tmp[2] |= tmp[1] << 15;
1054 tmp[1] = tmp[1] >> 1;
1055 tmp[1] |= tmp[0] << 15;
1056
1057 /* Now reverse all the bits. */
1058 tmp[3] = sis_reverse(tmp[3]);
1059 tmp[2] = sis_reverse(tmp[2]);
1060 tmp[1] = sis_reverse(tmp[1]);
1061
1062 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1063 }
1064 break;
94b23fe3 1065 case PCI_VENDOR_SIS:
984263bc
MD
1066 default:
1067#ifdef __i386__
1068 /*
1069 * If this is a SiS 630E chipset with an embedded
1070 * SiS 900 controller, we have to read the MAC address
1071 * from the APC CMOS RAM. Our method for doing this
1072 * is very ugly since we have to reach out and grab
1073 * ahold of hardware for which we cannot properly
1074 * allocate resources. This code is only compiled on
1075 * the i386 architecture since the SiS 630E chipset
1076 * is for x86 motherboards only. Note that there are
1077 * a lot of magic numbers in this hack. These are
1078 * taken from SiS's Linux driver. I'd like to replace
1079 * them with proper symbolic definitions, but that
1080 * requires some datasheets that I don't have access
1081 * to at the moment.
1082 */
1083 if (sc->sis_rev == SIS_REV_630S ||
1084 sc->sis_rev == SIS_REV_630E ||
1085 sc->sis_rev == SIS_REV_630EA1)
1086 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1087
1088 else if (sc->sis_rev == SIS_REV_635 ||
1089 sc->sis_rev == SIS_REV_630ET)
1090 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1091 else if (sc->sis_rev == SIS_REV_96x) {
1092 /*
1093 * Allow to read EEPROM from LAN. It is shared
1094 * between a 1394 controller and the NIC and each
1095 * time we access it, we need to set SIS_EECMD_REQ.
1096 */
1097 SIO_SET(SIS_EECMD_REQ);
1098 for (waittime = 0; waittime < SIS_TIMEOUT;
1099 waittime++) {
1100 /* Force EEPROM to idle state. */
1101 sis_eeprom_idle(sc);
1102 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1103 sis_read_eeprom(sc, (caddr_t)&eaddr,
1104 SIS_EE_NODEADDR, 3, 0);
1105 break;
1106 }
1107 DELAY(1);
1108 }
1109 /*
1110 * Set SIS_EECTL_CLK to high, so a other master
1111 * can operate on the i2c bus.
1112 */
1113 SIO_SET(SIS_EECTL_CLK);
1114 /* Refuse EEPROM access by LAN */
1115 SIO_SET(SIS_EECMD_DONE);
1116 } else
1117#endif
1118 sis_read_eeprom(sc, (caddr_t)&eaddr,
1119 SIS_EE_NODEADDR, 3, 0);
1120 break;
1121 }
1122
5047f29c 1123 callout_init(&sc->sis_timer);
984263bc 1124
9513d9d2 1125 error = sis_dma_alloc(dev);
4ddeda6c
JS
1126 if (error)
1127 goto fail;
984263bc
MD
1128
1129 ifp = &sc->arpcom.ac_if;
1130 ifp->if_softc = sc;
10c5bfa0 1131 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
1132 ifp->if_mtu = ETHERMTU;
1133 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1134 ifp->if_ioctl = sis_ioctl;
984263bc
MD
1135 ifp->if_start = sis_start;
1136 ifp->if_watchdog = sis_watchdog;
1137 ifp->if_init = sis_init;
1138 ifp->if_baudrate = 10000000;
e25db1f0
JS
1139 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1140 ifq_set_ready(&ifp->if_snd);
3bcfba15
SZ
1141#ifdef IFPOLL_ENABLE
1142 ifp->if_npoll = sis_npoll;
d9168eb7
JS
1143#endif
1144 ifp->if_capenable = ifp->if_capabilities;
984263bc
MD
1145
1146 /*
1147 * Do MII setup.
1148 */
1149 if (mii_phy_probe(dev, &sc->sis_miibus,
1150 sis_ifmedia_upd, sis_ifmedia_sts)) {
4ddeda6c 1151 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
1152 error = ENXIO;
1153 goto fail;
1154 }
1155
1156 /*
1157 * Call MI attach routine.
1158 */
78195a76 1159 ether_ifattach(ifp, eaddr, NULL);
3bcfba15
SZ
1160
1161#ifdef IFPOLL_ENABLE
1162 ifpoll_compat_setup(&sc->sis_npoll, NULL, NULL, device_get_unit(dev),
1163 ifp->if_serializer);
1164#endif
984263bc
MD
1165
1166 /*
1167 * Tell the upper layer(s) we support long frames.
1168 */
1169 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1170
95893fe4 1171 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE,
e9cb6d99 1172 sis_intr, sc,
78195a76
MD
1173 &sc->sis_intrhand,
1174 ifp->if_serializer);
4ddeda6c
JS
1175
1176 if (error) {
1177 device_printf(dev, "couldn't set up irq\n");
1178 ether_ifdetach(ifp);
1179 goto fail;
1180 }
1181
28e81a28 1182 ifp->if_cpuid = rman_get_cpuid(sc->sis_irq);
9db4b353
SZ
1183 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1184
984263bc 1185fail:
4ddeda6c
JS
1186 if (error)
1187 sis_detach(dev);
1188
984263bc
MD
1189 return(error);
1190}
1191
4ddeda6c
JS
1192/*
1193 * Shutdown hardware and free up resources. It is called in both the error case
1194 * and the normal detach case so it needs to be careful about only freeing
1195 * resources that have actually been allocated.
1196 */
49eef4c6
JS
1197static int
1198sis_detach(device_t dev)
984263bc 1199{
3b7f6d2b
JS
1200 struct sis_softc *sc = device_get_softc(dev);
1201 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1202
984263bc 1203
4ddeda6c 1204 if (device_is_attached(dev)) {
cdf89432 1205 lwkt_serialize_enter(ifp->if_serializer);
4ddeda6c
JS
1206 sis_reset(sc);
1207 sis_stop(sc);
cdf89432
SZ
1208 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1209 lwkt_serialize_exit(ifp->if_serializer);
1210
4ddeda6c
JS
1211 ether_ifdetach(ifp);
1212 }
1213 if (sc->sis_miibus)
1214 device_delete_child(dev, sc->sis_miibus);
984263bc 1215 bus_generic_detach(dev);
984263bc 1216
4ddeda6c
JS
1217 if (sc->sis_irq)
1218 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1219 if (sc->sis_res)
1220 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
984263bc 1221
9513d9d2 1222 sis_dma_free(dev);
984263bc 1223
984263bc
MD
1224 return(0);
1225}
1226
1227/*
1228 * Initialize the transmit descriptors.
1229 */
49eef4c6
JS
1230static int
1231sis_list_tx_init(struct sis_softc *sc)
984263bc 1232{
9513d9d2
SZ
1233 struct sis_list_data *ld = &sc->sis_ldata;
1234 struct sis_chain_data *cd = &sc->sis_cdata;
49eef4c6 1235 int i, nexti;
984263bc 1236
984263bc 1237 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
9513d9d2
SZ
1238 bus_addr_t paddr;
1239
1240 /*
1241 * Link the TX desc together
1242 */
984263bc 1243 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
9513d9d2
SZ
1244 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc));
1245 ld->sis_tx_list[i].sis_next = paddr;
984263bc 1246 }
984263bc
MD
1247 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1248
9513d9d2 1249 return 0;
984263bc
MD
1250}
1251
984263bc
MD
1252/*
1253 * Initialize the RX descriptors and allocate mbufs for them. Note that
1254 * we arrange the descriptors in a closed ring, so that the last descriptor
1255 * points back to the first.
1256 */
49eef4c6
JS
1257static int
1258sis_list_rx_init(struct sis_softc *sc)
984263bc 1259{
9513d9d2
SZ
1260 struct sis_list_data *ld = &sc->sis_ldata;
1261 struct sis_chain_data *cd = &sc->sis_cdata;
1262 int i, error;
984263bc
MD
1263
1264 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
9513d9d2
SZ
1265 bus_addr_t paddr;
1266 int nexti;
9d4c8d7d 1267
9513d9d2
SZ
1268 error = sis_newbuf(sc, i, 1);
1269 if (error)
1270 return error;
1271
1272 /*
1273 * Link the RX desc together
1274 */
984263bc 1275 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
9513d9d2
SZ
1276 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc));
1277 ld->sis_rx_list[i].sis_next = paddr;
984263bc 1278 }
984263bc
MD
1279 cd->sis_rx_prod = 0;
1280
9513d9d2 1281 return 0;
984263bc
MD
1282}
1283
1284/*
1285 * Initialize an RX descriptor and attach an MBUF cluster.
1286 */
49eef4c6 1287static int
9513d9d2 1288sis_newbuf(struct sis_softc *sc, int idx, int init)
984263bc 1289{
9513d9d2
SZ
1290 struct sis_chain_data *cd = &sc->sis_cdata;
1291 struct sis_rx_data *rd = &cd->sis_rx_data[idx];
1292 bus_dma_segment_t seg;
1293 bus_dmamap_t map;
1294 struct mbuf *m;
1295 int nseg, error;
9d4c8d7d 1296
9513d9d2 1297 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc 1298 if (m == NULL) {
9513d9d2
SZ
1299 if (init)
1300 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n");
1301 return ENOBUFS;
984263bc 1302 }
9513d9d2 1303 m->m_len = m->m_pkthdr.len = MCLBYTES;
984263bc 1304
9513d9d2
SZ
1305 /* Try loading the mbuf into tmp DMA map */
1306 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag,
1307 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1308 if (error) {
1309 m_freem(m);
1310 if (init)
1311 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1312 return error;
1313 }
1314
1315 /* Unload the currently loaded mbuf */
1316 if (rd->sis_mbuf != NULL) {
1317 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map,
1318 BUS_DMASYNC_POSTREAD);
1319 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
1320 }
1321
1322 /* Swap DMA maps */
1323 map = cd->sis_rx_tmpmap;
1324 cd->sis_rx_tmpmap = rd->sis_map;
1325 rd->sis_map = map;
1326
1327 /* Save necessary information */
9d4c8d7d 1328 rd->sis_mbuf = m;
9513d9d2 1329 rd->sis_paddr = seg.ds_addr;
984263bc 1330
9513d9d2
SZ
1331 sis_setup_rxdesc(sc, idx);
1332 return 0;
1333}
4ddeda6c 1334
9513d9d2
SZ
1335static void
1336sis_setup_rxdesc(struct sis_softc *sc, int idx)
1337{
1338 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx];
1339
1340 /* Setup the RX desc */
1341 c->sis_ctl = SIS_RXLEN;
1342 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr;
984263bc
MD
1343}
1344
1345/*
1346 * A frame has been uploaded: pass the resulting mbuf chain up to
1347 * the higher level protocols.
1348 */
49eef4c6
JS
1349static void
1350sis_rxeof(struct sis_softc *sc)
984263bc 1351{
9513d9d2 1352 struct ifnet *ifp = &sc->arpcom.ac_if;
49eef4c6
JS
1353 int i, total_len = 0;
1354 uint32_t rxstat;
984263bc 1355
984263bc 1356 i = sc->sis_cdata.sis_rx_prod;
9513d9d2 1357 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
9d4c8d7d
SZ
1358 struct sis_desc *cur_rx;
1359 struct sis_rx_data *rd;
9513d9d2 1360 struct mbuf *m;
9d4c8d7d 1361 int idx = i;
984263bc 1362
3bcfba15
SZ
1363#ifdef IFPOLL_ENABLE
1364 if (ifp->if_flags & IFF_NPOLLING) {
984263bc
MD
1365 if (sc->rxcycles <= 0)
1366 break;
1367 sc->rxcycles--;
1368 }
3bcfba15 1369#endif /* IFPOLL_ENABLE */
9d4c8d7d
SZ
1370
1371 cur_rx = &sc->sis_ldata.sis_rx_list[idx];
1372 rd = &sc->sis_cdata.sis_rx_data[idx];
1373
984263bc 1374 rxstat = cur_rx->sis_rxstat;
9513d9d2 1375 total_len = SIS_RXBYTES(cur_rx);
9d4c8d7d
SZ
1376
1377 m = rd->sis_mbuf;
9d4c8d7d 1378
984263bc
MD
1379 SIS_INC(i, SIS_RX_LIST_CNT);
1380
1381 /*
1382 * If an error occurs, update stats, clear the
1383 * status word and leave the mbuf cluster in place:
1384 * it should simply get re-used next time this descriptor
1385 * comes up in the ring.
1386 */
1387 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1388 ifp->if_ierrors++;
1389 if (rxstat & SIS_RXSTAT_COLL)
1390 ifp->if_collisions++;
9513d9d2 1391 sis_setup_rxdesc(sc, idx);
984263bc
MD
1392 continue;
1393 }
1394
1395 /* No errors; receive the packet. */
9513d9d2 1396 if (sis_newbuf(sc, idx, 0) == 0) {
984263bc 1397 m->m_pkthdr.len = m->m_len = total_len;
9513d9d2
SZ
1398 m->m_pkthdr.rcvif = ifp;
1399 } else {
1400 ifp->if_ierrors++;
1401 sis_setup_rxdesc(sc, idx);
1402 continue;
984263bc
MD
1403 }
1404
1405 ifp->if_ipackets++;
78195a76 1406 ifp->if_input(ifp, m);
984263bc 1407 }
984263bc 1408 sc->sis_cdata.sis_rx_prod = i;
984263bc
MD
1409}
1410
49eef4c6
JS
1411static void
1412sis_rxeoc(struct sis_softc *sc)
984263bc
MD
1413{
1414 sis_rxeof(sc);
4ddeda6c 1415 sis_init(sc);
984263bc
MD
1416}
1417
1418/*
1419 * A frame was downloaded to the chip. It's safe for us to clean up
1420 * the list buffers.
1421 */
1422
49eef4c6
JS
1423static void
1424sis_txeof(struct sis_softc *sc)
984263bc 1425{
9513d9d2
SZ
1426 struct ifnet *ifp = &sc->arpcom.ac_if;
1427 struct sis_chain_data *cd = &sc->sis_cdata;
49eef4c6 1428 uint32_t idx;
984263bc 1429
984263bc
MD
1430 /*
1431 * Go through our tx list and free mbufs for those
1432 * frames that have been transmitted.
1433 */
4ddeda6c
JS
1434 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1435 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
9d4c8d7d
SZ
1436 struct sis_desc *cur_tx;
1437 struct sis_tx_data *td;
1438
4ddeda6c 1439 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
9513d9d2 1440 td = &cd->sis_tx_data[idx];
984263bc
MD
1441
1442 if (SIS_OWNDESC(cur_tx))
1443 break;
1444
4ddeda6c 1445 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
984263bc 1446 continue;
984263bc
MD
1447
1448 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1449 ifp->if_oerrors++;
1450 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1451 ifp->if_collisions++;
1452 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1453 ifp->if_collisions++;
1454 }
1455
1456 ifp->if_collisions +=
1457 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1458
1459 ifp->if_opackets++;
9d4c8d7d 1460 if (td->sis_mbuf != NULL) {
9513d9d2 1461 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
9d4c8d7d
SZ
1462 m_freem(td->sis_mbuf);
1463 td->sis_mbuf = NULL;
984263bc 1464 }
984263bc
MD
1465 }
1466
1467 if (idx != sc->sis_cdata.sis_tx_cons) {
4ddeda6c 1468 /* we freed up some buffers */
984263bc 1469 sc->sis_cdata.sis_tx_cons = idx;
984263bc 1470 }
49eef4c6 1471
9513d9d2
SZ
1472 if (cd->sis_tx_cnt == 0)
1473 ifp->if_timer = 0;
1474 if (!SIS_IS_OACTIVE(sc))
9ed293e0 1475 ifq_clr_oactive(&ifp->if_snd);
984263bc
MD
1476}
1477
49eef4c6
JS
1478static void
1479sis_tick(void *xsc)
984263bc 1480{
3b7f6d2b 1481 struct sis_softc *sc = xsc;
49eef4c6 1482 struct mii_data *mii;
3b7f6d2b 1483 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1484
78195a76 1485 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
1486
1487 mii = device_get_softc(sc->sis_miibus);
1488 mii_tick(mii);
1489
1490 if (!sc->sis_link) {
1491 mii_pollstat(mii);
1492 if (mii->mii_media_status & IFM_ACTIVE &&
1493 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1494 sc->sis_link++;
e25db1f0 1495 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1496 if_devstart(ifp);
984263bc
MD
1497 }
1498
5047f29c 1499 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
78195a76 1500 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1501}
1502
3bcfba15 1503#ifdef IFPOLL_ENABLE
984263bc
MD
1504
1505static void
3bcfba15 1506sis_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
984263bc 1507{
3bcfba15 1508 struct sis_softc *sc = ifp->if_softc;
984263bc 1509
3bcfba15 1510 ASSERT_SERIALIZED(ifp->if_serializer);
984263bc 1511
3bcfba15
SZ
1512 /*
1513 * On the sis, reading the status register also clears it.
1514 * So before returning to intr mode we must make sure that all
1515 * possible pending sources of interrupts have been served.
1516 * In practice this means run to completion the *eof routines,
1517 * and then call the interrupt routine
1518 */
1519 sc->rxcycles = count;
1520 sis_rxeof(sc);
1521 sis_txeof(sc);
1522 if (!ifq_is_empty(&ifp->if_snd))
1523 if_devstart(ifp);
984263bc 1524
3bcfba15
SZ
1525 if (sc->sis_npoll.ifpc_stcount-- == 0) {
1526 uint32_t status;
984263bc 1527
3bcfba15 1528 sc->sis_npoll.ifpc_stcount = sc->sis_npoll.ifpc_stfrac;
984263bc 1529
3bcfba15
SZ
1530 /* Reading the ISR register clears all interrupts. */
1531 status = CSR_READ_4(sc, SIS_ISR);
984263bc 1532
3bcfba15
SZ
1533 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1534 sis_rxeoc(sc);
1535
1536 if (status & (SIS_ISR_RX_IDLE))
1537 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1538
1539 if (status & SIS_ISR_SYSERR) {
1540 sis_reset(sc);
1541 sis_init(sc);
984263bc
MD
1542 }
1543 }
1544}
3bcfba15
SZ
1545
1546static void
1547sis_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1548{
1549 struct sis_softc *sc = ifp->if_softc;
1550
1551 ASSERT_SERIALIZED(ifp->if_serializer);
1552
1553 if (info != NULL) {
1554 int cpuid = sc->sis_npoll.ifpc_cpuid;
1555
1556 info->ifpi_rx[cpuid].poll_func = sis_npoll_compat;
1557 info->ifpi_rx[cpuid].arg = NULL;
1558 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1559
1560 if (ifp->if_flags & IFF_RUNNING) {
1561 /* disable interrupts */
1562 CSR_WRITE_4(sc, SIS_IER, 0);
1563 sc->sis_npoll.ifpc_stcount = 0;
1564 }
1565 ifp->if_npoll_cpuid = cpuid;
1566 } else {
1567 if (ifp->if_flags & IFF_RUNNING) {
1568 /* enable interrupts */
1569 CSR_WRITE_4(sc, SIS_IER, 1);
1570 }
1571 ifp->if_npoll_cpuid = -1;
1572 }
1573}
1574
1575#endif /* IFPOLL_ENABLE */
984263bc 1576
49eef4c6
JS
1577static void
1578sis_intr(void *arg)
984263bc 1579{
49eef4c6
JS
1580 struct sis_softc *sc;
1581 struct ifnet *ifp;
1582 uint32_t status;
984263bc
MD
1583
1584 sc = arg;
1585 ifp = &sc->arpcom.ac_if;
1586
984263bc
MD
1587 /* Supress unwanted interrupts */
1588 if (!(ifp->if_flags & IFF_UP)) {
1589 sis_stop(sc);
1590 return;
1591 }
1592
1593 /* Disable interrupts. */
1594 CSR_WRITE_4(sc, SIS_IER, 0);
1595
1596 for (;;) {
1597 /* Reading the ISR register clears all interrupts. */
1598 status = CSR_READ_4(sc, SIS_ISR);
1599
1600 if ((status & SIS_INTRS) == 0)
1601 break;
1602
1603 if (status &
49eef4c6
JS
1604 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1605 SIS_ISR_TX_IDLE) )
984263bc
MD
1606 sis_txeof(sc);
1607
49eef4c6
JS
1608 if (status &
1609 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
984263bc
MD
1610 sis_rxeof(sc);
1611
49eef4c6 1612 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
984263bc
MD
1613 sis_rxeoc(sc);
1614
1615 if (status & (SIS_ISR_RX_IDLE))
1616 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1617
1618 if (status & SIS_ISR_SYSERR) {
1619 sis_reset(sc);
1620 sis_init(sc);
1621 }
1622 }
1623
1624 /* Re-enable interrupts. */
1625 CSR_WRITE_4(sc, SIS_IER, 1);
1626
e25db1f0 1627 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1628 if_devstart(ifp);
984263bc
MD
1629}
1630
1631/*
1632 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1633 * pointers to the fragment pointers.
1634 */
49eef4c6 1635static int
9513d9d2 1636sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
984263bc 1637{
9513d9d2
SZ
1638 struct sis_chain_data *cd = &sc->sis_cdata;
1639 struct sis_list_data *ld = &sc->sis_ldata;
1640 bus_dma_segment_t segs[SIS_NSEGS];
1641 bus_dmamap_t map;
1642 int frag, cur, maxsegs, nsegs, error, i;
1643
1644 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt;
ed20d0e3 1645 KASSERT(maxsegs >= 1, ("not enough TX descs"));
9513d9d2
SZ
1646 if (maxsegs > SIS_NSEGS)
1647 maxsegs = SIS_NSEGS;
1648
1649 map = cd->sis_tx_data[*txidx].sis_map;
1650 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head,
1651 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1652 if (error) {
1653 m_freem(*m_head);
1654 *m_head = NULL;
1655 return error;
1656 }
1657 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
984263bc 1658
984263bc 1659 cur = frag = *txidx;
9513d9d2
SZ
1660 for (i = 0; i < nsegs; ++i) {
1661 struct sis_desc *f = &ld->sis_tx_list[frag];
984263bc 1662
9513d9d2
SZ
1663 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len;
1664 f->sis_ptr = segs[i].ds_addr;
1665 if (i != 0)
1666 f->sis_ctl |= SIS_CMDSTS_OWN;
9d4c8d7d 1667
9513d9d2
SZ
1668 cur = frag;
1669 SIS_INC(frag, SIS_TX_LIST_CNT);
984263bc 1670 }
9513d9d2
SZ
1671 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1672 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
984263bc 1673
9513d9d2
SZ
1674 /* Swap DMA map */
1675 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map;
1676 cd->sis_tx_data[cur].sis_map = map;
9d4c8d7d 1677
9513d9d2
SZ
1678 cd->sis_tx_data[cur].sis_mbuf = *m_head;
1679
1680 cd->sis_tx_cnt += nsegs;
984263bc
MD
1681 *txidx = frag;
1682
9513d9d2 1683 return 0;
984263bc
MD
1684}
1685
1686/*
1687 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1688 * to the mbuf data regions directly in the transmit lists. We also save a
1689 * copy of the pointers since the transmit list fragment pointers are
1690 * physical addresses.
1691 */
1692
49eef4c6
JS
1693static void
1694sis_start(struct ifnet *ifp)
984263bc 1695{
9513d9d2
SZ
1696 struct sis_softc *sc = ifp->if_softc;
1697 int need_trans, error;
49eef4c6 1698 uint32_t idx;
984263bc 1699
9db4b353
SZ
1700 if (!sc->sis_link) {
1701 ifq_purge(&ifp->if_snd);
984263bc 1702 return;
9db4b353 1703 }
984263bc 1704
9ed293e0 1705 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
984263bc
MD
1706 return;
1707
9513d9d2 1708 idx = sc->sis_cdata.sis_tx_prod;
2f54d1d2 1709 need_trans = 0;
9513d9d2 1710
9d4c8d7d 1711 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) {
9513d9d2 1712 struct mbuf *m_head;
984263bc 1713
9db4b353
SZ
1714 /*
1715 * If there's no way we can send any packets, return now.
1716 */
9513d9d2 1717 if (SIS_IS_OACTIVE(sc)) {
9ed293e0 1718 ifq_set_oactive(&ifp->if_snd);
984263bc
MD
1719 break;
1720 }
9db4b353 1721
9db4b353
SZ
1722 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1723 if (m_head == NULL)
1724 break;
1725
9513d9d2
SZ
1726 error = sis_encap(sc, &m_head, &idx);
1727 if (error) {
1728 ifp->if_oerrors++;
1729 if (sc->sis_cdata.sis_tx_cnt == 0) {
1730 continue;
1731 } else {
9ed293e0 1732 ifq_set_oactive(&ifp->if_snd);
9db4b353
SZ
1733 break;
1734 }
9db4b353 1735 }
2f54d1d2 1736 need_trans = 1;
984263bc
MD
1737
1738 /*
1739 * If there's a BPF listener, bounce a copy of this frame
1740 * to him.
1741 */
49eef4c6 1742 BPF_MTAP(ifp, m_head);
984263bc
MD
1743 }
1744
2f54d1d2
SZ
1745 if (!need_trans)
1746 return;
1747
984263bc
MD
1748 /* Transmit */
1749 sc->sis_cdata.sis_tx_prod = idx;
1750 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1751
1752 /*
1753 * Set a timeout in case the chip goes out to lunch.
1754 */
1755 ifp->if_timer = 5;
984263bc
MD
1756}
1757
49eef4c6
JS
1758static void
1759sis_init(void *xsc)
984263bc 1760{
49eef4c6
JS
1761 struct sis_softc *sc = xsc;
1762 struct ifnet *ifp = &sc->arpcom.ac_if;
1763 struct mii_data *mii;
984263bc 1764
984263bc
MD
1765 /*
1766 * Cancel pending I/O and free all RX/TX buffers.
1767 */
1768 sis_stop(sc);
1769
1770 mii = device_get_softc(sc->sis_miibus);
1771
1772 /* Set MAC address */
1773 if (sc->sis_type == SIS_TYPE_83815) {
1774 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1775 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1776 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1777 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1778 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1779 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1780 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1781 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1782 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1783 } else {
1784 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1785 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1786 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1787 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1788 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1789 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1791 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
49eef4c6 1792 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1793 }
1794
1795 /* Init circular RX list. */
9513d9d2 1796 if (sis_list_rx_init(sc)) {
10c5bfa0
JS
1797 if_printf(ifp, "initialization failed: "
1798 "no memory for rx buffers\n");
984263bc 1799 sis_stop(sc);
984263bc
MD
1800 return;
1801 }
1802
1803 /*
1804 * Init tx descriptors.
1805 */
1806 sis_list_tx_init(sc);
1807
1808 /*
1809 * For the NatSemi chip, we have to explicitly enable the
1810 * reception of ARP frames, as well as turn on the 'perfect
1811 * match' filter where we store the station address, otherwise
1812 * we won't receive unicasts meant for this host.
1813 */
1814 if (sc->sis_type == SIS_TYPE_83815) {
1815 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1817 }
1818
1819 /* If we want promiscuous mode, set the allframes bit. */
49eef4c6 1820 if (ifp->if_flags & IFF_PROMISC)
984263bc 1821 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
49eef4c6 1822 else
984263bc 1823 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
984263bc
MD
1824
1825 /*
1826 * Set the capture broadcast bit to capture broadcast frames.
1827 */
49eef4c6 1828 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1829 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
49eef4c6 1830 else
984263bc 1831 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
984263bc
MD
1832
1833 /*
1834 * Load the multicast filter.
1835 */
1836 if (sc->sis_type == SIS_TYPE_83815)
1837 sis_setmulti_ns(sc);
1838 else
1839 sis_setmulti_sis(sc);
1840
1841 /* Turn the receive filter on */
1842 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1843
1844 /*
1845 * Load the address of the RX and TX lists.
1846 */
9d4c8d7d
SZ
1847 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr);
1848 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr);
984263bc
MD
1849
1850 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1851 * the PCI bus. When this bit is set, the Max DMA Burst Size
1852 * for TX/RX DMA should be no larger than 16 double words.
1853 */
49eef4c6 1854 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
984263bc 1855 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
49eef4c6 1856 else
984263bc 1857 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
984263bc
MD
1858
1859 /* Accept Long Packets for VLAN support */
1860 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1861
1862 /* Set TX configuration */
49eef4c6 1863 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
984263bc 1864 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
49eef4c6 1865 else
984263bc 1866 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
984263bc
MD
1867
1868 /* Set full/half duplex mode. */
1869 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1870 SIS_SETBIT(sc, SIS_TX_CFG,
1871 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1872 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1873 } else {
1874 SIS_CLRBIT(sc, SIS_TX_CFG,
1875 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1876 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1877 }
1878
1879 /*
1880 * Enable interrupts.
1881 */
1882 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
3bcfba15 1883#ifdef IFPOLL_ENABLE
984263bc
MD
1884 /*
1885 * ... only enable interrupts if we are not polling, make sure
1886 * they are off otherwise.
1887 */
3bcfba15 1888 if (ifp->if_flags & IFF_NPOLLING) {
984263bc 1889 CSR_WRITE_4(sc, SIS_IER, 0);
3bcfba15
SZ
1890 sc->sis_npoll.ifpc_stcount = 0;
1891 } else
1892#endif /* IFPOLL_ENABLE */
984263bc
MD
1893 CSR_WRITE_4(sc, SIS_IER, 1);
1894
1895 /* Enable receiver and transmitter. */
1896 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1897 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1898
1899#ifdef notdef
1900 mii_mediachg(mii);
1901#endif
1902
1903 /*
1904 * Page 75 of the DP83815 manual recommends the
1905 * following register settings "for optimum
1906 * performance." Note however that at least three
1907 * of the registers are listed as "reserved" in
1908 * the register map, so who knows what they do.
1909 */
1910 if (sc->sis_type == SIS_TYPE_83815) {
1911 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1912 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1913 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1914 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1915 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1916 }
1917
1918 ifp->if_flags |= IFF_RUNNING;
9ed293e0 1919 ifq_clr_oactive(&ifp->if_snd);
984263bc 1920
5047f29c 1921 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
984263bc
MD
1922}
1923
1924/*
1925 * Set media options.
1926 */
49eef4c6
JS
1927static int
1928sis_ifmedia_upd(struct ifnet *ifp)
984263bc 1929{
49eef4c6
JS
1930 struct sis_softc *sc;
1931 struct mii_data *mii;
984263bc
MD
1932
1933 sc = ifp->if_softc;
1934
1935 mii = device_get_softc(sc->sis_miibus);
1936 sc->sis_link = 0;
1937 if (mii->mii_instance) {
1938 struct mii_softc *miisc;
49eef4c6 1939 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
984263bc
MD
1940 mii_phy_reset(miisc);
1941 }
1942 mii_mediachg(mii);
1943
1944 return(0);
1945}
1946
1947/*
1948 * Report current media status.
1949 */
49eef4c6
JS
1950static void
1951sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1952{
49eef4c6
JS
1953 struct sis_softc *sc;
1954 struct mii_data *mii;
984263bc
MD
1955
1956 sc = ifp->if_softc;
1957
1958 mii = device_get_softc(sc->sis_miibus);
1959 mii_pollstat(mii);
1960 ifmr->ifm_active = mii->mii_media_active;
1961 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1962}
1963
49eef4c6 1964static int
bd4539cc 1965sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1966{
49eef4c6
JS
1967 struct sis_softc *sc = ifp->if_softc;
1968 struct ifreq *ifr = (struct ifreq *) data;
1969 struct mii_data *mii;
3b7f6d2b
JS
1970 int error = 0;
1971
984263bc 1972 switch(command) {
984263bc
MD
1973 case SIOCSIFFLAGS:
1974 if (ifp->if_flags & IFF_UP) {
1975 sis_init(sc);
1976 } else {
1977 if (ifp->if_flags & IFF_RUNNING)
1978 sis_stop(sc);
1979 }
1980 error = 0;
1981 break;
1982 case SIOCADDMULTI:
1983 case SIOCDELMULTI:
1984 if (sc->sis_type == SIS_TYPE_83815)
1985 sis_setmulti_ns(sc);
1986 else
1987 sis_setmulti_sis(sc);
1988 error = 0;
1989 break;
1990 case SIOCGIFMEDIA:
1991 case SIOCSIFMEDIA:
1992 mii = device_get_softc(sc->sis_miibus);
1993 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1994 break;
1995 default:
4ddeda6c 1996 error = ether_ioctl(ifp, command, data);
984263bc
MD
1997 break;
1998 }
984263bc
MD
1999 return(error);
2000}
2001
49eef4c6
JS
2002static void
2003sis_watchdog(struct ifnet *ifp)
984263bc 2004{
49eef4c6 2005 struct sis_softc *sc;
984263bc
MD
2006
2007 sc = ifp->if_softc;
2008
2009 ifp->if_oerrors++;
10c5bfa0 2010 if_printf(ifp, "watchdog timeout\n");
984263bc
MD
2011
2012 sis_stop(sc);
2013 sis_reset(sc);
2014 sis_init(sc);
2015
e25db1f0 2016 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 2017 if_devstart(ifp);
984263bc
MD
2018}
2019
2020/*
2021 * Stop the adapter and free any mbufs allocated to the
2022 * RX and TX lists.
2023 */
49eef4c6
JS
2024static void
2025sis_stop(struct sis_softc *sc)
984263bc 2026{
9513d9d2
SZ
2027 struct ifnet *ifp = &sc->arpcom.ac_if;
2028 struct sis_list_data *ld = &sc->sis_ldata;
2029 struct sis_chain_data *cd = &sc->sis_cdata;
49eef4c6 2030 int i;
984263bc 2031
5047f29c 2032 callout_stop(&sc->sis_timer);
984263bc 2033
9ed293e0
SZ
2034 ifp->if_flags &= ~IFF_RUNNING;
2035 ifq_clr_oactive(&ifp->if_snd);
9513d9d2
SZ
2036 ifp->if_timer = 0;
2037
984263bc
MD
2038 CSR_WRITE_4(sc, SIS_IER, 0);
2039 CSR_WRITE_4(sc, SIS_IMR, 0);
2040 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2041 DELAY(1000);
2042 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2043 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2044
2045 sc->sis_link = 0;
2046
2047 /*
2048 * Free data in the RX lists.
2049 */
2050 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
9513d9d2
SZ
2051 struct sis_rx_data *rd = &cd->sis_rx_data[i];
2052
2053 if (rd->sis_mbuf != NULL) {
2054 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
2055 m_freem(rd->sis_mbuf);
2056 rd->sis_mbuf = NULL;
984263bc
MD
2057 }
2058 }
9513d9d2 2059 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ);
984263bc
MD
2060
2061 /*
2062 * Free the TX list buffers.
2063 */
2064 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
9513d9d2
SZ
2065 struct sis_tx_data *td = &cd->sis_tx_data[i];
2066
2067 if (td->sis_mbuf != NULL) {
2068 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
2069 m_freem(td->sis_mbuf);
2070 td->sis_mbuf = NULL;
984263bc
MD
2071 }
2072 }
9513d9d2 2073 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ);
984263bc
MD
2074}
2075
2076/*
2077 * Stop all chip I/O so that the kernel's probe routines don't
2078 * get confused by errant DMAs when rebooting.
2079 */
49eef4c6
JS
2080static void
2081sis_shutdown(device_t dev)
984263bc
MD
2082{
2083 struct sis_softc *sc;
78195a76 2084 struct ifnet *ifp;
984263bc
MD
2085
2086 sc = device_get_softc(dev);
78195a76
MD
2087 ifp = &sc->arpcom.ac_if;
2088 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
2089 sis_reset(sc);
2090 sis_stop(sc);
78195a76 2091 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2092}
78195a76 2093
9513d9d2
SZ
2094static int
2095sis_dma_alloc(device_t dev)
2096{
2097 struct sis_softc *sc = device_get_softc(dev);
2098 struct sis_chain_data *cd = &sc->sis_cdata;
2099 struct sis_list_data *ld = &sc->sis_ldata;
2100 int i, error;
2101
2102 /* Create top level DMA tag */
2103 error = bus_dma_tag_create(NULL, /* parent */
2104 1, 0, /* alignment, boundary */
2105 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2106 BUS_SPACE_MAXADDR, /* highaddr */
2107 NULL, NULL, /* filter, filterarg */
2108 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2109 0, /* nsegments */
2110 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2111 0, /* flags */
2112 &sc->sis_parent_tag);
2113 if (error) {
2114 device_printf(dev, "could not create parent DMA tag\n");
2115 return error;
2116 }
2117
2118 /* Allocate RX ring */
2119 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2120 SIS_RING_ALIGN, SIS_RX_LIST_SZ,
2121 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2122 &ld->sis_rx_tag, &ld->sis_rx_dmamap,
2123 &ld->sis_rx_paddr);
2124 if (ld->sis_rx_list == NULL) {
2125 device_printf(dev, "could not allocate RX ring\n");
2126 return ENOMEM;
2127 }
2128
2129 /* Allocate TX ring */
2130 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2131 SIS_RING_ALIGN, SIS_TX_LIST_SZ,
2132 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2133 &ld->sis_tx_tag, &ld->sis_tx_dmamap,
2134 &ld->sis_tx_paddr);
2135 if (ld->sis_tx_list == NULL) {
2136 device_printf(dev, "could not allocate TX ring\n");
2137 return ENOMEM;
2138 }
2139
2140 /* Create DMA tag for TX mbuf */
2141 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2142 1, 0, /* alignment, boundary */
2143 BUS_SPACE_MAXADDR, /* lowaddr */
2144 BUS_SPACE_MAXADDR, /* highaddr */
2145 NULL, NULL, /* filter, filterarg */
2146 MCLBYTES, /* maxsize */
2147 SIS_NSEGS, /* nsegments */
2148 MCLBYTES, /* maxsegsize */
2149 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
2150 &cd->sis_txbuf_tag);
2151 if (error) {
2152 device_printf(dev, "could not create TX buf DMA tag\n");
2153 return error;
2154 }
2155
2156 /* Create DMA maps for TX mbufs */
2157 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2158 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK,
2159 &cd->sis_tx_data[i].sis_map);
2160 if (error) {
2161 int j;
2162
2163 for (j = 0; j < i; ++j) {
2164 bus_dmamap_destroy(cd->sis_txbuf_tag,
2165 cd->sis_tx_data[j].sis_map);
2166 }
2167 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2168 cd->sis_txbuf_tag = NULL;
2169
2170 device_printf(dev, "could not create %dth "
2171 "TX buf DMA map\n", i);
2172 return error;
2173 }
2174 }
2175
2176 /* Create DMA tag for RX mbuf */
2177 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2178 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */
2179 BUS_SPACE_MAXADDR, /* lowaddr */
2180 BUS_SPACE_MAXADDR, /* highaddr */
2181 NULL, NULL, /* filter, filterarg */
2182 MCLBYTES, /* maxsize */
2183 1, /* nsegments */
2184 MCLBYTES, /* maxsegsize */
2185 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2186 BUS_DMA_ALIGNED, /* flags */
2187 &cd->sis_rxbuf_tag);
2188 if (error) {
2189 device_printf(dev, "could not create RX buf DMA tag\n");
2190 return error;
2191 }
2192
2193 /* Create tmp DMA map for loading RX mbuf */
2194 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2195 &cd->sis_rx_tmpmap);
2196 if (error) {
2197 device_printf(dev, "could not create RX buf tmp DMA map\n");
2198 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2199 cd->sis_rxbuf_tag = NULL;
2200 return error;
2201 }
2202
2203 /* Create DMA maps for RX mbufs */
2204 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2205 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2206 &cd->sis_rx_data[i].sis_map);
2207 if (error) {
2208 int j;
2209
2210 for (j = 0; j < i; ++j) {
2211 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2212 cd->sis_rx_data[j].sis_map);
2213 }
2214 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2215 cd->sis_rx_tmpmap);
2216 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2217 cd->sis_rxbuf_tag = NULL;
2218
2219 device_printf(dev, "could not create %dth "
2220 "RX buf DMA map\n", i);
2221 return error;
2222 }
2223 }
2224 return 0;
2225}
2226
2227static void
2228sis_dma_free(device_t dev)
2229{
2230 struct sis_softc *sc = device_get_softc(dev);
2231 struct sis_list_data *ld = &sc->sis_ldata;
2232 struct sis_chain_data *cd = &sc->sis_cdata;
2233 int i;
2234
2235 /* Free TX ring */
2236 if (ld->sis_tx_list != NULL) {
2237 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap);
2238 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list,
2239 ld->sis_tx_dmamap);
2240 bus_dma_tag_destroy(ld->sis_tx_tag);
2241 }
2242
2243 /* Free RX ring */
2244 if (ld->sis_rx_list != NULL) {
2245 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap);
2246 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list,
2247 ld->sis_rx_dmamap);
2248 bus_dma_tag_destroy(ld->sis_rx_tag);
2249 }
2250
2251 /* Destroy DMA stuffs for TX mbufs */
2252 if (cd->sis_txbuf_tag != NULL) {
2253 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2254 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL);
2255 bus_dmamap_destroy(cd->sis_txbuf_tag,
2256 cd->sis_tx_data[i].sis_map);
2257 }
2258 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2259 }
2260
2261 /* Destroy DMA stuffs for RX mbufs */
2262 if (cd->sis_rxbuf_tag != NULL) {
2263 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2264 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL);
2265 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2266 cd->sis_rx_data[i].sis_map);
2267 }
2268 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap);
2269 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2270 }
2271}