emx: Pass emx_rxdata to RX related functions
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
e6cde6e6 68#include "opt_emx.h"
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69
70#include <sys/param.h>
71#include <sys/bus.h>
72#include <sys/endian.h>
73#include <sys/interrupt.h>
74#include <sys/kernel.h>
75#include <sys/ktr.h>
76#include <sys/malloc.h>
77#include <sys/mbuf.h>
78#include <sys/proc.h>
79#include <sys/rman.h>
80#include <sys/serialize.h>
bc197380 81#include <sys/serialize2.h>
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82#include <sys/socket.h>
83#include <sys/sockio.h>
84#include <sys/sysctl.h>
85#include <sys/systm.h>
86
87#include <net/bpf.h>
88#include <net/ethernet.h>
89#include <net/if.h>
90#include <net/if_arp.h>
91#include <net/if_dl.h>
92#include <net/if_media.h>
93#include <net/ifq_var.h>
89d8e73d 94#include <net/toeplitz.h>
9cc86e17 95#include <net/toeplitz2.h>
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96#include <net/vlan/if_vlan_var.h>
97#include <net/vlan/if_vlan_ether.h>
b3a7093f 98#include <net/if_poll.h>
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99
100#include <netinet/in_systm.h>
101#include <netinet/in.h>
102#include <netinet/ip.h>
103#include <netinet/tcp.h>
104#include <netinet/udp.h>
105
106#include <bus/pci/pcivar.h>
107#include <bus/pci/pcireg.h>
108
109#include <dev/netif/ig_hal/e1000_api.h>
110#include <dev/netif/ig_hal/e1000_82571.h>
111#include <dev/netif/emx/if_emx.h>
112
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113#ifdef EMX_RSS_DEBUG
114#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
115do { \
89d8e73d 116 if (sc->rss_debug >= lvl) \
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117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
118} while (0)
119#else /* !EMX_RSS_DEBUG */
120#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121#endif /* EMX_RSS_DEBUG */
122
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123#define EMX_TX_SERIALIZE 1
124#define EMX_RX_SERIALIZE 2
125
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126#define EMX_NAME "Intel(R) PRO/1000 "
127
128#define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130#define EMX_DEVICE_NULL { 0, 0, NULL }
131
132static const struct emx_device {
133 uint16_t vid;
134 uint16_t did;
135 const char *desc;
136} emx_devices[] = {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
147
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
151 EMX_DEVICE(82572EI),
152
153 EMX_DEVICE(82573E),
154 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(82573L),
156
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
161
162 EMX_DEVICE(82574L),
2d0e5700 163 EMX_DEVICE(82574LA),
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164
165 /* required last entry */
166 EMX_DEVICE_NULL
167};
168
169static int emx_probe(device_t);
170static int emx_attach(device_t);
171static int emx_detach(device_t);
172static int emx_shutdown(device_t);
173static int emx_suspend(device_t);
174static int emx_resume(device_t);
175
176static void emx_init(void *);
177static void emx_stop(struct emx_softc *);
178static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179static void emx_start(struct ifnet *);
b3a7093f 180#ifdef IFPOLL_ENABLE
f994de37 181static void emx_npoll(struct ifnet *, struct ifpoll_info *);
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182static void emx_npoll_status(struct ifnet *);
183static void emx_npoll_tx(struct ifnet *, void *, int);
184static void emx_npoll_rx(struct ifnet *, void *, int);
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185#endif
186static void emx_watchdog(struct ifnet *);
187static void emx_media_status(struct ifnet *, struct ifmediareq *);
188static int emx_media_change(struct ifnet *);
189static void emx_timer(void *);
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190static void emx_serialize(struct ifnet *, enum ifnet_serialize);
191static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
192static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
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193#ifdef INVARIANTS
194static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
195 boolean_t);
196#endif
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197
198static void emx_intr(void *);
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199static void emx_intr_mask(void *);
200static void emx_intr_body(struct emx_softc *, boolean_t);
9f831fa8 201static void emx_rxeof(struct emx_rxdata *, int);
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202static void emx_txeof(struct emx_softc *);
203static void emx_tx_collect(struct emx_softc *);
204static void emx_tx_purge(struct emx_softc *);
205static void emx_enable_intr(struct emx_softc *);
206static void emx_disable_intr(struct emx_softc *);
207
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208static int emx_dma_alloc(struct emx_softc *);
209static void emx_dma_free(struct emx_softc *);
5330213c 210static void emx_init_tx_ring(struct emx_softc *);
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211static int emx_init_rx_ring(struct emx_rxdata *);
212static void emx_free_rx_ring(struct emx_rxdata *);
5330213c 213static int emx_create_tx_ring(struct emx_softc *);
9f831fa8 214static int emx_create_rx_ring(struct emx_rxdata *);
5330213c 215static void emx_destroy_tx_ring(struct emx_softc *, int);
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216static void emx_destroy_rx_ring(struct emx_rxdata *, int);
217static int emx_newbuf(struct emx_rxdata *, int, int);
5330213c 218static int emx_encap(struct emx_softc *, struct mbuf **);
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219static int emx_txcsum(struct emx_softc *, struct mbuf *,
220 uint32_t *, uint32_t *);
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221static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
222static int emx_tso_setup(struct emx_softc *, struct mbuf *,
223 uint32_t *, uint32_t *);
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224
225static int emx_is_valid_eaddr(const uint8_t *);
2d0e5700 226static int emx_reset(struct emx_softc *);
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227static void emx_setup_ifp(struct emx_softc *);
228static void emx_init_tx_unit(struct emx_softc *);
229static void emx_init_rx_unit(struct emx_softc *);
230static void emx_update_stats(struct emx_softc *);
231static void emx_set_promisc(struct emx_softc *);
232static void emx_disable_promisc(struct emx_softc *);
233static void emx_set_multi(struct emx_softc *);
234static void emx_update_link_status(struct emx_softc *);
235static void emx_smartspeed(struct emx_softc *);
2d0e5700 236static void emx_set_itr(struct emx_softc *, uint32_t);
6d5e2922 237static void emx_disable_aspm(struct emx_softc *);
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238
239static void emx_print_debug_info(struct emx_softc *);
240static void emx_print_nvm_info(struct emx_softc *);
241static void emx_print_hw_stats(struct emx_softc *);
242
243static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
244static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
245static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
246static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
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247#ifdef IFPOLL_ENABLE
248static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
249static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
250#endif
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251static void emx_add_sysctl(struct emx_softc *);
252
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253static void emx_serialize_skipmain(struct emx_softc *);
254static void emx_deserialize_skipmain(struct emx_softc *);
255
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256/* Management and WOL Support */
257static void emx_get_mgmt(struct emx_softc *);
258static void emx_rel_mgmt(struct emx_softc *);
259static void emx_get_hw_control(struct emx_softc *);
260static void emx_rel_hw_control(struct emx_softc *);
261static void emx_enable_wol(device_t);
262
263static device_method_t emx_methods[] = {
264 /* Device interface */
265 DEVMETHOD(device_probe, emx_probe),
266 DEVMETHOD(device_attach, emx_attach),
267 DEVMETHOD(device_detach, emx_detach),
268 DEVMETHOD(device_shutdown, emx_shutdown),
269 DEVMETHOD(device_suspend, emx_suspend),
270 DEVMETHOD(device_resume, emx_resume),
271 { 0, 0 }
272};
273
274static driver_t emx_driver = {
275 "emx",
276 emx_methods,
277 sizeof(struct emx_softc),
278};
279
280static devclass_t emx_devclass;
281
282DECLARE_DUMMY_MODULE(if_emx);
283MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
aa2b9d05 284DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
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285
286/*
287 * Tunables
288 */
289static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
290static int emx_rxd = EMX_DEFAULT_RXD;
291static int emx_txd = EMX_DEFAULT_TXD;
704b6287 292static int emx_smart_pwr_down = 0;
724cbff8 293static int emx_rxr = 0;
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294
295/* Controls whether promiscuous also shows bad packets */
b4d8c36b 296static int emx_debug_sbp = 0;
5330213c 297
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298static int emx_82573_workaround = 1;
299static int emx_msi_enable = 1;
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300
301TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
302TUNABLE_INT("hw.emx.rxd", &emx_rxd);
724cbff8 303TUNABLE_INT("hw.emx.rxr", &emx_rxr);
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304TUNABLE_INT("hw.emx.txd", &emx_txd);
305TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
306TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
307TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
704b6287 308TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
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309
310/* Global used in WOL setup with multiport cards */
311static int emx_global_quad_port_a = 0;
312
313/* Set this to one to display debug statistics */
314static int emx_display_debug_stats = 0;
315
316#if !defined(KTR_IF_EMX)
317#define KTR_IF_EMX KTR_ALL
318#endif
319KTR_INFO_MASTER(if_emx);
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320KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
321KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
322KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
323KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
324KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
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325#define logif(name) KTR_LOG(if_emx_ ## name)
326
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327static __inline void
328emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
329{
330 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 331 /* DD bit must be cleared */
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332 rxd->rxd_staterr = 0;
333}
334
335static __inline void
336emx_rxcsum(uint32_t staterr, struct mbuf *mp)
337{
338 /* Ignore Checksum bit is set */
339 if (staterr & E1000_RXD_STAT_IXSM)
340 return;
341
342 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
343 E1000_RXD_STAT_IPCS)
344 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
345
346 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
347 E1000_RXD_STAT_TCPCS) {
348 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
349 CSUM_PSEUDO_HDR |
350 CSUM_FRAG_NOT_CHECKED;
351 mp->m_pkthdr.csum_data = htons(0xffff);
352 }
353}
354
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355static __inline struct pktinfo *
356emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
357 uint32_t mrq, uint32_t hash, uint32_t staterr)
358{
359 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
360 case EMX_RXDMRQ_IPV4_TCP:
361 pi->pi_netisr = NETISR_IP;
362 pi->pi_flags = 0;
363 pi->pi_l3proto = IPPROTO_TCP;
364 break;
365
366 case EMX_RXDMRQ_IPV6_TCP:
367 pi->pi_netisr = NETISR_IPV6;
368 pi->pi_flags = 0;
369 pi->pi_l3proto = IPPROTO_TCP;
370 break;
371
372 case EMX_RXDMRQ_IPV4:
373 if (staterr & E1000_RXD_STAT_IXSM)
374 return NULL;
375
376 if ((staterr &
377 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
378 E1000_RXD_STAT_TCPCS) {
379 pi->pi_netisr = NETISR_IP;
380 pi->pi_flags = 0;
381 pi->pi_l3proto = IPPROTO_UDP;
382 break;
383 }
384 /* FALL THROUGH */
385 default:
386 return NULL;
387 }
388
389 m->m_flags |= M_HASH;
390 m->m_pkthdr.hash = toeplitz_hash(hash);
391 return pi;
392}
393
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394static int
395emx_probe(device_t dev)
396{
397 const struct emx_device *d;
398 uint16_t vid, did;
399
400 vid = pci_get_vendor(dev);
401 did = pci_get_device(dev);
402
403 for (d = emx_devices; d->desc != NULL; ++d) {
404 if (vid == d->vid && did == d->did) {
405 device_set_desc(dev, d->desc);
406 device_set_async_attach(dev, TRUE);
407 return 0;
408 }
409 }
410 return ENXIO;
411}
412
413static int
414emx_attach(device_t dev)
415{
416 struct emx_softc *sc = device_get_softc(dev);
417 struct ifnet *ifp = &sc->arpcom.ac_if;
d01335e8 418 int error = 0, i, throttle, msi_enable;
704b6287 419 u_int intr_flags;
2d0e5700 420 uint16_t eeprom_data, device_id, apme_mask;
4cb541ae 421 driver_intr_t *intr_func;
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422#ifdef IFPOLL_ENABLE
423 int offset, offset_def;
424#endif
5330213c 425
167d2eae 426 /*
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427 * Setup RX rings
428 */
429 for (i = 0; i < EMX_NRX_RING; ++i) {
430 sc->rx_data[i].sc = sc;
431 sc->rx_data[i].idx = i;
432 }
433
434 /*
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435 * Initialize serializers
436 */
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437 lwkt_serialize_init(&sc->main_serialize);
438 lwkt_serialize_init(&sc->tx_serialize);
439 for (i = 0; i < EMX_NRX_RING; ++i)
440 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
441
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442 /*
443 * Initialize serializer array
444 */
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445 i = 0;
446 sc->serializes[i++] = &sc->main_serialize;
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447
448 KKASSERT(i == EMX_TX_SERIALIZE);
6d435846 449 sc->serializes[i++] = &sc->tx_serialize;
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450
451 KKASSERT(i == EMX_RX_SERIALIZE);
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452 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
453 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
454 KKASSERT(i == EMX_NSERIALIZE);
455
c2022416 456 callout_init_mp(&sc->timer);
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457
458 sc->dev = sc->osdep.dev = dev;
459
460 /*
461 * Determine hardware and mac type
462 */
463 sc->hw.vendor_id = pci_get_vendor(dev);
464 sc->hw.device_id = pci_get_device(dev);
465 sc->hw.revision_id = pci_get_revid(dev);
466 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
467 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
468
469 if (e1000_set_mac_type(&sc->hw))
470 return ENXIO;
471
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472 /*
473 * Pullup extra 4bytes into the first data segment, see:
474 * 82571/82572 specification update errata #7
475 *
476 * NOTE:
477 * 4bytes instead of 2bytes, which are mentioned in the errata,
478 * are pulled; mainly to keep rest of the data properly aligned.
479 */
480 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
481 sc->flags |= EMX_FLAG_TSO_PULLEX;
482
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483 /* Enable bus mastering */
484 pci_enable_busmaster(dev);
485
486 /*
487 * Allocate IO memory
488 */
489 sc->memory_rid = EMX_BAR_MEM;
490 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
491 &sc->memory_rid, RF_ACTIVE);
492 if (sc->memory == NULL) {
493 device_printf(dev, "Unable to allocate bus resource: memory\n");
494 error = ENXIO;
495 goto fail;
496 }
497 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
498 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
499
500 /* XXX This is quite goofy, it is not actually used */
501 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
502
503 /*
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504 * Don't enable MSI-X on 82574, see:
505 * 82574 specification update errata #15
506 *
d01335e8 507 * Don't enable MSI on 82571/82572, see:
a835687d 508 * 82571/82572 specification update errata #63
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509 */
510 msi_enable = emx_msi_enable;
511 if (msi_enable &&
512 (sc->hw.mac.type == e1000_82571 ||
513 sc->hw.mac.type == e1000_82572))
514 msi_enable = 0;
515
516 /*
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517 * Allocate interrupt
518 */
d01335e8 519 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
7fb43956 520 &sc->intr_rid, &intr_flags);
704b6287 521
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522 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
523 int unshared;
524
525 unshared = device_getenv_int(dev, "irq.unshared", 0);
526 if (!unshared) {
527 sc->flags |= EMX_FLAG_SHARED_INTR;
528 if (bootverbose)
529 device_printf(dev, "IRQ shared\n");
530 } else {
531 intr_flags &= ~RF_SHAREABLE;
532 if (bootverbose)
533 device_printf(dev, "IRQ unshared\n");
534 }
535 }
536
5330213c 537 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
704b6287 538 intr_flags);
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539 if (sc->intr_res == NULL) {
540 device_printf(dev, "Unable to allocate bus resource: "
541 "interrupt\n");
542 error = ENXIO;
543 goto fail;
544 }
545
546 /* Save PCI command register for Shared Code */
547 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
548 sc->hw.back = &sc->osdep;
549
550 /* Do Shared Code initialization */
551 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
552 device_printf(dev, "Setup of Shared code failed\n");
553 error = ENXIO;
554 goto fail;
555 }
556 e1000_get_bus_info(&sc->hw);
557
5330213c
SZ
558 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
559 sc->hw.phy.autoneg_wait_to_complete = FALSE;
560 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
5330213c
SZ
561
562 /*
563 * Interrupt throttle rate
564 */
b4d8c36b
SZ
565 throttle = device_getenv_int(dev, "int_throttle_ceil",
566 emx_int_throttle_ceil);
567 if (throttle == 0) {
5330213c
SZ
568 sc->int_throttle_ceil = 0;
569 } else {
5330213c
SZ
570 if (throttle < 0)
571 throttle = EMX_DEFAULT_ITR;
572
573 /* Recalculate the tunable value to get the exact frequency. */
574 throttle = 1000000000 / 256 / throttle;
575
576 /* Upper 16bits of ITR is reserved and should be zero */
577 if (throttle & 0xffff0000)
578 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
579
580 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
581 }
582
583 e1000_init_script_state_82541(&sc->hw, TRUE);
584 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
585
586 /* Copper options */
587 if (sc->hw.phy.media_type == e1000_media_type_copper) {
588 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
589 sc->hw.phy.disable_polarity_correction = FALSE;
590 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
591 }
592
593 /* Set the frame limits assuming standard ethernet sized frames. */
594 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
595 sc->min_frame_size = ETHER_MIN_LEN;
596
597 /* This controls when hardware reports transmit completion status. */
598 sc->hw.mac.report_tx_early = 1;
599
65c7a6af 600 /* Calculate # of RX rings */
724cbff8 601 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
a317449e 602 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
65c7a6af 603
071699f8
SZ
604 /* Allocate RX/TX rings' busdma(9) stuffs */
605 error = emx_dma_alloc(sc);
606 if (error)
e5b3bcc4 607 goto fail;
e5b3bcc4 608
2d0e5700
SZ
609 /* Allocate multicast array memory. */
610 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
611 M_DEVBUF, M_WAITOK);
612
613 /* Indicate SOL/IDER usage */
614 if (e1000_check_reset_block(&sc->hw)) {
615 device_printf(dev,
616 "PHY reset is blocked due to SOL/IDER session.\n");
617 }
618
619 /*
620 * Start from a known state, this is important in reading the
621 * nvm and mac from that.
622 */
623 e1000_reset_hw(&sc->hw);
624
5330213c
SZ
625 /* Make sure we have a good EEPROM before we read from it */
626 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
627 /*
628 * Some PCI-E parts fail the first check due to
629 * the link being in sleep state, call it again,
630 * if it fails a second time its a real issue.
631 */
632 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
633 device_printf(dev,
634 "The EEPROM Checksum Is Not Valid\n");
635 error = EIO;
636 goto fail;
637 }
638 }
639
5330213c
SZ
640 /* Copy the permanent MAC address out of the EEPROM */
641 if (e1000_read_mac_addr(&sc->hw) < 0) {
642 device_printf(dev, "EEPROM read error while reading MAC"
643 " address\n");
644 error = EIO;
645 goto fail;
646 }
647 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
648 device_printf(dev, "Invalid MAC address\n");
649 error = EIO;
650 goto fail;
651 }
652
5330213c 653 /* Determine if we have to control management hardware */
de0836d4
SZ
654 if (e1000_enable_mng_pass_thru(&sc->hw))
655 sc->flags |= EMX_FLAG_HAS_MGMT;
5330213c
SZ
656
657 /*
658 * Setup Wake-on-Lan
659 */
2d0e5700
SZ
660 apme_mask = EMX_EEPROM_APME;
661 eeprom_data = 0;
5330213c 662 switch (sc->hw.mac.type) {
2d0e5700 663 case e1000_82573:
de0836d4 664 sc->flags |= EMX_FLAG_HAS_AMT;
2d0e5700
SZ
665 /* FALL THROUGH */
666
5330213c 667 case e1000_82571:
2d0e5700 668 case e1000_82572:
5330213c
SZ
669 case e1000_80003es2lan:
670 if (sc->hw.bus.func == 1) {
671 e1000_read_nvm(&sc->hw,
672 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
673 } else {
674 e1000_read_nvm(&sc->hw,
675 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
676 }
5330213c
SZ
677 break;
678
679 default:
2d0e5700
SZ
680 e1000_read_nvm(&sc->hw,
681 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
5330213c
SZ
682 break;
683 }
2d0e5700
SZ
684 if (eeprom_data & apme_mask)
685 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
686
5330213c
SZ
687 /*
688 * We have the eeprom settings, now apply the special cases
689 * where the eeprom may be wrong or the board won't support
690 * wake on lan on a particular port
691 */
692 device_id = pci_get_device(dev);
693 switch (device_id) {
694 case E1000_DEV_ID_82571EB_FIBER:
695 /*
696 * Wake events only supported on port A for dual fiber
697 * regardless of eeprom setting
698 */
699 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
700 E1000_STATUS_FUNC_1)
701 sc->wol = 0;
702 break;
703
704 case E1000_DEV_ID_82571EB_QUAD_COPPER:
705 case E1000_DEV_ID_82571EB_QUAD_FIBER:
706 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
707 /* if quad port sc, disable WoL on all but port A */
708 if (emx_global_quad_port_a != 0)
709 sc->wol = 0;
710 /* Reset for multiple quad port adapters */
711 if (++emx_global_quad_port_a == 4)
712 emx_global_quad_port_a = 0;
713 break;
714 }
715
716 /* XXX disable wol */
717 sc->wol = 0;
718
09f49d52
SZ
719#ifdef IFPOLL_ENABLE
720 /*
721 * NPOLLING RX CPU offset
722 */
723 if (sc->rx_ring_cnt == ncpus2) {
724 offset = 0;
725 } else {
726 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
727 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
728 if (offset >= ncpus2 ||
729 offset % sc->rx_ring_cnt != 0) {
730 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
731 offset, offset_def);
732 offset = offset_def;
733 }
734 }
735 sc->rx_npoll_off = offset;
736
737 /*
738 * NPOLLING TX CPU offset
739 */
740 offset_def = sc->rx_npoll_off;
741 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
742 if (offset >= ncpus2) {
743 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
744 offset, offset_def);
745 offset = offset_def;
746 }
747 sc->tx_npoll_off = offset;
748#endif
749
2d0e5700
SZ
750 /* Setup OS specific network interface */
751 emx_setup_ifp(sc);
752
753 /* Add sysctl tree, must after em_setup_ifp() */
754 emx_add_sysctl(sc);
755
756 /* Reset the hardware */
757 error = emx_reset(sc);
758 if (error) {
759 device_printf(dev, "Unable to reset the hardware\n");
760 goto fail;
761 }
762
763 /* Initialize statistics */
764 emx_update_stats(sc);
765
766 sc->hw.mac.get_link_status = 1;
767 emx_update_link_status(sc);
768
5330213c
SZ
769 sc->spare_tx_desc = EMX_TX_SPARE;
770
771 /*
772 * Keep following relationship between spare_tx_desc, oact_tx_desc
773 * and tx_int_nsegs:
774 * (spare_tx_desc + EMX_TX_RESERVED) <=
775 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
776 */
777 sc->oact_tx_desc = sc->num_tx_desc / 8;
778 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
779 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
780 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
781 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
782
783 sc->tx_int_nsegs = sc->num_tx_desc / 16;
784 if (sc->tx_int_nsegs < sc->oact_tx_desc)
785 sc->tx_int_nsegs = sc->oact_tx_desc;
786
2d0e5700 787 /* Non-AMT based hardware can now take control from firmware */
de0836d4
SZ
788 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
789 EMX_FLAG_HAS_MGMT)
2d0e5700
SZ
790 emx_get_hw_control(sc);
791
4cb541ae
SZ
792 /*
793 * Missing Interrupt Following ICR read:
794 *
a835687d
SZ
795 * 82571/82572 specification update errata #76
796 * 82573 specification update errata #31
797 * 82574 specification update errata #12
4cb541ae
SZ
798 */
799 intr_func = emx_intr;
800 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
801 (sc->hw.mac.type == e1000_82571 ||
802 sc->hw.mac.type == e1000_82572 ||
803 sc->hw.mac.type == e1000_82573 ||
804 sc->hw.mac.type == e1000_82574))
805 intr_func = emx_intr_mask;
806
807 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
6d435846 808 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ
809 if (error) {
810 device_printf(dev, "Failed to register interrupt handler");
811 ether_ifdetach(&sc->arpcom.ac_if);
812 goto fail;
813 }
814
704b6287 815 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
5330213c
SZ
816 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
817 return (0);
818fail:
819 emx_detach(dev);
820 return (error);
821}
822
823static int
824emx_detach(device_t dev)
825{
826 struct emx_softc *sc = device_get_softc(dev);
827
828 if (device_is_attached(dev)) {
829 struct ifnet *ifp = &sc->arpcom.ac_if;
830
6d435846 831 ifnet_serialize_all(ifp);
5330213c
SZ
832
833 emx_stop(sc);
834
835 e1000_phy_hw_reset(&sc->hw);
836
837 emx_rel_mgmt(sc);
2d0e5700 838 emx_rel_hw_control(sc);
5330213c
SZ
839
840 if (sc->wol) {
841 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
842 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
843 emx_enable_wol(dev);
844 }
845
846 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
847
6d435846 848 ifnet_deserialize_all(ifp);
5330213c
SZ
849
850 ether_ifdetach(ifp);
a19a8754 851 } else if (sc->memory != NULL) {
2d0e5700 852 emx_rel_hw_control(sc);
5330213c
SZ
853 }
854 bus_generic_detach(dev);
855
856 if (sc->intr_res != NULL) {
857 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
858 sc->intr_res);
859 }
860
7fb43956 861 if (sc->intr_type == PCI_INTR_TYPE_MSI)
704b6287
SZ
862 pci_release_msi(dev);
863
5330213c
SZ
864 if (sc->memory != NULL) {
865 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
866 sc->memory);
867 }
868
071699f8 869 emx_dma_free(sc);
5330213c
SZ
870
871 /* Free sysctl tree */
872 if (sc->sysctl_tree != NULL)
873 sysctl_ctx_free(&sc->sysctl_ctx);
874
a19a8754
SZ
875 if (sc->mta != NULL)
876 kfree(sc->mta, M_DEVBUF);
877
5330213c
SZ
878 return (0);
879}
880
881static int
882emx_shutdown(device_t dev)
883{
884 return emx_suspend(dev);
885}
886
887static int
888emx_suspend(device_t dev)
889{
890 struct emx_softc *sc = device_get_softc(dev);
891 struct ifnet *ifp = &sc->arpcom.ac_if;
892
6d435846 893 ifnet_serialize_all(ifp);
5330213c
SZ
894
895 emx_stop(sc);
896
897 emx_rel_mgmt(sc);
2d0e5700 898 emx_rel_hw_control(sc);
5330213c 899
2d0e5700 900 if (sc->wol) {
5330213c
SZ
901 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
902 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
903 emx_enable_wol(dev);
2d0e5700 904 }
5330213c 905
6d435846 906 ifnet_deserialize_all(ifp);
5330213c
SZ
907
908 return bus_generic_suspend(dev);
909}
910
911static int
912emx_resume(device_t dev)
913{
914 struct emx_softc *sc = device_get_softc(dev);
915 struct ifnet *ifp = &sc->arpcom.ac_if;
916
6d435846 917 ifnet_serialize_all(ifp);
5330213c
SZ
918
919 emx_init(sc);
920 emx_get_mgmt(sc);
921 if_devstart(ifp);
922
6d435846 923 ifnet_deserialize_all(ifp);
5330213c
SZ
924
925 return bus_generic_resume(dev);
926}
927
928static void
929emx_start(struct ifnet *ifp)
930{
931 struct emx_softc *sc = ifp->if_softc;
932 struct mbuf *m_head;
933
6d435846 934 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ
935
936 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
937 return;
938
939 if (!sc->link_active) {
940 ifq_purge(&ifp->if_snd);
941 return;
942 }
943
944 while (!ifq_is_empty(&ifp->if_snd)) {
945 /* Now do we at least have a minimal? */
946 if (EMX_IS_OACTIVE(sc)) {
947 emx_tx_collect(sc);
948 if (EMX_IS_OACTIVE(sc)) {
949 ifp->if_flags |= IFF_OACTIVE;
5330213c
SZ
950 break;
951 }
952 }
953
954 logif(pkt_txqueue);
955 m_head = ifq_dequeue(&ifp->if_snd, NULL);
956 if (m_head == NULL)
957 break;
958
959 if (emx_encap(sc, &m_head)) {
960 ifp->if_oerrors++;
961 emx_tx_collect(sc);
962 continue;
963 }
964
965 /* Send a copy of the frame to the BPF listener */
966 ETHER_BPF_MTAP(ifp, m_head);
967
968 /* Set timeout in case hardware has problems transmitting. */
969 ifp->if_timer = EMX_TX_TIMEOUT;
970 }
971}
972
973static int
974emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
975{
976 struct emx_softc *sc = ifp->if_softc;
977 struct ifreq *ifr = (struct ifreq *)data;
978 uint16_t eeprom_data = 0;
979 int max_frame_size, mask, reinit;
980 int error = 0;
981
2c9effcf 982 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
983
984 switch (command) {
985 case SIOCSIFMTU:
986 switch (sc->hw.mac.type) {
987 case e1000_82573:
988 /*
989 * 82573 only supports jumbo frames
990 * if ASPM is disabled.
991 */
992 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
993 &eeprom_data);
994 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
995 max_frame_size = ETHER_MAX_LEN;
996 break;
997 }
998 /* FALL THROUGH */
999
1000 /* Limit Jumbo Frame size */
1001 case e1000_82571:
1002 case e1000_82572:
1003 case e1000_82574:
1004 case e1000_80003es2lan:
1005 max_frame_size = 9234;
1006 break;
1007
1008 default:
1009 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1010 break;
1011 }
1012 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1013 ETHER_CRC_LEN) {
1014 error = EINVAL;
1015 break;
1016 }
1017
1018 ifp->if_mtu = ifr->ifr_mtu;
1019 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1020 ETHER_CRC_LEN;
1021
1022 if (ifp->if_flags & IFF_RUNNING)
1023 emx_init(sc);
1024 break;
1025
1026 case SIOCSIFFLAGS:
1027 if (ifp->if_flags & IFF_UP) {
1028 if ((ifp->if_flags & IFF_RUNNING)) {
1029 if ((ifp->if_flags ^ sc->if_flags) &
1030 (IFF_PROMISC | IFF_ALLMULTI)) {
1031 emx_disable_promisc(sc);
1032 emx_set_promisc(sc);
1033 }
1034 } else {
1035 emx_init(sc);
1036 }
1037 } else if (ifp->if_flags & IFF_RUNNING) {
1038 emx_stop(sc);
1039 }
1040 sc->if_flags = ifp->if_flags;
1041 break;
1042
1043 case SIOCADDMULTI:
1044 case SIOCDELMULTI:
1045 if (ifp->if_flags & IFF_RUNNING) {
1046 emx_disable_intr(sc);
1047 emx_set_multi(sc);
b3a7093f
SZ
1048#ifdef IFPOLL_ENABLE
1049 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ
1050#endif
1051 emx_enable_intr(sc);
1052 }
1053 break;
1054
1055 case SIOCSIFMEDIA:
1056 /* Check SOL/IDER usage */
1057 if (e1000_check_reset_block(&sc->hw)) {
1058 device_printf(sc->dev, "Media change is"
1059 " blocked due to SOL/IDER session.\n");
1060 break;
1061 }
1062 /* FALL THROUGH */
1063
1064 case SIOCGIFMEDIA:
1065 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1066 break;
1067
1068 case SIOCSIFCAP:
1069 reinit = 0;
1070 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3eb0ea09
SZ
1071 if (mask & IFCAP_RXCSUM) {
1072 ifp->if_capenable ^= IFCAP_RXCSUM;
5330213c
SZ
1073 reinit = 1;
1074 }
1075 if (mask & IFCAP_VLAN_HWTAGGING) {
1076 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1077 reinit = 1;
1078 }
3eb0ea09
SZ
1079 if (mask & IFCAP_TXCSUM) {
1080 ifp->if_capenable ^= IFCAP_TXCSUM;
1081 if (ifp->if_capenable & IFCAP_TXCSUM)
1082 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1083 else
1084 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1085 }
1086 if (mask & IFCAP_TSO) {
1087 ifp->if_capenable ^= IFCAP_TSO;
1088 if (ifp->if_capenable & IFCAP_TSO)
1089 ifp->if_hwassist |= CSUM_TSO;
1090 else
1091 ifp->if_hwassist &= ~CSUM_TSO;
1092 }
13890b61 1093 if (mask & IFCAP_RSS)
8434a83b 1094 ifp->if_capenable ^= IFCAP_RSS;
5330213c
SZ
1095 if (reinit && (ifp->if_flags & IFF_RUNNING))
1096 emx_init(sc);
1097 break;
1098
1099 default:
1100 error = ether_ioctl(ifp, command, data);
1101 break;
1102 }
1103 return (error);
1104}
1105
1106static void
1107emx_watchdog(struct ifnet *ifp)
1108{
1109 struct emx_softc *sc = ifp->if_softc;
1110
2c9effcf 1111 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1112
1113 /*
1114 * The timer is set to 5 every time start queues a packet.
1115 * Then txeof keeps resetting it as long as it cleans at
1116 * least one descriptor.
1117 * Finally, anytime all descriptors are clean the timer is
1118 * set to 0.
1119 */
1120
1121 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1122 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1123 /*
1124 * If we reach here, all TX jobs are completed and
1125 * the TX engine should have been idled for some time.
1126 * We don't need to call if_devstart() here.
1127 */
1128 ifp->if_flags &= ~IFF_OACTIVE;
1129 ifp->if_timer = 0;
1130 return;
1131 }
1132
1133 /*
1134 * If we are in this routine because of pause frames, then
1135 * don't reset the hardware.
1136 */
1137 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1138 ifp->if_timer = EMX_TX_TIMEOUT;
1139 return;
1140 }
1141
1142 if (e1000_check_for_link(&sc->hw) == 0)
1143 if_printf(ifp, "watchdog timeout -- resetting\n");
1144
1145 ifp->if_oerrors++;
5330213c
SZ
1146
1147 emx_init(sc);
1148
1149 if (!ifq_is_empty(&ifp->if_snd))
1150 if_devstart(ifp);
1151}
1152
1153static void
1154emx_init(void *xsc)
1155{
1156 struct emx_softc *sc = xsc;
1157 struct ifnet *ifp = &sc->arpcom.ac_if;
1158 device_t dev = sc->dev;
1159 uint32_t pba;
3f939c23 1160 int i;
5330213c 1161
2c9effcf 1162 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1163
1164 emx_stop(sc);
1165
1166 /*
1167 * Packet Buffer Allocation (PBA)
1168 * Writing PBA sets the receive portion of the buffer
1169 * the remainder is used for the transmit buffer.
1170 */
1171 switch (sc->hw.mac.type) {
1172 /* Total Packet Buffer on these is 48K */
1173 case e1000_82571:
1174 case e1000_82572:
1175 case e1000_80003es2lan:
1176 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1177 break;
1178
1179 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1180 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1181 break;
1182
1183 case e1000_82574:
1184 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1185 break;
1186
1187 default:
1188 /* Devices before 82547 had a Packet Buffer of 64K. */
1189 if (sc->max_frame_size > 8192)
1190 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1191 else
1192 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1193 }
1194 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1195
1196 /* Get the latest mac address, User can use a LAA */
1197 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1198
1199 /* Put the address into the Receive Address Array */
1200 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1201
1202 /*
1203 * With the 82571 sc, RAR[0] may be overwritten
1204 * when the other port is reset, we make a duplicate
1205 * in RAR[14] for that eventuality, this assures
1206 * the interface continues to function.
1207 */
1208 if (sc->hw.mac.type == e1000_82571) {
1209 e1000_set_laa_state_82571(&sc->hw, TRUE);
1210 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1211 E1000_RAR_ENTRIES - 1);
1212 }
1213
1214 /* Initialize the hardware */
2d0e5700
SZ
1215 if (emx_reset(sc)) {
1216 device_printf(dev, "Unable to reset the hardware\n");
5330213c
SZ
1217 /* XXX emx_stop()? */
1218 return;
1219 }
1220 emx_update_link_status(sc);
1221
1222 /* Setup VLAN support, basic and offload if available */
1223 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1224
1225 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1226 uint32_t ctrl;
1227
1228 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1229 ctrl |= E1000_CTRL_VME;
1230 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1231 }
1232
5330213c
SZ
1233 /* Configure for OS presence */
1234 emx_get_mgmt(sc);
1235
1236 /* Prepare transmit descriptors and buffers */
1237 emx_init_tx_ring(sc);
1238 emx_init_tx_unit(sc);
1239
1240 /* Setup Multicast table */
1241 emx_set_multi(sc);
1242
1243 /* Prepare receive descriptors and buffers */
13890b61 1244 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9f831fa8 1245 if (emx_init_rx_ring(&sc->rx_data[i])) {
3f939c23
SZ
1246 device_printf(dev,
1247 "Could not setup receive structures\n");
1248 emx_stop(sc);
1249 return;
1250 }
5330213c
SZ
1251 }
1252 emx_init_rx_unit(sc);
1253
1254 /* Don't lose promiscuous settings */
1255 emx_set_promisc(sc);
1256
1257 ifp->if_flags |= IFF_RUNNING;
1258 ifp->if_flags &= ~IFF_OACTIVE;
1259
1260 callout_reset(&sc->timer, hz, emx_timer, sc);
1261 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1262
1263 /* MSI/X configuration for 82574 */
1264 if (sc->hw.mac.type == e1000_82574) {
1265 int tmp;
1266
1267 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1268 tmp |= E1000_CTRL_EXT_PBA_CLR;
1269 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1270 /*
2d0e5700 1271 * XXX MSIX
5330213c
SZ
1272 * Set the IVAR - interrupt vector routing.
1273 * Each nibble represents a vector, high bit
1274 * is enable, other 3 bits are the MSIX table
1275 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1276 * Link (other) to 2, hence the magic number.
1277 */
1278 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1279 }
1280
b3a7093f 1281#ifdef IFPOLL_ENABLE
5330213c
SZ
1282 /*
1283 * Only enable interrupts if we are not polling, make sure
1284 * they are off otherwise.
1285 */
b3a7093f 1286 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ
1287 emx_disable_intr(sc);
1288 else
b3a7093f 1289#endif /* IFPOLL_ENABLE */
5330213c
SZ
1290 emx_enable_intr(sc);
1291
2d0e5700 1292 /* AMT based hardware can now take control from firmware */
de0836d4
SZ
1293 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1294 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
2d0e5700
SZ
1295 emx_get_hw_control(sc);
1296
5330213c
SZ
1297 /* Don't reset the phy next time init gets called */
1298 sc->hw.phy.reset_disable = TRUE;
1299}
1300
5330213c
SZ
1301static void
1302emx_intr(void *xsc)
1303{
4cb541ae
SZ
1304 emx_intr_body(xsc, TRUE);
1305}
1306
1307static void
1308emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1309{
5330213c
SZ
1310 struct ifnet *ifp = &sc->arpcom.ac_if;
1311 uint32_t reg_icr;
1312
1313 logif(intr_beg);
6d435846 1314 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ
1315
1316 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1317
4cb541ae 1318 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
5330213c
SZ
1319 logif(intr_end);
1320 return;
1321 }
1322
1323 /*
1324 * XXX: some laptops trigger several spurious interrupts
df50f778 1325 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ
1326 * reports all-ones value in this case. Processing such
1327 * interrupts would lead to a freeze. I don't know why.
1328 */
1329 if (reg_icr == 0xffffffff) {
1330 logif(intr_end);
1331 return;
1332 }
1333
1334 if (ifp->if_flags & IFF_RUNNING) {
1335 if (reg_icr &
3f939c23
SZ
1336 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1337 int i;
1338
13890b61 1339 for (i = 0; i < sc->rx_ring_cnt; ++i) {
6d435846
SZ
1340 lwkt_serialize_enter(
1341 &sc->rx_data[i].rx_serialize);
9f831fa8 1342 emx_rxeof(&sc->rx_data[i], -1);
6d435846
SZ
1343 lwkt_serialize_exit(
1344 &sc->rx_data[i].rx_serialize);
1345 }
3f939c23 1346 }
6446af7b 1347 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1348 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ
1349 emx_txeof(sc);
1350 if (!ifq_is_empty(&ifp->if_snd))
1351 if_devstart(ifp);
6d435846 1352 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ
1353 }
1354 }
1355
1356 /* Link status change */
1357 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1358 emx_serialize_skipmain(sc);
6d435846 1359
5330213c
SZ
1360 callout_stop(&sc->timer);
1361 sc->hw.mac.get_link_status = 1;
1362 emx_update_link_status(sc);
1363
1364 /* Deal with TX cruft when link lost */
1365 emx_tx_purge(sc);
1366
1367 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1368
bca7c435 1369 emx_deserialize_skipmain(sc);
5330213c
SZ
1370 }
1371
1372 if (reg_icr & E1000_ICR_RXO)
1373 sc->rx_overruns++;
1374
1375 logif(intr_end);
1376}
1377
1378static void
4cb541ae
SZ
1379emx_intr_mask(void *xsc)
1380{
1381 struct emx_softc *sc = xsc;
1382
1383 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1384 /*
1385 * NOTE:
1386 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1387 * so don't check it.
1388 */
1389 emx_intr_body(sc, FALSE);
1390 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1391}
1392
1393static void
5330213c
SZ
1394emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1395{
1396 struct emx_softc *sc = ifp->if_softc;
1397
2c9effcf 1398 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1399
1400 emx_update_link_status(sc);
1401
1402 ifmr->ifm_status = IFM_AVALID;
1403 ifmr->ifm_active = IFM_ETHER;
1404
1405 if (!sc->link_active)
1406 return;
1407
1408 ifmr->ifm_status |= IFM_ACTIVE;
1409
1410 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1411 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1412 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1413 } else {
1414 switch (sc->link_speed) {
1415 case 10:
1416 ifmr->ifm_active |= IFM_10_T;
1417 break;
1418 case 100:
1419 ifmr->ifm_active |= IFM_100_TX;
1420 break;
1421
1422 case 1000:
1423 ifmr->ifm_active |= IFM_1000_T;
1424 break;
1425 }
1426 if (sc->link_duplex == FULL_DUPLEX)
1427 ifmr->ifm_active |= IFM_FDX;
1428 else
1429 ifmr->ifm_active |= IFM_HDX;
1430 }
1431}
1432
1433static int
1434emx_media_change(struct ifnet *ifp)
1435{
1436 struct emx_softc *sc = ifp->if_softc;
1437 struct ifmedia *ifm = &sc->media;
1438
2c9effcf 1439 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1440
1441 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1442 return (EINVAL);
1443
1444 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1445 case IFM_AUTO:
1446 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1447 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1448 break;
1449
1450 case IFM_1000_LX:
1451 case IFM_1000_SX:
1452 case IFM_1000_T:
1453 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1454 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1455 break;
1456
1457 case IFM_100_TX:
1458 sc->hw.mac.autoneg = FALSE;
1459 sc->hw.phy.autoneg_advertised = 0;
1460 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1461 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1462 else
1463 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1464 break;
1465
1466 case IFM_10_T:
1467 sc->hw.mac.autoneg = FALSE;
1468 sc->hw.phy.autoneg_advertised = 0;
1469 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1470 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1471 else
1472 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1473 break;
1474
1475 default:
1476 if_printf(ifp, "Unsupported media type\n");
1477 break;
1478 }
1479
1480 /*
1481 * As the speed/duplex settings my have changed we need to
1482 * reset the PHY.
1483 */
1484 sc->hw.phy.reset_disable = FALSE;
1485
1486 emx_init(sc);
1487
1488 return (0);
1489}
1490
1491static int
1492emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1493{
1494 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1495 bus_dmamap_t map;
323e5ecd 1496 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ
1497 struct e1000_tx_desc *ctxd = NULL;
1498 struct mbuf *m_head = *m_headp;
1499 uint32_t txd_upper, txd_lower, cmd = 0;
1500 int maxsegs, nsegs, i, j, first, last = 0, error;
1501
3eb0ea09
SZ
1502 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1503 error = emx_tso_pullup(sc, m_headp);
1504 if (error)
1505 return error;
1506 m_head = *m_headp;
1507 }
1508
5330213c
SZ
1509 txd_upper = txd_lower = 0;
1510
1511 /*
1512 * Capture the first descriptor index, this descriptor
1513 * will have the index of the EOP which is the only one
1514 * that now gets a DONE bit writeback.
1515 */
1516 first = sc->next_avail_tx_desc;
323e5ecd 1517 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
1518 tx_buffer_mapped = tx_buffer;
1519 map = tx_buffer->map;
1520
1521 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
ed20d0e3 1522 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
5330213c
SZ
1523 if (maxsegs > EMX_MAX_SCATTER)
1524 maxsegs = EMX_MAX_SCATTER;
1525
1526 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1527 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1528 if (error) {
5330213c
SZ
1529 m_freem(*m_headp);
1530 *m_headp = NULL;
1531 return error;
1532 }
1533 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1534
1535 m_head = *m_headp;
1536 sc->tx_nsegs += nsegs;
1537
3eb0ea09
SZ
1538 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1539 /* TSO will consume one TX desc */
1540 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1541 &txd_upper, &txd_lower);
1542 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
5330213c
SZ
1543 /* TX csum offloading will consume one TX desc */
1544 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1545 }
1546 i = sc->next_avail_tx_desc;
1547
1548 /* Set up our transmit descriptors */
1549 for (j = 0; j < nsegs; j++) {
323e5ecd 1550 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1551 ctxd = &sc->tx_desc_base[i];
1552
1553 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1554 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1555 txd_lower | segs[j].ds_len);
1556 ctxd->upper.data = htole32(txd_upper);
1557
1558 last = i;
1559 if (++i == sc->num_tx_desc)
1560 i = 0;
5330213c
SZ
1561 }
1562
1563 sc->next_avail_tx_desc = i;
1564
1565 KKASSERT(sc->num_tx_desc_avail > nsegs);
1566 sc->num_tx_desc_avail -= nsegs;
1567
1568 /* Handle VLAN tag */
1569 if (m_head->m_flags & M_VLANTAG) {
1570 /* Set the vlan id. */
1571 ctxd->upper.fields.special =
1572 htole16(m_head->m_pkthdr.ether_vlantag);
1573
1574 /* Tell hardware to add tag */
1575 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1576 }
1577
1578 tx_buffer->m_head = m_head;
1579 tx_buffer_mapped->map = tx_buffer->map;
1580 tx_buffer->map = map;
1581
1582 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1583 sc->tx_nsegs = 0;
4e4e8481
SZ
1584
1585 /*
1586 * Report Status (RS) is turned on
1587 * every tx_int_nsegs descriptors.
1588 */
5330213c
SZ
1589 cmd = E1000_TXD_CMD_RS;
1590
b4b0a2b4
SZ
1591 /*
1592 * Keep track of the descriptor, which will
1593 * be written back by hardware.
1594 */
5330213c
SZ
1595 sc->tx_dd[sc->tx_dd_tail] = last;
1596 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1597 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1598 }
1599
1600 /*
1601 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ
1602 */
1603 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1604
1605 /*
5330213c
SZ
1606 * Advance the Transmit Descriptor Tail (TDT), this tells
1607 * the E1000 that this frame is available to transmit.
1608 */
1609 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1610
1611 return (0);
1612}
1613
1614static void
1615emx_set_promisc(struct emx_softc *sc)
1616{
1617 struct ifnet *ifp = &sc->arpcom.ac_if;
1618 uint32_t reg_rctl;
1619
1620 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1621
1622 if (ifp->if_flags & IFF_PROMISC) {
1623 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1624 /* Turn this on if you want to see bad packets */
1625 if (emx_debug_sbp)
1626 reg_rctl |= E1000_RCTL_SBP;
1627 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1628 } else if (ifp->if_flags & IFF_ALLMULTI) {
1629 reg_rctl |= E1000_RCTL_MPE;
1630 reg_rctl &= ~E1000_RCTL_UPE;
1631 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1632 }
1633}
1634
1635static void
1636emx_disable_promisc(struct emx_softc *sc)
1637{
1638 uint32_t reg_rctl;
1639
1640 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1641
1642 reg_rctl &= ~E1000_RCTL_UPE;
1643 reg_rctl &= ~E1000_RCTL_MPE;
1644 reg_rctl &= ~E1000_RCTL_SBP;
1645 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1646}
1647
1648static void
1649emx_set_multi(struct emx_softc *sc)
1650{
1651 struct ifnet *ifp = &sc->arpcom.ac_if;
1652 struct ifmultiaddr *ifma;
1653 uint32_t reg_rctl = 0;
2d0e5700 1654 uint8_t *mta;
5330213c
SZ
1655 int mcnt = 0;
1656
2d0e5700
SZ
1657 mta = sc->mta;
1658 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1659
441d34b2 1660 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ
1661 if (ifma->ifma_addr->sa_family != AF_LINK)
1662 continue;
1663
1664 if (mcnt == EMX_MCAST_ADDR_MAX)
1665 break;
1666
1667 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1668 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1669 mcnt++;
1670 }
1671
1672 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1673 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1674 reg_rctl |= E1000_RCTL_MPE;
1675 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1676 } else {
6a5a645e 1677 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
5330213c
SZ
1678 }
1679}
1680
1681/*
1682 * This routine checks for link status and updates statistics.
1683 */
1684static void
1685emx_timer(void *xsc)
1686{
1687 struct emx_softc *sc = xsc;
1688 struct ifnet *ifp = &sc->arpcom.ac_if;
1689
37e854ff 1690 lwkt_serialize_enter(&sc->main_serialize);
5330213c
SZ
1691
1692 emx_update_link_status(sc);
1693 emx_update_stats(sc);
1694
1695 /* Reset LAA into RAR[0] on 82571 */
1696 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1697 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1698
1699 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1700 emx_print_hw_stats(sc);
1701
1702 emx_smartspeed(sc);
1703
1704 callout_reset(&sc->timer, hz, emx_timer, sc);
1705
37e854ff 1706 lwkt_serialize_exit(&sc->main_serialize);
5330213c
SZ
1707}
1708
1709static void
1710emx_update_link_status(struct emx_softc *sc)
1711{
1712 struct e1000_hw *hw = &sc->hw;
1713 struct ifnet *ifp = &sc->arpcom.ac_if;
1714 device_t dev = sc->dev;
1715 uint32_t link_check = 0;
1716
1717 /* Get the cached link value or read phy for real */
1718 switch (hw->phy.media_type) {
1719 case e1000_media_type_copper:
1720 if (hw->mac.get_link_status) {
1721 /* Do the work to read phy */
1722 e1000_check_for_link(hw);
1723 link_check = !hw->mac.get_link_status;
1724 if (link_check) /* ESB2 fix */
1725 e1000_cfg_on_link_up(hw);
1726 } else {
1727 link_check = TRUE;
1728 }
1729 break;
1730
1731 case e1000_media_type_fiber:
1732 e1000_check_for_link(hw);
1733 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1734 break;
1735
1736 case e1000_media_type_internal_serdes:
1737 e1000_check_for_link(hw);
1738 link_check = sc->hw.mac.serdes_has_link;
1739 break;
1740
1741 case e1000_media_type_unknown:
1742 default:
1743 break;
1744 }
1745
1746 /* Now check for a transition */
1747 if (link_check && sc->link_active == 0) {
1748 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1749 &sc->link_duplex);
1750
1751 /*
1752 * Check if we should enable/disable SPEED_MODE bit on
1753 * 82571EB/82572EI
1754 */
2d0e5700
SZ
1755 if (sc->link_speed != SPEED_1000 &&
1756 (hw->mac.type == e1000_82571 ||
1757 hw->mac.type == e1000_82572)) {
5330213c
SZ
1758 int tarc0;
1759
1760 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 1761 tarc0 &= ~EMX_TARC_SPEED_MODE;
5330213c
SZ
1762 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1763 }
1764 if (bootverbose) {
1765 device_printf(dev, "Link is up %d Mbps %s\n",
1766 sc->link_speed,
1767 ((sc->link_duplex == FULL_DUPLEX) ?
1768 "Full Duplex" : "Half Duplex"));
1769 }
1770 sc->link_active = 1;
1771 sc->smartspeed = 0;
1772 ifp->if_baudrate = sc->link_speed * 1000000;
1773 ifp->if_link_state = LINK_STATE_UP;
1774 if_link_state_change(ifp);
1775 } else if (!link_check && sc->link_active == 1) {
1776 ifp->if_baudrate = sc->link_speed = 0;
1777 sc->link_duplex = 0;
1778 if (bootverbose)
1779 device_printf(dev, "Link is Down\n");
1780 sc->link_active = 0;
1781#if 0
1782 /* Link down, disable watchdog */
1783 if->if_timer = 0;
1784#endif
1785 ifp->if_link_state = LINK_STATE_DOWN;
1786 if_link_state_change(ifp);
1787 }
1788}
1789
1790static void
1791emx_stop(struct emx_softc *sc)
1792{
1793 struct ifnet *ifp = &sc->arpcom.ac_if;
1794 int i;
1795
2c9effcf 1796 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1797
1798 emx_disable_intr(sc);
1799
1800 callout_stop(&sc->timer);
1801
1802 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1803 ifp->if_timer = 0;
1804
3f939c23
SZ
1805 /*
1806 * Disable multiple receive queues.
1807 *
1808 * NOTE:
1809 * We should disable multiple receive queues before
1810 * resetting the hardware.
1811 */
1812 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1813
5330213c
SZ
1814 e1000_reset_hw(&sc->hw);
1815 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1816
1817 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1818 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1819
1820 if (tx_buffer->m_head != NULL) {
1821 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1822 m_freem(tx_buffer->m_head);
1823 tx_buffer->m_head = NULL;
1824 }
1825 }
1826
13890b61 1827 for (i = 0; i < sc->rx_ring_cnt; ++i)
9f831fa8 1828 emx_free_rx_ring(&sc->rx_data[i]);
5330213c
SZ
1829
1830 sc->csum_flags = 0;
3eb0ea09 1831 sc->csum_lhlen = 0;
5330213c 1832 sc->csum_iphlen = 0;
3eb0ea09
SZ
1833 sc->csum_thlen = 0;
1834 sc->csum_mss = 0;
1835 sc->csum_pktlen = 0;
5330213c
SZ
1836
1837 sc->tx_dd_head = 0;
1838 sc->tx_dd_tail = 0;
1839 sc->tx_nsegs = 0;
1840}
1841
1842static int
2d0e5700 1843emx_reset(struct emx_softc *sc)
5330213c
SZ
1844{
1845 device_t dev = sc->dev;
1846 uint16_t rx_buffer_size;
1847
5330213c
SZ
1848 /* Set up smart power down as default off on newer adapters. */
1849 if (!emx_smart_pwr_down &&
1850 (sc->hw.mac.type == e1000_82571 ||
1851 sc->hw.mac.type == e1000_82572)) {
1852 uint16_t phy_tmp = 0;
1853
1854 /* Speed up time to link by disabling smart power down. */
1855 e1000_read_phy_reg(&sc->hw,
1856 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1857 phy_tmp &= ~IGP02E1000_PM_SPD;
1858 e1000_write_phy_reg(&sc->hw,
1859 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1860 }
1861
1862 /*
1863 * These parameters control the automatic generation (Tx) and
1864 * response (Rx) to Ethernet PAUSE frames.
1865 * - High water mark should allow for at least two frames to be
1866 * received after sending an XOFF.
1867 * - Low water mark works best when it is very near the high water mark.
1868 * This allows the receiver to restart by sending XON when it has
1869 * drained a bit. Here we use an arbitary value of 1500 which will
1870 * restart after one full frame is pulled from the buffer. There
1871 * could be several smaller frames in the buffer and if so they will
1872 * not trigger the XON until their total number reduces the buffer
1873 * by 1500.
1874 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1875 */
1876 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1877
1878 sc->hw.fc.high_water = rx_buffer_size -
1879 roundup2(sc->max_frame_size, 1024);
1880 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1881
1882 if (sc->hw.mac.type == e1000_80003es2lan)
1883 sc->hw.fc.pause_time = 0xFFFF;
1884 else
1885 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1886 sc->hw.fc.send_xon = TRUE;
1887 sc->hw.fc.requested_mode = e1000_fc_full;
1888
2d0e5700
SZ
1889 /* Issue a global reset */
1890 e1000_reset_hw(&sc->hw);
1891 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
6d5e2922 1892 emx_disable_aspm(sc);
2d0e5700 1893
5330213c
SZ
1894 if (e1000_init_hw(&sc->hw) < 0) {
1895 device_printf(dev, "Hardware Initialization Failed\n");
1896 return (EIO);
1897 }
1898
2d0e5700
SZ
1899 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1900 e1000_get_phy_info(&sc->hw);
5330213c
SZ
1901 e1000_check_for_link(&sc->hw);
1902
1903 return (0);
1904}
1905
1906static void
1907emx_setup_ifp(struct emx_softc *sc)
1908{
1909 struct ifnet *ifp = &sc->arpcom.ac_if;
1910
1911 if_initname(ifp, device_get_name(sc->dev),
1912 device_get_unit(sc->dev));
1913 ifp->if_softc = sc;
1914 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1915 ifp->if_init = emx_init;
1916 ifp->if_ioctl = emx_ioctl;
1917 ifp->if_start = emx_start;
b3a7093f 1918#ifdef IFPOLL_ENABLE
f994de37 1919 ifp->if_npoll = emx_npoll;
5330213c
SZ
1920#endif
1921 ifp->if_watchdog = emx_watchdog;
6d435846
SZ
1922 ifp->if_serialize = emx_serialize;
1923 ifp->if_deserialize = emx_deserialize;
1924 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ
1925#ifdef INVARIANTS
1926 ifp->if_serialize_assert = emx_serialize_assert;
1927#endif
5330213c
SZ
1928 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1929 ifq_set_ready(&ifp->if_snd);
1930
ae474cfa 1931 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ
1932
1933 ifp->if_capabilities = IFCAP_HWCSUM |
1934 IFCAP_VLAN_HWTAGGING |
3eb0ea09
SZ
1935 IFCAP_VLAN_MTU |
1936 IFCAP_TSO;
8434a83b
SZ
1937 if (sc->rx_ring_cnt > 1)
1938 ifp->if_capabilities |= IFCAP_RSS;
5330213c 1939 ifp->if_capenable = ifp->if_capabilities;
3eb0ea09 1940 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
5330213c
SZ
1941
1942 /*
1943 * Tell the upper layer(s) we support long frames.
1944 */
1945 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1946
1947 /*
1948 * Specify the media types supported by this sc and register
1949 * callbacks to update media and link information
1950 */
1951 ifmedia_init(&sc->media, IFM_IMASK,
1952 emx_media_change, emx_media_status);
1953 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1954 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1955 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1956 0, NULL);
1957 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1958 } else {
1959 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1960 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1961 0, NULL);
1962 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1963 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1964 0, NULL);
1965 if (sc->hw.phy.type != e1000_phy_ife) {
1966 ifmedia_add(&sc->media,
1967 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1968 ifmedia_add(&sc->media,
1969 IFM_ETHER | IFM_1000_T, 0, NULL);
1970 }
1971 }
1972 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1973 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1974}
1975
1976/*
1977 * Workaround for SmartSpeed on 82541 and 82547 controllers
1978 */
1979static void
1980emx_smartspeed(struct emx_softc *sc)
1981{
1982 uint16_t phy_tmp;
1983
1984 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1985 sc->hw.mac.autoneg == 0 ||
1986 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1987 return;
1988
1989 if (sc->smartspeed == 0) {
1990 /*
1991 * If Master/Slave config fault is asserted twice,
1992 * we assume back-to-back
1993 */
1994 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1995 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1996 return;
1997 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1998 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1999 e1000_read_phy_reg(&sc->hw,
2000 PHY_1000T_CTRL, &phy_tmp);
2001 if (phy_tmp & CR_1000T_MS_ENABLE) {
2002 phy_tmp &= ~CR_1000T_MS_ENABLE;
2003 e1000_write_phy_reg(&sc->hw,
2004 PHY_1000T_CTRL, phy_tmp);
2005 sc->smartspeed++;
2006 if (sc->hw.mac.autoneg &&
2007 !e1000_phy_setup_autoneg(&sc->hw) &&
2008 !e1000_read_phy_reg(&sc->hw,
2009 PHY_CONTROL, &phy_tmp)) {
2010 phy_tmp |= MII_CR_AUTO_NEG_EN |
2011 MII_CR_RESTART_AUTO_NEG;
2012 e1000_write_phy_reg(&sc->hw,
2013 PHY_CONTROL, phy_tmp);
2014 }
2015 }
2016 }
2017 return;
2018 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2019 /* If still no link, perhaps using 2/3 pair cable */
2020 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2021 phy_tmp |= CR_1000T_MS_ENABLE;
2022 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2023 if (sc->hw.mac.autoneg &&
2024 !e1000_phy_setup_autoneg(&sc->hw) &&
2025 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2026 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2027 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2028 }
2029 }
2030
2031 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2032 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2033 sc->smartspeed = 0;
2034}
2035
2036static int
5330213c
SZ
2037emx_create_tx_ring(struct emx_softc *sc)
2038{
2039 device_t dev = sc->dev;
323e5ecd 2040 struct emx_txbuf *tx_buffer;
b4d8c36b 2041 int error, i, tsize, ntxd;
bdca134f
SZ
2042
2043 /*
2044 * Validate number of transmit descriptors. It must not exceed
2045 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2046 */
b4d8c36b
SZ
2047 ntxd = device_getenv_int(dev, "txd", emx_txd);
2048 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2049 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
bdca134f 2050 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
b4d8c36b 2051 EMX_DEFAULT_TXD, ntxd);
bdca134f
SZ
2052 sc->num_tx_desc = EMX_DEFAULT_TXD;
2053 } else {
b4d8c36b 2054 sc->num_tx_desc = ntxd;
bdca134f
SZ
2055 }
2056
2057 /*
2058 * Allocate Transmit Descriptor ring
2059 */
2060 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2061 EMX_DBA_ALIGN);
a596084c
SZ
2062 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2063 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2064 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2065 &sc->tx_desc_paddr);
2066 if (sc->tx_desc_base == NULL) {
bdca134f 2067 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 2068 return ENOMEM;
bdca134f 2069 }
5330213c 2070
323e5ecd
SZ
2071 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2072 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2073
2074 /*
2075 * Create DMA tags for tx buffers
2076 */
2077 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2078 1, 0, /* alignment, bounds */
2079 BUS_SPACE_MAXADDR, /* lowaddr */
2080 BUS_SPACE_MAXADDR, /* highaddr */
2081 NULL, NULL, /* filter, filterarg */
2082 EMX_TSO_SIZE, /* maxsize */
2083 EMX_MAX_SCATTER, /* nsegments */
2084 EMX_MAX_SEGSIZE, /* maxsegsize */
2085 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2086 BUS_DMA_ONEBPAGE, /* flags */
2087 &sc->txtag);
2088 if (error) {
2089 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ
2090 kfree(sc->tx_buf, M_DEVBUF);
2091 sc->tx_buf = NULL;
5330213c
SZ
2092 return error;
2093 }
2094
2095 /*
2096 * Create DMA maps for tx buffers
2097 */
2098 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 2099 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2100
2101 error = bus_dmamap_create(sc->txtag,
2102 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2103 &tx_buffer->map);
2104 if (error) {
2105 device_printf(dev, "Unable to create TX DMA map\n");
2106 emx_destroy_tx_ring(sc, i);
2107 return error;
2108 }
2109 }
2110 return (0);
2111}
2112
2113static void
2114emx_init_tx_ring(struct emx_softc *sc)
2115{
2116 /* Clear the old ring contents */
2117 bzero(sc->tx_desc_base,
2118 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2119
2120 /* Reset state */
2121 sc->next_avail_tx_desc = 0;
2122 sc->next_tx_to_clean = 0;
2123 sc->num_tx_desc_avail = sc->num_tx_desc;
2124}
2125
2126static void
2127emx_init_tx_unit(struct emx_softc *sc)
2128{
2129 uint32_t tctl, tarc, tipg = 0;
2130 uint64_t bus_addr;
2131
2132 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 2133 bus_addr = sc->tx_desc_paddr;
5330213c
SZ
2134 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2135 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2136 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2137 (uint32_t)(bus_addr >> 32));
2138 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2139 (uint32_t)bus_addr);
2140 /* Setup the HW Tx Head and Tail descriptor pointers */
2141 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2142 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2143
2144 /* Set the default values for the Tx Inter Packet Gap timer */
2145 switch (sc->hw.mac.type) {
2146 case e1000_80003es2lan:
2147 tipg = DEFAULT_82543_TIPG_IPGR1;
2148 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2149 E1000_TIPG_IPGR2_SHIFT;
2150 break;
2151
2152 default:
2153 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2154 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2155 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2156 else
2157 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2158 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2159 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2160 break;
2161 }
2162
2163 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2164
2165 /* NOTE: 0 is not allowed for TIDV */
2166 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2167 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2168
2169 if (sc->hw.mac.type == e1000_82571 ||
2170 sc->hw.mac.type == e1000_82572) {
2171 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2172 tarc |= EMX_TARC_SPEED_MODE;
2173 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2174 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2175 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2176 tarc |= 1;
2177 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2178 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2179 tarc |= 1;
2180 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2181 }
2182
2183 /* Program the Transmit Control Register */
2184 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2185 tctl &= ~E1000_TCTL_CT;
2186 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2187 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2188 tctl |= E1000_TCTL_MULR;
2189
2190 /* This write will effectively turn on the transmit unit. */
2191 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2192}
2193
2194static void
2195emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2196{
323e5ecd 2197 struct emx_txbuf *tx_buffer;
5330213c
SZ
2198 int i;
2199
bdca134f 2200 /* Free Transmit Descriptor ring */
a596084c
SZ
2201 if (sc->tx_desc_base) {
2202 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2203 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2204 sc->tx_desc_dmap);
2205 bus_dma_tag_destroy(sc->tx_desc_dtag);
2206
2207 sc->tx_desc_base = NULL;
2208 }
bdca134f 2209
323e5ecd 2210 if (sc->tx_buf == NULL)
5330213c
SZ
2211 return;
2212
2213 for (i = 0; i < ndesc; i++) {
323e5ecd 2214 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2215
2216 KKASSERT(tx_buffer->m_head == NULL);
2217 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2218 }
2219 bus_dma_tag_destroy(sc->txtag);
2220
323e5ecd
SZ
2221 kfree(sc->tx_buf, M_DEVBUF);
2222 sc->tx_buf = NULL;
5330213c
SZ
2223}
2224
2225/*
2226 * The offload context needs to be set when we transfer the first
2227 * packet of a particular protocol (TCP/UDP). This routine has been
2228 * enhanced to deal with inserted VLAN headers.
2229 *
2230 * If the new packet's ether header length, ip header length and
2231 * csum offloading type are same as the previous packet, we should
2232 * avoid allocating a new csum context descriptor; mainly to take
2233 * advantage of the pipeline effect of the TX data read request.
2234 *
2235 * This function returns number of TX descrptors allocated for
2236 * csum context.
2237 */
2238static int
2239emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2240 uint32_t *txd_upper, uint32_t *txd_lower)
2241{
2242 struct e1000_context_desc *TXD;
5330213c
SZ
2243 int curr_txd, ehdrlen, csum_flags;
2244 uint32_t cmd, hdr_len, ip_hlen;
5330213c
SZ
2245
2246 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
68447568
SZ
2247 ip_hlen = mp->m_pkthdr.csum_iphlen;
2248 ehdrlen = mp->m_pkthdr.csum_lhlen;
5330213c 2249
3eb0ea09 2250 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
5330213c
SZ
2251 sc->csum_flags == csum_flags) {
2252 /*
2253 * Same csum offload context as the previous packets;
2254 * just return.
2255 */
2256 *txd_upper = sc->csum_txd_upper;
2257 *txd_lower = sc->csum_txd_lower;
2258 return 0;
2259 }
2260
2261 /*
2262 * Setup a new csum offload context.
2263 */
2264
2265 curr_txd = sc->next_avail_tx_desc;
5330213c
SZ
2266 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2267
2268 cmd = 0;
2269
2270 /* Setup of IP header checksum. */
2271 if (csum_flags & CSUM_IP) {
2272 /*
2273 * Start offset for header checksum calculation.
2274 * End offset for header checksum calculation.
2275 * Offset of place to put the checksum.
2276 */
2277 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2278 TXD->lower_setup.ip_fields.ipcse =
2279 htole16(ehdrlen + ip_hlen - 1);
2280 TXD->lower_setup.ip_fields.ipcso =
2281 ehdrlen + offsetof(struct ip, ip_sum);
2282 cmd |= E1000_TXD_CMD_IP;
2283 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2284 }
2285 hdr_len = ehdrlen + ip_hlen;
2286
2287 if (csum_flags & CSUM_TCP) {
2288 /*
2289 * Start offset for payload checksum calculation.
2290 * End offset for payload checksum calculation.
2291 * Offset of place to put the checksum.
2292 */
2293 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2294 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2295 TXD->upper_setup.tcp_fields.tucso =
2296 hdr_len + offsetof(struct tcphdr, th_sum);
2297 cmd |= E1000_TXD_CMD_TCP;
2298 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2299 } else if (csum_flags & CSUM_UDP) {
2300 /*
2301 * Start offset for header checksum calculation.
2302 * End offset for header checksum calculation.
2303 * Offset of place to put the checksum.
2304 */
2305 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2306 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2307 TXD->upper_setup.tcp_fields.tucso =
2308 hdr_len + offsetof(struct udphdr, uh_sum);
2309 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2310 }
2311
2312 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2313 E1000_TXD_DTYP_D; /* Data descr */
2314
2315 /* Save the information for this csum offloading context */
3eb0ea09 2316 sc->csum_lhlen = ehdrlen;
5330213c
SZ
2317 sc->csum_iphlen = ip_hlen;
2318 sc->csum_flags = csum_flags;
2319 sc->csum_txd_upper = *txd_upper;
2320 sc->csum_txd_lower = *txd_lower;
2321
2322 TXD->tcp_seg_setup.data = htole32(0);
2323 TXD->cmd_and_length =
2324 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ
2325
2326 if (++curr_txd == sc->num_tx_desc)
2327 curr_txd = 0;
2328
2329 KKASSERT(sc->num_tx_desc_avail > 0);
2330 sc->num_tx_desc_avail--;
2331
2332 sc->next_avail_tx_desc = curr_txd;
2333 return 1;
2334}
2335
5330213c
SZ
2336static void
2337emx_txeof(struct emx_softc *sc)
2338{
2339 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2340 struct emx_txbuf *tx_buffer;
5330213c
SZ
2341 int first, num_avail;
2342
2343 if (sc->tx_dd_head == sc->tx_dd_tail)
2344 return;
2345
2346 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2347 return;
2348
2349 num_avail = sc->num_tx_desc_avail;
2350 first = sc->next_tx_to_clean;
2351
2352 while (sc->tx_dd_head != sc->tx_dd_tail) {
2353 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2354 struct e1000_tx_desc *tx_desc;
5330213c
SZ
2355
2356 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ
2357 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2358 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2359
2360 if (++dd_idx == sc->num_tx_desc)
2361 dd_idx = 0;
2362
2363 while (first != dd_idx) {
2364 logif(pkt_txclean);
2365
5330213c
SZ
2366 num_avail++;
2367
323e5ecd 2368 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2369 if (tx_buffer->m_head) {
2370 ifp->if_opackets++;
2371 bus_dmamap_unload(sc->txtag,
2372 tx_buffer->map);
2373 m_freem(tx_buffer->m_head);
2374 tx_buffer->m_head = NULL;
2375 }
2376
2377 if (++first == sc->num_tx_desc)
2378 first = 0;
2379 }
2380 } else {
2381 break;
2382 }
2383 }
2384 sc->next_tx_to_clean = first;
2385 sc->num_tx_desc_avail = num_avail;
2386
2387 if (sc->tx_dd_head == sc->tx_dd_tail) {
2388 sc->tx_dd_head = 0;
2389 sc->tx_dd_tail = 0;
2390 }
2391
2392 if (!EMX_IS_OACTIVE(sc)) {
2393 ifp->if_flags &= ~IFF_OACTIVE;
2394
2395 /* All clean, turn off the timer */
2396 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2397 ifp->if_timer = 0;
2398 }
2399}
2400
2401static void
2402emx_tx_collect(struct emx_softc *sc)
2403{
2404 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2405 struct emx_txbuf *tx_buffer;
5330213c
SZ
2406 int tdh, first, num_avail, dd_idx = -1;
2407
2408 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2409 return;
2410
2411 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2412 if (tdh == sc->next_tx_to_clean)
2413 return;
2414
2415 if (sc->tx_dd_head != sc->tx_dd_tail)
2416 dd_idx = sc->tx_dd[sc->tx_dd_head];
2417
2418 num_avail = sc->num_tx_desc_avail;
2419 first = sc->next_tx_to_clean;
2420
2421 while (first != tdh) {
2422 logif(pkt_txclean);
2423
5330213c
SZ
2424 num_avail++;
2425
323e5ecd 2426 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2427 if (tx_buffer->m_head) {
2428 ifp->if_opackets++;
2429 bus_dmamap_unload(sc->txtag,
2430 tx_buffer->map);
2431 m_freem(tx_buffer->m_head);
2432 tx_buffer->m_head = NULL;
2433 }
2434
2435 if (first == dd_idx) {
2436 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2437 if (sc->tx_dd_head == sc->tx_dd_tail) {
2438 sc->tx_dd_head = 0;
2439 sc->tx_dd_tail = 0;
2440 dd_idx = -1;
2441 } else {
2442 dd_idx = sc->tx_dd[sc->tx_dd_head];
2443 }
2444 }
2445
2446 if (++first == sc->num_tx_desc)
2447 first = 0;
2448 }
2449 sc->next_tx_to_clean = first;
2450 sc->num_tx_desc_avail = num_avail;
2451
2452 if (!EMX_IS_OACTIVE(sc)) {
2453 ifp->if_flags &= ~IFF_OACTIVE;
2454
2455 /* All clean, turn off the timer */
2456 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2457 ifp->if_timer = 0;
2458 }
2459}
2460
2461/*
2462 * When Link is lost sometimes there is work still in the TX ring
2463 * which will result in a watchdog, rather than allow that do an
2464 * attempted cleanup and then reinit here. Note that this has been
2465 * seens mostly with fiber adapters.
2466 */
2467static void
2468emx_tx_purge(struct emx_softc *sc)
2469{
2470 struct ifnet *ifp = &sc->arpcom.ac_if;
2471
2472 if (!sc->link_active && ifp->if_timer) {
2473 emx_tx_collect(sc);
2474 if (ifp->if_timer) {
2475 if_printf(ifp, "Link lost, TX pending, reinit\n");
2476 ifp->if_timer = 0;
2477 emx_init(sc);
2478 }
2479 }
2480}
2481
2482static int
9f831fa8 2483emx_newbuf(struct emx_rxdata *rdata, int i, int init)
5330213c
SZ
2484{
2485 struct mbuf *m;
2486 bus_dma_segment_t seg;
2487 bus_dmamap_t map;
323e5ecd 2488 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2489 int error, nseg;
2490
2491 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2492 if (m == NULL) {
5330213c 2493 if (init) {
9f831fa8 2494 if_printf(&rdata->sc->arpcom.ac_if,
5330213c
SZ
2495 "Unable to allocate RX mbuf\n");
2496 }
2497 return (ENOBUFS);
2498 }
2499 m->m_len = m->m_pkthdr.len = MCLBYTES;
2500
9f831fa8 2501 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
5330213c
SZ
2502 m_adj(m, ETHER_ALIGN);
2503
c39e3a1f
SZ
2504 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2505 rdata->rx_sparemap, m,
5330213c
SZ
2506 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2507 if (error) {
2508 m_freem(m);
2509 if (init) {
9f831fa8 2510 if_printf(&rdata->sc->arpcom.ac_if,
5330213c
SZ
2511 "Unable to load RX mbuf\n");
2512 }
2513 return (error);
2514 }
2515
323e5ecd 2516 rx_buffer = &rdata->rx_buf[i];
5330213c 2517 if (rx_buffer->m_head != NULL)
c39e3a1f 2518 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ
2519
2520 map = rx_buffer->map;
c39e3a1f
SZ
2521 rx_buffer->map = rdata->rx_sparemap;
2522 rdata->rx_sparemap = map;
5330213c
SZ
2523
2524 rx_buffer->m_head = m;
235b9d30 2525 rx_buffer->paddr = seg.ds_addr;
5330213c 2526
235b9d30 2527 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ
2528 return (0);
2529}
2530
2531static int
9f831fa8 2532emx_create_rx_ring(struct emx_rxdata *rdata)
5330213c 2533{
9f831fa8 2534 device_t dev = rdata->sc->dev;
323e5ecd 2535 struct emx_rxbuf *rx_buffer;
b4d8c36b 2536 int i, error, rsize, nrxd;
bdca134f
SZ
2537
2538 /*
2539 * Validate number of receive descriptors. It must not exceed
2540 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2541 */
b4d8c36b
SZ
2542 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2543 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2544 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
bdca134f 2545 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
b4d8c36b 2546 EMX_DEFAULT_RXD, nrxd);
c39e3a1f 2547 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2548 } else {
b4d8c36b 2549 rdata->num_rx_desc = nrxd;
bdca134f
SZ
2550 }
2551
2552 /*
2553 * Allocate Receive Descriptor ring
2554 */
235b9d30 2555 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2556 EMX_DBA_ALIGN);
9f831fa8 2557 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
a596084c 2558 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ
2559 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2560 &rdata->rx_desc_paddr);
235b9d30 2561 if (rdata->rx_desc == NULL) {
bdca134f 2562 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2563 return ENOMEM;
bdca134f 2564 }
5330213c 2565
323e5ecd
SZ
2566 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2567 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2568
2569 /*
2570 * Create DMA tag for rx buffers
2571 */
9f831fa8 2572 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
5330213c
SZ
2573 1, 0, /* alignment, bounds */
2574 BUS_SPACE_MAXADDR, /* lowaddr */
2575 BUS_SPACE_MAXADDR, /* highaddr */
2576 NULL, NULL, /* filter, filterarg */
2577 MCLBYTES, /* maxsize */
2578 1, /* nsegments */
2579 MCLBYTES, /* maxsegsize */
2580 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2581 &rdata->rxtag);
5330213c
SZ
2582 if (error) {
2583 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ
2584 kfree(rdata->rx_buf, M_DEVBUF);
2585 rdata->rx_buf = NULL;
5330213c
SZ
2586 return error;
2587 }
2588
2589 /*
2590 * Create spare DMA map for rx buffers
2591 */
c39e3a1f
SZ
2592 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2593 &rdata->rx_sparemap);
5330213c
SZ
2594 if (error) {
2595 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2596 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ
2597 kfree(rdata->rx_buf, M_DEVBUF);
2598 rdata->rx_buf = NULL;
5330213c
SZ
2599 return error;
2600 }
2601
2602 /*
2603 * Create DMA maps for rx buffers
2604 */
c39e3a1f 2605 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2606 rx_buffer = &rdata->rx_buf[i];
5330213c 2607
c39e3a1f 2608 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ
2609 &rx_buffer->map);
2610 if (error) {
2611 device_printf(dev, "Unable to create RX DMA map\n");
9f831fa8 2612 emx_destroy_rx_ring(rdata, i);
5330213c
SZ
2613 return error;
2614 }
2615 }
2616 return (0);
2617}
2618
c39e3a1f 2619static void
9f831fa8 2620emx_free_rx_ring(struct emx_rxdata *rdata)
c39e3a1f
SZ
2621{
2622 int i;
2623
2624 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2625 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ
2626
2627 if (rx_buffer->m_head != NULL) {
2628 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2629 m_freem(rx_buffer->m_head);
2630 rx_buffer->m_head = NULL;
2631 }
2632 }
2633
2634 if (rdata->fmp != NULL)
2635 m_freem(rdata->fmp);
2636 rdata->fmp = NULL;
2637 rdata->lmp = NULL;
2638}
2639
5330213c 2640static int
9f831fa8 2641emx_init_rx_ring(struct emx_rxdata *rdata)
5330213c
SZ
2642{
2643 int i, error;
2644
2645 /* Reset descriptor ring */
235b9d30 2646 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ
2647
2648 /* Allocate new ones. */
c39e3a1f 2649 for (i = 0; i < rdata->num_rx_desc; i++) {
9f831fa8 2650 error = emx_newbuf(rdata, i, 1);
5330213c
SZ
2651 if (error)
2652 return (error);
2653 }
2654
2655 /* Setup our descriptor pointers */
c39e3a1f 2656 rdata->next_rx_desc_to_check = 0;
5330213c
SZ
2657
2658 return (0);
2659}
2660
2661static void
2662emx_init_rx_unit(struct emx_softc *sc)
2663{
2664 struct ifnet *ifp = &sc->arpcom.ac_if;
2665 uint64_t bus_addr;
2d0e5700 2666 uint32_t rctl, itr, rfctl;
3f939c23 2667 int i;
5330213c
SZ
2668
2669 /*
2670 * Make sure receives are disabled while setting
2671 * up the descriptor ring
2672 */
2673 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2674 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2675
2676 /*
2677 * Set the interrupt throttling rate. Value is calculated
2678 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2679 */
2d0e5700
SZ
2680 if (sc->int_throttle_ceil)
2681 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2682 else
2683 itr = 0;
2684 emx_set_itr(sc, itr);
5330213c 2685
235b9d30
SZ
2686 /* Use extended RX descriptor */
2687 rfctl = E1000_RFCTL_EXTEN;
2688
5330213c 2689 /* Disable accelerated ackknowledge */
235b9d30
SZ
2690 if (sc->hw.mac.type == e1000_82574)
2691 rfctl |= E1000_RFCTL_ACK_DIS;
2692
2693 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c 2694
65c7a6af
SZ
2695 /*
2696 * Receive Checksum Offload for TCP and UDP
2697 *
2698 * Checksum offloading is also enabled if multiple receive
2699 * queue is to be supported, since we need it to figure out
2700 * packet type.
2701 */
13890b61
SZ
2702 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2703 sc->rx_ring_cnt > 1) {
2d0e5700
SZ
2704 uint32_t rxcsum;
2705
5330213c 2706 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ
2707
2708 /*
2709 * NOTE:
2710 * PCSD must be enabled to enable multiple
2711 * receive queues.
2712 */
2713 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2714 E1000_RXCSUM_PCSD;
5330213c
SZ
2715 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2716 }
2717
2718 /*
65c7a6af 2719 * Configure multiple receive queue (RSS)
3f939c23 2720 */
13890b61 2721 if (sc->rx_ring_cnt > 1) {
89d8e73d
SZ
2722 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2723 uint32_t reta;
2724
13890b61
SZ
2725 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2726 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
89d8e73d 2727
65c7a6af
SZ
2728 /*
2729 * NOTE:
2730 * When we reach here, RSS has already been disabled
2731 * in emx_stop(), so we could safely configure RSS key
2732 * and redirect table.
2733 */
3f939c23 2734
65c7a6af
SZ
2735 /*
2736 * Configure RSS key
2737 */
89d8e73d
SZ
2738 toeplitz_get_key(key, sizeof(key));
2739 for (i = 0; i < EMX_NRSSRK; ++i) {
2740 uint32_t rssrk;
2741
2742 rssrk = EMX_RSSRK_VAL(key, i);
2743 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2744
2745 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2746 }
3f939c23 2747
65c7a6af 2748 /*
89d8e73d
SZ
2749 * Configure RSS redirect table in following fashion:
2750 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2751 */
89d8e73d
SZ
2752 reta = 0;
2753 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2754 uint32_t q;
2755
13890b61 2756 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
89d8e73d
SZ
2757 reta |= q << (8 * i);
2758 }
2759 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2760
65c7a6af
SZ
2761 for (i = 0; i < EMX_NRETA; ++i)
2762 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2763
65c7a6af
SZ
2764 /*
2765 * Enable multiple receive queues.
2766 * Enable IPv4 RSS standard hash functions.
2767 * Disable RSS interrupt.
2768 */
2769 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2770 E1000_MRQC_ENABLE_RSS_2Q |
2771 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2772 E1000_MRQC_RSS_FIELD_IPV4);
2773 }
3f939c23
SZ
2774
2775 /*
5330213c
SZ
2776 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2777 * long latencies are observed, like Lenovo X60. This
2778 * change eliminates the problem, but since having positive
2779 * values in RDTR is a known source of problems on other
2780 * platforms another solution is being sought.
2781 */
2782 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2783 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2784 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2785 }
2786
13890b61 2787 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2d0e5700
SZ
2788 struct emx_rxdata *rdata = &sc->rx_data[i];
2789
2790 /*
2791 * Setup the Base and Length of the Rx Descriptor Ring
2792 */
2793 bus_addr = rdata->rx_desc_paddr;
2794 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2795 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2796 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2797 (uint32_t)(bus_addr >> 32));
2798 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2799 (uint32_t)bus_addr);
2800
2801 /*
2802 * Setup the HW Rx Head and Tail Descriptor Pointers
2803 */
3f939c23
SZ
2804 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2805 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2806 sc->rx_data[i].num_rx_desc - 1);
2807 }
2808
2d0e5700
SZ
2809 /* Setup the Receive Control Register */
2810 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2811 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2812 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2813 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2814
2815 /* Make sure VLAN Filters are off */
2816 rctl &= ~E1000_RCTL_VFE;
2817
2818 /* Don't store bad paket */
2819 rctl &= ~E1000_RCTL_SBP;
2820
2821 /* MCLBYTES */
2822 rctl |= E1000_RCTL_SZ_2048;
2823
2824 if (ifp->if_mtu > ETHERMTU)
2825 rctl |= E1000_RCTL_LPE;
2826 else
2827 rctl &= ~E1000_RCTL_LPE;
2828
3f939c23
SZ
2829 /* Enable Receives */
2830 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ
2831}
2832
2833static void
9f831fa8 2834emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
5330213c 2835{
323e5ecd 2836 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2837 int i;
2838
bdca134f 2839 /* Free Receive Descriptor ring */
235b9d30 2840 if (rdata->rx_desc) {
c39e3a1f 2841 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2842 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ
2843 rdata->rx_desc_dmap);
2844 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2845
235b9d30 2846 rdata->rx_desc = NULL;
a596084c 2847 }
bdca134f 2848
323e5ecd 2849 if (rdata->rx_buf == NULL)
5330213c
SZ
2850 return;
2851
2852 for (i = 0; i < ndesc; i++) {
323e5ecd 2853 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ
2854
2855 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2856 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2857 }
c39e3a1f
SZ
2858 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2859 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2860
323e5ecd
SZ
2861 kfree(rdata->rx_buf, M_DEVBUF);
2862 rdata->rx_buf = NULL;
5330213c
SZ
2863}
2864
2865static void
9f831fa8 2866emx_rxeof(struct emx_rxdata *rdata, int count)
5330213c 2867{
9f831fa8 2868 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
235b9d30 2869 uint32_t staterr;
235b9d30 2870 emx_rxdesc_t *current_desc;
5330213c
SZ
2871 struct mbuf *mp;
2872 int i;
5330213c 2873
c39e3a1f 2874 i = rdata->next_rx_desc_to_check;
235b9d30
SZ
2875 current_desc = &rdata->rx_desc[i];
2876 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2877
235b9d30 2878 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ
2879 return;
2880
235b9d30 2881 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2882 struct pktinfo *pi = NULL, pi0;
235b9d30 2883 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2884 struct mbuf *m = NULL;
0acc29d6 2885 int eop, len;
5330213c
SZ
2886
2887 logif(pkt_receive);
2888
235b9d30 2889 mp = rx_buf->m_head;
5330213c
SZ
2890
2891 /*
2892 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2893 * needs to access the last received byte in the mbuf.
2894 */
235b9d30 2895 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ
2896 BUS_DMASYNC_POSTREAD);
2897
0acc29d6 2898 len = le16toh(current_desc->rxd_length);
235b9d30 2899 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ
2900 count--;
2901 eop = 1;
5330213c
SZ
2902 } else {
2903 eop = 0;
5330213c
SZ
2904 }
2905
235b9d30
SZ
2906 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2907 uint16_t vlan = 0;
3f939c23 2908 uint32_t mrq, rss_hash;
235b9d30
SZ
2909
2910 /*
2911 * Save several necessary information,
2912 * before emx_newbuf() destroy it.
2913 */
2914 if ((staterr & E1000_RXD_STAT_VP) && eop)
2915 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2916
3f939c23
SZ
2917 mrq = le32toh(current_desc->rxd_mrq);
2918 rss_hash = le32toh(current_desc->rxd_rss);
2919
9f831fa8 2920 EMX_RSS_DPRINTF(rdata->sc, 10,
3f939c23 2921 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
9f831fa8 2922 rdata->idx, mrq, rss_hash);
3f939c23 2923
9f831fa8 2924 if (emx_newbuf(rdata, i, 0) != 0) {
5330213c
SZ
2925 ifp->if_iqdrops++;
2926 goto discard;
2927 }
2928
2929 /* Assign correct length to the current fragment */
2930 mp->m_len = len;
2931
c39e3a1f 2932 if (rdata->fmp == NULL) {
5330213c 2933 mp->m_pkthdr.len = len;
c39e3a1f
SZ
2934 rdata->fmp = mp; /* Store the first mbuf */
2935 rdata->lmp = mp;
5330213c
SZ
2936 } else {
2937 /*
2938 * Chain mbuf's together
2939 */
c39e3a1f
SZ
2940 rdata->lmp->m_next = mp;
2941 rdata->lmp = rdata->lmp->m_next;
2942 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ
2943 }
2944
2945 if (eop) {
c39e3a1f 2946 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ
2947 ifp->if_ipackets++;
2948
235b9d30
SZ
2949 if (ifp->if_capenable & IFCAP_RXCSUM)
2950 emx_rxcsum(staterr, rdata->fmp);
5330213c 2951
235b9d30 2952 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2953 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2954 vlan;
c39e3a1f 2955 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2956 }
c39e3a1f
SZ
2957 m = rdata->fmp;
2958 rdata->fmp = NULL;
2959 rdata->lmp = NULL;
3f939c23 2960
9cc86e17
SZ
2961 if (ifp->if_capenable & IFCAP_RSS) {
2962 pi = emx_rssinfo(m, &pi0, mrq,
2963 rss_hash, staterr);
2964 }
3f939c23
SZ
2965#ifdef EMX_RSS_DEBUG
2966 rdata->rx_pkts++;
2967#endif
5330213c
SZ
2968 }
2969 } else {
2970 ifp->if_ierrors++;
2971discard:
235b9d30 2972 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ
2973 if (rdata->fmp != NULL) {
2974 m_freem(rdata->fmp);
2975 rdata->fmp = NULL;
2976 rdata->lmp = NULL;
5330213c
SZ
2977 }
2978 m = NULL;
2979 }
2980
5330213c 2981 if (m != NULL)
eda7db08 2982 ether_input_pkt(ifp, m, pi);
5330213c
SZ
2983
2984 /* Advance our pointers to the next descriptor. */
c39e3a1f 2985 if (++i == rdata->num_rx_desc)
5330213c 2986 i = 0;
235b9d30
SZ
2987
2988 current_desc = &rdata->rx_desc[i];
2989 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2990 }
c39e3a1f 2991 rdata->next_rx_desc_to_check = i;
5330213c 2992
3f939c23 2993 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2994 if (--i < 0)
c39e3a1f 2995 i = rdata->num_rx_desc - 1;
9f831fa8 2996 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
5330213c
SZ
2997}
2998
2999static void
5330213c
SZ
3000emx_enable_intr(struct emx_softc *sc)
3001{
2d0e5700
SZ
3002 uint32_t ims_mask = IMS_ENABLE_MASK;
3003
6d435846 3004 lwkt_serialize_handler_enable(&sc->main_serialize);
2d0e5700
SZ
3005
3006#if 0
3007 if (sc->hw.mac.type == e1000_82574) {
3008 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3009 ims_mask |= EM_MSIX_MASK;
3010 }
3011#endif
3012 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
5330213c
SZ
3013}
3014
3015static void
3016emx_disable_intr(struct emx_softc *sc)
3017{
2d0e5700
SZ
3018 if (sc->hw.mac.type == e1000_82574)
3019 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
5330213c 3020 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2d0e5700 3021
6d435846 3022 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ
3023}
3024
3025/*
3026 * Bit of a misnomer, what this really means is
3027 * to enable OS management of the system... aka
3028 * to disable special hardware management features
3029 */
3030static void
3031emx_get_mgmt(struct emx_softc *sc)
3032{
3033 /* A shared code workaround */
de0836d4 3034 if (sc->flags & EMX_FLAG_HAS_MGMT) {
5330213c
SZ
3035 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3036 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3037
3038 /* disable hardware interception of ARP */
3039 manc &= ~(E1000_MANC_ARP_EN);
3040
3041 /* enable receiving management packets to the host */
3042 manc |= E1000_MANC_EN_MNG2HOST;
3043#define E1000_MNG2HOST_PORT_623 (1 << 5)
3044#define E1000_MNG2HOST_PORT_664 (1 << 6)
3045 manc2h |= E1000_MNG2HOST_PORT_623;
3046 manc2h |= E1000_MNG2HOST_PORT_664;
3047 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3048
3049 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3050 }
3051}
3052
3053/*
3054 * Give control back to hardware management
3055 * controller if there is one.
3056 */
3057static void
3058emx_rel_mgmt(struct emx_softc *sc)
3059{
de0836d4 3060 if (sc->flags & EMX_FLAG_HAS_MGMT) {
5330213c
SZ
3061 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3062
3063 /* re-enable hardware interception of ARP */
3064 manc |= E1000_MANC_ARP_EN;
3065 manc &= ~E1000_MANC_EN_MNG2HOST;
3066
3067 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3068 }
3069}
3070
3071/*
3072 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3073 * For ASF and Pass Through versions of f/w this means that
3074 * the driver is loaded. For AMT version (only with 82573)
3075 * of the f/w this means that the network i/f is open.
3076 */
3077static void
3078emx_get_hw_control(struct emx_softc *sc)
3079{
5330213c 3080 /* Let firmware know the driver has taken over */
2d0e5700
SZ
3081 if (sc->hw.mac.type == e1000_82573) {
3082 uint32_t swsm;
3083
5330213c
SZ
3084 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3085 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3086 swsm | E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3087 } else {
3088 uint32_t ctrl_ext;
5330213c 3089
5330213c
SZ
3090 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3091 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3092 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
5330213c 3093 }
de0836d4 3094 sc->flags |= EMX_FLAG_HW_CTRL;
5330213c
SZ
3095}
3096
3097/*
3098 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3099 * For ASF and Pass Through versions of f/w this means that the
3100 * driver is no longer loaded. For AMT version (only with 82573)
3101 * of the f/w this means that the network i/f is closed.
3102 */
3103static void
3104emx_rel_hw_control(struct emx_softc *sc)
3105{
de0836d4 3106 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
2d0e5700 3107 return;
de0836d4 3108 sc->flags &= ~EMX_FLAG_HW_CTRL;
5330213c
SZ
3109
3110 /* Let firmware taken over control of h/w */
2d0e5700
SZ
3111 if (sc->hw.mac.type == e1000_82573) {
3112 uint32_t swsm;
3113
5330213c
SZ
3114 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3115 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3116 swsm & ~E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3117 } else {
3118 uint32_t ctrl_ext;
5330213c 3119
5330213c
SZ
3120 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3121 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3122 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
5330213c
SZ
3123 }
3124}
3125
3126static int
3127emx_is_valid_eaddr(const uint8_t *addr)
3128{
3129 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3130
3131 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3132 return (FALSE);
3133
3134 return (TRUE);
3135}
3136
3137/*
3138 * Enable PCI Wake On Lan capability
3139 */
3140void
3141emx_enable_wol(device_t dev)
3142{
3143 uint16_t cap, status;
3144 uint8_t id;
3145
3146 /* First find the capabilities pointer*/
3147 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3148
3149 /* Read the PM Capabilities */
3150 id = pci_read_config(dev, cap, 1);
3151 if (id != PCIY_PMG) /* Something wrong */
3152 return;
3153
3154 /*
3155 * OK, we have the power capabilities,
3156 * so now get the status register
3157 */
3158 cap += PCIR_POWER_STATUS;
3159 status = pci_read_config(dev, cap, 2);
3160 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3161 pci_write_config(dev, cap, status, 2);
3162}
3163
3164static void
3165emx_update_stats(struct emx_softc *sc)
3166{
3167 struct ifnet *ifp = &sc->arpcom.ac_if;
3168
3169 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3170 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3171 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3172 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3173 }
3174 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3175 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3176 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3177 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3178
3179 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3180 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3181 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3182 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3183 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3184 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3185 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3186 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3187 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3188 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3189 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3190 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3191 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3192 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3193 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3194 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3195 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3196 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3197 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3198 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3199
3200 /* For the 64-bit byte counters the low dword must be read first. */
3201 /* Both registers clear on the read of the high dword */
3202
3203 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3204 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3205
3206 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3207 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3208 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3209 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3210 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3211
3212 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3213 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3214
3215 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3216 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3217 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3218 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3219 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3220 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3221 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3222 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3223 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3224 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3225
3226 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3227 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3228 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3229 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3230 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3231 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3232
3233 ifp->if_collisions = sc->stats.colc;
3234
3235 /* Rx Errors */
ec1092aa 3236 ifp->if_ierrors = sc->stats.rxerrc +
5330213c
SZ
3237 sc->stats.crcerrs + sc->stats.algnerrc +
3238 sc->stats.ruc + sc->stats.roc +
3239 sc->stats.mpc + sc->stats.cexterr;
3240
3241 /* Tx Errors */
ec1092aa 3242 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol;
5330213c
SZ
3243}
3244
3245static void
3246emx_print_debug_info(struct emx_softc *sc)
3247{
3248 device_t dev = sc->dev;
3249 uint8_t *hw_addr = sc->hw.hw_addr;
3250
3251 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3252 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3253 E1000_READ_REG(&sc->hw, E1000_CTRL),
3254 E1000_READ_REG(&sc->hw, E1000_RCTL));
3255 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3256 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3257 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3258 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3259 sc->hw.fc.high_water, sc->hw.fc.low_water);
3260 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3261 E1000_READ_REG(&sc->hw, E1000_TIDV),
3262 E1000_READ_REG(&sc->hw, E1000_TADV));
3263 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3264 E1000_READ_REG(&sc->hw, E1000_RDTR),
3265 E1000_READ_REG(&sc->hw, E1000_RADV));
3266 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3267 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3268 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3269 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3270 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3271 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3272 device_printf(dev, "Num Tx descriptors avail = %d\n",
3273 sc->num_tx_desc_avail);
0c0e1638
SZ
3274
3275 device_printf(dev, "TSO segments %lu\n", sc->tso_segments);
3276 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused);
5330213c
SZ
3277}
3278
3279static void
3280emx_print_hw_stats(struct emx_softc *sc)
3281{
3282 device_t dev = sc->dev;
3283
3284 device_printf(dev, "Excessive collisions = %lld\n",
3285 (long long)sc->stats.ecol);
3286#if (DEBUG_HW > 0) /* Dont output these errors normally */
3287 device_printf(dev, "Symbol errors = %lld\n",
3288 (long long)sc->stats.symerrs);
3289#endif
3290 device_printf(dev, "Sequence errors = %lld\n",
3291 (long long)sc->stats.sec);
3292 device_printf(dev, "Defer count = %lld\n",
3293 (long long)sc->stats.dc);
3294 device_printf(dev, "Missed Packets = %lld\n",
3295 (long long)sc->stats.mpc);
3296 device_printf(dev, "Receive No Buffers = %lld\n",
3297 (long long)sc->stats.rnbc);
3298 /* RLEC is inaccurate on some hardware, calculate our own. */
3299 device_printf(dev, "Receive Length Errors = %lld\n",
3300 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3301 device_printf(dev, "Receive errors = %lld\n",
3302 (long long)sc->stats.rxerrc);
3303 device_printf(dev, "Crc errors = %lld\n",
3304 (long long)sc->stats.crcerrs);
3305 device_printf(dev, "Alignment errors = %lld\n",
3306 (long long)sc->stats.algnerrc);
3307 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3308 (long long)sc->stats.cexterr);
3309 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
5330213c
SZ
3310 device_printf(dev, "XON Rcvd = %lld\n",
3311 (long long)sc->stats.xonrxc);
3312 device_printf(dev, "XON Xmtd = %lld\n",
3313 (long long)sc->stats.xontxc);
3314 device_printf(dev, "XOFF Rcvd = %lld\n",
3315 (long long)sc->stats.xoffrxc);
3316 device_printf(dev, "XOFF Xmtd = %lld\n",
3317 (long long)sc->stats.xofftxc);
3318 device_printf(dev, "Good Packets Rcvd = %lld\n",
3319 (long long)sc->stats.gprc);
3320 device_printf(dev, "Good Packets Xmtd = %lld\n",
3321 (long long)sc->stats.gptc);
3322}
3323
3324static void
3325emx_print_nvm_info(struct emx_softc *sc)
3326{
3327 uint16_t eeprom_data;
3328 int i, j, row = 0;
3329
3330 /* Its a bit crude, but it gets the job done */
3331 kprintf("\nInterface EEPROM Dump:\n");
3332 kprintf("Offset\n0x0000 ");
3333 for (i = 0, j = 0; i < 32; i++, j++) {
3334 if (j == 8) { /* Make the offset block */
3335 j = 0; ++row;
3336 kprintf("\n0x00%x0 ",row);
3337 }
3338 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3339 kprintf("%04x ", eeprom_data);
3340 }
3341 kprintf("\n");
3342}
3343
3344static int
3345emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3346{
3347 struct emx_softc *sc;
3348 struct ifnet *ifp;
3349 int error, result;
3350
3351 result = -1;
3352 error = sysctl_handle_int(oidp, &result, 0, req);
3353 if (error || !req->newptr)
3354 return (error);
3355
3356 sc = (struct emx_softc *)arg1;
3357 ifp = &sc->arpcom.ac_if;
3358
6d435846 3359 ifnet_serialize_all(ifp);
5330213c
SZ
3360
3361 if (result == 1)
3362 emx_print_debug_info(sc);
3363
3364 /*
3365 * This value will cause a hex dump of the
3366 * first 32 16-bit words of the EEPROM to
3367 * the screen.
3368 */
3369 if (result == 2)
3370 emx_print_nvm_info(sc);
3371
6d435846 3372 ifnet_deserialize_all(ifp);
5330213c
SZ
3373
3374 return (error);
3375}
3376
3377static int
3378emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3379{
3380 int error, result;
3381
3382 result = -1;
3383 error = sysctl_handle_int(oidp, &result, 0, req);
3384 if (error || !req->newptr)
3385 return (error);
3386
3387 if (result == 1) {
3388 struct emx_softc *sc = (struct emx_softc *)arg1;
3389 struct ifnet *ifp = &sc->arpcom.ac_if;
3390
6d435846 3391 ifnet_serialize_all(ifp);
5330213c 3392 emx_print_hw_stats(sc);
6d435846 3393 ifnet_deserialize_all(ifp);
5330213c
SZ
3394 }
3395 return (error);
3396}
3397
3398static void
3399emx_add_sysctl(struct emx_softc *sc)
3400{
3f939c23
SZ
3401#ifdef EMX_RSS_DEBUG
3402 char rx_pkt[32];
3403 int i;
3404#endif
5330213c
SZ
3405
3406 sysctl_ctx_init(&sc->sysctl_ctx);
3407 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3408 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3409 device_get_nameunit(sc->dev),
3410 CTLFLAG_RD, 0, "");
3411 if (sc->sysctl_tree == NULL) {
3412 device_printf(sc->dev, "can't add sysctl node\n");
3413 return;
3414 }
3415
3416 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3417 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3418 emx_sysctl_debug_info, "I", "Debug Information");
3419
3420 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3421 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3422 emx_sysctl_stats, "I", "Statistics");
3423
3424 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ
3425 OID_AUTO, "rxd", CTLFLAG_RD,
3426 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3427 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3428 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3429
5330213c
SZ
3430 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3431 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3432 sc, 0, emx_sysctl_int_throttle, "I",
3433 "interrupt throttling rate");
3434 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3435 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3436 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3437 "# segments per TX interrupt");
3f939c23 3438
8434a83b 3439 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
13890b61
SZ
3440 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3441 &sc->rx_ring_cnt, 0, "RX ring count");
8434a83b 3442
09f49d52
SZ
3443#ifdef IFPOLL_ENABLE
3444 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3445 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3446 sc, 0, emx_sysctl_npoll_rxoff, "I",
3447 "NPOLLING RX cpu offset");
3448 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3449 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3450 sc, 0, emx_sysctl_npoll_txoff, "I",
3451 "NPOLLING TX cpu offset");
3452#endif
3453
3f939c23
SZ
3454#ifdef EMX_RSS_DEBUG
3455 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3456 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3457 0, "RSS debug level");
65c7a6af 3458 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3459 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3460 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3461 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3462 rx_pkt, CTLFLAG_RW,
3f939c23
SZ
3463 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3464 }
3465#endif
5330213c
SZ
3466}
3467
3468static int
3469emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3470{
3471 struct emx_softc *sc = (void *)arg1;
3472 struct ifnet *ifp = &sc->arpcom.ac_if;
3473 int error, throttle;
3474
3475 throttle = sc->int_throttle_ceil;
3476 error = sysctl_handle_int(oidp, &throttle, 0, req);
3477 if (error || req->newptr == NULL)
3478 return error;
3479 if (throttle < 0 || throttle > 1000000000 / 256)
3480 return EINVAL;
3481
3482 if (throttle) {
3483 /*
3484 * Set the interrupt throttling rate in 256ns increments,
3485 * recalculate sysctl value assignment to get exact frequency.
3486 */
3487 throttle = 1000000000 / 256 / throttle;
3488
3489 /* Upper 16bits of ITR is reserved and should be zero */
3490 if (throttle & 0xffff0000)
3491 return EINVAL;
3492 }
3493
6d435846 3494 ifnet_serialize_all(ifp);
5330213c
SZ
3495
3496 if (throttle)
3497 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3498 else
3499 sc->int_throttle_ceil = 0;
3500
3501 if (ifp->if_flags & IFF_RUNNING)
2d0e5700 3502 emx_set_itr(sc, throttle);
5330213c 3503
6d435846 3504 ifnet_deserialize_all(ifp);
5330213c
SZ
3505
3506 if (bootverbose) {
3507 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3508 sc->int_throttle_ceil);
3509 }
3510 return 0;
3511}
3512
3513static int
3514emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3515{
3516 struct emx_softc *sc = (void *)arg1;
3517 struct ifnet *ifp = &sc->arpcom.ac_if;
3518 int error, segs;
3519
3520 segs = sc->tx_int_nsegs;
3521 error = sysctl_handle_int(oidp, &segs, 0, req);
3522 if (error || req->newptr == NULL)
3523 return error;
3524 if (segs <= 0)
3525 return EINVAL;
3526
6d435846 3527 ifnet_serialize_all(ifp);
5330213c
SZ
3528
3529 /*
3530 * Don't allow int_tx_nsegs to become:
3531 * o Less the oact_tx_desc
3532 * o Too large that no TX desc will cause TX interrupt to
3533 * be generated (OACTIVE will never recover)
3534 * o Too small that will cause tx_dd[] overflow
3535 */
3536 if (segs < sc->oact_tx_desc ||
3537 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3538 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3539 error = EINVAL;
3540 } else {
3541 error = 0;
3542 sc->tx_int_nsegs = segs;
3543 }
3544
6d435846 3545 ifnet_deserialize_all(ifp);
5330213c
SZ
3546
3547 return error;
3548}
071699f8 3549
09f49d52
SZ
3550#ifdef IFPOLL_ENABLE
3551
3552static int
3553emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3554{
3555 struct emx_softc *sc = (void *)arg1;
3556 struct ifnet *ifp = &sc->arpcom.ac_if;
3557 int error, off;
3558
3559 off = sc->rx_npoll_off;
3560 error = sysctl_handle_int(oidp, &off, 0, req);
3561 if (error || req->newptr == NULL)
3562 return error;
3563 if (off < 0)
3564 return EINVAL;
3565
3566 ifnet_serialize_all(ifp);
3567 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3568 error = EINVAL;
3569 } else {
3570 error = 0;
3571 sc->rx_npoll_off = off;
3572 }
3573 ifnet_deserialize_all(ifp);
3574
3575 return error;
3576}
3577
3578static int
3579emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3580{
3581 struct emx_softc *sc = (void *)arg1;
3582 struct ifnet *ifp = &sc->arpcom.ac_if;
3583 int error, off;
3584
3585 off = sc->tx_npoll_off;
3586 error = sysctl_handle_int(oidp, &off, 0, req);
3587 if (error || req->newptr == NULL)
3588 return error;
3589 if (off < 0)
3590 return EINVAL;
3591
3592 ifnet_serialize_all(ifp);
3593 if (off >= ncpus2) {
3594 error = EINVAL;
3595 } else {
3596 error = 0;
3597 sc->tx_npoll_off = off;
3598 }
3599 ifnet_deserialize_all(ifp);
3600
3601 return error;
3602}
3603
3604#endif /* IFPOLL_ENABLE */
3605
071699f8
SZ
3606static int
3607emx_dma_alloc(struct emx_softc *sc)
3608{
3f939c23 3609 int error, i;
071699f8
SZ
3610
3611 /*
3612 * Create top level busdma tag
3613 */
3614 error = bus_dma_tag_create(NULL, 1, 0,
3615 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3616 NULL, NULL,
3617 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3618 0, &sc->parent_dtag);
3619 if (error) {
3620 device_printf(sc->dev, "could not create top level DMA tag\n");
3621 return error;
3622 }
3623
3624 /*
3625 * Allocate transmit descriptors ring and buffers
3626 */
3627 error = emx_create_tx_ring(sc);
3628 if (error) {
3629 device_printf(sc->dev, "Could not setup transmit structures\n");
3630 return error;
3631 }
3632
3633 /*
3634 * Allocate receive descriptors ring and buffers
3635 */
65c7a6af 3636 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9f831fa8 3637 error = emx_create_rx_ring(&sc->rx_data[i]);
3f939c23
SZ
3638 if (error) {
3639 device_printf(sc->dev,
3640 "Could not setup receive structures\n");
3641 return error;
3642 }
071699f8
SZ
3643 }
3644 return 0;
3645}
3646
3647static void
3648emx_dma_free(struct emx_softc *sc)
3649{
3f939c23
SZ
3650 int i;
3651
071699f8 3652 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3653
65c7a6af 3654 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9f831fa8 3655 emx_destroy_rx_ring(&sc->rx_data[i],
3f939c23
SZ
3656 sc->rx_data[i].num_rx_desc);
3657 }
071699f8
SZ
3658
3659 /* Free top level busdma tag */
3660 if (sc->parent_dtag != NULL)
3661 bus_dma_tag_destroy(sc->parent_dtag);
3662}
6d435846
SZ
3663
3664static void
3665emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3666{
3667 struct emx_softc *sc = ifp->if_softc;
6d435846 3668
8f594b38
SZ
3669 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3670 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3671}
3672
3673static void
3674emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3675{
3676 struct emx_softc *sc = ifp->if_softc;
6d435846 3677
8f594b38
SZ
3678 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3679 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3680}
3681
3682static int
3683emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3684{
3685 struct emx_softc *sc = ifp->if_softc;
6d435846 3686
8f594b38
SZ
3687 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3688 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);