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5330213c SZ |
1 | /* |
2 | * Copyright (c) 2001-2008, Intel Corporation | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * | |
8 | * 1. Redistributions of source code must retain the above copyright notice, | |
9 | * this list of conditions and the following disclaimer. | |
10 | * | |
11 | * 2. Redistributions in binary form must reproduce the above copyright | |
12 | * notice, this list of conditions and the following disclaimer in the | |
13 | * documentation and/or other materials provided with the distribution. | |
14 | * | |
15 | * 3. Neither the name of the Intel Corporation nor the names of its | |
16 | * contributors may be used to endorse or promote products derived from | |
17 | * this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
29 | * POSSIBILITY OF SUCH DAMAGE. | |
30 | */ | |
31 | ||
32 | #ifndef _IF_EMX_H_ | |
33 | #define _IF_EMX_H_ | |
34 | ||
35 | /* Tunables */ | |
36 | ||
37 | /* | |
38 | * EMX_TXD: Maximum number of Transmit Descriptors | |
39 | * Valid Range: 256-4096 for others | |
40 | * Default Value: 512 | |
41 | * This value is the number of transmit descriptors allocated by the driver. | |
42 | * Increasing this value allows the driver to queue more transmits. Each | |
43 | * descriptor is 16 bytes. | |
44 | * Since TDLEN should be multiple of 128bytes, the number of transmit | |
45 | * desscriptors should meet the following condition. | |
46 | * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | |
47 | */ | |
48 | #define EMX_MIN_TXD 256 | |
49 | #define EMX_MAX_TXD 4096 | |
50 | #define EMX_DEFAULT_TXD 512 | |
51 | ||
52 | /* | |
53 | * EMX_RXD - Maximum number of receive Descriptors | |
54 | * Valid Range: 256-4096 for others | |
55 | * Default Value: 512 | |
56 | * This value is the number of receive descriptors allocated by the driver. | |
57 | * Increasing this value allows the driver to buffer more incoming packets. | |
58 | * Each descriptor is 16 bytes. A receive buffer is also allocated for each | |
59 | * descriptor. The maximum MTU size is 16110. | |
60 | * Since TDLEN should be multiple of 128bytes, the number of transmit | |
61 | * desscriptors should meet the following condition. | |
62 | * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | |
63 | */ | |
64 | #define EMX_MIN_RXD 256 | |
65 | #define EMX_MAX_RXD 4096 | |
66 | #define EMX_DEFAULT_RXD 512 | |
67 | ||
68 | /* | |
69 | * Receive Interrupt Delay Timer (Packet Timer) | |
70 | * | |
71 | * NOTE: | |
72 | * RDTR and RADV are deprecated; use ITR instead. They are only used to | |
73 | * workaround hardware bug on certain 82573 based NICs. | |
74 | */ | |
75 | #define EMX_RDTR_82573 32 | |
76 | ||
77 | /* | |
78 | * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) | |
79 | * | |
80 | * NOTE: | |
81 | * RDTR and RADV are deprecated; use ITR instead. They are only used to | |
82 | * workaround hardware bug on certain 82573 based NICs. | |
83 | */ | |
84 | #define EMX_RADV_82573 64 | |
85 | ||
86 | /* | |
87 | * This parameter controls the duration of transmit watchdog timer. | |
88 | */ | |
89 | #define EMX_TX_TIMEOUT 5 | |
90 | ||
dc07210e SZ |
91 | /* One for TX csum offloading desc, the other 2 are reserved */ |
92 | #define EMX_TX_RESERVED 3 | |
5330213c | 93 | |
b1e3f139 SZ |
94 | /* Large enough for 64K TSO segment */ |
95 | #define EMX_TX_SPARE 33 | |
5330213c SZ |
96 | |
97 | #define EMX_TX_OACTIVE_MAX 64 | |
98 | ||
99 | /* Interrupt throttle rate */ | |
3245f71e | 100 | #define EMX_DEFAULT_ITR 6000 |
5330213c SZ |
101 | |
102 | /* | |
103 | * This parameter controls whether or not autonegotation is enabled. | |
104 | * 0 - Disable autonegotiation | |
105 | * 1 - Enable autonegotiation | |
106 | */ | |
107 | #define EMX_DO_AUTO_NEG 1 | |
108 | ||
109 | /* Tunables -- End */ | |
110 | ||
111 | #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ | |
112 | ADVERTISE_10_FULL | \ | |
113 | ADVERTISE_100_HALF | \ | |
114 | ADVERTISE_100_FULL | \ | |
115 | ADVERTISE_1000_FULL) | |
116 | ||
117 | #define EMX_AUTO_ALL_MODES 0 | |
118 | ||
119 | /* PHY master/slave setting */ | |
120 | #define EMX_MASTER_SLAVE e1000_ms_hw_default | |
121 | ||
122 | /* | |
123 | * Micellaneous constants | |
124 | */ | |
125 | #define EMX_VENDOR_ID 0x8086 | |
126 | ||
127 | #define EMX_BAR_MEM PCIR_BAR(0) | |
128 | ||
129 | #define EMX_JUMBO_PBA 0x00000028 | |
130 | #define EMX_DEFAULT_PBA 0x00000030 | |
131 | #define EMX_SMARTSPEED_DOWNSHIFT 3 | |
132 | #define EMX_SMARTSPEED_MAX 15 | |
133 | #define EMX_MAX_INTR 10 | |
134 | ||
135 | #define EMX_MCAST_ADDR_MAX 128 | |
136 | #define EMX_FC_PAUSE_TIME 1000 | |
137 | #define EMX_EEPROM_APME 0x400; | |
138 | ||
139 | /* | |
140 | * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be | |
141 | * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will | |
142 | * also optimize cache line size effect. H/W supports up to cache line size 128. | |
143 | */ | |
144 | #define EMX_DBA_ALIGN 128 | |
145 | ||
146 | /* | |
147 | * Speed mode bit in TARC0/TARC1. | |
148 | * 82571EB/82572EI only, used to improve small packet transmit performance. | |
149 | */ | |
150 | #define EMX_TARC_SPEED_MODE (1 << 21) | |
151 | ||
152 | #define EMX_MAX_SCATTER 64 | |
3eb0ea09 | 153 | #define EMX_TSO_SIZE (IP_MAXPACKET + \ |
5330213c | 154 | sizeof(struct ether_vlan_header)) |
3eb0ea09 | 155 | #define EMX_MAX_SEGSIZE PAGE_SIZE |
5330213c SZ |
156 | #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */ |
157 | ||
158 | #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) | |
5330213c SZ |
159 | |
160 | /* | |
161 | * 82574 has a nonstandard address for EIAC | |
162 | * and since its only used in MSIX, and in | |
163 | * the em driver only 82574 uses MSIX we can | |
164 | * solve it just using this define. | |
165 | */ | |
166 | #define EMX_EIAC 0x000DC | |
167 | ||
3f939c23 | 168 | #define EMX_NRSSRK 10 |
89d8e73d SZ |
169 | #define EMX_RSSRK_SIZE 4 |
170 | #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \ | |
171 | key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \ | |
172 | key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \ | |
173 | key[(i) * EMX_RSSRK_SIZE + 3] << 24) | |
174 | ||
3f939c23 | 175 | #define EMX_NRETA 32 |
89d8e73d SZ |
176 | #define EMX_RETA_SIZE 4 |
177 | #define EMX_RETA_RINGIDX_SHIFT 7 | |
3f939c23 | 178 | |
c39e3a1f | 179 | #define EMX_NRX_RING 2 |
6d435846 | 180 | #define EMX_NSERIALIZE 4 |
c39e3a1f | 181 | |
235b9d30 SZ |
182 | typedef union e1000_rx_desc_extended emx_rxdesc_t; |
183 | ||
184 | #define rxd_bufaddr read.buffer_addr /* 64bits */ | |
185 | #define rxd_length wb.upper.length /* 16bits */ | |
186 | #define rxd_vlan wb.upper.vlan /* 16bits */ | |
187 | #define rxd_staterr wb.upper.status_error /* 32bits */ | |
3f939c23 SZ |
188 | #define rxd_mrq wb.lower.mrq /* 32bits */ |
189 | #define rxd_rss wb.lower.hi_dword.rss /* 32bits */ | |
235b9d30 | 190 | |
9cc86e17 SZ |
191 | #define EMX_RXDMRQ_RSSTYPE_MASK 0xf |
192 | #define EMX_RXDMRQ_NO_HASH 0 | |
193 | #define EMX_RXDMRQ_IPV4_TCP 1 | |
194 | #define EMX_RXDMRQ_IPV4 2 | |
195 | #define EMX_RXDMRQ_IPV6_TCP 3 | |
196 | #define EMX_RXDMRQ_IPV6 5 | |
197 | ||
9f831fa8 SZ |
198 | struct emx_softc; |
199 | ||
c39e3a1f | 200 | struct emx_rxdata { |
6d435846 | 201 | struct lwkt_serialize rx_serialize; |
9f831fa8 SZ |
202 | struct emx_softc *sc; |
203 | int idx; | |
6d435846 | 204 | |
c39e3a1f SZ |
205 | /* |
206 | * Receive definitions | |
207 | * | |
208 | * we have an array of num_rx_desc rx_desc (handled by the | |
209 | * controller), and paired with an array of rx_buffers | |
210 | * (at rx_buffer_area). | |
211 | * The next pair to check on receive is at offset next_rx_desc_to_check | |
212 | */ | |
235b9d30 | 213 | emx_rxdesc_t *rx_desc; |
c39e3a1f SZ |
214 | uint32_t next_rx_desc_to_check; |
215 | int num_rx_desc; | |
323e5ecd | 216 | struct emx_rxbuf *rx_buf; |
c39e3a1f SZ |
217 | bus_dma_tag_t rxtag; |
218 | bus_dmamap_t rx_sparemap; | |
219 | ||
220 | /* | |
221 | * First/last mbuf pointers, for | |
222 | * collecting multisegment RX packets. | |
223 | */ | |
224 | struct mbuf *fmp; | |
225 | struct mbuf *lmp; | |
226 | ||
227 | /* RX statistics */ | |
3f939c23 | 228 | unsigned long rx_pkts; |
c39e3a1f SZ |
229 | |
230 | bus_dma_tag_t rx_desc_dtag; | |
231 | bus_dmamap_t rx_desc_dmap; | |
232 | bus_addr_t rx_desc_paddr; | |
d721525c | 233 | } __cachealign; |
c39e3a1f | 234 | |
5330213c SZ |
235 | struct emx_softc { |
236 | struct arpcom arpcom; | |
237 | struct e1000_hw hw; | |
4cb541ae | 238 | int flags; |
de0836d4 SZ |
239 | #define EMX_FLAG_SHARED_INTR 0x0001 |
240 | #define EMX_FLAG_TSO_PULLEX 0x0002 | |
241 | #define EMX_FLAG_HAS_MGMT 0x0004 | |
242 | #define EMX_FLAG_HAS_AMT 0x0008 | |
243 | #define EMX_FLAG_HW_CTRL 0x0010 | |
5330213c SZ |
244 | |
245 | /* DragonFly operating-system-specific structures. */ | |
246 | struct e1000_osdep osdep; | |
247 | device_t dev; | |
248 | ||
249 | bus_dma_tag_t parent_dtag; | |
a596084c | 250 | |
a596084c SZ |
251 | bus_dma_tag_t tx_desc_dtag; |
252 | bus_dmamap_t tx_desc_dmap; | |
253 | bus_addr_t tx_desc_paddr; | |
5330213c SZ |
254 | |
255 | struct resource *memory; | |
256 | int memory_rid; | |
257 | ||
258 | struct resource *intr_res; | |
259 | void *intr_tag; | |
260 | int intr_rid; | |
704b6287 | 261 | int intr_type; |
5330213c SZ |
262 | |
263 | struct ifmedia media; | |
264 | struct callout timer; | |
265 | int if_flags; | |
266 | int max_frame_size; | |
267 | int min_frame_size; | |
268 | ||
de0836d4 | 269 | /* WOL register value */ |
5330213c | 270 | int wol; |
2d0e5700 SZ |
271 | |
272 | /* Multicast array memory */ | |
273 | uint8_t *mta; | |
5330213c SZ |
274 | |
275 | /* Info about the board itself */ | |
276 | uint8_t link_active; | |
277 | uint16_t link_speed; | |
278 | uint16_t link_duplex; | |
279 | uint32_t smartspeed; | |
280 | int int_throttle_ceil; | |
281 | ||
09f49d52 SZ |
282 | int rx_npoll_off; |
283 | int tx_npoll_off; | |
284 | ||
6d435846 SZ |
285 | struct lwkt_serialize main_serialize; |
286 | struct lwkt_serialize tx_serialize; | |
287 | struct lwkt_serialize *serializes[EMX_NSERIALIZE]; | |
288 | ||
5330213c SZ |
289 | /* |
290 | * Transmit definitions | |
291 | * | |
292 | * We have an array of num_tx_desc descriptors (handled | |
293 | * by the controller) paired with an array of tx_buffers | |
294 | * (at tx_buffer_area). | |
295 | * The index of the next available descriptor is next_avail_tx_desc. | |
296 | * The number of remaining tx_desc is num_tx_desc_avail. | |
297 | */ | |
298 | struct e1000_tx_desc *tx_desc_base; | |
323e5ecd | 299 | struct emx_txbuf *tx_buf; |
5330213c SZ |
300 | uint32_t next_avail_tx_desc; |
301 | uint32_t next_tx_to_clean; | |
302 | int num_tx_desc_avail; | |
303 | int num_tx_desc; | |
304 | bus_dma_tag_t txtag; /* dma tag for tx */ | |
305 | int spare_tx_desc; | |
306 | int oact_tx_desc; | |
307 | ||
308 | /* Saved csum offloading context information */ | |
309 | int csum_flags; | |
3eb0ea09 | 310 | int csum_lhlen; |
5330213c | 311 | int csum_iphlen; |
3eb0ea09 SZ |
312 | |
313 | int csum_thlen; /* TSO */ | |
314 | int csum_mss; /* TSO */ | |
315 | int csum_pktlen; /* TSO */ | |
316 | ||
5330213c SZ |
317 | uint32_t csum_txd_upper; |
318 | uint32_t csum_txd_lower; | |
319 | ||
320 | /* | |
321 | * Variables used to reduce TX interrupt rate and | |
322 | * number of device's TX ring write requests. | |
323 | * | |
324 | * tx_nsegs: | |
325 | * Number of TX descriptors setup so far. | |
326 | * | |
327 | * tx_int_nsegs: | |
328 | * Once tx_nsegs > tx_int_nsegs, RS bit will be set | |
329 | * in the last TX descriptor of the packet, and | |
330 | * tx_nsegs will be reset to 0. So TX interrupt and | |
331 | * TX ring write request should be generated roughly | |
332 | * every tx_int_nsegs TX descriptors. | |
333 | * | |
334 | * tx_dd[]: | |
335 | * Index of the TX descriptors which have RS bit set, | |
336 | * i.e. DD bit will be set on this TX descriptor after | |
337 | * the data of the TX descriptor are transfered to | |
338 | * hardware's internal packet buffer. Only the TX | |
339 | * descriptors listed in tx_dd[] will be checked upon | |
340 | * TX interrupt. This array is used as circular ring. | |
341 | * | |
342 | * tx_dd_tail, tx_dd_head: | |
343 | * Tail and head index of valid elements in tx_dd[]. | |
344 | * tx_dd_tail == tx_dd_head means there is no valid | |
345 | * elements in tx_dd[]. tx_dd_tail points to the position | |
346 | * which is one beyond the last valid element in tx_dd[]. | |
347 | * tx_dd_head points to the first valid element in | |
348 | * tx_dd[]. | |
349 | */ | |
350 | int tx_int_nsegs; | |
351 | int tx_nsegs; | |
352 | int tx_dd_tail; | |
353 | int tx_dd_head; | |
354 | #define EMX_TXDD_MAX 64 | |
355 | #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */ | |
356 | int tx_dd[EMX_TXDD_MAX]; | |
357 | ||
13890b61 SZ |
358 | int rss_debug; |
359 | int rx_ring_cnt; | |
c39e3a1f | 360 | struct emx_rxdata rx_data[EMX_NRX_RING]; |
5330213c SZ |
361 | |
362 | /* Misc stats maintained by the driver */ | |
5330213c | 363 | unsigned long rx_overruns; |
0c0e1638 SZ |
364 | unsigned long tso_segments; |
365 | unsigned long tso_ctx_reused; | |
5330213c SZ |
366 | |
367 | /* sysctl tree glue */ | |
368 | struct sysctl_ctx_list sysctl_ctx; | |
369 | struct sysctl_oid *sysctl_tree; | |
370 | ||
371 | struct e1000_hw_stats stats; | |
372 | }; | |
373 | ||
323e5ecd | 374 | struct emx_txbuf { |
5330213c SZ |
375 | struct mbuf *m_head; |
376 | bus_dmamap_t map; | |
377 | }; | |
378 | ||
323e5ecd SZ |
379 | struct emx_rxbuf { |
380 | struct mbuf *m_head; | |
381 | bus_dmamap_t map; | |
382 | bus_addr_t paddr; | |
383 | }; | |
384 | ||
5330213c SZ |
385 | #define EMX_IS_OACTIVE(sc) ((sc)->num_tx_desc_avail <= (sc)->oact_tx_desc) |
386 | ||
387 | #define EMX_INC_TXDD_IDX(idx) \ | |
388 | do { \ | |
389 | if (++(idx) == EMX_TXDD_MAX) \ | |
390 | (idx) = 0; \ | |
391 | } while (0) | |
392 | ||
393 | #endif /* !_IF_EMX_H_ */ |