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[dragonfly.git] / sys / dev / agp / agp_amd64.c
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1/*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
7f9ec87c 26 * $FreeBSD: src/sys/dev/agp/agp_amd64.c,v 1.17 2009/01/12 16:07:03 jkim Exp $
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27 */
28
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29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/malloc.h>
32#include <sys/kernel.h>
33#include <sys/module.h>
34#include <sys/bus.h>
35#include <sys/lock.h>
36#include <sys/proc.h>
37
38#include <bus/pci/pcivar.h>
39#include <bus/pci/pcireg.h>
40#include "agppriv.h"
41#include "agpreg.h"
42
43#include <vm/vm.h>
44#include <vm/vm_object.h>
45#include <vm/pmap.h>
46#include <sys/rman.h>
47
48/* XXX */
49extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
50extern uint32_t pci_cfgregread(int, int, int, int, int);
51
52static void agp_amd64_apbase_fixup(device_t);
53
54static void agp_amd64_uli_init(device_t);
55static int agp_amd64_uli_set_aperture(device_t, uint32_t);
56
57static int agp_amd64_nvidia_match(uint16_t);
58static void agp_amd64_nvidia_init(device_t);
59static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
60
61static int agp_amd64_via_match(void);
62static void agp_amd64_via_init(device_t);
63static int agp_amd64_via_set_aperture(device_t, uint32_t);
64
65MALLOC_DECLARE(M_AGP);
66
67#define AMD64_MAX_MCTRL 8
68
69struct agp_amd64_softc {
70 struct agp_softc agp;
71 uint32_t initial_aperture;
72 struct agp_gatt *gatt;
73 uint32_t apbase;
74 int mctrl[AMD64_MAX_MCTRL];
75 int n_mctrl;
76 int via_agp;
77};
78
79static const char*
80agp_amd64_match(device_t dev)
81{
82 if (pci_get_class(dev) != PCIC_BRIDGE ||
83 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
84 agp_find_caps(dev) == 0)
85 return (NULL);
86
87 switch (pci_get_devid(dev)) {
88 case 0x74541022:
89 return ("AMD 8151 AGP graphics tunnel");
90 case 0x07551039:
91 return ("SiS 755 host to AGP bridge");
92 case 0x07601039:
93 return ("SiS 760 host to AGP bridge");
94 case 0x168910b9:
95 return ("ULi M1689 AGP Controller");
96 case 0x00d110de:
97 if (agp_amd64_nvidia_match(0x00d2))
98 return (NULL);
99 return ("NVIDIA nForce3 AGP Controller");
100 case 0x00e110de:
101 if (agp_amd64_nvidia_match(0x00e2))
102 return (NULL);
103 return ("NVIDIA nForce3-250 AGP Controller");
104 case 0x02041106:
105 return ("VIA 8380 host to PCI bridge");
106 case 0x02381106:
107 return ("VIA 3238 host to PCI bridge");
108 case 0x02821106:
109 return ("VIA K8T800Pro host to PCI bridge");
110 case 0x31881106:
111 return ("VIA 8385 host to PCI bridge");
0fdb7d01 112 }
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113
114 return (NULL);
115}
116
117static int
118agp_amd64_nvidia_match(uint16_t devid)
119{
120 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
121 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
122 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
123 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
124 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
125 return (ENXIO);
126
127 return (0);
128}
129
130static int
131agp_amd64_via_match(void)
132{
133 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
134 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
135 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
136 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
137 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
138 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
139 return (0);
140
141 return (1);
142}
143
144static int
145agp_amd64_probe(device_t dev)
146{
147 const char *desc;
148
149 if (resource_disabled("agp", device_get_unit(dev)))
150 return (ENXIO);
151 if ((desc = agp_amd64_match(dev))) {
152 device_set_desc(dev, desc);
153 return (BUS_PROBE_DEFAULT);
154 }
155
156 return (ENXIO);
157}
158
159static int
160agp_amd64_attach(device_t dev)
161{
162 struct agp_amd64_softc *sc = device_get_softc(dev);
163 struct agp_gatt *gatt;
7f9ec87c 164 uint32_t devid;
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165 int i, n, error;
166
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167 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
168 devid = pci_cfgregread(0, i, 3, 0, 4);
169 if (devid == 0x11031022 || devid == 0x12031022) {
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170 sc->mctrl[n] = i;
171 n++;
172 }
7f9ec87c 173 }
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174 if (n == 0)
175 return (ENXIO);
176
177 sc->n_mctrl = n;
178
179 if (bootverbose)
180 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
181 sc->n_mctrl);
182
183 if ((error = agp_generic_attach(dev)))
184 return (error);
185
186 sc->initial_aperture = AGP_GET_APERTURE(dev);
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187
188 for (;;) {
189 gatt = agp_alloc_gatt(dev);
190 if (gatt)
191 break;
192
193 /*
194 * Probably contigmalloc failure. Try reducing the
195 * aperture so that the gatt size reduces.
196 */
197 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
198 agp_generic_detach(dev);
199 return (ENOMEM);
200 }
201 }
202 sc->gatt = gatt;
203
204 switch (pci_get_vendor(dev)) {
205 case 0x10b9: /* ULi */
206 agp_amd64_uli_init(dev);
207 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
208 return (ENXIO);
209 break;
210
211 case 0x10de: /* nVidia */
212 agp_amd64_nvidia_init(dev);
213 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
214 return (ENXIO);
215 break;
216
217 case 0x1106: /* VIA */
218 sc->via_agp = agp_amd64_via_match();
219 if (sc->via_agp) {
220 agp_amd64_via_init(dev);
221 if (agp_amd64_via_set_aperture(dev,
222 sc->initial_aperture))
223 return (ENXIO);
224 }
225 break;
226 }
227
228 /* Install the gatt and enable aperture. */
229 for (i = 0; i < sc->n_mctrl; i++) {
230 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
231 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
232 4);
233 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
234 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
235 AGP_AMD64_APCTRL_GARTEN) &
236 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
237 4);
238 }
239
240 agp_flush_cache();
241
242 return (0);
243}
244
245static int
246agp_amd64_detach(device_t dev)
247{
248 struct agp_amd64_softc *sc = device_get_softc(dev);
67e2dc5d 249 int i;
fdc3c5be 250
67e2dc5d 251 agp_free_cdev(dev);
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252
253 for (i = 0; i < sc->n_mctrl; i++)
254 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
255 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
256 ~AGP_AMD64_APCTRL_GARTEN, 4);
257
258 AGP_SET_APERTURE(dev, sc->initial_aperture);
259 agp_free_gatt(sc->gatt);
67e2dc5d 260 agp_free_res(dev);
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261
262 return (0);
263}
264
265static uint32_t agp_amd64_table[] = {
266 0x02000000, /* 32 MB */
267 0x04000000, /* 64 MB */
268 0x08000000, /* 128 MB */
269 0x10000000, /* 256 MB */
270 0x20000000, /* 512 MB */
271 0x40000000, /* 1024 MB */
272 0x80000000, /* 2048 MB */
273};
274
c157ff7a 275#define AGP_AMD64_TABLE_SIZE NELEM(agp_amd64_table)
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276
277static uint32_t
278agp_amd64_get_aperture(device_t dev)
279{
280 struct agp_amd64_softc *sc = device_get_softc(dev);
281 uint32_t i;
282
283 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
284 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
285
286 if (i >= AGP_AMD64_TABLE_SIZE)
287 return (0);
288
289 return (agp_amd64_table[i]);
290}
291
292static int
293agp_amd64_set_aperture(device_t dev, uint32_t aperture)
294{
295 struct agp_amd64_softc *sc = device_get_softc(dev);
296 uint32_t i;
297 int j;
298
299 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
300 if (agp_amd64_table[i] == aperture)
301 break;
302 if (i >= AGP_AMD64_TABLE_SIZE)
303 return (EINVAL);
304
305 for (j = 0; j < sc->n_mctrl; j++)
306 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
307 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
308 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
309
310 switch (pci_get_vendor(dev)) {
311 case 0x10b9: /* ULi */
312 return (agp_amd64_uli_set_aperture(dev, aperture));
313 break;
314
315 case 0x10de: /* nVidia */
316 return (agp_amd64_nvidia_set_aperture(dev, aperture));
317 break;
318
319 case 0x1106: /* VIA */
320 if (sc->via_agp)
321 return (agp_amd64_via_set_aperture(dev, aperture));
322 break;
323 }
324
325 return (0);
326}
327
328static int
7f9ec87c 329agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
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330{
331 struct agp_amd64_softc *sc = device_get_softc(dev);
332
7f9ec87c 333 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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334 return (EINVAL);
335
336 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
337 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
338
339 return (0);
340}
341
342static int
7f9ec87c 343agp_amd64_unbind_page(device_t dev, vm_offset_t offset)
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344{
345 struct agp_amd64_softc *sc = device_get_softc(dev);
346
7f9ec87c 347 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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348 return (EINVAL);
349
350 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
351
352 return (0);
353}
354
355static void
356agp_amd64_flush_tlb(device_t dev)
357{
358 struct agp_amd64_softc *sc = device_get_softc(dev);
359 int i;
360
361 for (i = 0; i < sc->n_mctrl; i++)
362 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
363 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
364 AGP_AMD64_CACHECTRL_INVGART, 4);
365}
366
367static void
368agp_amd64_apbase_fixup(device_t dev)
369{
370 struct agp_amd64_softc *sc = device_get_softc(dev);
371 uint32_t apbase;
372 int i;
373
374 sc->apbase = rman_get_start(sc->agp.as_aperture);
375 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
376 for (i = 0; i < sc->n_mctrl; i++)
377 pci_cfgregwrite(0, sc->mctrl[i], 3,
378 AGP_AMD64_APBASE, apbase, 4);
379}
380
381static void
382agp_amd64_uli_init(device_t dev)
383{
384 struct agp_amd64_softc *sc = device_get_softc(dev);
385
386 agp_amd64_apbase_fixup(dev);
387 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
388 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
389 sc->apbase, 4);
390 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
391}
392
393static int
394agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
395{
396 struct agp_amd64_softc *sc = device_get_softc(dev);
397
398 switch (aperture) {
399 case 0x02000000: /* 32 MB */
400 case 0x04000000: /* 64 MB */
401 case 0x08000000: /* 128 MB */
402 case 0x10000000: /* 256 MB */
403 break;
404 default:
405 return (EINVAL);
406 }
407
408 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
409 sc->apbase + aperture - 1, 4);
410
411 return (0);
412}
413
414static void
415agp_amd64_nvidia_init(device_t dev)
416{
417 struct agp_amd64_softc *sc = device_get_softc(dev);
418
419 agp_amd64_apbase_fixup(dev);
420 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
421 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
422 sc->apbase, 4);
423 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
424 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
425}
426
427static int
428agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
429{
430 struct agp_amd64_softc *sc = device_get_softc(dev);
431 uint32_t apsize;
432
433 switch (aperture) {
434 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
435 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
436 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
437 case 0x10000000: apsize = 0x08; break; /* 256 MB */
438 case 0x20000000: apsize = 0x00; break; /* 512 MB */
439 default:
440 return (EINVAL);
441 }
442
443 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
444 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
445 0xfffffff0) | apsize, 4);
446 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
447 sc->apbase + aperture - 1, 4);
448 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
449 sc->apbase + aperture - 1, 4);
450
451 return (0);
452}
453
454static void
455agp_amd64_via_init(device_t dev)
456{
457 struct agp_amd64_softc *sc = device_get_softc(dev);
458
459 agp_amd64_apbase_fixup(dev);
460 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
461 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
462 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
463}
464
465static int
466agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
467{
468 uint32_t apsize;
469
470 apsize = ((aperture - 1) >> 20) ^ 0xff;
471 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
472 return (EINVAL);
473 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
474
475 return (0);
476}
477
478static device_method_t agp_amd64_methods[] = {
479 /* Device interface */
480 DEVMETHOD(device_probe, agp_amd64_probe),
481 DEVMETHOD(device_attach, agp_amd64_attach),
482 DEVMETHOD(device_detach, agp_amd64_detach),
483 DEVMETHOD(device_shutdown, bus_generic_shutdown),
484 DEVMETHOD(device_suspend, bus_generic_suspend),
485 DEVMETHOD(device_resume, bus_generic_resume),
486
487 /* AGP interface */
488 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
489 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
490 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
491 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
492 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
493 DEVMETHOD(agp_enable, agp_generic_enable),
494 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
495 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
496 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
497 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
498
d3c9c58e 499 DEVMETHOD_END
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500};
501
502static driver_t agp_amd64_driver = {
503 "agp",
504 agp_amd64_methods,
505 sizeof(struct agp_amd64_softc),
506};
507
508static devclass_t agp_devclass;
509
aa2b9d05 510DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, NULL, NULL);
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511MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
512MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);