alc: Stablize this driver and fix various porting overlooks
[dragonfly.git] / sys / dev / netif / alc / if_alc.c
CommitLineData
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1/*-
2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $
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28 */
29
30/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
31
bbf76eec 32#include <sys/param.h>
a0e18bfd 33#include <sys/bitops.h>
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34#include <sys/endian.h>
35#include <sys/kernel.h>
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36#include <sys/bus.h>
37#include <sys/interrupt.h>
bbf76eec 38#include <sys/malloc.h>
a0e18bfd 39#include <sys/proc.h>
bbf76eec 40#include <sys/rman.h>
a0e18bfd 41#include <sys/serialize.h>
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42#include <sys/socket.h>
43#include <sys/sockio.h>
44#include <sys/sysctl.h>
bbf76eec 45
a0e18bfd 46#include <net/ethernet.h>
bbf76eec 47#include <net/if.h>
a0e18bfd 48#include <net/bpf.h>
bbf76eec 49#include <net/if_arp.h>
bbf76eec 50#include <net/if_dl.h>
bbf76eec 51#include <net/if_media.h>
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52#include <net/ifq_var.h>
53#include <net/vlan/if_vlan_var.h>
54#include <net/vlan/if_vlan_ether.h>
55
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56#include <netinet/tcp.h>
57
58#include <dev/netif/mii_layer/mii.h>
59#include <dev/netif/mii_layer/miivar.h>
60
61#include <bus/pci/pcireg.h>
62#include <bus/pci/pcivar.h>
a0e18bfd 63#include <bus/pci/pcidevs.h>
bbf76eec 64
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65#include <dev/netif/alc/if_alcreg.h>
66#include <dev/netif/alc/if_alcvar.h>
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67
68/* "device miibus" required. See GENERIC if you get errors here. */
69#include "miibus_if.h"
bbf76eec 70
a0e18bfd 71#undef ALC_USE_CUSTOM_CSUM
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72#ifdef ALC_USE_CUSTOM_CSUM
73#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
74#else
75#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
76#endif
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77
78/* Tunables. */
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79static int alc_msi_enable = 1;
80TUNABLE_INT("hw.alc.msi.enable", &alc_msi_enable);
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81
82/*
83 * Devices supported by this driver.
84 */
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85
86static struct alc_ident alc_ident_table[] = {
87 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024,
bbf76eec 88 "Atheros AR8131 PCIe Gigabit Ethernet" },
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89 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024,
90 "Atheros AR8132 PCIe Fast Ethernet" },
91 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024,
92 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
93 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024,
94 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
95 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024,
96 "Atheros AR8152 v1.1 PCIe Fast Ethernet" },
97 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
98 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
a0e18bfd 99 { 0, 0, 0, NULL }
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100};
101
bbf76eec 102static int alc_attach(device_t);
a0e18bfd 103static int alc_probe(device_t);
bbf76eec 104static int alc_detach(device_t);
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105static int alc_shutdown(device_t);
106static int alc_suspend(device_t);
107static int alc_resume(device_t);
108static int alc_miibus_readreg(device_t, int, int);
109static void alc_miibus_statchg(device_t);
110static int alc_miibus_writereg(device_t, int, int, int);
111
112static void alc_init(void *);
113static void alc_start(struct ifnet *);
114static void alc_watchdog(struct alc_softc *);
115static int alc_mediachange(struct ifnet *);
116static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
117static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
118
119static void alc_aspm(struct alc_softc *, int);
120#ifdef foo
121static int alc_check_boundary(struct alc_softc *);
122#endif
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123static void alc_disable_l0s_l1(struct alc_softc *);
124static int alc_dma_alloc(struct alc_softc *);
125static void alc_dma_free(struct alc_softc *);
126static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
127static int alc_encap(struct alc_softc *, struct mbuf **);
cffbd125 128static struct alc_ident *alc_find_ident(device_t);
bbf76eec 129static void alc_get_macaddr(struct alc_softc *);
bbf76eec 130static void alc_init_cmb(struct alc_softc *);
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131static void alc_init_rr_ring(struct alc_softc *);
132static int alc_init_rx_ring(struct alc_softc *);
133static void alc_init_smb(struct alc_softc *);
134static void alc_init_tx_ring(struct alc_softc *);
bbf76eec 135static void alc_intr(void *);
bbf76eec 136static void alc_mac_config(struct alc_softc *);
a0e18bfd 137static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, boolean_t);
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138static void alc_phy_down(struct alc_softc *);
139static void alc_phy_reset(struct alc_softc *);
bbf76eec 140static void alc_reset(struct alc_softc *);
bbf76eec 141static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
a0e18bfd 142static int alc_rxintr(struct alc_softc *);
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143static void alc_rxfilter(struct alc_softc *);
144static void alc_rxvlan(struct alc_softc *);
bbf76eec 145#if 0
f753ef49 146static void alc_setlinkspeed(struct alc_softc *);
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147/* XXX: WOL */
148static void alc_setwol(struct alc_softc *);
149#endif
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150static void alc_start_queue(struct alc_softc *);
151static void alc_stats_clear(struct alc_softc *);
152static void alc_stats_update(struct alc_softc *);
153static void alc_stop(struct alc_softc *);
154static void alc_stop_mac(struct alc_softc *);
155static void alc_stop_queue(struct alc_softc *);
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156static void alc_sysctl_node(struct alc_softc *);
157static void alc_tick(void *);
bbf76eec 158static void alc_txeof(struct alc_softc *);
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159static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
160static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
161
162static device_method_t alc_methods[] = {
163 /* Device interface. */
164 DEVMETHOD(device_probe, alc_probe),
165 DEVMETHOD(device_attach, alc_attach),
166 DEVMETHOD(device_detach, alc_detach),
167 DEVMETHOD(device_shutdown, alc_shutdown),
168 DEVMETHOD(device_suspend, alc_suspend),
169 DEVMETHOD(device_resume, alc_resume),
170
171 /* MII interface. */
172 DEVMETHOD(miibus_readreg, alc_miibus_readreg),
173 DEVMETHOD(miibus_writereg, alc_miibus_writereg),
174 DEVMETHOD(miibus_statchg, alc_miibus_statchg),
175
176 { NULL, NULL }
177};
178
a0e18bfd 179static DEFINE_CLASS_0(alc, alc_driver, alc_methods, sizeof(struct alc_softc));
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180static devclass_t alc_devclass;
181
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182DECLARE_DUMMY_MODULE(if_alc);
183DRIVER_MODULE(if_alc, pci, alc_driver, alc_devclass, NULL, NULL);
aa2b9d05 184DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, NULL, NULL);
bbf76eec 185
a0e18bfd 186static const uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
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187
188static int
189alc_miibus_readreg(device_t dev, int phy, int reg)
190{
191 struct alc_softc *sc;
192 uint32_t v;
193 int i;
194
195 sc = device_get_softc(dev);
196
197 if (phy != sc->alc_phyaddr)
198 return (0);
199
200 /*
201 * For AR8132 fast ethernet controller, do not report 1000baseT
202 * capability to mii(4). Even though AR8132 uses the same
203 * model/revision number of F1 gigabit PHY, the PHY has no
204 * ability to establish 1000baseT link.
205 */
206 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
207 reg == MII_EXTSR)
208 return (0);
209
210 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
212 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
213 DELAY(5);
214 v = CSR_READ_4(sc, ALC_MDIO);
215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
216 break;
217 }
218
219 if (i == 0) {
220 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
221 return (0);
222 }
223
224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
225}
226
227static int
228alc_miibus_writereg(device_t dev, int phy, int reg, int val)
229{
230 struct alc_softc *sc;
231 uint32_t v;
232 int i;
233
234 sc = device_get_softc(dev);
235
236 if (phy != sc->alc_phyaddr)
237 return (0);
238
239 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
240 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
241 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
242 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
243 DELAY(5);
244 v = CSR_READ_4(sc, ALC_MDIO);
245 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
246 break;
247 }
248
249 if (i == 0)
250 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
251
252 return (0);
253}
254
255static void
256alc_miibus_statchg(device_t dev)
257{
258 struct alc_softc *sc;
259 struct mii_data *mii;
260 struct ifnet *ifp;
261 uint32_t reg;
262
263 sc = device_get_softc(dev);
264
265 mii = device_get_softc(sc->alc_miibus);
266 ifp = sc->alc_ifp;
267 if (mii == NULL || ifp == NULL ||
268 (ifp->if_flags & IFF_RUNNING) == 0)
269 return;
270
271 sc->alc_flags &= ~ALC_FLAG_LINK;
272 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
273 (IFM_ACTIVE | IFM_AVALID)) {
274 switch (IFM_SUBTYPE(mii->mii_media_active)) {
275 case IFM_10_T:
276 case IFM_100_TX:
277 sc->alc_flags |= ALC_FLAG_LINK;
278 break;
279 case IFM_1000_T:
280 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
281 sc->alc_flags |= ALC_FLAG_LINK;
282 break;
283 default:
284 break;
285 }
286 }
287 alc_stop_queue(sc);
288 /* Stop Rx/Tx MACs. */
289 alc_stop_mac(sc);
290
291 /* Program MACs with resolved speed/duplex/flow-control. */
292 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
293 alc_start_queue(sc);
294 alc_mac_config(sc);
295 /* Re-enable Tx/Rx MACs. */
296 reg = CSR_READ_4(sc, ALC_MAC_CFG);
297 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
298 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
299 }
cffbd125 300 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
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301}
302
303static void
304alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
305{
306 struct alc_softc *sc;
307 struct mii_data *mii;
308
309 sc = ifp->if_softc;
a0e18bfd 310 if ((ifp->if_flags & IFF_UP) == 0)
bbf76eec 311 return;
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312 mii = device_get_softc(sc->alc_miibus);
313
314 mii_pollstat(mii);
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315 ifmr->ifm_status = mii->mii_media_status;
316 ifmr->ifm_active = mii->mii_media_active;
317}
318
319static int
320alc_mediachange(struct ifnet *ifp)
321{
322 struct alc_softc *sc;
323 struct mii_data *mii;
324 struct mii_softc *miisc;
325 int error;
326
327 sc = ifp->if_softc;
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328 mii = device_get_softc(sc->alc_miibus);
329 if (mii->mii_instance != 0) {
330 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
331 mii_phy_reset(miisc);
332 }
333 error = mii_mediachg(mii);
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334
335 return (error);
336}
337
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338static struct alc_ident *
339alc_find_ident(device_t dev)
bbf76eec 340{
cffbd125 341 struct alc_ident *ident;
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342 uint16_t vendor, devid;
343
344 vendor = pci_get_vendor(dev);
345 devid = pci_get_device(dev);
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346 for (ident = alc_ident_table; ident->name != NULL; ident++) {
347 if (vendor == ident->vendorid && devid == ident->deviceid)
348 return (ident);
bbf76eec 349 }
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350 return (NULL);
351}
bbf76eec 352
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353static int
354alc_probe(device_t dev)
355{
356 struct alc_ident *ident;
357
358 ident = alc_find_ident(dev);
359 if (ident != NULL) {
360 device_set_desc(dev, ident->name);
361 return (BUS_PROBE_DEFAULT);
362 }
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363 return (ENXIO);
364}
365
366static void
367alc_get_macaddr(struct alc_softc *sc)
368{
369 uint32_t ea[2], opt;
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370 uint16_t val;
371 int eeprom, i;
bbf76eec 372
cffbd125 373 eeprom = 0;
bbf76eec 374 opt = CSR_READ_4(sc, ALC_OPT_CFG);
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375 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
376 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
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377 /*
378 * EEPROM found, let TWSI reload EEPROM configuration.
379 * This will set ethernet address of controller.
380 */
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381 eeprom++;
382 switch (sc->alc_ident->deviceid) {
383 case DEVICEID_ATHEROS_AR8131:
384 case DEVICEID_ATHEROS_AR8132:
385 if ((opt & OPT_CFG_CLK_ENB) == 0) {
386 opt |= OPT_CFG_CLK_ENB;
387 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
388 CSR_READ_4(sc, ALC_OPT_CFG);
389 DELAY(1000);
390 }
391 break;
392 case DEVICEID_ATHEROS_AR8151:
393 case DEVICEID_ATHEROS_AR8151_V2:
394 case DEVICEID_ATHEROS_AR8152_B:
395 case DEVICEID_ATHEROS_AR8152_B2:
396 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
397 ALC_MII_DBG_ADDR, 0x00);
398 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
399 ALC_MII_DBG_DATA);
400 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
401 ALC_MII_DBG_DATA, val & 0xFF7F);
402 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
403 ALC_MII_DBG_ADDR, 0x3B);
404 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
405 ALC_MII_DBG_DATA);
406 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
407 ALC_MII_DBG_DATA, val | 0x0008);
408 DELAY(20);
409 break;
bbf76eec 410 }
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411
412 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
413 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
414 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
415 CSR_READ_4(sc, ALC_WOL_CFG);
416
bbf76eec 417 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
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418 TWSI_CFG_SW_LD_START);
419
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420 for (i = 100; i > 0; i--) {
421 DELAY(1000);
422 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
423 TWSI_CFG_SW_LD_START) == 0)
424 break;
425 }
426 if (i == 0)
427 device_printf(sc->alc_dev,
428 "reloading EEPROM timeout!\n");
429 } else {
430 if (bootverbose)
431 device_printf(sc->alc_dev, "EEPROM not found!\n");
432 }
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433
434 if (eeprom != 0) {
435 switch (sc->alc_ident->deviceid) {
436 case DEVICEID_ATHEROS_AR8131:
437 case DEVICEID_ATHEROS_AR8132:
438 if ((opt & OPT_CFG_CLK_ENB) != 0) {
439 opt &= ~OPT_CFG_CLK_ENB;
440 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
441 CSR_READ_4(sc, ALC_OPT_CFG);
442 DELAY(1000);
443 }
444 break;
445 case DEVICEID_ATHEROS_AR8151:
446 case DEVICEID_ATHEROS_AR8151_V2:
447 case DEVICEID_ATHEROS_AR8152_B:
448 case DEVICEID_ATHEROS_AR8152_B2:
449 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
450 ALC_MII_DBG_ADDR, 0x00);
451 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
452 ALC_MII_DBG_DATA);
453 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
454 ALC_MII_DBG_DATA, val | 0x0080);
455 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
456 ALC_MII_DBG_ADDR, 0x3B);
457 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
458 ALC_MII_DBG_DATA);
459 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
460 ALC_MII_DBG_DATA, val & 0xFFF7);
461 DELAY(20);
462 break;
463 }
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464 }
465
466 ea[0] = CSR_READ_4(sc, ALC_PAR0);
467 ea[1] = CSR_READ_4(sc, ALC_PAR1);
468 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
469 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
470 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
471 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
472 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
473 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
474}
475
476static void
477alc_disable_l0s_l1(struct alc_softc *sc)
478{
479 uint32_t pmcfg;
480
481 /* Another magic from vendor. */
482 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
483 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
484 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK |
485 PM_CFG_SERDES_PD_EX_L1);
486 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
487 PM_CFG_SERDES_L1_ENB;
488 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
489}
490
491static void
492alc_phy_reset(struct alc_softc *sc)
493{
494 uint16_t data;
495
496 /* Reset magic from Linux. */
497 CSR_WRITE_2(sc, ALC_GPHY_CFG,
498 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET);
499 CSR_READ_2(sc, ALC_GPHY_CFG);
500 DELAY(10 * 1000);
501
502 CSR_WRITE_2(sc, ALC_GPHY_CFG,
503 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
504 GPHY_CFG_SEL_ANA_RESET);
505 CSR_READ_2(sc, ALC_GPHY_CFG);
506 DELAY(10 * 1000);
507
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508 /* DSP fixup, Vendor magic. */
509 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
510 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
511 ALC_MII_DBG_ADDR, 0x000A);
512 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
513 ALC_MII_DBG_DATA);
514 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
515 ALC_MII_DBG_DATA, data & 0xDFFF);
516 }
517 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
518 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
519 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
520 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
521 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
522 ALC_MII_DBG_ADDR, 0x003B);
523 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
524 ALC_MII_DBG_DATA);
525 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
526 ALC_MII_DBG_DATA, data & 0xFFF7);
527 DELAY(20 * 1000);
528 }
529 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) {
530 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
531 ALC_MII_DBG_ADDR, 0x0029);
532 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
533 ALC_MII_DBG_DATA, 0x929D);
534 }
535 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
536 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 ||
537 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
538 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
539 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
540 ALC_MII_DBG_ADDR, 0x0029);
541 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
542 ALC_MII_DBG_DATA, 0xB6DD);
543 }
544
bbf76eec
MD
545 /* Load DSP codes, vendor magic. */
546 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
547 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
548 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
549 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
550 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
551 ALC_MII_DBG_DATA, data);
552
553 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
554 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
555 ANA_SERDES_EN_LCKDT;
556 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
557 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
558 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
559 ALC_MII_DBG_DATA, data);
560
561 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
562 ANA_LONG_CABLE_TH_100_MASK) |
563 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
564 ANA_SHORT_CABLE_TH_100_SHIFT) |
565 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
566 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
567 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
568 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
569 ALC_MII_DBG_DATA, data);
570
571 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
572 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
573 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
574 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
575 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
576 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
577 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
578 ALC_MII_DBG_DATA, data);
579
580 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
581 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
582 ANA_OEN_125M;
583 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
584 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
585 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
586 ALC_MII_DBG_DATA, data);
587 DELAY(1000);
588}
589
590static void
591alc_phy_down(struct alc_softc *sc)
592{
cffbd125
MD
593 switch (sc->alc_ident->deviceid) {
594 case DEVICEID_ATHEROS_AR8151:
595 case DEVICEID_ATHEROS_AR8151_V2:
596 /*
597 * GPHY power down caused more problems on AR8151 v2.0.
598 * When driver is reloaded after GPHY power down,
599 * accesses to PHY/MAC registers hung the system. Only
600 * cold boot recovered from it. I'm not sure whether
601 * AR8151 v1.0 also requires this one though. I don't
602 * have AR8151 v1.0 controller in hand.
603 * The only option left is to isolate the PHY and
604 * initiates power down the PHY which in turn saves
605 * more power when driver is unloaded.
606 */
607 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
608 MII_BMCR, BMCR_ISO | BMCR_PDOWN);
609 break;
610 default:
611 /* Force PHY down. */
612 CSR_WRITE_2(sc, ALC_GPHY_CFG,
613 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
614 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
615 GPHY_CFG_PWDOWN_HW);
616 DELAY(1000);
617 break;
618 }
bbf76eec 619
bbf76eec
MD
620}
621
622static void
cffbd125 623alc_aspm(struct alc_softc *sc, int media)
bbf76eec
MD
624{
625 uint32_t pmcfg;
cffbd125 626 uint16_t linkcfg;
bbf76eec 627
bbf76eec 628 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
cffbd125
MD
629 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
630 (ALC_FLAG_APS | ALC_FLAG_PCIE)) {
631 linkcfg = CSR_READ_2(sc, sc->alc_expcap +
632 PCIR_EXPRESS_LINK_CTL);
633 } else {
634 linkcfg = 0;
635 }
636
bbf76eec 637 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
cffbd125 638 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
bbf76eec 639 pmcfg |= PM_CFG_MAC_ASPM_CHK;
cffbd125
MD
640 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB;
641 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
642
643 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
644 /* Disable extended sync except AR8152 B v1.0 */
645 linkcfg &= ~0x80;
646 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
647 sc->alc_rev == ATHEROS_AR8152_B_V10)
648 linkcfg |= 0x80;
649 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL,
650 linkcfg);
651 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
652 PM_CFG_HOTRST);
653 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
654 PM_CFG_L1_ENTRY_TIMER_SHIFT);
655 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
656 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
657 PM_CFG_PM_REQ_TIMER_SHIFT);
658 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
659 }
660
bbf76eec 661 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
cffbd125
MD
662 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
663 pmcfg |= PM_CFG_ASPM_L0S_ENB;
664 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
665 pmcfg |= PM_CFG_ASPM_L1_ENB;
666 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
667 if (sc->alc_ident->deviceid ==
668 DEVICEID_ATHEROS_AR8152_B) {
669 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
670 }
671 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
672 PM_CFG_SERDES_PLL_L1_ENB |
673 PM_CFG_SERDES_BUDS_RX_L1_ENB);
674 pmcfg |= PM_CFG_CLK_SWH_L1;
675 if (media == IFM_100_TX || media == IFM_1000_T) {
676 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
677 switch (sc->alc_ident->deviceid) {
678 case DEVICEID_ATHEROS_AR8152_B:
679 pmcfg |= (7 <<
680 PM_CFG_L1_ENTRY_TIMER_SHIFT);
681 break;
682 case DEVICEID_ATHEROS_AR8152_B2:
683 case DEVICEID_ATHEROS_AR8151_V2:
684 pmcfg |= (4 <<
685 PM_CFG_L1_ENTRY_TIMER_SHIFT);
686 break;
687 default:
688 pmcfg |= (15 <<
689 PM_CFG_L1_ENTRY_TIMER_SHIFT);
690 break;
691 }
692 }
693 } else {
694 pmcfg |= PM_CFG_SERDES_L1_ENB |
695 PM_CFG_SERDES_PLL_L1_ENB |
696 PM_CFG_SERDES_BUDS_RX_L1_ENB;
697 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
698 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
699 }
bbf76eec 700 } else {
cffbd125
MD
701 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
702 PM_CFG_SERDES_PLL_L1_ENB);
bbf76eec 703 pmcfg |= PM_CFG_CLK_SWH_L1;
cffbd125
MD
704 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
705 pmcfg |= PM_CFG_ASPM_L1_ENB;
bbf76eec
MD
706 }
707 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
708}
709
710static int
711alc_attach(device_t dev)
712{
713 struct alc_softc *sc;
714 struct ifnet *ifp;
a0e18bfd 715 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
bbf76eec 716 uint16_t burst;
a0e18bfd 717 int base, error, state;
bbf76eec 718 uint32_t cap, ctl, val;
a0e18bfd 719 u_int intr_flags;
bbf76eec
MD
720
721 error = 0;
722 sc = device_get_softc(dev);
723 sc->alc_dev = dev;
724
f753ef49 725 callout_init_mp(&sc->alc_tick_ch);
cffbd125 726 sc->alc_ident = alc_find_ident(dev);
bbf76eec 727
a0e18bfd 728 /* Enable bus mastering */
bbf76eec 729 pci_enable_busmaster(dev);
a0e18bfd
SZ
730
731 /* Map the device. */
732 sc->alc_res_rid = PCIR_BAR(0);
733 sc->alc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
734 &sc->alc_res_rid, RF_ACTIVE);
bbf76eec
MD
735 if (error != 0) {
736 device_printf(dev, "cannot allocate memory resources.\n");
737 goto fail;
738 }
a0e18bfd
SZ
739 sc->alc_res_btag = rman_get_bustag(sc->alc_res);
740 sc->alc_res_bhand = rman_get_bushandle(sc->alc_res);
bbf76eec
MD
741
742 /* Set PHY address. */
743 sc->alc_phyaddr = ALC_PHY_ADDR;
744
745 /* Initialize DMA parameters. */
746 sc->alc_dma_rd_burst = 0;
747 sc->alc_dma_wr_burst = 0;
748 sc->alc_rcb = DMA_CFG_RCB_64;
749 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
750 sc->alc_flags |= ALC_FLAG_PCIE;
cffbd125 751 sc->alc_expcap = base;
bbf76eec
MD
752 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
753 sc->alc_dma_rd_burst =
754 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12;
755 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5;
756 if (bootverbose) {
757 device_printf(dev, "Read request size : %u bytes.\n",
758 alc_dma_burst[sc->alc_dma_rd_burst]);
759 device_printf(dev, "TLP payload size : %u bytes.\n",
760 alc_dma_burst[sc->alc_dma_wr_burst]);
761 }
cffbd125
MD
762 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
763 sc->alc_dma_rd_burst = 3;
764 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
765 sc->alc_dma_wr_burst = 3;
bbf76eec
MD
766 /* Clear data link and flow-control protocol error. */
767 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
768 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
769 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
cffbd125
MD
770 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
771 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
772 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
773 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
774 PCIE_PHYMISC_FORCE_RCV_DET);
775 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
776 sc->alc_rev == ATHEROS_AR8152_B_V10) {
777 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
778 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
779 PCIE_PHYMISC2_SERDES_TH_MASK);
780 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
781 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
782 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
783 }
784
bbf76eec
MD
785 /* Disable ASPM L0S and L1. */
786 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP);
787 if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
788 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL);
789 if ((ctl & 0x08) != 0)
790 sc->alc_rcb = DMA_CFG_RCB_128;
791 if (bootverbose)
792 device_printf(dev, "RCB %u bytes\n",
793 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
794 state = ctl & 0x03;
cffbd125
MD
795 if (state & 0x01)
796 sc->alc_flags |= ALC_FLAG_L0S;
797 if (state & 0x02)
798 sc->alc_flags |= ALC_FLAG_L1S;
bbf76eec
MD
799 if (bootverbose)
800 device_printf(sc->alc_dev, "ASPM %s %s\n",
801 aspm_state[state],
802 state == 0 ? "disabled" : "enabled");
cffbd125
MD
803 alc_disable_l0s_l1(sc);
804 } else {
805 if (bootverbose)
806 device_printf(sc->alc_dev, "no ASPM support\n");
bbf76eec
MD
807 }
808 }
809
810 /* Reset PHY. */
811 alc_phy_reset(sc);
812
813 /* Reset the ethernet controller. */
814 alc_reset(sc);
815
816 /*
817 * One odd thing is AR8132 uses the same PHY hardware(F1
818 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
819 * the PHY supports 1000Mbps but that's not true. The PHY
820 * used in AR8132 can't establish gigabit link even if it
821 * shows the same PHY model/revision number of AR8131.
822 */
cffbd125
MD
823 switch (sc->alc_ident->deviceid) {
824 case DEVICEID_ATHEROS_AR8152_B:
825 case DEVICEID_ATHEROS_AR8152_B2:
826 sc->alc_flags |= ALC_FLAG_APS;
827 /* FALLTHROUGH */
828 case DEVICEID_ATHEROS_AR8132:
829 sc->alc_flags |= ALC_FLAG_FASTETHER;
830 break;
831 case DEVICEID_ATHEROS_AR8151:
832 case DEVICEID_ATHEROS_AR8151_V2:
833 sc->alc_flags |= ALC_FLAG_APS;
834 /* FALLTHROUGH */
835 default:
836 break;
837 }
838 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
839
bbf76eec 840 /*
cffbd125 841 * It seems that AR813x/AR815x has silicon bug for SMB. In
bbf76eec
MD
842 * addition, Atheros said that enabling SMB wouldn't improve
843 * performance. However I think it's bad to access lots of
844 * registers to extract MAC statistics.
845 */
846 sc->alc_flags |= ALC_FLAG_SMB_BUG;
cffbd125 847
bbf76eec
MD
848 /*
849 * Don't use Tx CMB. It is known to have silicon bug.
850 */
851 sc->alc_flags |= ALC_FLAG_CMB_BUG;
852 sc->alc_rev = pci_get_revid(dev);
853 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
854 MASTER_CHIP_REV_SHIFT;
855 if (bootverbose) {
856 device_printf(dev, "PCI device revision : 0x%04x\n",
857 sc->alc_rev);
858 device_printf(dev, "Chip id/revision : 0x%04x\n",
859 sc->alc_chip_rev);
860 }
861 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
862 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
863 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
864
a0e18bfd
SZ
865 sc->alc_irq_type = pci_alloc_1intr(dev, alc_msi_enable,
866 &sc->alc_irq_rid, &intr_flags);
bbf76eec 867
a0e18bfd
SZ
868 /* Allocate IRQ resources. */
869 sc->alc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
870 &sc->alc_irq_rid, intr_flags);
bbf76eec
MD
871 if (error != 0) {
872 device_printf(dev, "cannot allocate IRQ resources.\n");
873 goto fail;
874 }
875
876 /* Create device sysctl node. */
877 alc_sysctl_node(sc);
878
879 if ((error = alc_dma_alloc(sc) != 0))
880 goto fail;
881
882 /* Load station address. */
883 alc_get_macaddr(sc);
884
885 ifp = sc->alc_ifp = &sc->arpcom.ac_if;
886 ifp->if_softc = sc;
887 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
888 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
889 ifp->if_ioctl = alc_ioctl;
890 ifp->if_start = alc_start;
891 ifp->if_init = alc_init;
a0e18bfd 892 ifq_set_maxlen(&ifp->if_snd, ALC_TX_RING_CNT - 1);
bbf76eec 893 ifq_set_ready(&ifp->if_snd);
a0e18bfd
SZ
894 ifp->if_capabilities = IFCAP_TXCSUM;
895 ifp->if_hwassist = ALC_CSUM_FEATURES;
bbf76eec
MD
896#if 0
897/* XXX: WOL */
cffbd125 898 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
bbf76eec 899 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
cffbd125
MD
900 sc->alc_flags |= ALC_FLAG_PM;
901 sc->alc_pmcap = base;
902 }
bbf76eec
MD
903#endif
904 ifp->if_capenable = ifp->if_capabilities;
905
bbf76eec
MD
906 /* VLAN capability setup. */
907 ifp->if_capabilities |= IFCAP_VLAN_MTU;
908 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
909 ifp->if_capenable = ifp->if_capabilities;
a0e18bfd 910
bbf76eec
MD
911 /*
912 * XXX
913 * It seems enabling Tx checksum offloading makes more trouble.
914 * Sometimes the controller does not receive any frames when
915 * Tx checksum offloading is enabled. I'm not sure whether this
916 * is a bug in Tx checksum offloading logic or I got broken
917 * sample boards. To safety, don't enable Tx checksum offloading
918 * by default but give chance to users to toggle it if they know
919 * their controllers work without problems.
920 */
921 ifp->if_capenable &= ~IFCAP_TXCSUM;
922 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
923
a0e18bfd
SZ
924 /* Set up MII bus. */
925 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange,
926 alc_mediastatus)) != 0) {
927 device_printf(dev, "no PHY found!\n");
928 goto fail;
929 }
930
931 ether_ifattach(ifp, sc->alc_eaddr, NULL);
932
bbf76eec
MD
933 /* Tell the upper layer(s) we support long frames. */
934 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
935
a0e18bfd 936#if 0
bbf76eec
MD
937 /* Create local taskq. */
938 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp);
939 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK,
f753ef49 940 taskqueue_thread_enqueue, &sc->alc_tq);
bbf76eec
MD
941 if (sc->alc_tq == NULL) {
942 device_printf(dev, "could not create taskqueue.\n");
943 ether_ifdetach(ifp);
944 error = ENXIO;
945 goto fail;
946 }
947 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq",
948 device_get_nameunit(sc->alc_dev));
949
950 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
951 msic = ALC_MSIX_MESSAGES;
952 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
953 msic = ALC_MSI_MESSAGES;
954 else
955 msic = 1;
956 for (i = 0; i < msic; i++) {
957 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE,
f753ef49
MD
958 alc_intr, sc,
959 &sc->alc_intrhand[i], NULL);
bbf76eec
MD
960 if (error != 0)
961 break;
962 }
963 if (error != 0) {
964 device_printf(dev, "could not set up interrupt handler.\n");
965 taskqueue_free(sc->alc_tq);
966 sc->alc_tq = NULL;
967 ether_ifdetach(ifp);
968 goto fail;
969 }
a0e18bfd
SZ
970#else
971 error = bus_setup_intr(dev, sc->alc_irq, INTR_MPSAFE, alc_intr, sc,
972 &sc->alc_intrhand, ifp->if_serializer);
973 if (error) {
974 device_printf(dev, "could not set up interrupt handler.\n");
975 ether_ifdetach(ifp);
976 goto fail;
977 }
978#endif
bbf76eec
MD
979
980fail:
981 if (error != 0)
982 alc_detach(dev);
983
984 return (error);
985}
986
987static int
988alc_detach(device_t dev)
989{
a0e18bfd 990 struct alc_softc *sc = device_get_softc(dev);
bbf76eec 991
bbf76eec 992 if (device_is_attached(dev)) {
a0e18bfd
SZ
993 struct ifnet *ifp = sc->alc_ifp;
994
995 lwkt_serialize_enter(ifp->if_serializer);
bbf76eec 996 alc_stop(sc);
a0e18bfd
SZ
997 bus_teardown_intr(dev, sc->alc_irq, sc->alc_intrhand);
998 lwkt_serialize_exit(ifp->if_serializer);
bbf76eec 999
a0e18bfd 1000 ether_ifdetach(ifp);
bbf76eec
MD
1001 }
1002
a0e18bfd 1003 if (sc->alc_miibus != NULL)
bbf76eec 1004 device_delete_child(dev, sc->alc_miibus);
bbf76eec 1005 bus_generic_detach(dev);
bbf76eec 1006
a0e18bfd
SZ
1007 if (sc->alc_res != NULL)
1008 alc_phy_down(sc);
bbf76eec 1009
a0e18bfd
SZ
1010 if (sc->alc_irq != NULL) {
1011 bus_release_resource(dev, SYS_RES_IRQ, sc->alc_irq_rid,
1012 sc->alc_irq);
bbf76eec 1013 }
a0e18bfd 1014 if (sc->alc_irq_type == PCI_INTR_TYPE_MSI)
bbf76eec 1015 pci_release_msi(dev);
a0e18bfd
SZ
1016
1017 if (sc->alc_res != NULL) {
1018 bus_release_resource(dev, SYS_RES_MEMORY, sc->alc_res_rid,
1019 sc->alc_res);
1020 }
1021
1022 alc_dma_free(sc);
bbf76eec
MD
1023
1024 return (0);
1025}
1026
1027#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \
1028 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1029#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \
1030 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1031
1032static void
1033alc_sysctl_node(struct alc_softc *sc)
1034{
1035 struct sysctl_ctx_list *ctx;
1036 struct sysctl_oid *tree;
1037 struct sysctl_oid_list *child, *parent;
1038 struct alc_hw_stats *stats;
1039 int error;
1040
1041 stats = &sc->alc_stats;
1042 ctx = &sc->alc_sysctl_ctx;
1043 sysctl_ctx_init(ctx);
1044
1045 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw),
1046 OID_AUTO,
1047 device_get_nameunit(sc->alc_dev),
1048 CTLFLAG_RD, 0, "");
1049 if (tree == NULL) {
1050 device_printf(sc->alc_dev, "can't add sysctl node\n");
1051 return;
1052 }
1053 child = SYSCTL_CHILDREN(tree);
1054
1055 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
1056 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0,
1057 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
1058 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
1059 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0,
1060 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
1061 /* Pull in device tunables. */
1062 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1063 error = resource_int_value(device_get_name(sc->alc_dev),
1064 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
1065 if (error == 0) {
1066 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
1067 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
1068 device_printf(sc->alc_dev, "int_rx_mod value out of "
1069 "range; using default: %d\n",
1070 ALC_IM_RX_TIMER_DEFAULT);
1071 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1072 }
1073 }
1074 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1075 error = resource_int_value(device_get_name(sc->alc_dev),
1076 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
1077 if (error == 0) {
1078 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
1079 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
1080 device_printf(sc->alc_dev, "int_tx_mod value out of "
1081 "range; using default: %d\n",
1082 ALC_IM_TX_TIMER_DEFAULT);
1083 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1084 }
1085 }
1086 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
1087 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0,
1088 sysctl_hw_alc_proc_limit, "I",
1089 "max number of Rx events to process");
1090 /* Pull in device tunables. */
1091 sc->alc_process_limit = ALC_PROC_DEFAULT;
1092 error = resource_int_value(device_get_name(sc->alc_dev),
1093 device_get_unit(sc->alc_dev), "process_limit",
1094 &sc->alc_process_limit);
1095 if (error == 0) {
1096 if (sc->alc_process_limit < ALC_PROC_MIN ||
1097 sc->alc_process_limit > ALC_PROC_MAX) {
1098 device_printf(sc->alc_dev,
1099 "process_limit value out of range; "
1100 "using default: %d\n", ALC_PROC_DEFAULT);
1101 sc->alc_process_limit = ALC_PROC_DEFAULT;
1102 }
1103 }
1104
1105 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1106 NULL, "ALC statistics");
1107 parent = SYSCTL_CHILDREN(tree);
1108
1109 /* Rx statistics. */
1110 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1111 NULL, "Rx MAC statistics");
1112 child = SYSCTL_CHILDREN(tree);
1113 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1114 &stats->rx_frames, "Good frames");
1115 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1116 &stats->rx_bcast_frames, "Good broadcast frames");
1117 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1118 &stats->rx_mcast_frames, "Good multicast frames");
1119 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1120 &stats->rx_pause_frames, "Pause control frames");
1121 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1122 &stats->rx_control_frames, "Control frames");
1123 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1124 &stats->rx_crcerrs, "CRC errors");
1125 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1126 &stats->rx_lenerrs, "Frames with length mismatched");
1127 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1128 &stats->rx_bytes, "Good octets");
1129 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1130 &stats->rx_bcast_bytes, "Good broadcast octets");
1131 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1132 &stats->rx_mcast_bytes, "Good multicast octets");
1133 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
1134 &stats->rx_runts, "Too short frames");
1135 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
1136 &stats->rx_fragments, "Fragmented frames");
1137 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1138 &stats->rx_pkts_64, "64 bytes frames");
1139 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1140 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
1141 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1142 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
1143 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1144 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
1145 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1146 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
1147 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1148 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
1149 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1150 &stats->rx_pkts_1519_max, "1519 to max frames");
1151 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1152 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
1153 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1154 &stats->rx_fifo_oflows, "FIFO overflows");
1155 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1156 &stats->rx_rrs_errs, "Return status write-back errors");
1157 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1158 &stats->rx_alignerrs, "Alignment errors");
1159 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1160 &stats->rx_pkts_filtered,
1161 "Frames dropped due to address filtering");
1162
1163 /* Tx statistics. */
1164 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1165 NULL, "Tx MAC statistics");
1166 child = SYSCTL_CHILDREN(tree);
1167 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1168 &stats->tx_frames, "Good frames");
1169 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1170 &stats->tx_bcast_frames, "Good broadcast frames");
1171 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1172 &stats->tx_mcast_frames, "Good multicast frames");
1173 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1174 &stats->tx_pause_frames, "Pause control frames");
1175 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1176 &stats->tx_control_frames, "Control frames");
1177 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1178 &stats->tx_excess_defer, "Frames with excessive derferrals");
1179 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1180 &stats->tx_excess_defer, "Frames with derferrals");
1181 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1182 &stats->tx_bytes, "Good octets");
1183 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1184 &stats->tx_bcast_bytes, "Good broadcast octets");
1185 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1186 &stats->tx_mcast_bytes, "Good multicast octets");
1187 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1188 &stats->tx_pkts_64, "64 bytes frames");
1189 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1190 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1191 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1192 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1193 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1194 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1195 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1196 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1197 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1198 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1199 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1200 &stats->tx_pkts_1519_max, "1519 to max frames");
1201 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1202 &stats->tx_single_colls, "Single collisions");
1203 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1204 &stats->tx_multi_colls, "Multiple collisions");
1205 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1206 &stats->tx_late_colls, "Late collisions");
1207 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1208 &stats->tx_excess_colls, "Excessive collisions");
1209 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort",
1210 &stats->tx_abort, "Aborted frames due to Excessive collisions");
1211 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1212 &stats->tx_underrun, "FIFO underruns");
1213 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1214 &stats->tx_desc_underrun, "Descriptor write-back errors");
1215 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1216 &stats->tx_lenerrs, "Frames with length mismatched");
1217 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1218 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1219}
1220
1221#undef ALC_SYSCTL_STAT_ADD32
1222#undef ALC_SYSCTL_STAT_ADD64
1223
1224struct alc_dmamap_arg {
1225 bus_addr_t alc_busaddr;
1226};
1227
1228static void
1229alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1230{
1231 struct alc_dmamap_arg *ctx;
1232
1233 if (error != 0)
1234 return;
1235
1236 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1237
1238 ctx = (struct alc_dmamap_arg *)arg;
1239 ctx->alc_busaddr = segs[0].ds_addr;
1240}
1241
a0e18bfd 1242#ifdef foo
bbf76eec
MD
1243/*
1244 * Normal and high Tx descriptors shares single Tx high address.
1245 * Four Rx descriptor/return rings and CMB shares the same Rx
1246 * high address.
1247 */
1248static int
1249alc_check_boundary(struct alc_softc *sc)
1250{
1251 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1252
1253 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1254 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1255 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1256 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1257
1258 /* 4GB boundary crossing is not allowed. */
1259 if ((ALC_ADDR_HI(rx_ring_end) !=
1260 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1261 (ALC_ADDR_HI(rr_ring_end) !=
1262 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1263 (ALC_ADDR_HI(cmb_end) !=
1264 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1265 (ALC_ADDR_HI(tx_ring_end) !=
1266 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1267 return (EFBIG);
1268 /*
1269 * Make sure Rx return descriptor/Rx descriptor/CMB use
1270 * the same high address.
1271 */
1272 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1273 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1274 return (EFBIG);
1275
1276 return (0);
1277}
a0e18bfd 1278#endif
bbf76eec
MD
1279
1280static int
1281alc_dma_alloc(struct alc_softc *sc)
1282{
1283 struct alc_txdesc *txd;
1284 struct alc_rxdesc *rxd;
bbf76eec
MD
1285 struct alc_dmamap_arg ctx;
1286 int error, i;
1287
bbf76eec
MD
1288 /* Create parent DMA tag. */
1289 error = bus_dma_tag_create(
1290 sc->alc_cdata.alc_parent_tag, /* parent */
1291 1, 0, /* alignment, boundary */
a0e18bfd 1292 BUS_SPACE_MAXADDR, /* lowaddr */
bbf76eec
MD
1293 BUS_SPACE_MAXADDR, /* highaddr */
1294 NULL, NULL, /* filter, filterarg */
1295 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1296 0, /* nsegments */
1297 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1298 0, /* flags */
1299 &sc->alc_cdata.alc_parent_tag);
1300 if (error != 0) {
1301 device_printf(sc->alc_dev,
1302 "could not create parent DMA tag.\n");
1303 goto fail;
1304 }
1305
1306 /* Create DMA tag for Tx descriptor ring. */
1307 error = bus_dma_tag_create(
1308 sc->alc_cdata.alc_parent_tag, /* parent */
1309 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
a0e18bfd 1310 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
bbf76eec
MD
1311 BUS_SPACE_MAXADDR, /* highaddr */
1312 NULL, NULL, /* filter, filterarg */
1313 ALC_TX_RING_SZ, /* maxsize */
1314 1, /* nsegments */
1315 ALC_TX_RING_SZ, /* maxsegsize */
1316 0, /* flags */
1317 &sc->alc_cdata.alc_tx_ring_tag);
1318 if (error != 0) {
1319 device_printf(sc->alc_dev,
1320 "could not create Tx ring DMA tag.\n");
1321 goto fail;
1322 }
1323
1324 /* Create DMA tag for Rx free descriptor ring. */
1325 error = bus_dma_tag_create(
1326 sc->alc_cdata.alc_parent_tag, /* parent */
1327 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
a0e18bfd 1328 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
bbf76eec
MD
1329 BUS_SPACE_MAXADDR, /* highaddr */
1330 NULL, NULL, /* filter, filterarg */
1331 ALC_RX_RING_SZ, /* maxsize */
1332 1, /* nsegments */
1333 ALC_RX_RING_SZ, /* maxsegsize */
1334 0, /* flags */
1335 &sc->alc_cdata.alc_rx_ring_tag);
1336 if (error != 0) {
1337 device_printf(sc->alc_dev,
1338 "could not create Rx ring DMA tag.\n");
1339 goto fail;
1340 }
1341 /* Create DMA tag for Rx return descriptor ring. */
1342 error = bus_dma_tag_create(
1343 sc->alc_cdata.alc_parent_tag, /* parent */
1344 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
a0e18bfd 1345 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
bbf76eec
MD
1346 BUS_SPACE_MAXADDR, /* highaddr */
1347 NULL, NULL, /* filter, filterarg */
1348 ALC_RR_RING_SZ, /* maxsize */
1349 1, /* nsegments */
1350 ALC_RR_RING_SZ, /* maxsegsize */
1351 0, /* flags */
1352 &sc->alc_cdata.alc_rr_ring_tag);
1353 if (error != 0) {
1354 device_printf(sc->alc_dev,
1355 "could not create Rx return ring DMA tag.\n");
1356 goto fail;
1357 }
1358
1359 /* Create DMA tag for coalescing message block. */
1360 error = bus_dma_tag_create(
1361 sc->alc_cdata.alc_parent_tag, /* parent */
1362 ALC_CMB_ALIGN, 0, /* alignment, boundary */
a0e18bfd 1363 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
bbf76eec
MD
1364 BUS_SPACE_MAXADDR, /* highaddr */
1365 NULL, NULL, /* filter, filterarg */
1366 ALC_CMB_SZ, /* maxsize */
1367 1, /* nsegments */
1368 ALC_CMB_SZ, /* maxsegsize */
1369 0, /* flags */
1370 &sc->alc_cdata.alc_cmb_tag);
1371 if (error != 0) {
1372 device_printf(sc->alc_dev,
1373 "could not create CMB DMA tag.\n");
1374 goto fail;
1375 }
1376 /* Create DMA tag for status message block. */
1377 error = bus_dma_tag_create(
1378 sc->alc_cdata.alc_parent_tag, /* parent */
1379 ALC_SMB_ALIGN, 0, /* alignment, boundary */
a0e18bfd 1380 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
bbf76eec
MD
1381 BUS_SPACE_MAXADDR, /* highaddr */
1382 NULL, NULL, /* filter, filterarg */
1383 ALC_SMB_SZ, /* maxsize */
1384 1, /* nsegments */
1385 ALC_SMB_SZ, /* maxsegsize */
1386 0, /* flags */
1387 &sc->alc_cdata.alc_smb_tag);
1388 if (error != 0) {
1389 device_printf(sc->alc_dev,
1390 "could not create SMB DMA tag.\n");
1391 goto fail;
1392 }
1393
1394 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1395 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
1396 (void **)&sc->alc_rdata.alc_tx_ring,
1397 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1398 &sc->alc_cdata.alc_tx_ring_map);
1399 if (error != 0) {
1400 device_printf(sc->alc_dev,
1401 "could not allocate DMA'able memory for Tx ring.\n");
1402 goto fail;
1403 }
1404 ctx.alc_busaddr = 0;
1405 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
1406 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
1407 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1408 if (error != 0 || ctx.alc_busaddr == 0) {
1409 device_printf(sc->alc_dev,
1410 "could not load DMA'able memory for Tx ring.\n");
1411 goto fail;
1412 }
1413 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
1414
1415 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1416 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
1417 (void **)&sc->alc_rdata.alc_rx_ring,
1418 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1419 &sc->alc_cdata.alc_rx_ring_map);
1420 if (error != 0) {
1421 device_printf(sc->alc_dev,
1422 "could not allocate DMA'able memory for Rx ring.\n");
1423 goto fail;
1424 }
1425 ctx.alc_busaddr = 0;
1426 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
1427 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
1428 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
1429 if (error != 0 || ctx.alc_busaddr == 0) {
1430 device_printf(sc->alc_dev,
1431 "could not load DMA'able memory for Rx ring.\n");
1432 goto fail;
1433 }
1434 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
1435
1436 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */
1437 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
1438 (void **)&sc->alc_rdata.alc_rr_ring,
1439 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1440 &sc->alc_cdata.alc_rr_ring_map);
1441 if (error != 0) {
1442 device_printf(sc->alc_dev,
1443 "could not allocate DMA'able memory for Rx return ring.\n");
1444 goto fail;
1445 }
1446 ctx.alc_busaddr = 0;
1447 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
1448 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
1449 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
1450 if (error != 0 || ctx.alc_busaddr == 0) {
1451 device_printf(sc->alc_dev,
1452 "could not load DMA'able memory for Tx ring.\n");
1453 goto fail;
1454 }
1455 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
1456
1457 /* Allocate DMA'able memory and load the DMA map for CMB. */
1458 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
1459 (void **)&sc->alc_rdata.alc_cmb,
1460 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1461 &sc->alc_cdata.alc_cmb_map);
1462 if (error != 0) {
1463 device_printf(sc->alc_dev,
1464 "could not allocate DMA'able memory for CMB.\n");
1465 goto fail;
1466 }
1467 ctx.alc_busaddr = 0;
1468 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
1469 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
1470 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
1471 if (error != 0 || ctx.alc_busaddr == 0) {
1472 device_printf(sc->alc_dev,
1473 "could not load DMA'able memory for CMB.\n");
1474 goto fail;
1475 }
1476 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
1477
1478 /* Allocate DMA'able memory and load the DMA map for SMB. */
1479 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
1480 (void **)&sc->alc_rdata.alc_smb,
1481 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1482 &sc->alc_cdata.alc_smb_map);
1483 if (error != 0) {
1484 device_printf(sc->alc_dev,
1485 "could not allocate DMA'able memory for SMB.\n");
1486 goto fail;
1487 }
1488 ctx.alc_busaddr = 0;
1489 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
1490 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
1491 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
1492 if (error != 0 || ctx.alc_busaddr == 0) {
1493 device_printf(sc->alc_dev,
1494 "could not load DMA'able memory for CMB.\n");
1495 goto fail;
1496 }
1497 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
1498
a0e18bfd
SZ
1499#ifdef foo
1500 /*
1501 * All of the status blocks and descriptor rings are
1502 * allocated at lower 4GB, their addresses high 32bits
1503 * part are same (all 0).
1504 */
1505
bbf76eec 1506 /* Make sure we've not crossed 4GB boundary. */
a0e18bfd 1507 if ((error = alc_check_boundary(sc)) != 0) {
bbf76eec
MD
1508 device_printf(sc->alc_dev, "4GB boundary crossed, "
1509 "switching to 32bit DMA addressing mode.\n");
1510 alc_dma_free(sc);
1511 /*
1512 * Limit max allowable DMA address space to 32bit
1513 * and try again.
1514 */
1515 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1516 goto again;
1517 }
a0e18bfd 1518#endif
bbf76eec
MD
1519
1520 /*
1521 * Create Tx buffer parent tag.
cffbd125 1522 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers
bbf76eec
MD
1523 * so it needs separate parent DMA tag as parent DMA address
1524 * space could be restricted to be within 32bit address space
1525 * by 4GB boundary crossing.
1526 */
1527 error = bus_dma_tag_create(
1528 sc->alc_cdata.alc_parent_tag, /* parent */
1529 1, 0, /* alignment, boundary */
1530 BUS_SPACE_MAXADDR, /* lowaddr */
1531 BUS_SPACE_MAXADDR, /* highaddr */
1532 NULL, NULL, /* filter, filterarg */
1533 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1534 0, /* nsegments */
1535 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1536 0, /* flags */
1537 &sc->alc_cdata.alc_buffer_tag);
1538 if (error != 0) {
1539 device_printf(sc->alc_dev,
1540 "could not create parent buffer DMA tag.\n");
1541 goto fail;
1542 }
1543
1544 /* Create DMA tag for Tx buffers. */
1545 error = bus_dma_tag_create(
1546 sc->alc_cdata.alc_buffer_tag, /* parent */
1547 1, 0, /* alignment, boundary */
1548 BUS_SPACE_MAXADDR, /* lowaddr */
1549 BUS_SPACE_MAXADDR, /* highaddr */
1550 NULL, NULL, /* filter, filterarg */
1551 ALC_TSO_MAXSIZE, /* maxsize */
1552 ALC_MAXTXSEGS, /* nsegments */
1553 ALC_TSO_MAXSEGSIZE, /* maxsegsize */
a0e18bfd 1554 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, /* flags */
bbf76eec
MD
1555 &sc->alc_cdata.alc_tx_tag);
1556 if (error != 0) {
1557 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
1558 goto fail;
1559 }
1560
1561 /* Create DMA tag for Rx buffers. */
1562 error = bus_dma_tag_create(
1563 sc->alc_cdata.alc_buffer_tag, /* parent */
1564 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
1565 BUS_SPACE_MAXADDR, /* lowaddr */
1566 BUS_SPACE_MAXADDR, /* highaddr */
1567 NULL, NULL, /* filter, filterarg */
1568 MCLBYTES, /* maxsize */
1569 1, /* nsegments */
1570 MCLBYTES, /* maxsegsize */
a0e18bfd 1571 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED, /* flags */
bbf76eec
MD
1572 &sc->alc_cdata.alc_rx_tag);
1573 if (error != 0) {
1574 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
1575 goto fail;
1576 }
1577 /* Create DMA maps for Tx buffers. */
1578 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1579 txd = &sc->alc_cdata.alc_txdesc[i];
1580 txd->tx_m = NULL;
1581 txd->tx_dmamap = NULL;
f753ef49 1582 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag,
a0e18bfd
SZ
1583 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1584 &txd->tx_dmamap);
bbf76eec
MD
1585 if (error != 0) {
1586 device_printf(sc->alc_dev,
1587 "could not create Tx dmamap.\n");
1588 goto fail;
1589 }
1590 }
1591 /* Create DMA maps for Rx buffers. */
f753ef49
MD
1592 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag,
1593 BUS_DMA_WAITOK,
1594 &sc->alc_cdata.alc_rx_sparemap);
1595 if (error) {
bbf76eec
MD
1596 device_printf(sc->alc_dev,
1597 "could not create spare Rx dmamap.\n");
1598 goto fail;
1599 }
1600 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1601 rxd = &sc->alc_cdata.alc_rxdesc[i];
1602 rxd->rx_m = NULL;
1603 rxd->rx_dmamap = NULL;
f753ef49
MD
1604 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag,
1605 BUS_DMA_WAITOK,
1606 &rxd->rx_dmamap);
bbf76eec
MD
1607 if (error != 0) {
1608 device_printf(sc->alc_dev,
1609 "could not create Rx dmamap.\n");
1610 goto fail;
1611 }
1612 }
1613
1614fail:
1615 return (error);
1616}
1617
1618static void
1619alc_dma_free(struct alc_softc *sc)
1620{
1621 struct alc_txdesc *txd;
1622 struct alc_rxdesc *rxd;
1623 int i;
1624
1625 /* Tx buffers. */
1626 if (sc->alc_cdata.alc_tx_tag != NULL) {
1627 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1628 txd = &sc->alc_cdata.alc_txdesc[i];
1629 if (txd->tx_dmamap != NULL) {
1630 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
1631 txd->tx_dmamap);
1632 txd->tx_dmamap = NULL;
1633 }
1634 }
1635 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
1636 sc->alc_cdata.alc_tx_tag = NULL;
1637 }
1638 /* Rx buffers */
1639 if (sc->alc_cdata.alc_rx_tag != NULL) {
1640 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1641 rxd = &sc->alc_cdata.alc_rxdesc[i];
1642 if (rxd->rx_dmamap != NULL) {
1643 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1644 rxd->rx_dmamap);
1645 rxd->rx_dmamap = NULL;
1646 }
1647 }
1648 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
1649 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
1650 sc->alc_cdata.alc_rx_sparemap);
1651 sc->alc_cdata.alc_rx_sparemap = NULL;
1652 }
1653 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
1654 sc->alc_cdata.alc_rx_tag = NULL;
1655 }
1656 /* Tx descriptor ring. */
1657 if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
1658 if (sc->alc_cdata.alc_tx_ring_map != NULL)
1659 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
1660 sc->alc_cdata.alc_tx_ring_map);
1661 if (sc->alc_cdata.alc_tx_ring_map != NULL &&
1662 sc->alc_rdata.alc_tx_ring != NULL)
1663 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
1664 sc->alc_rdata.alc_tx_ring,
1665 sc->alc_cdata.alc_tx_ring_map);
1666 sc->alc_rdata.alc_tx_ring = NULL;
1667 sc->alc_cdata.alc_tx_ring_map = NULL;
1668 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
1669 sc->alc_cdata.alc_tx_ring_tag = NULL;
1670 }
1671 /* Rx ring. */
1672 if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
1673 if (sc->alc_cdata.alc_rx_ring_map != NULL)
1674 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
1675 sc->alc_cdata.alc_rx_ring_map);
1676 if (sc->alc_cdata.alc_rx_ring_map != NULL &&
1677 sc->alc_rdata.alc_rx_ring != NULL)
1678 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
1679 sc->alc_rdata.alc_rx_ring,
1680 sc->alc_cdata.alc_rx_ring_map);
1681 sc->alc_rdata.alc_rx_ring = NULL;
1682 sc->alc_cdata.alc_rx_ring_map = NULL;
1683 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
1684 sc->alc_cdata.alc_rx_ring_tag = NULL;
1685 }
1686 /* Rx return ring. */
1687 if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
1688 if (sc->alc_cdata.alc_rr_ring_map != NULL)
1689 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
1690 sc->alc_cdata.alc_rr_ring_map);
1691 if (sc->alc_cdata.alc_rr_ring_map != NULL &&
1692 sc->alc_rdata.alc_rr_ring != NULL)
1693 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
1694 sc->alc_rdata.alc_rr_ring,
1695 sc->alc_cdata.alc_rr_ring_map);
1696 sc->alc_rdata.alc_rr_ring = NULL;
1697 sc->alc_cdata.alc_rr_ring_map = NULL;
1698 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
1699 sc->alc_cdata.alc_rr_ring_tag = NULL;
1700 }
1701 /* CMB block */
1702 if (sc->alc_cdata.alc_cmb_tag != NULL) {
1703 if (sc->alc_cdata.alc_cmb_map != NULL)
1704 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
1705 sc->alc_cdata.alc_cmb_map);
1706 if (sc->alc_cdata.alc_cmb_map != NULL &&
1707 sc->alc_rdata.alc_cmb != NULL)
1708 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
1709 sc->alc_rdata.alc_cmb,
1710 sc->alc_cdata.alc_cmb_map);
1711 sc->alc_rdata.alc_cmb = NULL;
1712 sc->alc_cdata.alc_cmb_map = NULL;
1713 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
1714 sc->alc_cdata.alc_cmb_tag = NULL;
1715 }
1716 /* SMB block */
1717 if (sc->alc_cdata.alc_smb_tag != NULL) {
1718 if (sc->alc_cdata.alc_smb_map != NULL)
1719 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
1720 sc->alc_cdata.alc_smb_map);
1721 if (sc->alc_cdata.alc_smb_map != NULL &&
1722 sc->alc_rdata.alc_smb != NULL)
1723 bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
1724 sc->alc_rdata.alc_smb,
1725 sc->alc_cdata.alc_smb_map);
1726 sc->alc_rdata.alc_smb = NULL;
1727 sc->alc_cdata.alc_smb_map = NULL;
1728 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
1729 sc->alc_cdata.alc_smb_tag = NULL;
1730 }
1731 if (sc->alc_cdata.alc_buffer_tag != NULL) {
1732 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
1733 sc->alc_cdata.alc_buffer_tag = NULL;
1734 }
1735 if (sc->alc_cdata.alc_parent_tag != NULL) {
1736 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
1737 sc->alc_cdata.alc_parent_tag = NULL;
1738 }
1739}
1740
1741static int
1742alc_shutdown(device_t dev)
1743{
1744
1745 return (alc_suspend(dev));
1746}
1747
1748#if 0
1749/* XXX: LINK SPEED */
1750/*
1751 * Note, this driver resets the link speed to 10/100Mbps by
1752 * restarting auto-negotiation in suspend/shutdown phase but we
1753 * don't know whether that auto-negotiation would succeed or not
1754 * as driver has no control after powering off/suspend operation.
1755 * If the renegotiation fail WOL may not work. Running at 1Gbps
1756 * will draw more power than 375mA at 3.3V which is specified in
1757 * PCI specification and that would result in complete
1758 * shutdowning power to ethernet controller.
1759 *
1760 * TODO
1761 * Save current negotiated media speed/duplex/flow-control to
1762 * softc and restore the same link again after resuming. PHY
1763 * handling such as power down/resetting to 100Mbps may be better
1764 * handled in suspend method in phy driver.
1765 */
1766static void
1767alc_setlinkspeed(struct alc_softc *sc)
1768{
1769 struct mii_data *mii;
1770 int aneg, i;
1771
1772 mii = device_get_softc(sc->alc_miibus);
1773 mii_pollstat(mii);
1774 aneg = 0;
1775 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1776 (IFM_ACTIVE | IFM_AVALID)) {
1777 switch IFM_SUBTYPE(mii->mii_media_active) {
1778 case IFM_10_T:
1779 case IFM_100_TX:
1780 return;
1781 case IFM_1000_T:
1782 aneg++;
1783 break;
1784 default:
1785 break;
1786 }
1787 }
1788 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
1789 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1790 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1791 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1792 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1793 DELAY(1000);
1794 if (aneg != 0) {
1795 /*
1796 * Poll link state until alc(4) get a 10/100Mbps link.
1797 */
1798 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1799 mii_pollstat(mii);
1800 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1801 == (IFM_ACTIVE | IFM_AVALID)) {
1802 switch (IFM_SUBTYPE(
1803 mii->mii_media_active)) {
1804 case IFM_10_T:
1805 case IFM_100_TX:
1806 alc_mac_config(sc);
1807 return;
1808 default:
1809 break;
1810 }
1811 }
1812 ALC_UNLOCK(sc);
1813 pause("alclnk", hz);
1814 ALC_LOCK(sc);
1815 }
1816 if (i == MII_ANEGTICKS_GIGE)
1817 device_printf(sc->alc_dev,
1818 "establishing a link failed, WOL may not work!");
1819 }
1820 /*
1821 * No link, force MAC to have 100Mbps, full-duplex link.
1822 * This is the last resort and may/may not work.
1823 */
1824 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1825 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1826 alc_mac_config(sc);
1827}
1828#endif
1829
1830#if 0
1831/* XXX: WOL */
1832static void
1833alc_setwol(struct alc_softc *sc)
1834{
1835 struct ifnet *ifp;
cffbd125 1836 uint32_t reg, pmcs;
bbf76eec 1837 uint16_t pmstat;
bbf76eec
MD
1838
1839 ALC_LOCK_ASSERT(sc);
1840
cffbd125
MD
1841 alc_disable_l0s_l1(sc);
1842 ifp = sc->alc_ifp;
1843 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
bbf76eec
MD
1844 /* Disable WOL. */
1845 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
1846 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1847 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1848 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1849 /* Force PHY power down. */
1850 alc_phy_down(sc);
cffbd125
MD
1851 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1852 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
bbf76eec
MD
1853 return;
1854 }
1855
bbf76eec
MD
1856 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1857 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
1858 alc_setlinkspeed(sc);
cffbd125
MD
1859 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1860 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
bbf76eec
MD
1861 }
1862
1863 pmcs = 0;
1864 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1865 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1866 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
1867 reg = CSR_READ_4(sc, ALC_MAC_CFG);
1868 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1869 MAC_CFG_BCAST);
1870 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1871 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1872 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1873 reg |= MAC_CFG_RX_ENB;
1874 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
1875
1876 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1877 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1878 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1879 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1880 /* WOL disabled, PHY power down. */
1881 alc_phy_down(sc);
cffbd125
MD
1882 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1883 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1884
bbf76eec
MD
1885 }
1886 /* Request PME. */
cffbd125
MD
1887 pmstat = pci_read_config(sc->alc_dev,
1888 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
bbf76eec
MD
1889 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1890 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1891 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
cffbd125
MD
1892 pci_write_config(sc->alc_dev,
1893 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
bbf76eec
MD
1894}
1895#endif
1896
1897static int
1898alc_suspend(device_t dev)
1899{
a0e18bfd
SZ
1900 struct alc_softc *sc = device_get_softc(dev);
1901 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec 1902
a0e18bfd 1903 lwkt_serialize_enter(ifp->if_serializer);
bbf76eec
MD
1904 alc_stop(sc);
1905#if 0
1906/* XXX: WOL */
1907 alc_setwol(sc);
1908#endif
a0e18bfd 1909 lwkt_serialize_exit(ifp->if_serializer);
bbf76eec
MD
1910
1911 return (0);
1912}
1913
1914static int
1915alc_resume(device_t dev)
1916{
a0e18bfd
SZ
1917 struct alc_softc *sc = device_get_softc(dev);
1918 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec
MD
1919 uint16_t pmstat;
1920
a0e18bfd 1921 lwkt_serialize_enter(ifp->if_serializer);
bbf76eec 1922
cffbd125 1923 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
bbf76eec
MD
1924 /* Disable PME and clear PME status. */
1925 pmstat = pci_read_config(sc->alc_dev,
cffbd125 1926 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
bbf76eec
MD
1927 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1928 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1929 pci_write_config(sc->alc_dev,
cffbd125 1930 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
bbf76eec
MD
1931 }
1932 }
a0e18bfd 1933
bbf76eec
MD
1934 /* Reset PHY. */
1935 alc_phy_reset(sc);
a0e18bfd
SZ
1936 if (ifp->if_flags & IFF_UP)
1937 alc_init(sc);
1938
1939 lwkt_serialize_exit(ifp->if_serializer);
bbf76eec
MD
1940
1941 return (0);
1942}
1943
1944static int
1945alc_encap(struct alc_softc *sc, struct mbuf **m_head)
1946{
1947 struct alc_txdesc *txd, *txd_last;
1948 struct tx_desc *desc;
1949 struct mbuf *m;
db2a8882 1950#if 0 /* XXX: TSO */
bbf76eec 1951 struct ip *ip;
db2a8882 1952#endif
bbf76eec
MD
1953 struct tcphdr *tcp;
1954 bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
1955 bus_dmamap_t map;
1956 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1957 int error, idx, nsegs, prod;
1958
bbf76eec
MD
1959 M_ASSERTPKTHDR((*m_head));
1960
1961 m = *m_head;
bbf76eec
MD
1962 tcp = NULL;
1963 ip_off = poff = 0;
db2a8882
SW
1964#if 0 /* XXX: TSO */
1965 ip = NULL;
1966
bbf76eec
MD
1967 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
1968 /*
cffbd125 1969 * AR813x/AR815x requires offset of TCP/UDP header in its
bbf76eec
MD
1970 * Tx descriptor to perform Tx checksum offloading. TSO
1971 * also requires TCP header offset and modification of
1972 * IP/TCP header. This kind of operation takes many CPU
1973 * cycles on FreeBSD so fast host CPU is required to get
1974 * smooth TSO performance.
1975 */
1976 struct ether_header *eh;
1977
1978 if (M_WRITABLE(m) == 0) {
1979 /* Get a writable copy. */
1980 m = m_dup(*m_head, MB_DONTWAIT);
1981 /* Release original mbufs. */
1982 m_freem(*m_head);
1983 if (m == NULL) {
1984 *m_head = NULL;
1985 return (ENOBUFS);
1986 }
1987 *m_head = m;
1988 }
1989
1990 ip_off = sizeof(struct ether_header);
cffbd125 1991 m = m_pullup(m, ip_off + sizeof(struct ip));
bbf76eec
MD
1992 if (m == NULL) {
1993 *m_head = NULL;
1994 return (ENOBUFS);
1995 }
1996 eh = mtod(m, struct ether_header *);
1997 /*
1998 * Check if hardware VLAN insertion is off.
1999 * Additional check for LLC/SNAP frame?
2000 */
2001 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2002 ip_off = sizeof(struct ether_vlan_header);
2003 m = m_pullup(m, ip_off);
2004 if (m == NULL) {
2005 *m_head = NULL;
2006 return (ENOBUFS);
2007 }
2008 }
2009 m = m_pullup(m, ip_off + sizeof(struct ip));
2010 if (m == NULL) {
2011 *m_head = NULL;
2012 return (ENOBUFS);
2013 }
2014 ip = (struct ip *)(mtod(m, char *) + ip_off);
2015 poff = ip_off + (ip->ip_hl << 2);
2016
2017 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2018 m = m_pullup(m, poff + sizeof(struct tcphdr));
2019 if (m == NULL) {
2020 *m_head = NULL;
2021 return (ENOBUFS);
2022 }
2023 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2024 m = m_pullup(m, poff + (tcp->th_off << 2));
2025 if (m == NULL) {
2026 *m_head = NULL;
2027 return (ENOBUFS);
2028 }
2029 /*
2030 * Due to strict adherence of Microsoft NDIS
2031 * Large Send specification, hardware expects
2032 * a pseudo TCP checksum inserted by upper
2033 * stack. Unfortunately the pseudo TCP
2034 * checksum that NDIS refers to does not include
2035 * TCP payload length so driver should recompute
2036 * the pseudo checksum here. Hopefully this
2037 * wouldn't be much burden on modern CPUs.
2038 *
2039 * Reset IP checksum and recompute TCP pseudo
2040 * checksum as NDIS specification said.
2041 */
2042 ip->ip_sum = 0;
2043 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
2044 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2045 }
2046 *m_head = m;
2047 }
2048#endif /* TSO */
2049
2050 prod = sc->alc_cdata.alc_tx_prod;
2051 txd = &sc->alc_cdata.alc_txdesc[prod];
2052 txd_last = txd;
2053 map = txd->tx_dmamap;
2054
f753ef49
MD
2055 error = bus_dmamap_load_mbuf_defrag(
2056 sc->alc_cdata.alc_tx_tag, map, m_head,
2057 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT);
2058 if (error) {
2059 m_freem(*m_head);
2060 *m_head = NULL;
bbf76eec 2061 return (error);
f753ef49 2062 }
bbf76eec
MD
2063 if (nsegs == 0) {
2064 m_freem(*m_head);
2065 *m_head = NULL;
2066 return (EIO);
2067 }
2068
2069 /* Check descriptor overrun. */
2070 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
2071 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
2072 return (ENOBUFS);
2073 }
2074 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
2075
2076 m = *m_head;
2077 cflags = TD_ETHERNET;
2078 vtag = 0;
2079 desc = NULL;
2080 idx = 0;
2081 /* Configure VLAN hardware tag insertion. */
2082 if ((m->m_flags & M_VLANTAG) != 0) {
2083 vtag = htons(m->m_pkthdr.ether_vlantag);
2084 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
2085 cflags |= TD_INS_VLAN_TAG;
2086 }
2087 /* Configure Tx checksum offload. */
2088 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
2089#ifdef ALC_USE_CUSTOM_CSUM
2090 cflags |= TD_CUSTOM_CSUM;
2091 /* Set checksum start offset. */
2092 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
2093 TD_PLOAD_OFFSET_MASK;
2094 /* Set checksum insertion position of TCP/UDP. */
2095 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
2096 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
2097#else
2098 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2099 cflags |= TD_IPCSUM;
2100 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2101 cflags |= TD_TCPCSUM;
2102 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2103 cflags |= TD_UDPCSUM;
2104 /* Set TCP/UDP header offset. */
2105 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
2106 TD_L4HDR_OFFSET_MASK;
2107#endif
2108 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2109 /* Request TSO and set MSS. */
2110 cflags |= TD_TSO | TD_TSO_DESCV1;
2111#if 0
2112/* XXX: TSO */
2113 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
2114 TD_MSS_MASK;
2115 /* Set TCP header offset. */
2116#endif
2117 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
2118 TD_TCPHDR_OFFSET_MASK;
2119 /*
cffbd125 2120 * AR813x/AR815x requires the first buffer should
bbf76eec
MD
2121 * only hold IP/TCP header data. Payload should
2122 * be handled in other descriptors.
2123 */
2124 hdrlen = poff + (tcp->th_off << 2);
2125 desc = &sc->alc_rdata.alc_tx_ring[prod];
2126 desc->len = htole32(TX_BYTES(hdrlen | vtag));
2127 desc->flags = htole32(cflags);
2128 desc->addr = htole64(txsegs[0].ds_addr);
2129 sc->alc_cdata.alc_tx_cnt++;
2130 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2131 if (m->m_len - hdrlen > 0) {
2132 /* Handle remaining payload of the first fragment. */
2133 desc = &sc->alc_rdata.alc_tx_ring[prod];
2134 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
2135 vtag));
2136 desc->flags = htole32(cflags);
2137 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2138 sc->alc_cdata.alc_tx_cnt++;
2139 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2140 }
2141 /* Handle remaining fragments. */
2142 idx = 1;
2143 }
2144 for (; idx < nsegs; idx++) {
2145 desc = &sc->alc_rdata.alc_tx_ring[prod];
2146 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
2147 desc->flags = htole32(cflags);
2148 desc->addr = htole64(txsegs[idx].ds_addr);
2149 sc->alc_cdata.alc_tx_cnt++;
2150 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2151 }
2152 /* Update producer index. */
2153 sc->alc_cdata.alc_tx_prod = prod;
2154
2155 /* Finally set EOP on the last descriptor. */
2156 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
2157 desc = &sc->alc_rdata.alc_tx_ring[prod];
2158 desc->flags |= htole32(TD_EOP);
2159
2160 /* Swap dmamap of the first and the last. */
2161 txd = &sc->alc_cdata.alc_txdesc[prod];
2162 map = txd_last->tx_dmamap;
2163 txd_last->tx_dmamap = txd->tx_dmamap;
2164 txd->tx_dmamap = map;
2165 txd->tx_m = m;
2166
2167 return (0);
2168}
2169
2170static void
bbf76eec
MD
2171alc_start(struct ifnet *ifp)
2172{
a0e18bfd 2173 struct alc_softc *sc = ifp->if_softc;
bbf76eec
MD
2174 struct mbuf *m_head;
2175 int enq;
2176
a0e18bfd 2177 ASSERT_SERIALIZED(ifp->if_serializer);
bbf76eec
MD
2178
2179 /* Reclaim transmitted frames. */
2180 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2181 alc_txeof(sc);
2182
a0e18bfd 2183 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
f753ef49 2184 return;
f753ef49
MD
2185 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2186 ifq_purge(&ifp->if_snd);
bbf76eec
MD
2187 return;
2188 }
2189
2190 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) {
2191 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2192 if (m_head == NULL)
2193 break;
2194 /*
2195 * Pack the data into the transmit ring. If we
2196 * don't have room, set the OACTIVE flag and wait
2197 * for the NIC to drain the ring.
2198 */
2199 if (alc_encap(sc, &m_head)) {
2200 if (m_head == NULL)
2201 break;
2202 ifq_prepend(&ifp->if_snd, m_head);
2203 ifp->if_flags |= IFF_OACTIVE;
2204 break;
2205 }
2206
2207 enq++;
2208 /*
2209 * If there's a BPF listener, bounce a copy of this frame
2210 * to him.
2211 */
2212 ETHER_BPF_MTAP(ifp, m_head);
2213 }
2214
2215 if (enq > 0) {
2216 /* Sync descriptors. */
2217 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2218 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
2219 /* Kick. Assume we're using normal Tx priority queue. */
2220 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
2221 (sc->alc_cdata.alc_tx_prod <<
2222 MBOX_TD_PROD_LO_IDX_SHIFT) &
2223 MBOX_TD_PROD_LO_IDX_MASK);
2224 /* Set a timeout in case the chip goes out to lunch. */
2225 sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
2226 }
bbf76eec
MD
2227}
2228
2229static void
2230alc_watchdog(struct alc_softc *sc)
2231{
a0e18bfd 2232 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec 2233
a0e18bfd 2234 ASSERT_SERIALIZED(ifp->if_serializer);
bbf76eec
MD
2235
2236 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
2237 return;
2238
bbf76eec
MD
2239 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2240 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
2241 ifp->if_oerrors++;
a0e18bfd 2242 alc_init(sc);
bbf76eec
MD
2243 return;
2244 }
2245 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
2246 ifp->if_oerrors++;
a0e18bfd 2247 alc_init(sc);
bbf76eec 2248 if (!ifq_is_empty(&ifp->if_snd))
a0e18bfd 2249 if_devstart(ifp);
bbf76eec
MD
2250}
2251
2252static int
2253alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2254{
2255 struct alc_softc *sc;
2256 struct ifreq *ifr;
2257 struct mii_data *mii;
2258 int error, mask;
2259
a0e18bfd
SZ
2260 ASSERT_SERIALIZED(ifp->if_serializer);
2261
bbf76eec
MD
2262 sc = ifp->if_softc;
2263 ifr = (struct ifreq *)data;
2264 error = 0;
2265 switch (cmd) {
2266 case SIOCSIFMTU:
cffbd125
MD
2267 if (ifr->ifr_mtu < ETHERMIN ||
2268 ifr->ifr_mtu > (sc->alc_ident->max_framelen -
2269 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) ||
bbf76eec 2270 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
cffbd125 2271 ifr->ifr_mtu > ETHERMTU)) {
bbf76eec 2272 error = EINVAL;
cffbd125 2273 } else if (ifp->if_mtu != ifr->ifr_mtu) {
bbf76eec 2274 ifp->if_mtu = ifr->ifr_mtu;
a0e18bfd 2275#if 0
cffbd125 2276 /* AR813x/AR815x has 13 bits MSS field. */
bbf76eec
MD
2277 if (ifp->if_mtu > ALC_TSO_MTU &&
2278 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2279 ifp->if_capenable &= ~IFCAP_TSO4;
2280 ifp->if_hwassist &= ~CSUM_TSO;
2281 }
a0e18bfd 2282#endif
bbf76eec
MD
2283 }
2284 break;
2285 case SIOCSIFFLAGS:
bbf76eec
MD
2286 if ((ifp->if_flags & IFF_UP) != 0) {
2287 if ((ifp->if_flags & IFF_RUNNING) != 0 &&
2288 ((ifp->if_flags ^ sc->alc_if_flags) &
2289 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2290 alc_rxfilter(sc);
a0e18bfd
SZ
2291 else if ((ifp->if_flags & IFF_RUNNING) == 0)
2292 alc_init(sc);
bbf76eec
MD
2293 } else if ((ifp->if_flags & IFF_RUNNING) != 0)
2294 alc_stop(sc);
2295 sc->alc_if_flags = ifp->if_flags;
bbf76eec
MD
2296 break;
2297 case SIOCADDMULTI:
2298 case SIOCDELMULTI:
bbf76eec
MD
2299 if ((ifp->if_flags & IFF_RUNNING) != 0)
2300 alc_rxfilter(sc);
bbf76eec
MD
2301 break;
2302 case SIOCSIFMEDIA:
2303 case SIOCGIFMEDIA:
2304 mii = device_get_softc(sc->alc_miibus);
2305 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2306 break;
2307 case SIOCSIFCAP:
bbf76eec
MD
2308 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2309 if ((mask & IFCAP_TXCSUM) != 0 &&
2310 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2311 ifp->if_capenable ^= IFCAP_TXCSUM;
2312 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2313 ifp->if_hwassist |= ALC_CSUM_FEATURES;
2314 else
2315 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
2316 }
bbf76eec
MD
2317#if 0
2318/* XXX: WOL */
2319 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2320 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2321 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2322 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2323 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2324 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2325#endif
2326 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2327 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2328 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2329 alc_rxvlan(sc);
2330 }
2331 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2332 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2333 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
a0e18bfd 2334
bbf76eec
MD
2335 /*
2336 * VLAN hardware tagging is required to do checksum
2337 * offload or TSO on VLAN interface. Checksum offload
2338 * on VLAN interface also requires hardware checksum
2339 * offload of parent interface.
2340 */
2341 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0)
2342 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
2343 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
a0e18bfd 2344 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
bbf76eec
MD
2345// XXX VLAN_CAPABILITIES(ifp);
2346 break;
2347 default:
2348 error = ether_ioctl(ifp, cmd, data);
2349 break;
2350 }
2351
2352 return (error);
2353}
2354
2355static void
2356alc_mac_config(struct alc_softc *sc)
2357{
2358 struct mii_data *mii;
2359 uint32_t reg;
2360
bbf76eec
MD
2361 mii = device_get_softc(sc->alc_miibus);
2362 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2363 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2364 MAC_CFG_SPEED_MASK);
cffbd125
MD
2365 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
2366 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
2367 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
2368 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
2369 }
bbf76eec
MD
2370 /* Reprogram MAC with resolved speed/duplex. */
2371 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2372 case IFM_10_T:
2373 case IFM_100_TX:
2374 reg |= MAC_CFG_SPEED_10_100;
2375 break;
2376 case IFM_1000_T:
2377 reg |= MAC_CFG_SPEED_1000;
2378 break;
2379 }
2380 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2381 reg |= MAC_CFG_FULL_DUPLEX;
2382#ifdef notyet
2383 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2384 reg |= MAC_CFG_TX_FC;
2385 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2386 reg |= MAC_CFG_RX_FC;
2387#endif
2388 }
2389 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2390}
2391
2392static void
2393alc_stats_clear(struct alc_softc *sc)
2394{
2395 struct smb sb, *smb;
2396 uint32_t *reg;
2397 int i;
2398
2399 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2400 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2401 sc->alc_cdata.alc_smb_map,
2402 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2403 smb = sc->alc_rdata.alc_smb;
2404 /* Update done, clear. */
2405 smb->updated = 0;
2406 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2407 sc->alc_cdata.alc_smb_map,
2408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2409 } else {
2410 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2411 reg++) {
2412 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2413 i += sizeof(uint32_t);
2414 }
2415 /* Read Tx statistics. */
2416 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2417 reg++) {
2418 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2419 i += sizeof(uint32_t);
2420 }
2421 }
2422}
2423
2424static void
2425alc_stats_update(struct alc_softc *sc)
2426{
2427 struct alc_hw_stats *stat;
2428 struct smb sb, *smb;
2429 struct ifnet *ifp;
2430 uint32_t *reg;
2431 int i;
2432
bbf76eec
MD
2433 ifp = sc->alc_ifp;
2434 stat = &sc->alc_stats;
2435 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2436 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2437 sc->alc_cdata.alc_smb_map,
2438 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2439 smb = sc->alc_rdata.alc_smb;
2440 if (smb->updated == 0)
2441 return;
2442 } else {
2443 smb = &sb;
2444 /* Read Rx statistics. */
2445 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2446 reg++) {
2447 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2448 i += sizeof(uint32_t);
2449 }
2450 /* Read Tx statistics. */
2451 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2452 reg++) {
2453 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2454 i += sizeof(uint32_t);
2455 }
2456 }
2457
2458 /* Rx stats. */
2459 stat->rx_frames += smb->rx_frames;
2460 stat->rx_bcast_frames += smb->rx_bcast_frames;
2461 stat->rx_mcast_frames += smb->rx_mcast_frames;
2462 stat->rx_pause_frames += smb->rx_pause_frames;
2463 stat->rx_control_frames += smb->rx_control_frames;
2464 stat->rx_crcerrs += smb->rx_crcerrs;
2465 stat->rx_lenerrs += smb->rx_lenerrs;
2466 stat->rx_bytes += smb->rx_bytes;
2467 stat->rx_runts += smb->rx_runts;
2468 stat->rx_fragments += smb->rx_fragments;
2469 stat->rx_pkts_64 += smb->rx_pkts_64;
2470 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2471 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2472 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2473 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2474 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2475 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2476 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2477 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2478 stat->rx_rrs_errs += smb->rx_rrs_errs;
2479 stat->rx_alignerrs += smb->rx_alignerrs;
2480 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2481 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2482 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2483
2484 /* Tx stats. */
2485 stat->tx_frames += smb->tx_frames;
2486 stat->tx_bcast_frames += smb->tx_bcast_frames;
2487 stat->tx_mcast_frames += smb->tx_mcast_frames;
2488 stat->tx_pause_frames += smb->tx_pause_frames;
2489 stat->tx_excess_defer += smb->tx_excess_defer;
2490 stat->tx_control_frames += smb->tx_control_frames;
2491 stat->tx_deferred += smb->tx_deferred;
2492 stat->tx_bytes += smb->tx_bytes;
2493 stat->tx_pkts_64 += smb->tx_pkts_64;
2494 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2495 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2496 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2497 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2498 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2499 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2500 stat->tx_single_colls += smb->tx_single_colls;
2501 stat->tx_multi_colls += smb->tx_multi_colls;
2502 stat->tx_late_colls += smb->tx_late_colls;
2503 stat->tx_excess_colls += smb->tx_excess_colls;
2504 stat->tx_abort += smb->tx_abort;
2505 stat->tx_underrun += smb->tx_underrun;
2506 stat->tx_desc_underrun += smb->tx_desc_underrun;
2507 stat->tx_lenerrs += smb->tx_lenerrs;
2508 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2509 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2510 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2511
2512 /* Update counters in ifnet. */
2513 ifp->if_opackets += smb->tx_frames;
2514
2515 ifp->if_collisions += smb->tx_single_colls +
2516 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2517 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2518
2519 /*
2520 * XXX
2521 * tx_pkts_truncated counter looks suspicious. It constantly
2522 * increments with no sign of Tx errors. This may indicate
2523 * the counter name is not correct one so I've removed the
2524 * counter in output errors.
2525 */
2526 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2527 smb->tx_underrun;
2528
2529 ifp->if_ipackets += smb->rx_frames;
2530
2531 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2532 smb->rx_runts + smb->rx_pkts_truncated +
2533 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2534 smb->rx_alignerrs;
2535
2536 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2537 /* Update done, clear. */
2538 smb->updated = 0;
2539 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
2540 sc->alc_cdata.alc_smb_map,
2541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2542 }
2543}
2544
2545static void
2546alc_intr(void *arg)
2547{
a0e18bfd
SZ
2548 struct alc_softc *sc = arg;
2549 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec
MD
2550 uint32_t status;
2551
a0e18bfd 2552 ASSERT_SERIALIZED(ifp->if_serializer);
bbf76eec
MD
2553
2554 status = CSR_READ_4(sc, ALC_INTR_STATUS);
bbf76eec 2555 if ((status & ALC_INTRS) == 0)
a0e18bfd 2556 return;
bbf76eec 2557
a0e18bfd 2558 /* Acknowledge interrupts and disable interrupts. */
bbf76eec
MD
2559 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2560
a0e18bfd
SZ
2561 if (ifp->if_flags & IFF_RUNNING) {
2562 if (status & INTR_RX_PKT) {
2563 if (alc_rxintr(sc)) {
2564 alc_init(sc);
bbf76eec
MD
2565 return;
2566 }
2567 }
a0e18bfd
SZ
2568 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
2569 INTR_TXQ_TO_RST)) {
2570 if (status & INTR_DMA_RD_TO_RST) {
2571 if_printf(ifp,
bbf76eec 2572 "DMA read error! -- resetting\n");
a0e18bfd
SZ
2573 }
2574 if (status & INTR_DMA_WR_TO_RST) {
2575 if_printf(ifp,
bbf76eec 2576 "DMA write error! -- resetting\n");
a0e18bfd
SZ
2577 }
2578 if (status & INTR_TXQ_TO_RST)
2579 if_printf(ifp, "TxQ reset! -- resetting\n");
2580 alc_init(sc);
bbf76eec
MD
2581 return;
2582 }
a0e18bfd
SZ
2583 if (!ifq_is_empty(&ifp->if_snd))
2584 if_devstart(ifp);
bbf76eec 2585
a0e18bfd 2586 /* Re-enable interrupts */
bbf76eec
MD
2587 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2588 }
2589}
2590
2591static void
2592alc_txeof(struct alc_softc *sc)
2593{
2594 struct ifnet *ifp;
2595 struct alc_txdesc *txd;
2596 uint32_t cons, prod;
2597 int prog;
2598
bbf76eec
MD
2599 ifp = sc->alc_ifp;
2600
2601 if (sc->alc_cdata.alc_tx_cnt == 0)
2602 return;
2603 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2604 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2605 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2606 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2607 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
2608 prod = sc->alc_rdata.alc_cmb->cons;
2609 } else
2610 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2611 /* Assume we're using normal Tx priority queue. */
2612 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
2613 MBOX_TD_CONS_LO_IDX_SHIFT;
2614 cons = sc->alc_cdata.alc_tx_cons;
2615 /*
2616 * Go through our Tx list and free mbufs for those
2617 * frames which have been transmitted.
2618 */
2619 for (prog = 0; cons != prod; prog++,
2620 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
2621 if (sc->alc_cdata.alc_tx_cnt <= 0)
2622 break;
2623 prog++;
2624 ifp->if_flags &= ~IFF_OACTIVE;
2625 sc->alc_cdata.alc_tx_cnt--;
2626 txd = &sc->alc_cdata.alc_txdesc[cons];
2627 if (txd->tx_m != NULL) {
2628 /* Reclaim transmitted mbufs. */
2629 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
2630 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2631 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
2632 txd->tx_dmamap);
2633 m_freem(txd->tx_m);
2634 txd->tx_m = NULL;
2635 }
2636 }
2637
2638 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2639 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
2640 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
2641 sc->alc_cdata.alc_tx_cons = cons;
2642 /*
2643 * Unarm watchdog timer only when there is no pending
2644 * frames in Tx queue.
2645 */
2646 if (sc->alc_cdata.alc_tx_cnt == 0)
2647 sc->alc_watchdog_timer = 0;
2648}
2649
2650static int
a0e18bfd 2651alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, boolean_t wait)
bbf76eec
MD
2652{
2653 struct mbuf *m;
2654 bus_dma_segment_t segs[1];
2655 bus_dmamap_t map;
2656 int nsegs;
f753ef49 2657 int error;
bbf76eec 2658
a0e18bfd 2659 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
bbf76eec
MD
2660 if (m == NULL)
2661 return (ENOBUFS);
a0e18bfd
SZ
2662 m->m_len = m->m_pkthdr.len = MCLBYTES;
2663#ifdef foo
2664 /* Hardware require 4 bytes align */
2665 m_adj(m, ETHER_ALIGN);
bbf76eec
MD
2666#endif
2667
f753ef49
MD
2668 error = bus_dmamap_load_mbuf_segment(
2669 sc->alc_cdata.alc_rx_tag,
2670 sc->alc_cdata.alc_rx_sparemap,
2671 m, segs, 1, &nsegs, BUS_DMA_NOWAIT);
2672 if (error) {
bbf76eec
MD
2673 m_freem(m);
2674 return (ENOBUFS);
2675 }
2676 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2677
2678 if (rxd->rx_m != NULL) {
2679 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2680 BUS_DMASYNC_POSTREAD);
2681 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
2682 }
2683 map = rxd->rx_dmamap;
2684 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
2685 sc->alc_cdata.alc_rx_sparemap = map;
2686 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
2687 BUS_DMASYNC_PREREAD);
2688 rxd->rx_m = m;
2689 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
2690 return (0);
2691}
2692
2693static int
a0e18bfd 2694alc_rxintr(struct alc_softc *sc)
bbf76eec
MD
2695{
2696 struct ifnet *ifp;
2697 struct rx_rdesc *rrd;
2698 uint32_t nsegs, status;
2699 int rr_cons, prog;
2700
2701 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2702 sc->alc_cdata.alc_rr_ring_map,
2703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2704 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2705 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2706 rr_cons = sc->alc_cdata.alc_rr_cons;
2707 ifp = sc->alc_ifp;
2708 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) {
bbf76eec
MD
2709 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
2710 status = le32toh(rrd->status);
2711 if ((status & RRD_VALID) == 0)
2712 break;
2713 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
2714 if (nsegs == 0) {
2715 /* This should not happen! */
2716 device_printf(sc->alc_dev,
2717 "unexpected segment count -- resetting\n");
2718 return (EIO);
2719 }
2720 alc_rxeof(sc, rrd);
2721 /* Clear Rx return status. */
2722 rrd->status = 0;
2723 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
2724 sc->alc_cdata.alc_rx_cons += nsegs;
2725 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
2726 prog += nsegs;
2727 }
2728
2729 if (prog > 0) {
2730 /* Update the consumer index. */
2731 sc->alc_cdata.alc_rr_cons = rr_cons;
2732 /* Sync Rx return descriptors. */
2733 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
2734 sc->alc_cdata.alc_rr_ring_map,
2735 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2736 /*
2737 * Sync updated Rx descriptors such that controller see
2738 * modified buffer addresses.
2739 */
2740 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
2741 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
2742 /*
2743 * Let controller know availability of new Rx buffers.
2744 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
2745 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
2746 * only when Rx buffer pre-fetching is required. In
2747 * addition we already set ALC_RX_RD_FREE_THRESH to
2748 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
2749 * it still seems that pre-fetching needs more
2750 * experimentation.
2751 */
2752 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2753 sc->alc_cdata.alc_rx_cons);
2754 }
2755
a0e18bfd 2756 return 0;
bbf76eec
MD
2757}
2758
bbf76eec
MD
2759/* Receive a frame. */
2760static void
2761alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
2762{
2763 struct alc_rxdesc *rxd;
2764 struct ifnet *ifp;
2765 struct mbuf *mp, *m;
2766 uint32_t rdinfo, status, vtag;
2767 int count, nsegs, rx_cons;
2768
2769 ifp = sc->alc_ifp;
2770 status = le32toh(rrd->status);
2771 rdinfo = le32toh(rrd->rdinfo);
2772 rx_cons = RRD_RD_IDX(rdinfo);
2773 nsegs = RRD_RD_CNT(rdinfo);
2774
2775 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
2776 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
2777 /*
2778 * We want to pass the following frames to upper
2779 * layer regardless of error status of Rx return
2780 * ring.
2781 *
2782 * o IP/TCP/UDP checksum is bad.
2783 * o frame length and protocol specific length
2784 * does not match.
2785 *
2786 * Force network stack compute checksum for
2787 * errored frames.
2788 */
2789 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
2790 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
2791 RRD_ERR_RUNT) != 0)
2792 return;
2793 }
2794
2795 for (count = 0; count < nsegs; count++,
2796 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
2797 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
2798 mp = rxd->rx_m;
2799 /* Add a new receive buffer to the ring. */
a0e18bfd 2800 if (alc_newbuf(sc, rxd, FALSE) != 0) {
bbf76eec
MD
2801 ifp->if_iqdrops++;
2802 /* Reuse Rx buffers. */
2803 if (sc->alc_cdata.alc_rxhead != NULL)
2804 m_freem(sc->alc_cdata.alc_rxhead);
2805 break;
2806 }
2807
2808 /*
2809 * Assume we've received a full sized frame.
2810 * Actual size is fixed when we encounter the end of
2811 * multi-segmented frame.
2812 */
2813 mp->m_len = sc->alc_buf_size;
2814
2815 /* Chain received mbufs. */
2816 if (sc->alc_cdata.alc_rxhead == NULL) {
2817 sc->alc_cdata.alc_rxhead = mp;
2818 sc->alc_cdata.alc_rxtail = mp;
2819 } else {
bbf76eec
MD
2820 sc->alc_cdata.alc_rxprev_tail =
2821 sc->alc_cdata.alc_rxtail;
2822 sc->alc_cdata.alc_rxtail->m_next = mp;
2823 sc->alc_cdata.alc_rxtail = mp;
2824 }
2825
2826 if (count == nsegs - 1) {
2827 /* Last desc. for this frame. */
2828 m = sc->alc_cdata.alc_rxhead;
bbf76eec
MD
2829 /*
2830 * It seems that L1C/L2C controller has no way
2831 * to tell hardware to strip CRC bytes.
2832 */
2833 m->m_pkthdr.len =
2834 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
2835 if (nsegs > 1) {
2836 /* Set last mbuf size. */
2837 mp->m_len = sc->alc_cdata.alc_rxlen -
2838 (nsegs - 1) * sc->alc_buf_size;
2839 /* Remove the CRC bytes in chained mbufs. */
2840 if (mp->m_len <= ETHER_CRC_LEN) {
2841 sc->alc_cdata.alc_rxtail =
2842 sc->alc_cdata.alc_rxprev_tail;
2843 sc->alc_cdata.alc_rxtail->m_len -=
2844 (ETHER_CRC_LEN - mp->m_len);
2845 sc->alc_cdata.alc_rxtail->m_next = NULL;
2846 m_freem(mp);
2847 } else {
2848 mp->m_len -= ETHER_CRC_LEN;
2849 }
2850 } else
2851 m->m_len = m->m_pkthdr.len;
2852 m->m_pkthdr.rcvif = ifp;
2853 /*
2854 * Due to hardware bugs, Rx checksum offloading
2855 * was intentionally disabled.
2856 */
2857 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2858 (status & RRD_VLAN_TAG) != 0) {
2859 vtag = RRD_VLAN(le32toh(rrd->vtag));
2860 m->m_pkthdr.ether_vlantag = ntohs(vtag);
2861 m->m_flags |= M_VLANTAG;
2862 }
a0e18bfd 2863
bbf76eec 2864 /* Pass it on. */
a0e18bfd 2865 ifp->if_input(ifp, m);
bbf76eec
MD
2866 }
2867 }
2868 /* Reset mbuf chains. */
2869 ALC_RXCHAIN_RESET(sc);
2870}
2871
2872static void
2873alc_tick(void *arg)
2874{
a0e18bfd
SZ
2875 struct alc_softc *sc = arg;
2876 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec
MD
2877 struct mii_data *mii;
2878
a0e18bfd 2879 lwkt_serialize_enter(ifp->if_serializer);
bbf76eec
MD
2880
2881 mii = device_get_softc(sc->alc_miibus);
2882 mii_tick(mii);
2883 alc_stats_update(sc);
2884 /*
2885 * alc(4) does not rely on Tx completion interrupts to reclaim
2886 * transferred buffers. Instead Tx completion interrupts are
2887 * used to hint for scheduling Tx task. So it's necessary to
2888 * release transmitted buffers by kicking Tx completion
2889 * handler. This limits the maximum reclamation delay to a hz.
2890 */
2891 alc_txeof(sc);
2892 alc_watchdog(sc);
2893 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
a0e18bfd
SZ
2894
2895 lwkt_serialize_exit(ifp->if_serializer);
bbf76eec
MD
2896}
2897
2898static void
2899alc_reset(struct alc_softc *sc)
2900{
2901 uint32_t reg;
2902 int i;
2903
cffbd125
MD
2904 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
2905 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
2906 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2907
bbf76eec
MD
2908 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2909 DELAY(10);
2910 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
2911 break;
2912 }
2913 if (i == 0)
2914 device_printf(sc->alc_dev, "master reset timeout!\n");
2915
2916 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2917 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
2918 break;
2919 DELAY(10);
2920 }
2921
2922 if (i == 0)
2923 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
2924}
2925
2926static void
2927alc_init(void *xsc)
2928{
a0e18bfd
SZ
2929 struct alc_softc *sc = xsc;
2930 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec
MD
2931 struct mii_data *mii;
2932 uint8_t eaddr[ETHER_ADDR_LEN];
2933 bus_addr_t paddr;
2934 uint32_t reg, rxf_hi, rxf_lo;
2935
a0e18bfd 2936 ASSERT_SERIALIZED(ifp->if_serializer);
bbf76eec 2937
bbf76eec
MD
2938 mii = device_get_softc(sc->alc_miibus);
2939
bbf76eec
MD
2940 /*
2941 * Cancel any pending I/O.
2942 */
2943 alc_stop(sc);
2944 /*
2945 * Reset the chip to a known state.
2946 */
2947 alc_reset(sc);
2948
2949 /* Initialize Rx descriptors. */
2950 if (alc_init_rx_ring(sc) != 0) {
2951 device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
2952 alc_stop(sc);
2953 return;
2954 }
2955 alc_init_rr_ring(sc);
2956 alc_init_tx_ring(sc);
2957 alc_init_cmb(sc);
2958 alc_init_smb(sc);
2959
2960 /* Reprogram the station address. */
2961 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2962 CSR_WRITE_4(sc, ALC_PAR0,
2963 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2964 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2965 /*
2966 * Clear WOL status and disable all WOL feature as WOL
2967 * would interfere Rx operation under normal environments.
2968 */
2969 CSR_READ_4(sc, ALC_WOL_CFG);
2970 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2971 /* Set Tx descriptor base addresses. */
2972 paddr = sc->alc_rdata.alc_tx_ring_paddr;
2973 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2974 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2975 /* We don't use high priority ring. */
2976 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2977 /* Set Tx descriptor counter. */
2978 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2979 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
2980 /* Set Rx descriptor base addresses. */
2981 paddr = sc->alc_rdata.alc_rx_ring_paddr;
2982 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2983 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2984 /* We use one Rx ring. */
2985 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2986 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2987 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2988 /* Set Rx descriptor counter. */
2989 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2990 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
2991
2992 /*
2993 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
2994 * if it do not fit the buffer size. Rx return descriptor holds
2995 * a counter that indicates how many fragments were made by the
2996 * hardware. The buffer size should be multiple of 8 bytes.
2997 * Since hardware has limit on the size of buffer size, always
2998 * use the maximum value.
2999 * For strict-alignment architectures make sure to reduce buffer
3000 * size by 8 bytes to make room for alignment fixup.
3001 */
bbf76eec 3002 sc->alc_buf_size = RX_BUF_SIZE_MAX;
bbf76eec
MD
3003 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
3004
3005 paddr = sc->alc_rdata.alc_rr_ring_paddr;
3006 /* Set Rx return descriptor base addresses. */
3007 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3008 /* We use one Rx return ring. */
3009 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
3010 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
3011 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
3012 /* Set Rx return descriptor counter. */
3013 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
3014 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
3015 paddr = sc->alc_rdata.alc_cmb_paddr;
3016 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
3017 paddr = sc->alc_rdata.alc_smb_paddr;
3018 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3019 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
3020
cffbd125
MD
3021 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
3022 /* Reconfigure SRAM - Vendor magic. */
3023 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
3024 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
3025 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
3026 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
3027 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
3028 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
3029 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
3030 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
3031 }
3032
bbf76eec
MD
3033 /* Tell hardware that we're ready to load DMA blocks. */
3034 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
3035
3036 /* Configure interrupt moderation timer. */
3037 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
3038 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
3039 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
bbf76eec
MD
3040 /*
3041 * We don't want to automatic interrupt clear as task queue
3042 * for the interrupt should know interrupt status.
3043 */
cffbd125 3044 reg = MASTER_SA_TIMER_ENB;
bbf76eec
MD
3045 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
3046 reg |= MASTER_IM_RX_TIMER_ENB;
3047 if (ALC_USECS(sc->alc_int_tx_mod) != 0)
3048 reg |= MASTER_IM_TX_TIMER_ENB;
3049 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3050 /*
3051 * Disable interrupt re-trigger timer. We don't want automatic
3052 * re-triggering of un-ACKed interrupts.
3053 */
3054 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
3055 /* Configure CMB. */
cffbd125
MD
3056 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
3057 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
bbf76eec 3058 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
cffbd125 3059 } else {
bbf76eec 3060 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
cffbd125 3061 }
bbf76eec
MD
3062 /*
3063 * Hardware can be configured to issue SMB interrupt based
3064 * on programmed interval. Since there is a callout that is
3065 * invoked for every hz in driver we use that instead of
3066 * relying on periodic SMB interrupt.
3067 */
3068 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
3069 /* Clear MAC statistics. */
3070 alc_stats_clear(sc);
3071
3072 /*
3073 * Always use maximum frame size that controller can support.
3074 * Otherwise received frames that has larger frame length
3075 * than alc(4) MTU would be silently dropped in hardware. This
3076 * would make path-MTU discovery hard as sender wouldn't get
3077 * any responses from receiver. alc(4) supports
3078 * multi-fragmented frames on Rx path so it has no issue on
3079 * assembling fragmented frames. Using maximum frame size also
3080 * removes the need to reinitialize hardware when interface
3081 * MTU configuration was changed.
3082 *
3083 * Be conservative in what you do, be liberal in what you
3084 * accept from others - RFC 793.
3085 */
cffbd125 3086 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
bbf76eec
MD
3087
3088 /* Disable header split(?) */
3089 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
3090
3091 /* Configure IPG/IFG parameters. */
3092 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
3093 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
3094 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
3095 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
3096 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
3097 /* Set parameters for half-duplex media. */
3098 CSR_WRITE_4(sc, ALC_HDPX_CFG,
3099 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
3100 HDPX_CFG_LCOL_MASK) |
3101 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
3102 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
3103 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
3104 HDPX_CFG_ABEBT_MASK) |
3105 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
3106 HDPX_CFG_JAMIPG_MASK));
3107 /*
3108 * Set TSO/checksum offload threshold. For frames that is
3109 * larger than this threshold, hardware wouldn't do
3110 * TSO/checksum offloading.
3111 */
3112 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
cffbd125 3113 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
bbf76eec
MD
3114 TSO_OFFLOAD_THRESH_MASK);
3115 /* Configure TxQ. */
3116 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
3117 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
cffbd125
MD
3118 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3119 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
3120 reg >>= 1;
3121 }
bbf76eec
MD
3122 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
3123 TXQ_CFG_TD_BURST_MASK;
3124 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
3125
3126 /* Configure Rx free descriptor pre-fetching. */
3127 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
3128 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) &
3129 RX_RD_FREE_THRESH_HI_MASK) |
3130 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) &
3131 RX_RD_FREE_THRESH_LO_MASK));
3132
3133 /*
3134 * Configure flow control parameters.
3135 * XON : 80% of Rx FIFO
3136 * XOFF : 30% of Rx FIFO
3137 */
cffbd125
MD
3138 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
3139 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) {
3140 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3141 rxf_hi = (reg * 8) / 10;
3142 rxf_lo = (reg * 3) / 10;
3143 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3144 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
3145 RX_FIFO_PAUSE_THRESH_LO_MASK) |
3146 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
3147 RX_FIFO_PAUSE_THRESH_HI_MASK));
3148 }
3149
3150 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3151 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) {
3152 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
3153 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
3154 SERDES_PHY_CLK_SLOWDOWN);
3155 }
bbf76eec
MD
3156
3157 /* Disable RSS until I understand L1C/L2C's RSS logic. */
3158 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
3159 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
3160
3161 /* Configure RxQ. */
3162 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
3163 RXQ_CFG_RD_BURST_MASK;
3164 reg |= RXQ_CFG_RSS_MODE_DIS;
3165 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
cffbd125 3166 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
bbf76eec
MD
3167 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3168
bbf76eec
MD
3169 /* Configure DMA parameters. */
3170 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
3171 reg |= sc->alc_rcb;
3172 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3173 reg |= DMA_CFG_CMB_ENB;
3174 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
3175 reg |= DMA_CFG_SMB_ENB;
3176 else
3177 reg |= DMA_CFG_SMB_DIS;
3178 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
3179 DMA_CFG_RD_BURST_SHIFT;
3180 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
3181 DMA_CFG_WR_BURST_SHIFT;
3182 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
3183 DMA_CFG_RD_DELAY_CNT_MASK;
3184 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
3185 DMA_CFG_WR_DELAY_CNT_MASK;
3186 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3187
3188 /*
3189 * Configure Tx/Rx MACs.
3190 * - Auto-padding for short frames.
3191 * - Enable CRC generation.
3192 * Actual reconfiguration of MAC for resolved speed/duplex
3193 * is followed after detection of link establishment.
cffbd125 3194 * AR813x/AR815x always does checksum computation regardless
bbf76eec
MD
3195 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
3196 * have bug in protocol field in Rx return structure so
3197 * these controllers can't handle fragmented frames. Disable
3198 * Rx checksum offloading until there is a newer controller
3199 * that has sane implementation.
3200 */
3201 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
3202 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
3203 MAC_CFG_PREAMBLE_MASK);
cffbd125
MD
3204 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
3205 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
3206 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
3207 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
3208 }
bbf76eec
MD
3209 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
3210 reg |= MAC_CFG_SPEED_10_100;
3211 else
3212 reg |= MAC_CFG_SPEED_1000;
3213 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3214
3215 /* Set up the receive filter. */
3216 alc_rxfilter(sc);
3217 alc_rxvlan(sc);
3218
3219 /* Acknowledge all pending interrupts and clear it. */
3220 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3221 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3222 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3223
3224 sc->alc_flags &= ~ALC_FLAG_LINK;
3225 /* Switch to the current media. */
3226 mii_mediachg(mii);
3227
3228 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3229
3230 ifp->if_flags |= IFF_RUNNING;
3231 ifp->if_flags &= ~IFF_OACTIVE;
3232}
3233
3234static void
3235alc_stop(struct alc_softc *sc)
3236{
a0e18bfd 3237 struct ifnet *ifp = &sc->arpcom.ac_if;
bbf76eec
MD
3238 struct alc_txdesc *txd;
3239 struct alc_rxdesc *rxd;
3240 uint32_t reg;
3241 int i;
3242
a0e18bfd
SZ
3243 ASSERT_SERIALIZED(ifp->if_serializer);
3244
bbf76eec
MD
3245 /*
3246 * Mark the interface down and cancel the watchdog timer.
3247 */
bbf76eec
MD
3248 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3249 sc->alc_flags &= ~ALC_FLAG_LINK;
3250 callout_stop(&sc->alc_tick_ch);
3251 sc->alc_watchdog_timer = 0;
3252 alc_stats_update(sc);
3253 /* Disable interrupts. */
3254 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3255 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3256 alc_stop_queue(sc);
3257 /* Disable DMA. */
3258 reg = CSR_READ_4(sc, ALC_DMA_CFG);
3259 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
3260 reg |= DMA_CFG_SMB_DIS;
3261 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3262 DELAY(1000);
3263 /* Stop Rx/Tx MACs. */
3264 alc_stop_mac(sc);
3265 /* Disable interrupts which might be touched in taskq handler. */
3266 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3267
3268 /* Reclaim Rx buffers that have been processed. */
3269 if (sc->alc_cdata.alc_rxhead != NULL)
3270 m_freem(sc->alc_cdata.alc_rxhead);
3271 ALC_RXCHAIN_RESET(sc);
3272 /*
3273 * Free Tx/Rx mbufs still in the queues.
3274 */
3275 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3276 rxd = &sc->alc_cdata.alc_rxdesc[i];
3277 if (rxd->rx_m != NULL) {
3278 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
3279 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3280 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
3281 rxd->rx_dmamap);
3282 m_freem(rxd->rx_m);
3283 rxd->rx_m = NULL;
3284 }
3285 }
3286 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3287 txd = &sc->alc_cdata.alc_txdesc[i];
3288 if (txd->tx_m != NULL) {
3289 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3290 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3291 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3292 txd->tx_dmamap);
3293 m_freem(txd->tx_m);
3294 txd->tx_m = NULL;
3295 }
3296 }
3297}
3298
3299static void
3300alc_stop_mac(struct alc_softc *sc)
3301{
3302 uint32_t reg;
3303 int i;
3304
bbf76eec
MD
3305 /* Disable Rx/Tx MAC. */
3306 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3307 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
3308 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
3309 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3310 }
3311 for (i = ALC_TIMEOUT; i > 0; i--) {
3312 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3313 if (reg == 0)
3314 break;
3315 DELAY(10);
3316 }
3317 if (i == 0)
3318 device_printf(sc->alc_dev,
3319 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
3320}
3321
3322static void
3323alc_start_queue(struct alc_softc *sc)
3324{
3325 uint32_t qcfg[] = {
3326 0,
3327 RXQ_CFG_QUEUE0_ENB,
3328 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
3329 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
3330 RXQ_CFG_ENB
3331 };
3332 uint32_t cfg;
3333
bbf76eec
MD
3334 /* Enable RxQ. */
3335 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3336 cfg &= ~RXQ_CFG_ENB;
3337 cfg |= qcfg[1];
3338 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3339 /* Enable TxQ. */
3340 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3341 cfg |= TXQ_CFG_ENB;
3342 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3343}
3344
3345static void
3346alc_stop_queue(struct alc_softc *sc)
3347{
3348 uint32_t reg;
3349 int i;
3350
bbf76eec
MD
3351 /* Disable RxQ. */
3352 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3353 if ((reg & RXQ_CFG_ENB) != 0) {
3354 reg &= ~RXQ_CFG_ENB;
3355 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3356 }
3357 /* Disable TxQ. */
3358 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3359 if ((reg & TXQ_CFG_ENB) == 0) {
3360 reg &= ~TXQ_CFG_ENB;
3361 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3362 }
3363 for (i = ALC_TIMEOUT; i > 0; i--) {
3364 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3365 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3366 break;
3367 DELAY(10);
3368 }
3369 if (i == 0)
3370 device_printf(sc->alc_dev,
3371 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
3372}
3373
3374static void
3375alc_init_tx_ring(struct alc_softc *sc)
3376{
3377 struct alc_ring_data *rd;
3378 struct alc_txdesc *txd;
3379 int i;
3380
bbf76eec
MD
3381 sc->alc_cdata.alc_tx_prod = 0;
3382 sc->alc_cdata.alc_tx_cons = 0;
3383 sc->alc_cdata.alc_tx_cnt = 0;
3384
3385 rd = &sc->alc_rdata;
3386 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
3387 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3388 txd = &sc->alc_cdata.alc_txdesc[i];
3389 txd->tx_m = NULL;
3390 }
3391
3392 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3393 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
3394}
3395
3396static int
3397alc_init_rx_ring(struct alc_softc *sc)
3398{
3399 struct alc_ring_data *rd;
3400 struct alc_rxdesc *rxd;
3401 int i;
3402
bbf76eec 3403 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
bbf76eec
MD
3404 rd = &sc->alc_rdata;
3405 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
3406 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3407 rxd = &sc->alc_cdata.alc_rxdesc[i];
3408 rxd->rx_m = NULL;
3409 rxd->rx_desc = &rd->alc_rx_ring[i];
a0e18bfd 3410 if (alc_newbuf(sc, rxd, TRUE) != 0)
bbf76eec
MD
3411 return (ENOBUFS);
3412 }
3413
3414 /*
3415 * Since controller does not update Rx descriptors, driver
3416 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
3417 * is enough to ensure coherence.
3418 */
3419 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3420 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3421 /* Let controller know availability of new Rx buffers. */
3422 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3423
3424 return (0);
3425}
3426
3427static void
3428alc_init_rr_ring(struct alc_softc *sc)
3429{
3430 struct alc_ring_data *rd;
3431
bbf76eec
MD
3432 sc->alc_cdata.alc_rr_cons = 0;
3433 ALC_RXCHAIN_RESET(sc);
3434
3435 rd = &sc->alc_rdata;
3436 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
3437 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3438 sc->alc_cdata.alc_rr_ring_map,
3439 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3440}
3441
3442static void
3443alc_init_cmb(struct alc_softc *sc)
3444{
3445 struct alc_ring_data *rd;
3446
bbf76eec
MD
3447 rd = &sc->alc_rdata;
3448 bzero(rd->alc_cmb, ALC_CMB_SZ);
3449 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
3450 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3451}
3452
3453static void
3454alc_init_smb(struct alc_softc *sc)
3455{
3456 struct alc_ring_data *rd;
3457
bbf76eec
MD
3458 rd = &sc->alc_rdata;
3459 bzero(rd->alc_smb, ALC_SMB_SZ);
3460 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
3461 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3462}
3463
3464static void
3465alc_rxvlan(struct alc_softc *sc)
3466{
3467 struct ifnet *ifp;
3468 uint32_t reg;
3469
bbf76eec
MD
3470 ifp = sc->alc_ifp;
3471 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3472 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3473 reg |= MAC_CFG_VLAN_TAG_STRIP;
3474 else
3475 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3476 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3477}
3478
3479static void
3480alc_rxfilter(struct alc_softc *sc)
3481{
3482 struct ifnet *ifp;
3483 struct ifmultiaddr *ifma;
3484 uint32_t crc;
3485 uint32_t mchash[2];
3486 uint32_t rxcfg;
3487
bbf76eec
MD
3488 ifp = sc->alc_ifp;
3489
3490 bzero(mchash, sizeof(mchash));
3491 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
3492 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3493 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3494 rxcfg |= MAC_CFG_BCAST;
3495 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3496 if ((ifp->if_flags & IFF_PROMISC) != 0)
3497 rxcfg |= MAC_CFG_PROMISC;
3498 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3499 rxcfg |= MAC_CFG_ALLMULTI;
3500 mchash[0] = 0xFFFFFFFF;
3501 mchash[1] = 0xFFFFFFFF;
3502 goto chipit;
3503 }
3504
3505#if 0
3506 /* XXX */
3507 if_maddr_rlock(ifp);
3508#endif
441d34b2 3509 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) {
bbf76eec
MD
3510 if (ifma->ifma_addr->sa_family != AF_LINK)
3511 continue;
3512 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3513 ifma->ifma_addr), ETHER_ADDR_LEN);
3514 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3515 }
3516#if 0
3517 /* XXX */
3518 if_maddr_runlock(ifp);
3519#endif
3520
3521chipit:
3522 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3523 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3524 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
3525}
3526
3527static int
3528sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
3529{
3530 return (sysctl_int_range(oidp, arg1, arg2, req,
3531 ALC_PROC_MIN, ALC_PROC_MAX));
3532}
3533
3534static int
3535sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
3536{
3537
3538 return (sysctl_int_range(oidp, arg1, arg2, req,
3539 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));
3540}