em/emx: Fix up detach path
[dragonfly.git] / sys / dev / netif / em / if_em.c
CommitLineData
78195a76 1/*
78195a76
MD
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
9c80d176 4 * Copyright (c) 2001-2008, Intel Corporation
78195a76
MD
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9c80d176 9 *
78195a76
MD
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
9c80d176 12 *
78195a76
MD
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
9c80d176 16 *
78195a76
MD
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
9c80d176 20 *
78195a76
MD
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
9c80d176 35 *
78195a76
MD
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
9c80d176 38 *
78195a76
MD
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
9c80d176 42 *
78195a76
MD
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
9c80d176 52 *
78195a76
MD
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
9c80d176 65 *
78195a76
MD
66 */
67/*
68 * SERIALIZATION API RULES:
69 *
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
9c80d176 72 * driver.
78195a76
MD
73 *
74 * - ifmedia entry points will be serialized by the ifmedia code using the
75 * ifnet serializer.
76 *
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
79 *
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
82 *
83 * - The device driver typically holds the serializer at the time it wishes
9c80d176
SZ
84 * to call if_input.
85 *
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
78195a76
MD
90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
2b71c8f1
SZ
95
96#include "opt_polling.h"
87307ba1
SZ
97
98#include <sys/param.h>
99#include <sys/bus.h>
100#include <sys/endian.h>
9db4b353 101#include <sys/interrupt.h>
87307ba1
SZ
102#include <sys/kernel.h>
103#include <sys/ktr.h>
104#include <sys/malloc.h>
105#include <sys/mbuf.h>
9c80d176 106#include <sys/proc.h>
87307ba1
SZ
107#include <sys/rman.h>
108#include <sys/serialize.h>
109#include <sys/socket.h>
110#include <sys/sockio.h>
111#include <sys/sysctl.h>
9c80d176 112#include <sys/systm.h>
87307ba1
SZ
113
114#include <net/bpf.h>
115#include <net/ethernet.h>
116#include <net/if.h>
117#include <net/if_arp.h>
118#include <net/if_dl.h>
119#include <net/if_media.h>
87307ba1
SZ
120#include <net/ifq_var.h>
121#include <net/vlan/if_vlan_var.h>
b637f170 122#include <net/vlan/if_vlan_ether.h>
87307ba1 123
87307ba1 124#include <netinet/in_systm.h>
9c80d176 125#include <netinet/in.h>
87307ba1
SZ
126#include <netinet/ip.h>
127#include <netinet/tcp.h>
128#include <netinet/udp.h>
984263bc 129
9c80d176
SZ
130#include <bus/pci/pcivar.h>
131#include <bus/pci/pcireg.h>
984263bc 132
9c80d176
SZ
133#include <dev/netif/ig_hal/e1000_api.h>
134#include <dev/netif/ig_hal/e1000_82571.h>
135#include <dev/netif/em/if_em.h>
984263bc 136
9c80d176 137#define EM_NAME "Intel(R) PRO/1000 Network Connection "
6d5e2922 138#define EM_VER " 7.2.4"
9c80d176 139
96ced48a
SZ
140#define _EM_DEVICE(id, ret) \
141 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
142#define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
143#define EM_DEVICE(id) _EM_DEVICE(id, 0)
144#define EM_DEVICE_NULL { 0, 0, 0, NULL }
9c80d176
SZ
145
146static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM),
148 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP),
150 EM_DEVICE(82540EP_LOM),
151 EM_DEVICE(82540EP_LP),
152
153 EM_DEVICE(82541EI),
154 EM_DEVICE(82541ER),
155 EM_DEVICE(82541ER_LOM),
156 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI),
158 EM_DEVICE(82541GI_LF),
159 EM_DEVICE(82541GI_MOBILE),
160
161 EM_DEVICE(82542),
162
163 EM_DEVICE(82543GC_FIBER),
164 EM_DEVICE(82543GC_COPPER),
165
166 EM_DEVICE(82544EI_COPPER),
167 EM_DEVICE(82544EI_FIBER),
168 EM_DEVICE(82544GC_COPPER),
169 EM_DEVICE(82544GC_LOM),
170
171 EM_DEVICE(82545EM_COPPER),
172 EM_DEVICE(82545EM_FIBER),
173 EM_DEVICE(82545GM_COPPER),
174 EM_DEVICE(82545GM_FIBER),
175 EM_DEVICE(82545GM_SERDES),
176
177 EM_DEVICE(82546EB_COPPER),
178 EM_DEVICE(82546EB_FIBER),
179 EM_DEVICE(82546EB_QUAD_COPPER),
180 EM_DEVICE(82546GB_COPPER),
181 EM_DEVICE(82546GB_FIBER),
182 EM_DEVICE(82546GB_SERDES),
183 EM_DEVICE(82546GB_PCIE),
184 EM_DEVICE(82546GB_QUAD_COPPER),
185 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
186
187 EM_DEVICE(82547EI),
188 EM_DEVICE(82547EI_MOBILE),
189 EM_DEVICE(82547GI),
190
96ced48a
SZ
191 EM_EMX_DEVICE(82571EB_COPPER),
192 EM_EMX_DEVICE(82571EB_FIBER),
193 EM_EMX_DEVICE(82571EB_SERDES),
194 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
195 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
96ced48a
SZ
198 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
199 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
200 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201
202 EM_EMX_DEVICE(82572EI_COPPER),
203 EM_EMX_DEVICE(82572EI_FIBER),
204 EM_EMX_DEVICE(82572EI_SERDES),
205 EM_EMX_DEVICE(82572EI),
206
207 EM_EMX_DEVICE(82573E),
208 EM_EMX_DEVICE(82573E_IAMT),
209 EM_EMX_DEVICE(82573L),
210
2d0e5700
SZ
211 EM_DEVICE(82583V),
212
96ced48a
SZ
213 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
215 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
216 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
9c80d176
SZ
217
218 EM_DEVICE(ICH8_IGP_M_AMT),
219 EM_DEVICE(ICH8_IGP_AMT),
220 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE),
222 EM_DEVICE(ICH8_IFE_GT),
223 EM_DEVICE(ICH8_IFE_G),
224 EM_DEVICE(ICH8_IGP_M),
2d0e5700 225 EM_DEVICE(ICH8_82567V_3),
9c80d176
SZ
226
227 EM_DEVICE(ICH9_IGP_M_AMT),
228 EM_DEVICE(ICH9_IGP_AMT),
229 EM_DEVICE(ICH9_IGP_C),
230 EM_DEVICE(ICH9_IGP_M),
231 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE),
233 EM_DEVICE(ICH9_IFE_GT),
234 EM_DEVICE(ICH9_IFE_G),
235 EM_DEVICE(ICH9_BM),
236
96ced48a 237 EM_EMX_DEVICE(82574L),
2d0e5700 238 EM_EMX_DEVICE(82574LA),
9c80d176
SZ
239
240 EM_DEVICE(ICH10_R_BM_LM),
241 EM_DEVICE(ICH10_R_BM_LF),
242 EM_DEVICE(ICH10_R_BM_V),
243 EM_DEVICE(ICH10_D_BM_LM),
244 EM_DEVICE(ICH10_D_BM_LF),
2d0e5700
SZ
245 EM_DEVICE(ICH10_D_BM_V),
246
247 EM_DEVICE(PCH_M_HV_LM),
248 EM_DEVICE(PCH_M_HV_LC),
249 EM_DEVICE(PCH_D_HV_DM),
250 EM_DEVICE(PCH_D_HV_DC),
251
252 EM_DEVICE(PCH2_LV_LM),
253 EM_DEVICE(PCH2_LV_V),
984263bc 254
f647ad3d 255 /* required last entry */
9c80d176 256 EM_DEVICE_NULL
984263bc
MD
257};
258
f647ad3d
JS
259static int em_probe(device_t);
260static int em_attach(device_t);
261static int em_detach(device_t);
262static int em_shutdown(device_t);
87307ba1
SZ
263static int em_suspend(device_t);
264static int em_resume(device_t);
9c80d176
SZ
265
266static void em_init(void *);
267static void em_stop(struct adapter *);
f647ad3d 268static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
9c80d176
SZ
269static void em_start(struct ifnet *);
270#ifdef DEVICE_POLLING
271static void em_poll(struct ifnet *, enum poll_cmd, int);
272#endif
f647ad3d 273static void em_watchdog(struct ifnet *);
f647ad3d
JS
274static void em_media_status(struct ifnet *, struct ifmediareq *);
275static int em_media_change(struct ifnet *);
9c80d176
SZ
276static void em_timer(void *);
277
278static void em_intr(void *);
87ab432b
SZ
279static void em_intr_mask(void *);
280static void em_intr_body(struct adapter *, boolean_t);
9c80d176
SZ
281static void em_rxeof(struct adapter *, int);
282static void em_txeof(struct adapter *);
9f60d74b 283static void em_tx_collect(struct adapter *);
9c80d176 284static void em_tx_purge(struct adapter *);
f647ad3d
JS
285static void em_enable_intr(struct adapter *);
286static void em_disable_intr(struct adapter *);
9c80d176
SZ
287
288static int em_dma_malloc(struct adapter *, bus_size_t,
289 struct em_dma_alloc *);
290static void em_dma_free(struct adapter *, struct em_dma_alloc *);
291static void em_init_tx_ring(struct adapter *);
292static int em_init_rx_ring(struct adapter *);
293static int em_create_tx_ring(struct adapter *);
294static int em_create_rx_ring(struct adapter *);
295static void em_destroy_tx_ring(struct adapter *, int);
296static void em_destroy_rx_ring(struct adapter *, int);
297static int em_newbuf(struct adapter *, int, int);
298static int em_encap(struct adapter *, struct mbuf **);
299static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
300 struct mbuf *);
002b3a05 301static int em_txcsum_pullup(struct adapter *, struct mbuf **);
9f60d74b 302static int em_txcsum(struct adapter *, struct mbuf *,
9c80d176
SZ
303 uint32_t *, uint32_t *);
304
305static int em_get_hw_info(struct adapter *);
306static int em_is_valid_eaddr(const uint8_t *);
307static int em_alloc_pci_res(struct adapter *);
308static void em_free_pci_res(struct adapter *);
2d0e5700 309static int em_reset(struct adapter *);
9c80d176
SZ
310static void em_setup_ifp(struct adapter *);
311static void em_init_tx_unit(struct adapter *);
312static void em_init_rx_unit(struct adapter *);
313static void em_update_stats(struct adapter *);
f647ad3d
JS
314static void em_set_promisc(struct adapter *);
315static void em_disable_promisc(struct adapter *);
316static void em_set_multi(struct adapter *);
87307ba1 317static void em_update_link_status(struct adapter *);
f647ad3d 318static void em_smartspeed(struct adapter *);
2d0e5700 319static void em_set_itr(struct adapter *, uint32_t);
6d5e2922 320static void em_disable_aspm(struct adapter *);
9c80d176
SZ
321
322/* Hardware workarounds */
f647ad3d
JS
323static int em_82547_fifo_workaround(struct adapter *, int);
324static void em_82547_update_fifo_head(struct adapter *, int);
325static int em_82547_tx_fifo_reset(struct adapter *);
1eca7b82
SZ
326static void em_82547_move_tail(void *);
327static void em_82547_move_tail_serialized(struct adapter *);
9c80d176
SZ
328static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
329
f647ad3d 330static void em_print_debug_info(struct adapter *);
9c80d176
SZ
331static void em_print_nvm_info(struct adapter *);
332static void em_print_hw_stats(struct adapter *);
333
f647ad3d
JS
334static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
335static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
d0870c72 336static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
9f60d74b 337static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
9c80d176 338static void em_add_sysctl(struct adapter *adapter);
984263bc 339
9c80d176
SZ
340/* Management and WOL Support */
341static void em_get_mgmt(struct adapter *);
342static void em_rel_mgmt(struct adapter *);
343static void em_get_hw_control(struct adapter *);
344static void em_rel_hw_control(struct adapter *);
345static void em_enable_wol(device_t);
984263bc
MD
346
347static device_method_t em_methods[] = {
348 /* Device interface */
9c80d176
SZ
349 DEVMETHOD(device_probe, em_probe),
350 DEVMETHOD(device_attach, em_attach),
351 DEVMETHOD(device_detach, em_detach),
352 DEVMETHOD(device_shutdown, em_shutdown),
353 DEVMETHOD(device_suspend, em_suspend),
354 DEVMETHOD(device_resume, em_resume),
355 { 0, 0 }
984263bc
MD
356};
357
358static driver_t em_driver = {
9c80d176
SZ
359 "em",
360 em_methods,
361 sizeof(struct adapter),
984263bc
MD
362};
363
364static devclass_t em_devclass;
32832096
MD
365
366DECLARE_DUMMY_MODULE(if_em);
9c80d176 367MODULE_DEPEND(em, ig_hal, 1, 1, 1);
aa2b9d05 368DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
984263bc 369
91e8debf
SZ
370/*
371 * Tunables
372 */
9c80d176
SZ
373static int em_int_throttle_ceil = EM_DEFAULT_ITR;
374static int em_rxd = EM_DEFAULT_RXD;
375static int em_txd = EM_DEFAULT_TXD;
053f3ae6 376static int em_smart_pwr_down = 0;
0d366ee7 377
9c80d176
SZ
378/* Controls whether promiscuous also shows bad packets */
379static int em_debug_sbp = FALSE;
0d366ee7 380
053f3ae6
SZ
381static int em_82573_workaround = 1;
382static int em_msi_enable = 1;
05580856 383
d0870c72 384TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
1eca7b82
SZ
385TUNABLE_INT("hw.em.rxd", &em_rxd);
386TUNABLE_INT("hw.em.txd", &em_txd);
387TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
9c80d176 388TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
05580856 389TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
053f3ae6 390TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
9c80d176
SZ
391
392/* Global used in WOL setup with multiport cards */
393static int em_global_quad_port_a = 0;
394
395/* Set this to one to display debug statistics */
396static int em_display_debug_stats = 0;
0d366ee7 397
07855a48
MD
398#if !defined(KTR_IF_EM)
399#define KTR_IF_EM KTR_ALL
400#endif
401KTR_INFO_MASTER(if_em);
5bf48697
AE
402KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
403KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
404KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
405KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
406KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
07855a48
MD
407#define logif(name) KTR_LOG(if_em_ ## name)
408
984263bc
MD
409static int
410em_probe(device_t dev)
411{
9c80d176
SZ
412 const struct em_vendor_info *ent;
413 uint16_t vid, did;
984263bc 414
9c80d176
SZ
415 vid = pci_get_vendor(dev);
416 did = pci_get_device(dev);
984263bc 417
9c80d176
SZ
418 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
419 if (vid == ent->vendor_id && did == ent->device_id) {
420 device_set_desc(dev, ent->desc);
dbcd0c9b 421 device_set_async_attach(dev, TRUE);
96ced48a 422 return (ent->ret);
984263bc 423 }
984263bc 424 }
87307ba1 425 return (ENXIO);
984263bc
MD
426}
427
984263bc
MD
428static int
429em_attach(device_t dev)
430{
9c80d176
SZ
431 struct adapter *adapter = device_get_softc(dev);
432 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d
JS
433 int tsize, rsize;
434 int error = 0;
2d0e5700 435 uint16_t eeprom_data, device_id, apme_mask;
87ab432b 436 driver_intr_t *intr_func;
984263bc 437
9c80d176 438 adapter->dev = adapter->osdep.dev = dev;
f647ad3d 439
bf0ecf68
MD
440 callout_init_mp(&adapter->timer);
441 callout_init_mp(&adapter->tx_fifo_timer);
af82d4bb 442
9c80d176
SZ
443 /* Determine hardware and mac info */
444 error = em_get_hw_info(adapter);
445 if (error) {
446 device_printf(dev, "Identify hardware failed\n");
447 goto fail;
f647ad3d
JS
448 }
449
9c80d176
SZ
450 /* Setup PCI resources */
451 error = em_alloc_pci_res(adapter);
452 if (error) {
453 device_printf(dev, "Allocation of PCI resources failed\n");
454 goto fail;
455 }
984263bc 456
9c80d176
SZ
457 /*
458 * For ICH8 and family we need to map the flash memory,
459 * and this must happen after the MAC is identified.
460 */
461 if (adapter->hw.mac.type == e1000_ich8lan ||
2d0e5700 462 adapter->hw.mac.type == e1000_ich9lan ||
9c80d176 463 adapter->hw.mac.type == e1000_ich10lan ||
2d0e5700
SZ
464 adapter->hw.mac.type == e1000_pchlan ||
465 adapter->hw.mac.type == e1000_pch2lan) {
9c80d176
SZ
466 adapter->flash_rid = EM_BAR_FLASH;
467
468 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
469 &adapter->flash_rid, RF_ACTIVE);
470 if (adapter->flash == NULL) {
471 device_printf(dev, "Mapping of Flash failed\n");
472 error = ENXIO;
473 goto fail;
474 }
475 adapter->osdep.flash_bus_space_tag =
476 rman_get_bustag(adapter->flash);
477 adapter->osdep.flash_bus_space_handle =
478 rman_get_bushandle(adapter->flash);
984263bc 479
9c80d176
SZ
480 /*
481 * This is used in the shared code
482 * XXX this goof is actually not used.
483 */
484 adapter->hw.flash_address = (uint8_t *)adapter->flash;
485 }
0d366ee7 486
9c80d176
SZ
487 /* Do Shared Code initialization */
488 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
489 device_printf(dev, "Setup of Shared code failed\n");
490 error = ENXIO;
491 goto fail;
f647ad3d 492 }
7ea52455 493
9c80d176
SZ
494 e1000_get_bus_info(&adapter->hw);
495
1eca7b82 496 /*
9c80d176 497 * Validate number of transmit and receive descriptors. It
1eca7b82 498 * must not exceed hardware maximum, and must be multiple
9c80d176 499 * of E1000_DBA_ALIGN.
1eca7b82 500 */
9c80d176
SZ
501 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
502 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
503 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
504 em_txd < EM_MIN_TXD) {
1eca7b82 505 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
9c80d176 506 EM_DEFAULT_TXD, em_txd);
1eca7b82
SZ
507 adapter->num_tx_desc = EM_DEFAULT_TXD;
508 } else {
509 adapter->num_tx_desc = em_txd;
510 }
9c80d176
SZ
511 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
512 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
513 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
514 em_rxd < EM_MIN_RXD) {
1eca7b82 515 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
9c80d176 516 EM_DEFAULT_RXD, em_rxd);
1eca7b82
SZ
517 adapter->num_rx_desc = EM_DEFAULT_RXD;
518 } else {
519 adapter->num_rx_desc = em_rxd;
520 }
521
9c80d176
SZ
522 adapter->hw.mac.autoneg = DO_AUTO_NEG;
523 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
524 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
525 adapter->rx_buffer_len = MCLBYTES;
e94c2bf4 526
9c80d176
SZ
527 /*
528 * Interrupt throttle rate
529 */
530 if (em_int_throttle_ceil == 0) {
531 adapter->int_throttle_ceil = 0;
532 } else {
533 int throttle = em_int_throttle_ceil;
f647ad3d 534
9c80d176
SZ
535 if (throttle < 0)
536 throttle = EM_DEFAULT_ITR;
0d366ee7 537
9c80d176
SZ
538 /* Recalculate the tunable value to get the exact frequency. */
539 throttle = 1000000000 / 256 / throttle;
664c7645
SZ
540
541 /* Upper 16bits of ITR is reserved and should be zero */
542 if (throttle & 0xffff0000)
543 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
544
9c80d176
SZ
545 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
546 }
984263bc 547
9c80d176
SZ
548 e1000_init_script_state_82541(&adapter->hw, TRUE);
549 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
550
551 /* Copper options */
552 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
553 adapter->hw.phy.mdix = AUTO_ALL_MODES;
554 adapter->hw.phy.disable_polarity_correction = FALSE;
555 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
556 }
557
558 /* Set the frame limits assuming standard ethernet sized frames. */
559 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
560 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
984263bc 561
9c80d176
SZ
562 /* This controls when hardware reports transmit completion status. */
563 adapter->hw.mac.report_tx_early = 1;
984263bc 564
87307ba1 565 /*
9c80d176 566 * Create top level busdma tag
984263bc 567 */
9c80d176
SZ
568 error = bus_dma_tag_create(NULL, 1, 0,
569 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
570 NULL, NULL,
571 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
572 0, &adapter->parent_dtag);
573 if (error) {
574 device_printf(dev, "could not create top level DMA tag\n");
af82d4bb 575 goto fail;
9c80d176 576 }
af82d4bb 577
9c80d176
SZ
578 /*
579 * Allocate Transmit Descriptor ring
580 */
581 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
1eca7b82 582 EM_DBA_ALIGN);
87307ba1
SZ
583 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
584 if (error) {
9c80d176 585 device_printf(dev, "Unable to allocate tx_desc memory\n");
af82d4bb 586 goto fail;
984263bc 587 }
9c80d176 588 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
984263bc 589
9c80d176
SZ
590 /*
591 * Allocate Receive Descriptor ring
592 */
593 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
1eca7b82 594 EM_DBA_ALIGN);
87307ba1
SZ
595 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
596 if (error) {
9ccd8c1f 597 device_printf(dev, "Unable to allocate rx_desc memory\n");
af82d4bb 598 goto fail;
984263bc 599 }
9c80d176
SZ
600 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
601
2d0e5700
SZ
602 /* Allocate multicast array memory. */
603 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
604 M_DEVBUF, M_WAITOK);
605
606 /* Indicate SOL/IDER usage */
607 if (e1000_check_reset_block(&adapter->hw)) {
608 device_printf(dev,
609 "PHY reset is blocked due to SOL/IDER session.\n");
610 }
611
612 /*
613 * Start from a known state, this is important in reading the
614 * nvm and mac from that.
615 */
616 e1000_reset_hw(&adapter->hw);
617
9c80d176
SZ
618 /* Make sure we have a good EEPROM before we read from it */
619 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
620 /*
621 * Some PCI-E parts fail the first check due to
622 * the link being in sleep state, call it again,
623 * if it fails a second time its a real issue.
624 */
625 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
626 device_printf(dev,
627 "The EEPROM Checksum Is Not Valid\n");
628 error = EIO;
629 goto fail;
630 }
631 }
984263bc 632
984263bc 633 /* Copy the permanent MAC address out of the EEPROM */
9c80d176
SZ
634 if (e1000_read_mac_addr(&adapter->hw) < 0) {
635 device_printf(dev, "EEPROM read error while reading MAC"
636 " address\n");
984263bc 637 error = EIO;
af82d4bb 638 goto fail;
984263bc 639 }
9c80d176 640 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
87307ba1 641 device_printf(dev, "Invalid MAC address\n");
984263bc 642 error = EIO;
af82d4bb 643 goto fail;
984263bc
MD
644 }
645
9c80d176
SZ
646 /* Allocate transmit descriptors and buffers */
647 error = em_create_tx_ring(adapter);
648 if (error) {
649 device_printf(dev, "Could not setup transmit structures\n");
650 goto fail;
651 }
652
653 /* Allocate receive descriptors and buffers */
654 error = em_create_rx_ring(adapter);
655 if (error) {
656 device_printf(dev, "Could not setup receive structures\n");
657 goto fail;
658 }
659
660 /* Manually turn off all interrupts */
661 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
662
9c80d176
SZ
663 /* Determine if we have to control management hardware */
664 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
665
666 /*
667 * Setup Wake-on-Lan
668 */
2d0e5700
SZ
669 apme_mask = EM_EEPROM_APME;
670 eeprom_data = 0;
9c80d176
SZ
671 switch (adapter->hw.mac.type) {
672 case e1000_82542:
673 case e1000_82543:
674 break;
675
2d0e5700
SZ
676 case e1000_82573:
677 case e1000_82583:
678 adapter->has_amt = 1;
679 /* FALL THROUGH */
680
9c80d176
SZ
681 case e1000_82546:
682 case e1000_82546_rev_3:
683 case e1000_82571:
2d0e5700 684 case e1000_82572:
9c80d176
SZ
685 case e1000_80003es2lan:
686 if (adapter->hw.bus.func == 1) {
687 e1000_read_nvm(&adapter->hw,
688 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
689 } else {
690 e1000_read_nvm(&adapter->hw,
691 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
692 }
2d0e5700
SZ
693 break;
694
695 case e1000_ich8lan:
696 case e1000_ich9lan:
697 case e1000_ich10lan:
698 case e1000_pchlan:
699 case e1000_pch2lan:
700 apme_mask = E1000_WUC_APME;
701 adapter->has_amt = TRUE;
702 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
9c80d176
SZ
703 break;
704
705 default:
2d0e5700
SZ
706 e1000_read_nvm(&adapter->hw,
707 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9c80d176
SZ
708 break;
709 }
2d0e5700
SZ
710 if (eeprom_data & apme_mask)
711 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
712
9c80d176
SZ
713 /*
714 * We have the eeprom settings, now apply the special cases
715 * where the eeprom may be wrong or the board won't support
716 * wake on lan on a particular port
717 */
718 device_id = pci_get_device(dev);
719 switch (device_id) {
720 case E1000_DEV_ID_82546GB_PCIE:
721 adapter->wol = 0;
722 break;
723
724 case E1000_DEV_ID_82546EB_FIBER:
725 case E1000_DEV_ID_82546GB_FIBER:
726 case E1000_DEV_ID_82571EB_FIBER:
727 /*
728 * Wake events only supported on port A for dual fiber
729 * regardless of eeprom setting
730 */
731 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
732 E1000_STATUS_FUNC_1)
733 adapter->wol = 0;
734 break;
735
736 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
737 case E1000_DEV_ID_82571EB_QUAD_COPPER:
738 case E1000_DEV_ID_82571EB_QUAD_FIBER:
739 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
740 /* if quad port adapter, disable WoL on all but port A */
741 if (em_global_quad_port_a != 0)
742 adapter->wol = 0;
743 /* Reset for multiple quad port adapters */
744 if (++em_global_quad_port_a == 4)
745 em_global_quad_port_a = 0;
746 break;
747 }
748
749 /* XXX disable wol */
750 adapter->wol = 0;
751
2d0e5700
SZ
752 /* Setup OS specific network interface */
753 em_setup_ifp(adapter);
754
755 /* Add sysctl tree, must after em_setup_ifp() */
756 em_add_sysctl(adapter);
757
758 /* Reset the hardware */
759 error = em_reset(adapter);
760 if (error) {
761 device_printf(dev, "Unable to reset the hardware\n");
762 goto fail;
763 }
764
765 /* Initialize statistics */
766 em_update_stats(adapter);
767
768 adapter->hw.mac.get_link_status = 1;
769 em_update_link_status(adapter);
770
9c80d176
SZ
771 /* Do we need workaround for 82544 PCI-X adapter? */
772 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
773 adapter->hw.mac.type == e1000_82544)
f647ad3d 774 adapter->pcix_82544 = TRUE;
87307ba1 775 else
f647ad3d 776 adapter->pcix_82544 = FALSE;
af82d4bb 777
9c80d176
SZ
778 if (adapter->pcix_82544) {
779 /*
780 * 82544 on PCI-X may split one TX segment
781 * into two TX descs, so we double its number
782 * of spare TX desc here.
783 */
784 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
785 } else {
786 adapter->spare_tx_desc = EM_TX_SPARE;
787 }
788
9f60d74b
SZ
789 /*
790 * Keep following relationship between spare_tx_desc, oact_tx_desc
791 * and tx_int_nsegs:
792 * (spare_tx_desc + EM_TX_RESERVED) <=
793 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
794 */
795 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
796 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
797 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
798 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
799 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
800
801 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
802 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
803 adapter->tx_int_nsegs = adapter->oact_tx_desc;
804
2d0e5700
SZ
805 /* Non-AMT based hardware can now take control from firmware */
806 if (adapter->has_manage && !adapter->has_amt &&
807 adapter->hw.mac.type >= e1000_82571)
808 em_get_hw_control(adapter);
809
87ab432b
SZ
810 /*
811 * Missing Interrupt Following ICR read:
812 *
a835687d
SZ
813 * 82571/82572 specification update errata #76
814 * 82573 specification update errata #31
815 * 82574 specification update errata #12
816 * 82583 specification update errata #4
87ab432b
SZ
817 */
818 intr_func = em_intr;
819 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
820 (adapter->hw.mac.type == e1000_82571 ||
821 adapter->hw.mac.type == e1000_82572 ||
822 adapter->hw.mac.type == e1000_82573 ||
823 adapter->hw.mac.type == e1000_82574 ||
824 adapter->hw.mac.type == e1000_82583))
825 intr_func = em_intr_mask;
826
9c80d176 827 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
87ab432b 828 intr_func, adapter, &adapter->intr_tag,
9c80d176 829 ifp->if_serializer);
af82d4bb 830 if (error) {
9c80d176
SZ
831 device_printf(dev, "Failed to register interrupt handler");
832 ether_ifdetach(&adapter->arpcom.ac_if);
af82d4bb
JS
833 goto fail;
834 }
835
a749d1d2 836 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res);
9db4b353 837 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
9c80d176 838 return (0);
af82d4bb
JS
839fail:
840 em_detach(dev);
9c80d176 841 return (error);
984263bc
MD
842}
843
984263bc
MD
844static int
845em_detach(device_t dev)
846{
78195a76 847 struct adapter *adapter = device_get_softc(dev);
984263bc 848
af82d4bb 849 if (device_is_attached(dev)) {
9c80d176 850 struct ifnet *ifp = &adapter->arpcom.ac_if;
cdf89432
SZ
851
852 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 853
af82d4bb 854 em_stop(adapter);
9c80d176
SZ
855
856 e1000_phy_hw_reset(&adapter->hw);
857
858 em_rel_mgmt(adapter);
2d0e5700 859 em_rel_hw_control(adapter);
9c80d176
SZ
860
861 if (adapter->wol) {
862 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
863 E1000_WUC_PME_EN);
864 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
865 em_enable_wol(dev);
866 }
867
868 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
869
cdf89432
SZ
870 lwkt_serialize_exit(ifp->if_serializer);
871
872 ether_ifdetach(ifp);
a19a8754 873 } else if (adapter->memory != NULL) {
2d0e5700 874 em_rel_hw_control(adapter);
7ea52455 875 }
cdf89432
SZ
876 bus_generic_detach(dev);
877
9c80d176
SZ
878 em_free_pci_res(adapter);
879
880 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
881 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
af82d4bb 882
984263bc 883 /* Free Transmit Descriptor ring */
9c80d176 884 if (adapter->tx_desc_base)
9ccd8c1f 885 em_dma_free(adapter, &adapter->txdma);
984263bc 886
984263bc 887 /* Free Receive Descriptor ring */
9c80d176 888 if (adapter->rx_desc_base)
9ccd8c1f 889 em_dma_free(adapter, &adapter->rxdma);
9c80d176
SZ
890
891 /* Free top level busdma tag */
892 if (adapter->parent_dtag != NULL)
893 bus_dma_tag_destroy(adapter->parent_dtag);
984263bc 894
1eca7b82 895 /* Free sysctl tree */
9c80d176 896 if (adapter->sysctl_tree != NULL)
1eca7b82 897 sysctl_ctx_free(&adapter->sysctl_ctx);
984263bc 898
a19a8754
SZ
899 if (adapter->mta != NULL)
900 kfree(adapter->mta, M_DEVBUF);
901
87307ba1 902 return (0);
984263bc
MD
903}
904
984263bc
MD
905static int
906em_shutdown(device_t dev)
907{
9c80d176 908 return em_suspend(dev);
87307ba1
SZ
909}
910
87307ba1
SZ
911static int
912em_suspend(device_t dev)
913{
914 struct adapter *adapter = device_get_softc(dev);
9c80d176 915 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
916
917 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 918
87307ba1 919 em_stop(adapter);
9c80d176
SZ
920
921 em_rel_mgmt(adapter);
2d0e5700 922 em_rel_hw_control(adapter);
9c80d176 923
2d0e5700 924 if (adapter->wol) {
9c80d176
SZ
925 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
926 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
927 em_enable_wol(dev);
2d0e5700 928 }
9c80d176 929
87307ba1 930 lwkt_serialize_exit(ifp->if_serializer);
9c80d176
SZ
931
932 return bus_generic_suspend(dev);
87307ba1
SZ
933}
934
935static int
936em_resume(device_t dev)
937{
938 struct adapter *adapter = device_get_softc(dev);
9c80d176 939 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
940
941 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 942
87307ba1 943 em_init(adapter);
9c80d176 944 em_get_mgmt(adapter);
9db4b353 945 if_devstart(ifp);
9c80d176 946
87307ba1
SZ
947 lwkt_serialize_exit(ifp->if_serializer);
948
949 return bus_generic_resume(dev);
984263bc
MD
950}
951
984263bc
MD
952static void
953em_start(struct ifnet *ifp)
954{
f647ad3d 955 struct adapter *adapter = ifp->if_softc;
9c80d176 956 struct mbuf *m_head;
984263bc 957
1eca7b82 958 ASSERT_SERIALIZED(ifp->if_serializer);
78195a76 959
87307ba1
SZ
960 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
961 return;
9c80d176 962
9db4b353
SZ
963 if (!adapter->link_active) {
964 ifq_purge(&ifp->if_snd);
f647ad3d 965 return;
9db4b353 966 }
9c80d176 967
e26dc3e9 968 while (!ifq_is_empty(&ifp->if_snd)) {
9f60d74b
SZ
969 /* Now do we at least have a minimal? */
970 if (EM_IS_OACTIVE(adapter)) {
971 em_tx_collect(adapter);
9c80d176 972 if (EM_IS_OACTIVE(adapter)) {
9c80d176 973 ifp->if_flags |= IFF_OACTIVE;
9f60d74b 974 adapter->no_tx_desc_avail1++;
9c80d176
SZ
975 break;
976 }
977 }
978
979 logif(pkt_txqueue);
9db4b353 980 m_head = ifq_dequeue(&ifp->if_snd, NULL);
f647ad3d
JS
981 if (m_head == NULL)
982 break;
984263bc 983
9c80d176 984 if (em_encap(adapter, &m_head)) {
002b3a05 985 ifp->if_oerrors++;
9f60d74b
SZ
986 em_tx_collect(adapter);
987 continue;
f647ad3d 988 }
984263bc
MD
989
990 /* Send a copy of the frame to the BPF listener */
b637f170 991 ETHER_BPF_MTAP(ifp, m_head);
87307ba1
SZ
992
993 /* Set timeout in case hardware has problems transmitting. */
994 ifp->if_timer = EM_TX_TIMEOUT;
f647ad3d 995 }
984263bc
MD
996}
997
984263bc 998static int
bd4539cc 999em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1000{
f647ad3d 1001 struct adapter *adapter = ifp->if_softc;
9c80d176 1002 struct ifreq *ifr = (struct ifreq *)data;
1eca7b82 1003 uint16_t eeprom_data = 0;
9c80d176
SZ
1004 int max_frame_size, mask, reinit;
1005 int error = 0;
0d366ee7 1006
9c80d176 1007 ASSERT_SERIALIZED(ifp->if_serializer);
0d366ee7 1008
984263bc 1009 switch (command) {
984263bc 1010 case SIOCSIFMTU:
9c80d176
SZ
1011 switch (adapter->hw.mac.type) {
1012 case e1000_82573:
1eca7b82
SZ
1013 /*
1014 * 82573 only supports jumbo frames
1015 * if ASPM is disabled.
1016 */
9c80d176
SZ
1017 e1000_read_nvm(&adapter->hw,
1018 NVM_INIT_3GIO_3, 1, &eeprom_data);
1019 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1eca7b82
SZ
1020 max_frame_size = ETHER_MAX_LEN;
1021 break;
1022 }
9c80d176
SZ
1023 /* FALL THROUGH */
1024
1025 /* Limit Jumbo Frame size */
1026 case e1000_82571:
1027 case e1000_82572:
1028 case e1000_ich9lan:
1029 case e1000_ich10lan:
2d0e5700 1030 case e1000_pch2lan:
9c80d176 1031 case e1000_82574:
6d5e2922 1032 case e1000_82583:
9c80d176 1033 case e1000_80003es2lan:
1eca7b82 1034 max_frame_size = 9234;
7ea52455 1035 break;
9c80d176 1036
2d0e5700
SZ
1037 case e1000_pchlan:
1038 max_frame_size = 4096;
1039 break;
1040
9c80d176
SZ
1041 /* Adapters that do not support jumbo frames */
1042 case e1000_82542:
1043 case e1000_ich8lan:
7ea52455
SZ
1044 max_frame_size = ETHER_MAX_LEN;
1045 break;
9c80d176 1046
7ea52455
SZ
1047 default:
1048 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1049 break;
1050 }
9c80d176
SZ
1051 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1052 ETHER_CRC_LEN) {
984263bc 1053 error = EINVAL;
9c80d176 1054 break;
984263bc 1055 }
9c80d176
SZ
1056
1057 ifp->if_mtu = ifr->ifr_mtu;
1058 adapter->max_frame_size =
1059 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1060
1061 if (ifp->if_flags & IFF_RUNNING)
1062 em_init(adapter);
984263bc 1063 break;
9c80d176 1064
984263bc 1065 case SIOCSIFFLAGS:
984263bc 1066 if (ifp->if_flags & IFF_UP) {
9c80d176
SZ
1067 if ((ifp->if_flags & IFF_RUNNING)) {
1068 if ((ifp->if_flags ^ adapter->if_flags) &
1069 (IFF_PROMISC | IFF_ALLMULTI)) {
1070 em_disable_promisc(adapter);
1071 em_set_promisc(adapter);
1072 }
1073 } else {
78195a76 1074 em_init(adapter);
87307ba1 1075 }
9c80d176
SZ
1076 } else if (ifp->if_flags & IFF_RUNNING) {
1077 em_stop(adapter);
984263bc 1078 }
87307ba1 1079 adapter->if_flags = ifp->if_flags;
984263bc 1080 break;
9c80d176 1081
984263bc
MD
1082 case SIOCADDMULTI:
1083 case SIOCDELMULTI:
984263bc
MD
1084 if (ifp->if_flags & IFF_RUNNING) {
1085 em_disable_intr(adapter);
1086 em_set_multi(adapter);
9c80d176
SZ
1087 if (adapter->hw.mac.type == e1000_82542 &&
1088 adapter->hw.revision_id == E1000_REVISION_2)
1089 em_init_rx_unit(adapter);
1eca7b82 1090#ifdef DEVICE_POLLING
9c80d176 1091 if (!(ifp->if_flags & IFF_POLLING))
1eca7b82 1092#endif
9c80d176 1093 em_enable_intr(adapter);
984263bc
MD
1094 }
1095 break;
9c80d176 1096
984263bc 1097 case SIOCSIFMEDIA:
87307ba1 1098 /* Check SOL/IDER usage */
9c80d176
SZ
1099 if (e1000_check_reset_block(&adapter->hw)) {
1100 device_printf(adapter->dev, "Media change is"
1101 " blocked due to SOL/IDER session.\n");
87307ba1
SZ
1102 break;
1103 }
9c80d176
SZ
1104 /* FALL THROUGH */
1105
984263bc 1106 case SIOCGIFMEDIA:
984263bc
MD
1107 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1108 break;
9c80d176 1109
984263bc 1110 case SIOCSIFCAP:
9c80d176 1111 reinit = 0;
984263bc
MD
1112 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1113 if (mask & IFCAP_HWCSUM) {
9c80d176 1114 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
1eca7b82 1115 reinit = 1;
984263bc 1116 }
1eca7b82
SZ
1117 if (mask & IFCAP_VLAN_HWTAGGING) {
1118 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1119 reinit = 1;
1120 }
9c80d176 1121 if (reinit && (ifp->if_flags & IFF_RUNNING))
1eca7b82 1122 em_init(adapter);
984263bc 1123 break;
9c80d176 1124
984263bc 1125 default:
1eca7b82
SZ
1126 error = ether_ioctl(ifp, command, data);
1127 break;
984263bc 1128 }
87307ba1 1129 return (error);
984263bc
MD
1130}
1131
984263bc
MD
1132static void
1133em_watchdog(struct ifnet *ifp)
1134{
1eca7b82 1135 struct adapter *adapter = ifp->if_softc;
984263bc 1136
9c80d176
SZ
1137 ASSERT_SERIALIZED(ifp->if_serializer);
1138
1139 /*
1140 * The timer is set to 5 every time start queues a packet.
1141 * Then txeof keeps resetting it as long as it cleans at
1142 * least one descriptor.
1143 * Finally, anytime all descriptors are clean the timer is
1144 * set to 0.
1145 */
1146
9f60d74b
SZ
1147 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1148 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1149 /*
1150 * If we reach here, all TX jobs are completed and
1151 * the TX engine should have been idled for some time.
1152 * We don't need to call if_devstart() here.
1153 */
1154 ifp->if_flags &= ~IFF_OACTIVE;
1155 ifp->if_timer = 0;
1156 return;
1157 }
1158
1eca7b82
SZ
1159 /*
1160 * If we are in this routine because of pause frames, then
984263bc
MD
1161 * don't reset the hardware.
1162 */
9c80d176
SZ
1163 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1164 E1000_STATUS_TXOFF) {
984263bc
MD
1165 ifp->if_timer = EM_TX_TIMEOUT;
1166 return;
1167 }
1168
9c80d176 1169 if (e1000_check_for_link(&adapter->hw) == 0)
f647ad3d 1170 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc 1171
9c80d176
SZ
1172 ifp->if_oerrors++;
1173 adapter->watchdog_events++;
1174
984263bc
MD
1175 em_init(adapter);
1176
9c80d176
SZ
1177 if (!ifq_is_empty(&ifp->if_snd))
1178 if_devstart(ifp);
984263bc
MD
1179}
1180
984263bc 1181static void
9c80d176 1182em_init(void *xsc)
984263bc 1183{
9c80d176
SZ
1184 struct adapter *adapter = xsc;
1185 struct ifnet *ifp = &adapter->arpcom.ac_if;
1186 device_t dev = adapter->dev;
eac00e59 1187 uint32_t pba;
984263bc 1188
87307ba1
SZ
1189 ASSERT_SERIALIZED(ifp->if_serializer);
1190
984263bc
MD
1191 em_stop(adapter);
1192
eac00e59
SZ
1193 /*
1194 * Packet Buffer Allocation (PBA)
1195 * Writing PBA sets the receive portion of the buffer
1196 * the remainder is used for the transmit buffer.
1eca7b82
SZ
1197 *
1198 * Devices before the 82547 had a Packet Buffer of 64K.
1199 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1200 * After the 82547 the buffer was reduced to 40K.
1201 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1202 * Note: default does not leave enough room for Jumbo Frame >10k.
eac00e59 1203 */
9c80d176
SZ
1204 switch (adapter->hw.mac.type) {
1205 case e1000_82547:
1206 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1207 if (adapter->max_frame_size > 8192)
eac00e59 1208 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
7ea52455
SZ
1209 else
1210 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
eac00e59
SZ
1211 adapter->tx_fifo_head = 0;
1212 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1213 adapter->tx_fifo_size =
9c80d176 1214 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
7ea52455 1215 break;
9c80d176 1216
87307ba1 1217 /* Total Packet Buffer on these is 48K */
9c80d176
SZ
1218 case e1000_82571:
1219 case e1000_82572:
1220 case e1000_80003es2lan:
7ea52455
SZ
1221 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1222 break;
9c80d176
SZ
1223
1224 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
7ea52455
SZ
1225 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1226 break;
9c80d176
SZ
1227
1228 case e1000_82574:
2d0e5700 1229 case e1000_82583:
9c80d176 1230 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1eca7b82 1231 break;
9c80d176 1232
2d0e5700
SZ
1233 case e1000_ich8lan:
1234 pba = E1000_PBA_8K;
1235 break;
1236
9c80d176
SZ
1237 case e1000_ich9lan:
1238 case e1000_ich10lan:
1239#define E1000_PBA_10K 0x000A
b0ff1d56
MS
1240 pba = E1000_PBA_10K;
1241 break;
9c80d176 1242
2d0e5700
SZ
1243 case e1000_pchlan:
1244 case e1000_pch2lan:
1245 pba = E1000_PBA_26K;
9c80d176
SZ
1246 break;
1247
7ea52455
SZ
1248 default:
1249 /* Devices before 82547 had a Packet Buffer of 64K. */
9c80d176 1250 if (adapter->max_frame_size > 8192)
7ea52455
SZ
1251 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1252 else
1253 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
eac00e59 1254 }
9c80d176 1255 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
a4a205fa 1256
0d366ee7 1257 /* Get the latest mac address, User can use a LAA */
9c80d176
SZ
1258 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1259
1260 /* Put the address into the Receive Address Array */
1261 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1262
1263 /*
1264 * With the 82571 adapter, RAR[0] may be overwritten
1265 * when the other port is reset, we make a duplicate
1266 * in RAR[14] for that eventuality, this assures
1267 * the interface continues to function.
1268 */
1269 if (adapter->hw.mac.type == e1000_82571) {
1270 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1271 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1272 E1000_RAR_ENTRIES - 1);
1273 }
0d366ee7 1274
2d0e5700
SZ
1275 /* Reset the hardware */
1276 if (em_reset(adapter)) {
1277 device_printf(dev, "Unable to reset the hardware\n");
9c80d176 1278 /* XXX em_stop()? */
984263bc
MD
1279 return;
1280 }
87307ba1 1281 em_update_link_status(adapter);
984263bc 1282
9c80d176
SZ
1283 /* Setup VLAN support, basic and offload if available */
1284 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
984263bc 1285
9c80d176
SZ
1286 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1287 uint32_t ctrl;
1288
1289 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1290 ctrl |= E1000_CTRL_VME;
1291 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
87307ba1
SZ
1292 }
1293
9c80d176
SZ
1294 /* Set hardware offload abilities */
1295 if (ifp->if_capenable & IFCAP_TXCSUM)
1296 ifp->if_hwassist = EM_CSUM_FEATURES;
1297 else
1298 ifp->if_hwassist = 0;
1299
1300 /* Configure for OS presence */
1301 em_get_mgmt(adapter);
1302
984263bc 1303 /* Prepare transmit descriptors and buffers */
9c80d176
SZ
1304 em_init_tx_ring(adapter);
1305 em_init_tx_unit(adapter);
984263bc
MD
1306
1307 /* Setup Multicast table */
1308 em_set_multi(adapter);
1309
1310 /* Prepare receive descriptors and buffers */
9c80d176
SZ
1311 if (em_init_rx_ring(adapter)) {
1312 device_printf(dev, "Could not setup receive structures\n");
984263bc 1313 em_stop(adapter);
984263bc
MD
1314 return;
1315 }
9c80d176 1316 em_init_rx_unit(adapter);
7ea52455 1317
87307ba1 1318 /* Don't lose promiscuous settings */
0d366ee7 1319 em_set_promisc(adapter);
984263bc 1320
984263bc
MD
1321 ifp->if_flags |= IFF_RUNNING;
1322 ifp->if_flags &= ~IFF_OACTIVE;
1323
9c80d176
SZ
1324 callout_reset(&adapter->timer, hz, em_timer, adapter);
1325 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1326
1327 /* MSI/X configuration for 82574 */
1328 if (adapter->hw.mac.type == e1000_82574) {
1329 int tmp;
1330
1331 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1332 tmp |= E1000_CTRL_EXT_PBA_CLR;
1333 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1334 /*
2d0e5700 1335 * XXX MSIX
9c80d176
SZ
1336 * Set the IVAR - interrupt vector routing.
1337 * Each nibble represents a vector, high bit
1338 * is enable, other 3 bits are the MSIX table
1339 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1340 * Link (other) to 2, hence the magic number.
1341 */
1342 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1343 }
1eca7b82
SZ
1344
1345#ifdef DEVICE_POLLING
9c80d176
SZ
1346 /*
1347 * Only enable interrupts if we are not polling, make sure
1348 * they are off otherwise.
1349 */
1eca7b82
SZ
1350 if (ifp->if_flags & IFF_POLLING)
1351 em_disable_intr(adapter);
1352 else
9c80d176
SZ
1353#endif /* DEVICE_POLLING */
1354 em_enable_intr(adapter);
0d366ee7 1355
2d0e5700
SZ
1356 /* AMT based hardware can now take control from firmware */
1357 if (adapter->has_manage && adapter->has_amt &&
1358 adapter->hw.mac.type >= e1000_82571)
1359 em_get_hw_control(adapter);
1360
0d366ee7 1361 /* Don't reset the phy next time init gets called */
9c80d176 1362 adapter->hw.phy.reset_disable = TRUE;
984263bc
MD
1363}
1364
984263bc 1365#ifdef DEVICE_POLLING
f647ad3d
JS
1366
1367static void
984263bc
MD
1368em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1369{
f647ad3d
JS
1370 struct adapter *adapter = ifp->if_softc;
1371 uint32_t reg_icr;
984263bc 1372
78195a76
MD
1373 ASSERT_SERIALIZED(ifp->if_serializer);
1374
9c80d176 1375 switch (cmd) {
9c095379
MD
1376 case POLL_REGISTER:
1377 em_disable_intr(adapter);
1378 break;
9c80d176 1379
9c095379 1380 case POLL_DEREGISTER:
f647ad3d 1381 em_enable_intr(adapter);
9c095379 1382 break;
9c80d176 1383
9c095379 1384 case POLL_AND_CHECK_STATUS:
9c80d176 1385 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
f647ad3d 1386 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
9ccd8c1f 1387 callout_stop(&adapter->timer);
9c80d176 1388 adapter->hw.mac.get_link_status = 1;
87307ba1 1389 em_update_link_status(adapter);
9c80d176 1390 callout_reset(&adapter->timer, hz, em_timer, adapter);
f647ad3d 1391 }
9c80d176 1392 /* FALL THROUGH */
9c095379
MD
1393 case POLL_ONLY:
1394 if (ifp->if_flags & IFF_RUNNING) {
87307ba1
SZ
1395 em_rxeof(adapter, count);
1396 em_txeof(adapter);
1eca7b82 1397
9c095379 1398 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1399 if_devstart(ifp);
9c095379
MD
1400 }
1401 break;
f647ad3d 1402 }
984263bc 1403}
9c095379 1404
984263bc
MD
1405#endif /* DEVICE_POLLING */
1406
984263bc 1407static void
9c80d176 1408em_intr(void *xsc)
984263bc 1409{
87ab432b
SZ
1410 em_intr_body(xsc, TRUE);
1411}
1412
1413static void
1414em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1415{
9c80d176 1416 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1417 uint32_t reg_icr;
984263bc 1418
07855a48 1419 logif(intr_beg);
78195a76
MD
1420 ASSERT_SERIALIZED(ifp->if_serializer);
1421
9c80d176
SZ
1422 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1423
87ab432b
SZ
1424 if (chk_asserted &&
1425 ((adapter->hw.mac.type >= e1000_82571 &&
1426 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1427 reg_icr == 0)) {
07855a48 1428 logif(intr_end);
984263bc 1429 return;
07855a48 1430 }
984263bc 1431
87307ba1 1432 /*
9c80d176
SZ
1433 * XXX: some laptops trigger several spurious interrupts
1434 * on em(4) when in the resume cycle. The ICR register
1435 * reports all-ones value in this case. Processing such
1436 * interrupts would lead to a freeze. I don't know why.
87307ba1
SZ
1437 */
1438 if (reg_icr == 0xffffffff) {
1439 logif(intr_end);
1440 return;
984263bc
MD
1441 }
1442
79938e61 1443 if (ifp->if_flags & IFF_RUNNING) {
9f60d74b 1444 if (reg_icr &
6643d744 1445 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
9f60d74b 1446 em_rxeof(adapter, -1);
6643d744 1447 if (reg_icr & E1000_ICR_TXDW) {
9f60d74b
SZ
1448 em_txeof(adapter);
1449 if (!ifq_is_empty(&ifp->if_snd))
1450 if_devstart(ifp);
1451 }
f647ad3d 1452 }
984263bc 1453
87307ba1
SZ
1454 /* Link status change */
1455 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1456 callout_stop(&adapter->timer);
9c80d176 1457 adapter->hw.mac.get_link_status = 1;
87307ba1 1458 em_update_link_status(adapter);
9c80d176
SZ
1459
1460 /* Deal with TX cruft when link lost */
1461 em_tx_purge(adapter);
1462
1463 callout_reset(&adapter->timer, hz, em_timer, adapter);
87307ba1
SZ
1464 }
1465
1466 if (reg_icr & E1000_ICR_RXO)
1467 adapter->rx_overruns++;
1468
07855a48 1469 logif(intr_end);
984263bc
MD
1470}
1471
984263bc 1472static void
87ab432b
SZ
1473em_intr_mask(void *xsc)
1474{
1475 struct adapter *adapter = xsc;
1476
1477 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1478 /*
1479 * NOTE:
1480 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1481 * so don't check it.
1482 */
1483 em_intr_body(adapter, FALSE);
1484 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1485}
1486
1487static void
984263bc
MD
1488em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1489{
87307ba1 1490 struct adapter *adapter = ifp->if_softc;
1eca7b82 1491 u_char fiber_type = IFM_1000_SX;
984263bc 1492
78195a76
MD
1493 ASSERT_SERIALIZED(ifp->if_serializer);
1494
87307ba1 1495 em_update_link_status(adapter);
984263bc
MD
1496
1497 ifmr->ifm_status = IFM_AVALID;
1498 ifmr->ifm_active = IFM_ETHER;
1499
1500 if (!adapter->link_active)
1501 return;
1502
1503 ifmr->ifm_status |= IFM_ACTIVE;
1504
9c80d176
SZ
1505 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1506 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1507 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
1508 fiber_type = IFM_1000_LX;
1509 ifmr->ifm_active |= fiber_type | IFM_FDX;
984263bc
MD
1510 } else {
1511 switch (adapter->link_speed) {
1512 case 10:
1513 ifmr->ifm_active |= IFM_10_T;
1514 break;
1515 case 100:
1516 ifmr->ifm_active |= IFM_100_TX;
1517 break;
9c80d176 1518
984263bc 1519 case 1000:
7f259627 1520 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD
1521 break;
1522 }
1523 if (adapter->link_duplex == FULL_DUPLEX)
1524 ifmr->ifm_active |= IFM_FDX;
1525 else
1526 ifmr->ifm_active |= IFM_HDX;
1527 }
984263bc
MD
1528}
1529
984263bc
MD
1530static int
1531em_media_change(struct ifnet *ifp)
1532{
87307ba1
SZ
1533 struct adapter *adapter = ifp->if_softc;
1534 struct ifmedia *ifm = &adapter->media;
984263bc 1535
78195a76 1536 ASSERT_SERIALIZED(ifp->if_serializer);
9c095379 1537
87307ba1
SZ
1538 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1539 return (EINVAL);
1540
984263bc
MD
1541 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1542 case IFM_AUTO:
9c80d176
SZ
1543 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1544 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
984263bc 1545 break;
9c80d176 1546
1eca7b82 1547 case IFM_1000_LX:
984263bc 1548 case IFM_1000_SX:
7f259627 1549 case IFM_1000_T:
9c80d176
SZ
1550 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1551 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
984263bc 1552 break;
9c80d176 1553
984263bc 1554 case IFM_100_TX:
9c80d176
SZ
1555 adapter->hw.mac.autoneg = FALSE;
1556 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1557 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1558 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
984263bc 1559 else
9c80d176 1560 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
984263bc 1561 break;
9c80d176 1562
984263bc 1563 case IFM_10_T:
9c80d176
SZ
1564 adapter->hw.mac.autoneg = FALSE;
1565 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1566 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1567 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
984263bc 1568 else
9c80d176 1569 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
984263bc 1570 break;
9c80d176 1571
984263bc 1572 default:
f647ad3d 1573 if_printf(ifp, "Unsupported media type\n");
9c80d176 1574 break;
984263bc 1575 }
9c80d176 1576
f647ad3d 1577 /*
9c80d176 1578 * As the speed/duplex settings my have changed we need to
f647ad3d
JS
1579 * reset the PHY.
1580 */
9c80d176 1581 adapter->hw.phy.reset_disable = FALSE;
984263bc 1582
78195a76 1583 em_init(adapter);
984263bc 1584
9c80d176 1585 return (0);
9ccd8c1f
JS
1586}
1587
984263bc 1588static int
9c80d176 1589em_encap(struct adapter *adapter, struct mbuf **m_headp)
9ccd8c1f 1590{
9c80d176 1591 bus_dma_segment_t segs[EM_MAX_SCATTER];
1eca7b82 1592 bus_dmamap_t map;
9c80d176
SZ
1593 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1594 struct e1000_tx_desc *ctxd = NULL;
002b3a05 1595 struct mbuf *m_head = *m_headp;
9f60d74b 1596 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
9c80d176 1597 int maxsegs, nsegs, i, j, first, last = 0, error;
984263bc 1598
3752657e 1599 if (m_head->m_len < EM_TXCSUM_MINHL &&
002b3a05
SZ
1600 (m_head->m_flags & EM_CSUM_FEATURES)) {
1601 /*
1602 * Make sure that ethernet header and ip.ip_hl are in
1603 * contiguous memory, since if TXCSUM is enabled, later
1604 * TX context descriptor's setup need to access ip.ip_hl.
1605 */
1606 error = em_txcsum_pullup(adapter, m_headp);
1607 if (error) {
1608 KKASSERT(*m_headp == NULL);
1609 return error;
1610 }
1611 m_head = *m_headp;
1612 }
1613
9c80d176
SZ
1614 txd_upper = txd_lower = 0;
1615 txd_used = 0;
87307ba1
SZ
1616
1617 /*
9c80d176
SZ
1618 * Capture the first descriptor index, this descriptor
1619 * will have the index of the EOP which is the only one
1620 * that now gets a DONE bit writeback.
87307ba1 1621 */
9c80d176
SZ
1622 first = adapter->next_avail_tx_desc;
1623 tx_buffer = &adapter->tx_buffer_area[first];
1624 tx_buffer_mapped = tx_buffer;
1625 map = tx_buffer->map;
87307ba1 1626
9c80d176
SZ
1627 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1628 KASSERT(maxsegs >= adapter->spare_tx_desc,
ed20d0e3 1629 ("not enough spare TX desc"));
9c80d176
SZ
1630 if (adapter->pcix_82544) {
1631 /* Half it; see the comment in em_attach() */
1632 maxsegs >>= 1;
9ccd8c1f 1633 }
9c80d176
SZ
1634 if (maxsegs > EM_MAX_SCATTER)
1635 maxsegs = EM_MAX_SCATTER;
984263bc 1636
9c80d176
SZ
1637 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1638 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1639 if (error) {
1640 if (error == ENOBUFS)
1641 adapter->mbuf_alloc_failed++;
1642 else
1643 adapter->no_tx_dma_setup++;
984263bc 1644
9c80d176
SZ
1645 m_freem(*m_headp);
1646 *m_headp = NULL;
1647 return error;
7ea52455 1648 }
9c80d176 1649 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
984263bc 1650
9c80d176 1651 m_head = *m_headp;
9f60d74b 1652 adapter->tx_nsegs += nsegs;
9c80d176 1653
002b3a05 1654 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
9c80d176 1655 /* TX csum offloading will consume one TX desc */
9f60d74b
SZ
1656 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1657 &txd_upper, &txd_lower);
9c80d176 1658 }
984263bc 1659 i = adapter->next_avail_tx_desc;
87307ba1
SZ
1660
1661 /* Set up our transmit descriptors */
9c80d176 1662 for (j = 0; j < nsegs; j++) {
9ccd8c1f
JS
1663 /* If adapter is 82544 and on PCIX bus */
1664 if(adapter->pcix_82544) {
87307ba1
SZ
1665 DESC_ARRAY desc_array;
1666 uint32_t array_elements, counter;
1667
9c80d176 1668 /*
f647ad3d
JS
1669 * Check the Address and Length combination and
1670 * split the data accordingly
9ccd8c1f 1671 */
9c80d176
SZ
1672 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1673 segs[j].ds_len, &desc_array);
9ccd8c1f 1674 for (counter = 0; counter < array_elements; counter++) {
9c80d176
SZ
1675 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1676
9ccd8c1f 1677 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176
SZ
1678 ctxd = &adapter->tx_desc_base[i];
1679
1680 ctxd->buffer_addr = htole64(
1681 desc_array.descriptor[counter].address);
1682 ctxd->lower.data = htole32(
2af74b85 1683 E1000_TXD_CMD_IFCS | txd_lower |
9c80d176
SZ
1684 desc_array.descriptor[counter].length);
1685 ctxd->upper.data = htole32(txd_upper);
87307ba1
SZ
1686
1687 last = i;
9ccd8c1f
JS
1688 if (++i == adapter->num_tx_desc)
1689 i = 0;
1690
9ccd8c1f 1691 txd_used++;
9c80d176 1692 }
9ccd8c1f 1693 } else {
0d366ee7 1694 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176 1695 ctxd = &adapter->tx_desc_base[i];
9ccd8c1f 1696
9c80d176 1697 ctxd->buffer_addr = htole64(segs[j].ds_addr);
2af74b85 1698 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
9c80d176
SZ
1699 txd_lower | segs[j].ds_len);
1700 ctxd->upper.data = htole32(txd_upper);
984263bc 1701
87307ba1 1702 last = i;
0d366ee7
MD
1703 if (++i == adapter->num_tx_desc)
1704 i = 0;
0d366ee7 1705 }
984263bc 1706 }
9ccd8c1f 1707
984263bc 1708 adapter->next_avail_tx_desc = i;
9c80d176
SZ
1709 if (adapter->pcix_82544) {
1710 KKASSERT(adapter->num_tx_desc_avail > txd_used);
9ccd8c1f 1711 adapter->num_tx_desc_avail -= txd_used;
9c80d176
SZ
1712 } else {
1713 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1714 adapter->num_tx_desc_avail -= nsegs;
1715 }
984263bc 1716
9c80d176 1717 /* Handle VLAN tag */
83790f85 1718 if (m_head->m_flags & M_VLANTAG) {
9c80d176
SZ
1719 /* Set the vlan id. */
1720 ctxd->upper.fields.special =
1721 htole16(m_head->m_pkthdr.ether_vlantag);
9ccd8c1f 1722
f647ad3d 1723 /* Tell hardware to add tag */
9c80d176 1724 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
f647ad3d 1725 }
984263bc
MD
1726
1727 tx_buffer->m_head = m_head;
9c80d176 1728 tx_buffer_mapped->map = tx_buffer->map;
1eca7b82 1729 tx_buffer->map = map;
9ccd8c1f 1730
9f60d74b
SZ
1731 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1732 adapter->tx_nsegs = 0;
4e4e8481
SZ
1733
1734 /*
1735 * Report Status (RS) is turned on
1736 * every tx_int_nsegs descriptors.
1737 */
9f60d74b
SZ
1738 cmd = E1000_TXD_CMD_RS;
1739
b4b0a2b4
SZ
1740 /*
1741 * Keep track of the descriptor, which will
1742 * be written back by hardware.
1743 */
9f60d74b
SZ
1744 adapter->tx_dd[adapter->tx_dd_tail] = last;
1745 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1746 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1747 }
1748
9ccd8c1f 1749 /*
984263bc 1750 * Last Descriptor of Packet needs End Of Packet (EOP)
87307ba1 1751 */
9f60d74b 1752 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
87307ba1
SZ
1753
1754 /*
9c80d176 1755 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
984263bc
MD
1756 * that this frame is available to transmit.
1757 */
9c80d176 1758 if (adapter->hw.mac.type == e1000_82547 &&
984263bc 1759 adapter->link_duplex == HALF_DUPLEX) {
cfefda96 1760 em_82547_move_tail_serialized(adapter);
9ccd8c1f 1761 } else {
9c80d176
SZ
1762 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1763 if (adapter->hw.mac.type == e1000_82547) {
cfefda96 1764 em_82547_update_fifo_head(adapter,
9c80d176 1765 m_head->m_pkthdr.len);
984263bc
MD
1766 }
1767 }
87307ba1 1768 return (0);
984263bc
MD
1769}
1770
9c80d176 1771/*
984263bc 1772 * 82547 workaround to avoid controller hang in half-duplex environment.
87307ba1 1773 * The workaround is to avoid queuing a large packet that would span
9c80d176
SZ
1774 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1775 * in this case. We do that only when FIFO is quiescent.
1776 */
9c095379 1777static void
1eca7b82 1778em_82547_move_tail_serialized(struct adapter *adapter)
9c095379 1779{
9c80d176
SZ
1780 struct e1000_tx_desc *tx_desc;
1781 uint16_t hw_tdt, sw_tdt, length = 0;
1782 bool eop = 0;
984263bc 1783
9c80d176
SZ
1784 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1785
1786 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
984263bc 1787 sw_tdt = adapter->next_avail_tx_desc;
f647ad3d 1788
984263bc
MD
1789 while (hw_tdt != sw_tdt) {
1790 tx_desc = &adapter->tx_desc_base[hw_tdt];
1791 length += tx_desc->lower.flags.length;
1792 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
87307ba1 1793 if (++hw_tdt == adapter->num_tx_desc)
984263bc
MD
1794 hw_tdt = 0;
1795
87307ba1 1796 if (eop) {
984263bc 1797 if (em_82547_fifo_workaround(adapter, length)) {
eac00e59 1798 adapter->tx_fifo_wrk_cnt++;
9ccd8c1f
JS
1799 callout_reset(&adapter->tx_fifo_timer, 1,
1800 em_82547_move_tail, adapter);
1801 break;
984263bc 1802 }
9c80d176 1803 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
9ccd8c1f
JS
1804 em_82547_update_fifo_head(adapter, length);
1805 length = 0;
984263bc 1806 }
9c80d176
SZ
1807 }
1808}
1809
1810static void
1811em_82547_move_tail(void *xsc)
1812{
1813 struct adapter *adapter = xsc;
1814 struct ifnet *ifp = &adapter->arpcom.ac_if;
1815
1816 lwkt_serialize_enter(ifp->if_serializer);
1817 em_82547_move_tail_serialized(adapter);
1818 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1819}
1820
1821static int
1822em_82547_fifo_workaround(struct adapter *adapter, int len)
1823{
1824 int fifo_space, fifo_pkt_len;
1825
1eca7b82 1826 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
984263bc
MD
1827
1828 if (adapter->link_duplex == HALF_DUPLEX) {
eac00e59 1829 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
984263bc
MD
1830
1831 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
f647ad3d 1832 if (em_82547_tx_fifo_reset(adapter))
87307ba1 1833 return (0);
f647ad3d 1834 else
87307ba1 1835 return (1);
984263bc
MD
1836 }
1837 }
87307ba1 1838 return (0);
984263bc
MD
1839}
1840
1841static void
1842em_82547_update_fifo_head(struct adapter *adapter, int len)
1843{
1eca7b82 1844 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
f647ad3d 1845
984263bc
MD
1846 /* tx_fifo_head is always 16 byte aligned */
1847 adapter->tx_fifo_head += fifo_pkt_len;
eac00e59
SZ
1848 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1849 adapter->tx_fifo_head -= adapter->tx_fifo_size;
984263bc
MD
1850}
1851
984263bc
MD
1852static int
1853em_82547_tx_fifo_reset(struct adapter *adapter)
7ea52455 1854{
984263bc
MD
1855 uint32_t tctl;
1856
9c80d176
SZ
1857 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1858 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1859 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1860 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1861 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1862 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1863 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
984263bc 1864 /* Disable TX unit */
9c80d176
SZ
1865 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1866 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1867 tctl & ~E1000_TCTL_EN);
984263bc
MD
1868
1869 /* Reset FIFO pointers */
9c80d176
SZ
1870 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1871 adapter->tx_head_addr);
1872 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1873 adapter->tx_head_addr);
1874 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1875 adapter->tx_head_addr);
1876 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1877 adapter->tx_head_addr);
984263bc
MD
1878
1879 /* Re-enable TX unit */
9c80d176 1880 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
1881 E1000_WRITE_FLUSH(&adapter->hw);
1882
1883 adapter->tx_fifo_head = 0;
eac00e59 1884 adapter->tx_fifo_reset_cnt++;
984263bc 1885
87307ba1 1886 return (TRUE);
eac00e59 1887 } else {
87307ba1 1888 return (FALSE);
984263bc
MD
1889 }
1890}
1891
1892static void
f647ad3d 1893em_set_promisc(struct adapter *adapter)
984263bc 1894{
9c80d176 1895 struct ifnet *ifp = &adapter->arpcom.ac_if;
1eca7b82 1896 uint32_t reg_rctl;
984263bc 1897
9c80d176 1898 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc
MD
1899
1900 if (ifp->if_flags & IFF_PROMISC) {
1901 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
9c80d176
SZ
1902 /* Turn this on if you want to see bad packets */
1903 if (em_debug_sbp)
1904 reg_rctl |= E1000_RCTL_SBP;
1905 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1906 } else if (ifp->if_flags & IFF_ALLMULTI) {
1907 reg_rctl |= E1000_RCTL_MPE;
1908 reg_rctl &= ~E1000_RCTL_UPE;
9c80d176 1909 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc 1910 }
984263bc
MD
1911}
1912
1913static void
f647ad3d 1914em_disable_promisc(struct adapter *adapter)
984263bc 1915{
f647ad3d 1916 uint32_t reg_rctl;
984263bc 1917
9c80d176 1918 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc 1919
9c80d176
SZ
1920 reg_rctl &= ~E1000_RCTL_UPE;
1921 reg_rctl &= ~E1000_RCTL_MPE;
1922 reg_rctl &= ~E1000_RCTL_SBP;
1923 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1924}
1925
984263bc 1926static void
f647ad3d 1927em_set_multi(struct adapter *adapter)
984263bc 1928{
9c80d176 1929 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1930 struct ifmultiaddr *ifma;
9c80d176 1931 uint32_t reg_rctl = 0;
2d0e5700 1932 uint8_t *mta;
f647ad3d 1933 int mcnt = 0;
f647ad3d 1934
2d0e5700
SZ
1935 mta = adapter->mta;
1936 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1937
9c80d176
SZ
1938 if (adapter->hw.mac.type == e1000_82542 &&
1939 adapter->hw.revision_id == E1000_REVISION_2) {
1940 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1941 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1942 e1000_pci_clear_mwi(&adapter->hw);
f647ad3d 1943 reg_rctl |= E1000_RCTL_RST;
9c80d176 1944 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d
JS
1945 msec_delay(5);
1946 }
984263bc 1947
441d34b2 1948 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
f647ad3d
JS
1949 if (ifma->ifma_addr->sa_family != AF_LINK)
1950 continue;
1951
1952 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1953 break;
984263bc 1954
f647ad3d 1955 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
9c80d176 1956 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
f647ad3d
JS
1957 mcnt++;
1958 }
1959
1960 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
9c80d176 1961 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1962 reg_rctl |= E1000_RCTL_MPE;
9c80d176 1963 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
7ea52455 1964 } else {
6a5a645e 1965 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
7ea52455 1966 }
f647ad3d 1967
9c80d176
SZ
1968 if (adapter->hw.mac.type == e1000_82542 &&
1969 adapter->hw.revision_id == E1000_REVISION_2) {
1970 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1971 reg_rctl &= ~E1000_RCTL_RST;
9c80d176 1972 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d 1973 msec_delay(5);
9c80d176
SZ
1974 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1975 e1000_pci_set_mwi(&adapter->hw);
f647ad3d
JS
1976 }
1977}
984263bc 1978
9c80d176
SZ
1979/*
1980 * This routine checks for link status and updates statistics.
1981 */
984263bc 1982static void
9c80d176 1983em_timer(void *xsc)
984263bc 1984{
9c80d176
SZ
1985 struct adapter *adapter = xsc;
1986 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 1987
78195a76 1988 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1989
87307ba1 1990 em_update_link_status(adapter);
9c80d176
SZ
1991 em_update_stats(adapter);
1992
1993 /* Reset LAA into RAR[0] on 82571 */
1994 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1995 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1996
1997 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
984263bc 1998 em_print_hw_stats(adapter);
9c80d176 1999
984263bc
MD
2000 em_smartspeed(adapter);
2001
9c80d176 2002 callout_reset(&adapter->timer, hz, em_timer, adapter);
984263bc 2003
78195a76 2004 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2005}
2006
2007static void
87307ba1 2008em_update_link_status(struct adapter *adapter)
984263bc 2009{
9c80d176
SZ
2010 struct e1000_hw *hw = &adapter->hw;
2011 struct ifnet *ifp = &adapter->arpcom.ac_if;
2012 device_t dev = adapter->dev;
2013 uint32_t link_check = 0;
2014
2015 /* Get the cached link value or read phy for real */
2016 switch (hw->phy.media_type) {
2017 case e1000_media_type_copper:
2018 if (hw->mac.get_link_status) {
2019 /* Do the work to read phy */
2020 e1000_check_for_link(hw);
2021 link_check = !hw->mac.get_link_status;
2022 if (link_check) /* ESB2 fix */
2023 e1000_cfg_on_link_up(hw);
2024 } else {
2025 link_check = TRUE;
984263bc 2026 }
9c80d176
SZ
2027 break;
2028
2029 case e1000_media_type_fiber:
2030 e1000_check_for_link(hw);
2031 link_check =
2032 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2033 break;
2034
2035 case e1000_media_type_internal_serdes:
2036 e1000_check_for_link(hw);
2037 link_check = adapter->hw.mac.serdes_has_link;
2038 break;
2039
2040 case e1000_media_type_unknown:
2041 default:
2042 break;
2043 }
2044
2045 /* Now check for a transition */
2046 if (link_check && adapter->link_active == 0) {
2047 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2048 &adapter->link_duplex);
cb5a6be6
SZ
2049
2050 /*
2051 * Check if we should enable/disable SPEED_MODE bit on
2052 * 82571/82572
2053 */
2d0e5700
SZ
2054 if (adapter->link_speed != SPEED_1000 &&
2055 (hw->mac.type == e1000_82571 ||
2056 hw->mac.type == e1000_82572)) {
9c80d176
SZ
2057 int tarc0;
2058
2059 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 2060 tarc0 &= ~SPEED_MODE_BIT;
9c80d176 2061 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
984263bc 2062 }
9c80d176
SZ
2063 if (bootverbose) {
2064 device_printf(dev, "Link is up %d Mbps %s\n",
2065 adapter->link_speed,
2066 ((adapter->link_duplex == FULL_DUPLEX) ?
2067 "Full Duplex" : "Half Duplex"));
2068 }
2069 adapter->link_active = 1;
2070 adapter->smartspeed = 0;
2071 ifp->if_baudrate = adapter->link_speed * 1000000;
2072 ifp->if_link_state = LINK_STATE_UP;
2073 if_link_state_change(ifp);
2074 } else if (!link_check && adapter->link_active == 1) {
2075 ifp->if_baudrate = adapter->link_speed = 0;
2076 adapter->link_duplex = 0;
2077 if (bootverbose)
2078 device_printf(dev, "Link is Down\n");
2079 adapter->link_active = 0;
2080#if 0
2081 /* Link down, disable watchdog */
2082 if->if_timer = 0;
2083#endif
2084 ifp->if_link_state = LINK_STATE_DOWN;
2085 if_link_state_change(ifp);
984263bc 2086 }
984263bc
MD
2087}
2088
984263bc 2089static void
9c80d176 2090em_stop(struct adapter *adapter)
984263bc 2091{
9c80d176
SZ
2092 struct ifnet *ifp = &adapter->arpcom.ac_if;
2093 int i;
984263bc 2094
1eca7b82
SZ
2095 ASSERT_SERIALIZED(ifp->if_serializer);
2096
984263bc 2097 em_disable_intr(adapter);
9c80d176 2098
9ccd8c1f
JS
2099 callout_stop(&adapter->timer);
2100 callout_stop(&adapter->tx_fifo_timer);
984263bc 2101
984263bc 2102 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
af82d4bb 2103 ifp->if_timer = 0;
9c80d176
SZ
2104
2105 e1000_reset_hw(&adapter->hw);
2106 if (adapter->hw.mac.type >= e1000_82544)
2107 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2108
2109 for (i = 0; i < adapter->num_tx_desc; i++) {
2110 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2111
2112 if (tx_buffer->m_head != NULL) {
2113 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2114 m_freem(tx_buffer->m_head);
2115 tx_buffer->m_head = NULL;
2116 }
9c80d176
SZ
2117 }
2118
2119 for (i = 0; i < adapter->num_rx_desc; i++) {
2120 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2121
2122 if (rx_buffer->m_head != NULL) {
2123 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2124 m_freem(rx_buffer->m_head);
2125 rx_buffer->m_head = NULL;
2126 }
2127 }
c9ff32cc
SZ
2128
2129 if (adapter->fmp != NULL)
2130 m_freem(adapter->fmp);
2131 adapter->fmp = NULL;
2132 adapter->lmp = NULL;
51e6819f
SZ
2133
2134 adapter->csum_flags = 0;
2135 adapter->csum_ehlen = 0;
2136 adapter->csum_iphlen = 0;
9f60d74b
SZ
2137
2138 adapter->tx_dd_head = 0;
2139 adapter->tx_dd_tail = 0;
2140 adapter->tx_nsegs = 0;
984263bc
MD
2141}
2142
9c80d176
SZ
2143static int
2144em_get_hw_info(struct adapter *adapter)
984263bc
MD
2145{
2146 device_t dev = adapter->dev;
2147
984263bc
MD
2148 /* Save off the information about this board */
2149 adapter->hw.vendor_id = pci_get_vendor(dev);
2150 adapter->hw.device_id = pci_get_device(dev);
f647ad3d
JS
2151 adapter->hw.revision_id = pci_get_revid(dev);
2152 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
9c80d176 2153 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
984263bc 2154
9c80d176
SZ
2155 /* Do Shared Code Init and Setup */
2156 if (e1000_set_mac_type(&adapter->hw))
2157 return ENXIO;
2158 return 0;
984263bc
MD
2159}
2160
1eca7b82 2161static int
9c80d176 2162em_alloc_pci_res(struct adapter *adapter)
1eca7b82 2163{
9c80d176 2164 device_t dev = adapter->dev;
053f3ae6 2165 u_int intr_flags;
84e26aaa 2166 int val, rid, msi_enable;
9c80d176
SZ
2167
2168 /* Enable bus mastering */
2169 pci_enable_busmaster(dev);
1eca7b82 2170
9c80d176
SZ
2171 adapter->memory_rid = EM_BAR_MEM;
2172 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2173 &adapter->memory_rid, RF_ACTIVE);
2174 if (adapter->memory == NULL) {
1eca7b82 2175 device_printf(dev, "Unable to allocate bus resource: memory\n");
9c80d176 2176 return (ENXIO);
1eca7b82
SZ
2177 }
2178 adapter->osdep.mem_bus_space_tag =
9c80d176 2179 rman_get_bustag(adapter->memory);
1eca7b82 2180 adapter->osdep.mem_bus_space_handle =
9c80d176
SZ
2181 rman_get_bushandle(adapter->memory);
2182
2183 /* XXX This is quite goofy, it is not actually used */
1eca7b82
SZ
2184 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2185
9c80d176
SZ
2186 /* Only older adapters use IO mapping */
2187 if (adapter->hw.mac.type > e1000_82543 &&
2188 adapter->hw.mac.type < e1000_82571) {
1eca7b82 2189 /* Figure our where our IO BAR is ? */
9c80d176 2190 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
1eca7b82 2191 val = pci_read_config(dev, rid, 4);
87307ba1 2192 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1eca7b82
SZ
2193 adapter->io_rid = rid;
2194 break;
2195 }
2196 rid += 4;
87307ba1
SZ
2197 /* check for 64bit BAR */
2198 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2199 rid += 4;
1eca7b82 2200 }
9c80d176 2201 if (rid >= PCIR_CARDBUSCIS) {
87307ba1
SZ
2202 device_printf(dev, "Unable to locate IO BAR\n");
2203 return (ENXIO);
9c80d176
SZ
2204 }
2205 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2206 &adapter->io_rid, RF_ACTIVE);
2207 if (adapter->ioport == NULL) {
1eca7b82 2208 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2209 "ioport\n");
2210 return (ENXIO);
1eca7b82 2211 }
87307ba1
SZ
2212 adapter->hw.io_base = 0;
2213 adapter->osdep.io_bus_space_tag =
9c80d176 2214 rman_get_bustag(adapter->ioport);
87307ba1 2215 adapter->osdep.io_bus_space_handle =
9c80d176 2216 rman_get_bushandle(adapter->ioport);
1eca7b82
SZ
2217 }
2218
84e26aaa 2219 /*
a835687d
SZ
2220 * Don't enable MSI-X on 82574, see:
2221 * 82574 specification update errata #15
2222 *
84e26aaa 2223 * Don't enable MSI on PCI/PCI-X chips, see:
a835687d
SZ
2224 * 82540 specification update errata #6
2225 * 82545 specification update errata #4
84e26aaa
SZ
2226 *
2227 * Don't enable MSI on 82571/82572, see:
a835687d 2228 * 82571/82572 specification update errata #63
84e26aaa
SZ
2229 */
2230 msi_enable = em_msi_enable;
2231 if (msi_enable &&
2232 (!pci_is_pcie(dev) ||
2233 adapter->hw.mac.type == e1000_82571 ||
2234 adapter->hw.mac.type == e1000_82572))
2235 msi_enable = 0;
2236
2237 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
053f3ae6
SZ
2238 &adapter->intr_rid, &intr_flags);
2239
87ab432b
SZ
2240 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2241 int unshared;
2242
2243 unshared = device_getenv_int(dev, "irq.unshared", 0);
2244 if (!unshared) {
2245 adapter->flags |= EM_FLAG_SHARED_INTR;
2246 if (bootverbose)
2247 device_printf(dev, "IRQ shared\n");
2248 } else {
2249 intr_flags &= ~RF_SHAREABLE;
2250 if (bootverbose)
2251 device_printf(dev, "IRQ unshared\n");
2252 }
2253 }
2254
9c80d176 2255 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
053f3ae6 2256 &adapter->intr_rid, intr_flags);
9c80d176 2257 if (adapter->intr_res == NULL) {
1eca7b82 2258 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2259 "interrupt\n");
2260 return (ENXIO);
1eca7b82
SZ
2261 }
2262
9c80d176 2263 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1eca7b82 2264 adapter->hw.back = &adapter->osdep;
a483bd34 2265 return (0);
1eca7b82
SZ
2266}
2267
2268static void
9c80d176 2269em_free_pci_res(struct adapter *adapter)
1eca7b82 2270{
9c80d176 2271 device_t dev = adapter->dev;
1eca7b82 2272
9c80d176
SZ
2273 if (adapter->intr_res != NULL) {
2274 bus_release_resource(dev, SYS_RES_IRQ,
2275 adapter->intr_rid, adapter->intr_res);
1eca7b82 2276 }
9c80d176 2277
053f3ae6
SZ
2278 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2279 pci_release_msi(dev);
2280
9c80d176
SZ
2281 if (adapter->memory != NULL) {
2282 bus_release_resource(dev, SYS_RES_MEMORY,
2283 adapter->memory_rid, adapter->memory);
1eca7b82
SZ
2284 }
2285
9c80d176
SZ
2286 if (adapter->flash != NULL) {
2287 bus_release_resource(dev, SYS_RES_MEMORY,
2288 adapter->flash_rid, adapter->flash);
1eca7b82
SZ
2289 }
2290
9c80d176
SZ
2291 if (adapter->ioport != NULL) {
2292 bus_release_resource(dev, SYS_RES_IOPORT,
2293 adapter->io_rid, adapter->ioport);
1eca7b82
SZ
2294 }
2295}
2296
984263bc 2297static int
2d0e5700 2298em_reset(struct adapter *adapter)
984263bc 2299{
9c80d176
SZ
2300 device_t dev = adapter->dev;
2301 uint16_t rx_buffer_size;
7ea52455 2302
984263bc
MD
2303 /* When hardware is reset, fifo_head is also reset */
2304 adapter->tx_fifo_head = 0;
2305
87307ba1 2306 /* Set up smart power down as default off on newer adapters. */
1eca7b82 2307 if (!em_smart_pwr_down &&
9c80d176
SZ
2308 (adapter->hw.mac.type == e1000_82571 ||
2309 adapter->hw.mac.type == e1000_82572)) {
1eca7b82
SZ
2310 uint16_t phy_tmp = 0;
2311
87307ba1 2312 /* Speed up time to link by disabling smart power down. */
9c80d176
SZ
2313 e1000_read_phy_reg(&adapter->hw,
2314 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1eca7b82 2315 phy_tmp &= ~IGP02E1000_PM_SPD;
9c80d176
SZ
2316 e1000_write_phy_reg(&adapter->hw,
2317 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1eca7b82
SZ
2318 }
2319
7ea52455 2320 /*
87307ba1
SZ
2321 * These parameters control the automatic generation (Tx) and
2322 * response (Rx) to Ethernet PAUSE frames.
7ea52455
SZ
2323 * - High water mark should allow for at least two frames to be
2324 * received after sending an XOFF.
2325 * - Low water mark works best when it is very near the high water mark.
2326 * This allows the receiver to restart by sending XON when it has
9c80d176
SZ
2327 * drained a bit. Here we use an arbitary value of 1500 which will
2328 * restart after one full frame is pulled from the buffer. There
7ea52455
SZ
2329 * could be several smaller frames in the buffer and if so they will
2330 * not trigger the XON until their total number reduces the buffer
2331 * by 1500.
2332 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2333 */
9c80d176
SZ
2334 rx_buffer_size =
2335 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
7ea52455 2336
9c80d176
SZ
2337 adapter->hw.fc.high_water = rx_buffer_size -
2338 roundup2(adapter->max_frame_size, 1024);
2339 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2340
2341 if (adapter->hw.mac.type == e1000_80003es2lan)
2342 adapter->hw.fc.pause_time = 0xFFFF;
1eca7b82 2343 else
9c80d176 2344 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2d0e5700 2345
9c80d176 2346 adapter->hw.fc.send_xon = TRUE;
2d0e5700 2347
9c80d176 2348 adapter->hw.fc.requested_mode = e1000_fc_full;
7ea52455 2349
2d0e5700
SZ
2350 /* Workaround: no TX flow ctrl for PCH */
2351 if (adapter->hw.mac.type == e1000_pchlan)
2352 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2353
2354 /* Override - settings for PCH2LAN, ya its magic :) */
2355 if (adapter->hw.mac.type == e1000_pch2lan) {
2356 adapter->hw.fc.high_water = 0x5C20;
2357 adapter->hw.fc.low_water = 0x5048;
2358 adapter->hw.fc.pause_time = 0x0650;
2359 adapter->hw.fc.refresh_time = 0x0400;
2360
2361 /* Jumbos need adjusted PBA */
2362 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2363 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2364 else
2365 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2366 }
2367
2368 /* Issue a global reset */
2369 e1000_reset_hw(&adapter->hw);
2370 if (adapter->hw.mac.type >= e1000_82544)
2371 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
6d5e2922 2372 em_disable_aspm(adapter);
2d0e5700 2373
9c80d176
SZ
2374 if (e1000_init_hw(&adapter->hw) < 0) {
2375 device_printf(dev, "Hardware Initialization Failed\n");
87307ba1 2376 return (EIO);
984263bc
MD
2377 }
2378
2d0e5700
SZ
2379 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2380 e1000_get_phy_info(&adapter->hw);
9c80d176 2381 e1000_check_for_link(&adapter->hw);
984263bc 2382
87307ba1 2383 return (0);
984263bc
MD
2384}
2385
984263bc 2386static void
9c80d176 2387em_setup_ifp(struct adapter *adapter)
984263bc 2388{
9c80d176 2389 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2390
9c80d176
SZ
2391 if_initname(ifp, device_get_name(adapter->dev),
2392 device_get_unit(adapter->dev));
984263bc
MD
2393 ifp->if_softc = adapter;
2394 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c80d176 2395 ifp->if_init = em_init;
984263bc
MD
2396 ifp->if_ioctl = em_ioctl;
2397 ifp->if_start = em_start;
9c095379
MD
2398#ifdef DEVICE_POLLING
2399 ifp->if_poll = em_poll;
2400#endif
984263bc 2401 ifp->if_watchdog = em_watchdog;
e26dc3e9 2402 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
19b1d5b8 2403 ifq_set_ready(&ifp->if_snd);
984263bc 2404
9c80d176 2405 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
984263bc 2406
9c80d176
SZ
2407 if (adapter->hw.mac.type >= e1000_82543)
2408 ifp->if_capabilities = IFCAP_HWCSUM;
e095c7aa 2409
9c80d176
SZ
2410 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2411 ifp->if_capenable = ifp->if_capabilities;
984263bc 2412
9c80d176
SZ
2413 if (ifp->if_capenable & IFCAP_TXCSUM)
2414 ifp->if_hwassist = EM_CSUM_FEATURES;
21fa6062 2415
f647ad3d
JS
2416 /*
2417 * Tell the upper layer(s) we support long frames.
2418 */
2419 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
984263bc 2420
87307ba1 2421 /*
984263bc
MD
2422 * Specify the media types supported by this adapter and register
2423 * callbacks to update media and link information
2424 */
9c80d176
SZ
2425 ifmedia_init(&adapter->media, IFM_IMASK,
2426 em_media_change, em_media_status);
2427 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2428 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2429 u_char fiber_type = IFM_1000_SX; /* default type */
2430
2431 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
2432 fiber_type = IFM_1000_LX;
2433 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
984263bc 2434 0, NULL);
87307ba1 2435 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
984263bc
MD
2436 } else {
2437 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
87307ba1 2438 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
984263bc 2439 0, NULL);
87307ba1 2440 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
984263bc 2441 0, NULL);
87307ba1 2442 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
984263bc 2443 0, NULL);
9c80d176
SZ
2444 if (adapter->hw.phy.type != e1000_phy_ife) {
2445 ifmedia_add(&adapter->media,
2446 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2447 ifmedia_add(&adapter->media,
2448 IFM_ETHER | IFM_1000_T, 0, NULL);
2449 }
984263bc
MD
2450 }
2451 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2452 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
984263bc
MD
2453}
2454
9c80d176
SZ
2455
2456/*
2457 * Workaround for SmartSpeed on 82541 and 82547 controllers
2458 */
984263bc
MD
2459static void
2460em_smartspeed(struct adapter *adapter)
2461{
f647ad3d
JS
2462 uint16_t phy_tmp;
2463
9c80d176
SZ
2464 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2465 adapter->hw.mac.autoneg == 0 ||
2466 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
984263bc
MD
2467 return;
2468
f647ad3d
JS
2469 if (adapter->smartspeed == 0) {
2470 /*
2471 * If Master/Slave config fault is asserted twice,
9c80d176 2472 * we assume back-to-back
f647ad3d 2473 */
9c80d176 2474 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d
JS
2475 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2476 return;
9c80d176 2477 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d 2478 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
9c80d176
SZ
2479 e1000_read_phy_reg(&adapter->hw,
2480 PHY_1000T_CTRL, &phy_tmp);
f647ad3d
JS
2481 if (phy_tmp & CR_1000T_MS_ENABLE) {
2482 phy_tmp &= ~CR_1000T_MS_ENABLE;
9c80d176
SZ
2483 e1000_write_phy_reg(&adapter->hw,
2484 PHY_1000T_CTRL, phy_tmp);
f647ad3d 2485 adapter->smartspeed++;
9c80d176
SZ
2486 if (adapter->hw.mac.autoneg &&
2487 !e1000_phy_setup_autoneg(&adapter->hw) &&
2488 !e1000_read_phy_reg(&adapter->hw,
2489 PHY_CONTROL, &phy_tmp)) {
2490 phy_tmp |= MII_CR_AUTO_NEG_EN |
2491 MII_CR_RESTART_AUTO_NEG;
2492 e1000_write_phy_reg(&adapter->hw,
2493 PHY_CONTROL, phy_tmp);
f647ad3d
JS
2494 }
2495 }
2496 }
87307ba1 2497 return;
f647ad3d
JS
2498 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2499 /* If still no link, perhaps using 2/3 pair cable */
9c80d176 2500 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
f647ad3d 2501 phy_tmp |= CR_1000T_MS_ENABLE;
9c80d176
SZ
2502 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2503 if (adapter->hw.mac.autoneg &&
2504 !e1000_phy_setup_autoneg(&adapter->hw) &&
2505 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2506 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2507 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
f647ad3d
JS
2508 }
2509 }
9c80d176 2510
f647ad3d
JS
2511 /* Restart process after EM_SMARTSPEED_MAX iterations */
2512 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2513 adapter->smartspeed = 0;
984263bc
MD
2514}
2515
9ccd8c1f
JS
2516static int
2517em_dma_malloc(struct adapter *adapter, bus_size_t size,
87307ba1 2518 struct em_dma_alloc *dma)
9ccd8c1f 2519{
9c80d176
SZ
2520 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2521 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2522 &dma->dma_tag, &dma->dma_map,
2523 &dma->dma_paddr);
2524 if (dma->dma_vaddr == NULL)
2525 return ENOMEM;
2526 else
2527 return 0;
9ccd8c1f
JS
2528}
2529
2530static void
2531em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2532{
9c80d176
SZ
2533 if (dma->dma_tag == NULL)
2534 return;
2535 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2536 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2537 bus_dma_tag_destroy(dma->dma_tag);
984263bc
MD
2538}
2539
984263bc 2540static int
9c80d176 2541em_create_tx_ring(struct adapter *adapter)
984263bc 2542{
9c80d176 2543 device_t dev = adapter->dev;
1eca7b82 2544 struct em_buffer *tx_buffer;
1eca7b82
SZ
2545 int error, i;
2546
87307ba1
SZ
2547 adapter->tx_buffer_area =
2548 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2549 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 2550
9c80d176
SZ
2551 /*
2552 * Create DMA tags for tx buffers
2553 */
2554 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2555 1, 0, /* alignment, bounds */
2556 BUS_SPACE_MAXADDR, /* lowaddr */
2557 BUS_SPACE_MAXADDR, /* highaddr */
2558 NULL, NULL, /* filter, filterarg */
2559 EM_TSO_SIZE, /* maxsize */
2560 EM_MAX_SCATTER, /* nsegments */
2561 EM_MAX_SEGSIZE, /* maxsegsize */
2562 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2563 BUS_DMA_ONEBPAGE, /* flags */
2564 &adapter->txtag);
2565 if (error) {
2566 device_printf(dev, "Unable to allocate TX DMA tag\n");
2567 kfree(adapter->tx_buffer_area, M_DEVBUF);
2568 adapter->tx_buffer_area = NULL;
2569 return error;
2570 }
2571
2572 /*
2573 * Create DMA maps for tx buffers
2574 */
1eca7b82 2575 for (i = 0; i < adapter->num_tx_desc; i++) {
9c80d176
SZ
2576 tx_buffer = &adapter->tx_buffer_area[i];
2577
2578 error = bus_dmamap_create(adapter->txtag,
2579 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2580 &tx_buffer->map);
1eca7b82 2581 if (error) {
9c80d176
SZ
2582 device_printf(dev, "Unable to create TX DMA map\n");
2583 em_destroy_tx_ring(adapter, i);
2584 return error;
1eca7b82 2585 }
1eca7b82 2586 }
9c80d176
SZ
2587 return (0);
2588}
9ccd8c1f 2589
9c80d176
SZ
2590static void
2591em_init_tx_ring(struct adapter *adapter)
2592{
2593 /* Clear the old ring contents */
2594 bzero(adapter->tx_desc_base,
2595 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2596
2597 /* Reset state */
87307ba1
SZ
2598 adapter->next_avail_tx_desc = 0;
2599 adapter->next_tx_to_clean = 0;
984263bc 2600 adapter->num_tx_desc_avail = adapter->num_tx_desc;
984263bc
MD
2601}
2602
984263bc 2603static void
9c80d176 2604em_init_tx_unit(struct adapter *adapter)
984263bc 2605{
9c80d176 2606 uint32_t tctl, tarc, tipg = 0;
9ccd8c1f
JS
2607 uint64_t bus_addr;
2608
984263bc 2609 /* Setup the Base and Length of the Tx Descriptor Ring */
9ccd8c1f 2610 bus_addr = adapter->txdma.dma_paddr;
9c80d176
SZ
2611 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2612 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2613 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2614 (uint32_t)(bus_addr >> 32));
2615 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2616 (uint32_t)bus_addr);
984263bc 2617 /* Setup the HW Tx Head and Tail descriptor pointers */
9c80d176
SZ
2618 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2619 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
984263bc 2620
984263bc 2621 /* Set the default values for the Tx Inter Packet Gap timer */
9c80d176
SZ
2622 switch (adapter->hw.mac.type) {
2623 case e1000_82542:
2624 tipg = DEFAULT_82542_TIPG_IPGT;
2625 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2626 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
984263bc 2627 break;
9c80d176
SZ
2628
2629 case e1000_80003es2lan:
2630 tipg = DEFAULT_82543_TIPG_IPGR1;
2631 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2632 E1000_TIPG_IPGR2_SHIFT;
1eca7b82 2633 break;
9c80d176 2634
984263bc 2635 default:
9c80d176
SZ
2636 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2637 adapter->hw.phy.media_type ==
2638 e1000_media_type_internal_serdes)
2639 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
984263bc 2640 else
9c80d176
SZ
2641 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2642 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2643 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2644 break;
2645 }
2646
2647 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
91e8debf
SZ
2648
2649 /* NOTE: 0 is not allowed for TIDV */
2650 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2651 if(adapter->hw.mac.type >= e1000_82540)
2652 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
984263bc 2653
9c80d176
SZ
2654 if (adapter->hw.mac.type == e1000_82571 ||
2655 adapter->hw.mac.type == e1000_82572) {
2656 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2657 tarc |= SPEED_MODE_BIT;
2658 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2659 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2660 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2661 tarc |= 1;
2662 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2663 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2664 tarc |= 1;
2665 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
1eca7b82
SZ
2666 }
2667
984263bc 2668 /* Program the Transmit Control Register */
9c80d176
SZ
2669 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2670 tctl &= ~E1000_TCTL_CT;
2671 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2672 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2673
2674 if (adapter->hw.mac.type >= e1000_82571)
2675 tctl |= E1000_TCTL_MULR;
1eca7b82 2676
87307ba1 2677 /* This write will effectively turn on the transmit unit. */
9c80d176 2678 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
2679}
2680
984263bc 2681static void
9c80d176 2682em_destroy_tx_ring(struct adapter *adapter, int ndesc)
984263bc 2683{
f647ad3d
JS
2684 struct em_buffer *tx_buffer;
2685 int i;
984263bc 2686
9c80d176
SZ
2687 if (adapter->tx_buffer_area == NULL)
2688 return;
984263bc 2689
9c80d176
SZ
2690 for (i = 0; i < ndesc; i++) {
2691 tx_buffer = &adapter->tx_buffer_area[i];
1eca7b82 2692
9c80d176
SZ
2693 KKASSERT(tx_buffer->m_head == NULL);
2694 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
9ccd8c1f 2695 }
9c80d176
SZ
2696 bus_dma_tag_destroy(adapter->txtag);
2697
2698 kfree(adapter->tx_buffer_area, M_DEVBUF);
2699 adapter->tx_buffer_area = NULL;
984263bc
MD
2700}
2701
9c80d176
SZ
2702/*
2703 * The offload context needs to be set when we transfer the first
2704 * packet of a particular protocol (TCP/UDP). This routine has been
002b3a05 2705 * enhanced to deal with inserted VLAN headers.
51e6819f
SZ
2706 *
2707 * If the new packet's ether header length, ip header length and
2708 * csum offloading type are same as the previous packet, we should
2709 * avoid allocating a new csum context descriptor; mainly to take
2710 * advantage of the pipeline effect of the TX data read request.
9f60d74b
SZ
2711 *
2712 * This function returns number of TX descrptors allocated for
2713 * csum context.
9c80d176 2714 */
9f60d74b 2715static int
9c80d176
SZ
2716em_txcsum(struct adapter *adapter, struct mbuf *mp,
2717 uint32_t *txd_upper, uint32_t *txd_lower)
984263bc 2718{
9c80d176 2719 struct e1000_context_desc *TXD;
984263bc 2720 struct em_buffer *tx_buffer;
9c80d176 2721 struct ether_vlan_header *eh;
51e6819f
SZ
2722 struct ip *ip;
2723 int curr_txd, ehdrlen, csum_flags;
9c80d176
SZ
2724 uint32_t cmd, hdr_len, ip_hlen;
2725 uint16_t etype;
9c80d176 2726
9c80d176
SZ
2727 /*
2728 * Determine where frame payload starts.
2729 * Jump over vlan headers if already present,
2730 * helpful for QinQ too.
2731 */
252dfd0d 2732 KASSERT(mp->m_len >= ETHER_HDR_LEN,
ed20d0e3 2733 ("em_txcsum_pullup is not called (eh)?"));
9c80d176
SZ
2734 eh = mtod(mp, struct ether_vlan_header *);
2735 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
252dfd0d 2736 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
ed20d0e3 2737 ("em_txcsum_pullup is not called (evh)?"));
9c80d176
SZ
2738 etype = ntohs(eh->evl_proto);
2739 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
984263bc 2740 } else {
9c80d176
SZ
2741 etype = ntohs(eh->evl_encap_proto);
2742 ehdrlen = ETHER_HDR_LEN;
984263bc
MD
2743 }
2744
1eca7b82 2745 /*
002b3a05 2746 * We only support TCP/UDP for IPv4 for the moment.
9c80d176 2747 * TODO: Support SCTP too when it hits the tree.
984263bc 2748 */
51e6819f 2749 if (etype != ETHERTYPE_IP)
9f60d74b 2750 return 0;
002b3a05 2751
51e6819f 2752 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE,
ed20d0e3 2753 ("em_txcsum_pullup is not called (eh+ip_vhl)?"));
9c80d176 2754
51e6819f
SZ
2755 /* NOTE: We could only safely access ip.ip_vhl part */
2756 ip = (struct ip *)(mp->m_data + ehdrlen);
2757 ip_hlen = ip->ip_hl << 2;
984263bc 2758
51e6819f
SZ
2759 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2760
2761 if (adapter->csum_ehlen == ehdrlen &&
2762 adapter->csum_iphlen == ip_hlen &&
2763 adapter->csum_flags == csum_flags) {
2764 /*
2765 * Same csum offload context as the previous packets;
2766 * just return.
2767 */
2768 *txd_upper = adapter->csum_txd_upper;
2769 *txd_lower = adapter->csum_txd_lower;
9f60d74b 2770 return 0;
984263bc
MD
2771 }
2772
51e6819f
SZ
2773 /*
2774 * Setup a new csum offload context.
2775 */
2776
2777 curr_txd = adapter->next_avail_tx_desc;
2778 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2779 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2780
2781 cmd = 0;
2782
2783 /* Setup of IP header checksum. */
2784 if (csum_flags & CSUM_IP) {
2785 /*
2786 * Start offset for header checksum calculation.
2787 * End offset for header checksum calculation.
2788 * Offset of place to put the checksum.
2789 */
2790 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2791 TXD->lower_setup.ip_fields.ipcse =
2792 htole16(ehdrlen + ip_hlen - 1);
2793 TXD->lower_setup.ip_fields.ipcso =
2794 ehdrlen + offsetof(struct ip, ip_sum);
2795 cmd |= E1000_TXD_CMD_IP;
2796 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2797 }
2798 hdr_len = ehdrlen + ip_hlen;
2799
2800 if (csum_flags & CSUM_TCP) {
002b3a05
SZ
2801 /*
2802 * Start offset for payload checksum calculation.
2803 * End offset for payload checksum calculation.
2804 * Offset of place to put the checksum.
2805 */
2806 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2807 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2808 TXD->upper_setup.tcp_fields.tucso =
2809 hdr_len + offsetof(struct tcphdr, th_sum);
2810 cmd |= E1000_TXD_CMD_TCP;
2811 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
51e6819f 2812 } else if (csum_flags & CSUM_UDP) {
002b3a05
SZ
2813 /*
2814 * Start offset for header checksum calculation.
2815 * End offset for header checksum calculation.
2816 * Offset of place to put the checksum.
2817 */
2818 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2819 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2820 TXD->upper_setup.tcp_fields.tucso =
2821 hdr_len + offsetof(struct udphdr, uh_sum);
2822 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
9c80d176
SZ
2823 }
2824
2825 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2826 E1000_TXD_DTYP_D; /* Data descr */
51e6819f
SZ
2827
2828 /* Save the information for this csum offloading context */
2829 adapter->csum_ehlen = ehdrlen;
2830 adapter->csum_iphlen = ip_hlen;
2831 adapter->csum_flags = csum_flags;
2832 adapter->csum_txd_upper = *txd_upper;
2833 adapter->csum_txd_lower = *txd_lower;
2834
9c80d176
SZ
2835 TXD->tcp_seg_setup.data = htole32(0);
2836 TXD->cmd_and_length =
2af74b85 2837 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
984263bc
MD
2838
2839 if (++curr_txd == adapter->num_tx_desc)
2840 curr_txd = 0;
2841
9c80d176 2842 KKASSERT(adapter->num_tx_desc_avail > 0);
984263bc 2843 adapter->num_tx_desc_avail--;
9c80d176 2844
984263bc 2845 adapter->next_avail_tx_desc = curr_txd;
9f60d74b 2846 return 1;
984263bc
MD
2847}
2848
002b3a05
SZ
2849static int
2850em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0)
2851{
2852 struct mbuf *m = *m0;
2853 struct ether_header *eh;
2854 int len;
2855
2856 adapter->tx_csum_try_pullup++;
2857
2858 len = ETHER_HDR_LEN + EM_IPVHL_SIZE;
2859
2860 if (__predict_false(!M_WRITABLE(m))) {
2861 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2862 adapter->tx_csum_drop1++;
2863 m_freem(m);
2864 *m0 = NULL;
2865 return ENOBUFS;
2866 }
2867 eh = mtod(m, struct ether_header *);
2868
2869 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2870 len += EVL_ENCAPLEN;
2871
3752657e 2872 if (m->m_len < len) {
002b3a05
SZ
2873 adapter->tx_csum_drop2++;
2874 m_freem(m);
2875 *m0 = NULL;
2876 return ENOBUFS;
2877 }
2878 return 0;
2879 }
2880
2881 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2882 adapter->tx_csum_pullup1++;
2883 m = m_pullup(m, ETHER_HDR_LEN);
2884 if (m == NULL) {
2885 adapter->tx_csum_pullup1_failed++;
2886 *m0 = NULL;
2887 return ENOBUFS;
2888 }
2889 *m0 = m;
2890 }
2891 eh = mtod(m, struct ether_header *);
2892
2893 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2894 len += EVL_ENCAPLEN;
2895
3752657e 2896 if (m->m_len < len) {
002b3a05
SZ
2897 adapter->tx_csum_pullup2++;
2898 m = m_pullup(m, len);
2899 if (m == NULL) {
2900 adapter->tx_csum_pullup2_failed++;
2901 *m0 = NULL;
2902 return ENOBUFS;
2903 }
2904 *m0 = m;
2905 }
2906 return 0;
2907}
2908
984263bc 2909static void
87307ba1 2910em_txeof(struct adapter *adapter)
984263bc 2911{
9c80d176 2912 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2913 struct em_buffer *tx_buffer;
2914 int first, num_avail;
2915
2916 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2917 return;
984263bc 2918
f647ad3d
JS
2919 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2920 return;
984263bc 2921
9c80d176 2922 num_avail = adapter->num_tx_desc_avail;
87307ba1 2923 first = adapter->next_tx_to_clean;
9c80d176 2924
9f60d74b 2925 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
4e499730 2926 struct e1000_tx_desc *tx_desc;
9f60d74b 2927 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
984263bc 2928
9f60d74b 2929 tx_desc = &adapter->tx_desc_base[dd_idx];
9f60d74b
SZ
2930 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2931 EM_INC_TXDD_IDX(adapter->tx_dd_head);
984263bc 2932
9f60d74b
SZ
2933 if (++dd_idx == adapter->num_tx_desc)
2934 dd_idx = 0;
9c80d176 2935
9f60d74b 2936 while (first != dd_idx) {
edbfa193
SZ
2937 logif(pkt_txclean);
2938
9f60d74b
SZ
2939 num_avail++;
2940
4e499730 2941 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
2942 if (tx_buffer->m_head) {
2943 ifp->if_opackets++;
2944 bus_dmamap_unload(adapter->txtag,
2945 tx_buffer->map);
2946 m_freem(tx_buffer->m_head);
2947 tx_buffer->m_head = NULL;
2948 }
2949
2950 if (++first == adapter->num_tx_desc)
2951 first = 0;
2952 }
87307ba1
SZ
2953 } else {
2954 break;
2955 }
f647ad3d 2956 }
9f60d74b
SZ
2957 adapter->next_tx_to_clean = first;
2958 adapter->num_tx_desc_avail = num_avail;
2959
2960 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2961 adapter->tx_dd_head = 0;
2962 adapter->tx_dd_tail = 0;
2963 }
2964
2965 if (!EM_IS_OACTIVE(adapter)) {
2966 ifp->if_flags &= ~IFF_OACTIVE;
2967
2968 /* All clean, turn off the timer */
2969 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2970 ifp->if_timer = 0;
2971 }
2972}
2973
2974static void
2975em_tx_collect(struct adapter *adapter)
2976{
2977 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2978 struct em_buffer *tx_buffer;
2979 int tdh, first, num_avail, dd_idx = -1;
2980
2981 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2982 return;
2983
2984 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2985 if (tdh == adapter->next_tx_to_clean)
2986 return;
2987
2988 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2989 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2990
2991 num_avail = adapter->num_tx_desc_avail;
2992 first = adapter->next_tx_to_clean;
2993
2994 while (first != tdh) {
edbfa193
SZ
2995 logif(pkt_txclean);
2996
9f60d74b
SZ
2997 num_avail++;
2998
4e499730 2999 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
3000 if (tx_buffer->m_head) {
3001 ifp->if_opackets++;
3002 bus_dmamap_unload(adapter->txtag,
3003 tx_buffer->map);
3004 m_freem(tx_buffer->m_head);
3005 tx_buffer->m_head = NULL;
3006 }
3007
3008 if (first == dd_idx) {
3009 EM_INC_TXDD_IDX(adapter->tx_dd_head);
3010 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3011 adapter->tx_dd_head = 0;
3012 adapter->tx_dd_tail = 0;
3013 dd_idx = -1;
3014 } else {
3015 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3016 }
3017 }
3018
3019 if (++first == adapter->num_tx_desc)
3020 first = 0;
3021 }
3022 adapter->next_tx_to_clean = first;
9c80d176 3023 adapter->num_tx_desc_avail = num_avail;
984263bc 3024
9f60d74b 3025 if (!EM_IS_OACTIVE(adapter)) {
9c80d176 3026 ifp->if_flags &= ~IFF_OACTIVE;
afa68aa1 3027
9c80d176
SZ
3028 /* All clean, turn off the timer */
3029 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3030 ifp->if_timer = 0;
3031 }
3032}
984263bc 3033
9c80d176
SZ
3034/*
3035 * When Link is lost sometimes there is work still in the TX ring
3036 * which will result in a watchdog, rather than allow that do an
3037 * attempted cleanup and then reinit here. Note that this has been
3038 * seens mostly with fiber adapters.
3039 */
3040static void
3041em_tx_purge(struct adapter *adapter)
3042{
3043 struct ifnet *ifp = &adapter->arpcom.ac_if;
3044
3045 if (!adapter->link_active && ifp->if_timer) {
9f60d74b 3046 em_tx_collect(adapter);
9c80d176
SZ
3047 if (ifp->if_timer) {
3048 if_printf(ifp, "Link lost, TX pending, reinit\n");
f647ad3d 3049 ifp->if_timer = 0;
9c80d176
SZ
3050 em_init(adapter);
3051 }
f647ad3d 3052 }
984263bc
MD
3053}
3054
984263bc 3055static int
9c80d176 3056em_newbuf(struct adapter *adapter, int i, int init)
984263bc 3057{
9c80d176
SZ
3058 struct mbuf *m;
3059 bus_dma_segment_t seg;
3060 bus_dmamap_t map;
9ccd8c1f 3061 struct em_buffer *rx_buffer;
9c80d176
SZ
3062 int error, nseg;
3063
3064 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3065 if (m == NULL) {
3066 adapter->mbuf_cluster_failed++;
3067 if (init) {
3068 if_printf(&adapter->arpcom.ac_if,
3069 "Unable to allocate RX mbuf\n");
984263bc 3070 }
9c80d176 3071 return (ENOBUFS);
984263bc 3072 }
9c80d176 3073 m->m_len = m->m_pkthdr.len = MCLBYTES;
87307ba1 3074
9c80d176
SZ
3075 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3076 m_adj(m, ETHER_ALIGN);
9ccd8c1f 3077
9c80d176
SZ
3078 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3079 adapter->rx_sparemap, m,
3080 &seg, 1, &nseg, BUS_DMA_NOWAIT);
9ccd8c1f 3081 if (error) {
9c80d176
SZ
3082 m_freem(m);
3083 if (init) {
3084 if_printf(&adapter->arpcom.ac_if,
3085 "Unable to load RX mbuf\n");
3086 }
87307ba1 3087 return (error);
9ccd8c1f 3088 }
984263bc 3089
9c80d176
SZ
3090 rx_buffer = &adapter->rx_buffer_area[i];
3091 if (rx_buffer->m_head != NULL)
3092 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3093
3094 map = rx_buffer->map;
3095 rx_buffer->map = adapter->rx_sparemap;
3096 adapter->rx_sparemap = map;
3097
3098 rx_buffer->m_head = m;
3099
3100 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
87307ba1 3101 return (0);
984263bc
MD
3102}
3103
984263bc 3104static int
9c80d176 3105em_create_rx_ring(struct adapter *adapter)
984263bc 3106{
9c80d176 3107 device_t dev = adapter->dev;
9ccd8c1f 3108 struct em_buffer *rx_buffer;
9c80d176
SZ
3109 int i, error;
3110
3111 adapter->rx_buffer_area =
3112 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3113 M_DEVBUF, M_WAITOK | M_ZERO);
9ccd8c1f 3114
9c80d176
SZ
3115 /*
3116 * Create DMA tag for rx buffers
3117 */
3118 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3119 1, 0, /* alignment, bounds */
3120 BUS_SPACE_MAXADDR, /* lowaddr */
3121 BUS_SPACE_MAXADDR, /* highaddr */
3122 NULL, NULL, /* filter, filterarg */
3123 MCLBYTES, /* maxsize */
3124 1, /* nsegments */
3125 MCLBYTES, /* maxsegsize */
3126 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3127 &adapter->rxtag);
87307ba1 3128 if (error) {
9c80d176
SZ
3129 device_printf(dev, "Unable to allocate RX DMA tag\n");
3130 kfree(adapter->rx_buffer_area, M_DEVBUF);
3131 adapter->rx_buffer_area = NULL;
3132 return error;
3133 }
3134
3135 /*
3136 * Create spare DMA map for rx buffers
3137 */
3138 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3139 &adapter->rx_sparemap);
3140 if (error) {
3141 device_printf(dev, "Unable to create spare RX DMA map\n");
3142 bus_dma_tag_destroy(adapter->rxtag);
3143 kfree(adapter->rx_buffer_area, M_DEVBUF);
3144 adapter->rx_buffer_area = NULL;
3145 return error;
9ccd8c1f 3146 }
9c80d176
SZ
3147
3148 /*
3149 * Create DMA maps for rx buffers
3150 */
3151 for (i = 0; i < adapter->num_rx_desc; i++) {
3152 rx_buffer = &adapter->rx_buffer_area[i];
3153
3154 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
9ccd8c1f 3155 &rx_buffer->map);
87307ba1 3156 if (error) {
9c80d176
SZ
3157 device_printf(dev, "Unable to create RX DMA map\n");
3158 em_destroy_rx_ring(adapter, i);
3159 return error;
9ccd8c1f 3160 }
984263bc 3161 }
87307ba1 3162 return (0);
984263bc
MD
3163}
3164
984263bc 3165static int
9c80d176 3166em_init_rx_ring(struct adapter *adapter)
984263bc 3167{
9c80d176 3168 int i, error;
984263bc 3169
9c80d176 3170 /* Reset descriptor ring */
87307ba1 3171 bzero(adapter->rx_desc_base,
9c80d176 3172 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
87307ba1 3173
9c80d176
SZ
3174 /* Allocate new ones. */
3175 for (i = 0; i < adapter->num_rx_desc; i++) {
3176 error = em_newbuf(adapter, i, 1);
3177 if (error)
3178 return (error);
3179 }
984263bc
MD
3180
3181 /* Setup our descriptor pointers */
f647ad3d 3182 adapter->next_rx_desc_to_check = 0;
87307ba1
SZ
3183
3184 return (0);
984263bc
MD
3185}
3186
984263bc 3187static void
9c80d176 3188em_init_rx_unit(struct adapter *adapter)
984263bc 3189{
9c80d176 3190 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 3191 uint64_t bus_addr;
2d0e5700 3192 uint32_t rctl;
984263bc 3193
87307ba1
SZ
3194 /*
3195 * Make sure receives are disabled while setting
3196 * up the descriptor ring
3197 */
9c80d176
SZ
3198 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3199 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
984263bc 3200
9c80d176 3201 if (adapter->hw.mac.type >= e1000_82540) {
2d0e5700
SZ
3202 uint32_t itr;
3203
9c80d176
SZ
3204 /*
3205 * Set the interrupt throttling rate. Value is calculated
3206 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3207 */
2d0e5700
SZ
3208 if (adapter->int_throttle_ceil)
3209 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3210 else
3211 itr = 0;
3212 em_set_itr(adapter, itr);
f647ad3d 3213 }
984263bc 3214
9c80d176
SZ
3215 /* Disable accelerated ackknowledge */
3216 if (adapter->hw.mac.type == e1000_82574) {
3217 E1000_WRITE_REG(&adapter->hw,
3218 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3219 }
3220
2d0e5700
SZ
3221 /* Receive Checksum Offload for TCP and UDP */
3222 if (ifp->if_capenable & IFCAP_RXCSUM) {
3223 uint32_t rxcsum;
3224
3225 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3226 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3227 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3228 }
3229
3230 /*
3231 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3232 * long latencies are observed, like Lenovo X60. This
3233 * change eliminates the problem, but since having positive
3234 * values in RDTR is a known source of problems on other
3235 * platforms another solution is being sought.
3236 */
3237 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3238 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3239 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3240 }
3241
3242 /*
3243 * Setup the Base and Length of the Rx Descriptor Ring
3244 */
9ccd8c1f 3245 bus_addr = adapter->rxdma.dma_paddr;
9c80d176
SZ
3246 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3247 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3248 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3249 (uint32_t)(bus_addr >> 32));
3250 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3251 (uint32_t)bus_addr);
984263bc 3252
2d0e5700
SZ
3253 /*
3254 * Setup the HW Rx Head and Tail Descriptor Pointers
3255 */
3256 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3257 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3258
3259 /* Set early receive threshold on appropriate hw */
3260 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3261 (adapter->hw.mac.type == e1000_pch2lan) ||
3262 (adapter->hw.mac.type == e1000_ich10lan)) &&
3263 (ifp->if_mtu > ETHERMTU)) {
3264 uint32_t rxdctl;