MP Implmentation 3/4: MAJOR progress on SMP, full userland MP is now working!
[dragonfly.git] / sys / platform / pc32 / isa / npx.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
a2a5ad0d 36 * $DragonFly: src/sys/platform/pc32/isa/npx.c,v 1.9 2003/07/10 04:47:54 dillon Exp $
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37 */
38
39#include "opt_cpu.h"
40#include "opt_debug_npx.h"
41#include "opt_math_emulate.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/bus.h>
46#include <sys/kernel.h>
47#include <sys/malloc.h>
48#include <sys/module.h>
49#include <sys/sysctl.h>
50#include <sys/proc.h>
51#include <machine/bus.h>
52#include <sys/rman.h>
53#ifdef NPX_DEBUG
54#include <sys/syslog.h>
55#endif
56#include <sys/signalvar.h>
57
58#ifndef SMP
59#include <machine/asmacros.h>
60#endif
61#include <machine/cputypes.h>
62#include <machine/frame.h>
63#include <machine/ipl.h>
64#include <machine/md_var.h>
65#include <machine/pcb.h>
66#include <machine/psl.h>
67#ifndef SMP
68#include <machine/clock.h>
69#endif
70#include <machine/resource.h>
71#include <machine/specialreg.h>
72#include <machine/segments.h>
85100692 73#include <machine/globaldata.h>
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74
75#ifndef SMP
76#include <i386/isa/icu.h>
77#include <i386/isa/intr_machdep.h>
78#include <i386/isa/isa.h>
79#endif
80
81/*
82 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
83 */
84
85/* Configuration flags. */
86#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
87#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
88#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
89#define NPX_PREFER_EMULATOR (1 << 3)
90
91#ifdef __GNUC__
92
93#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
94#define fnclex() __asm("fnclex")
95#define fninit() __asm("fninit")
96#define fnop() __asm("fnop")
97#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
98#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
99#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
100#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
101#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
102#ifdef CPU_ENABLE_SSE
103#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
104#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
105#endif
106#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
107 : : "n" (CR0_TS) : "ax")
108#define stop_emulating() __asm("clts")
109
110#else /* not __GNUC__ */
111
112void fldcw __P((caddr_t addr));
113void fnclex __P((void));
114void fninit __P((void));
115void fnop __P((void));
116void fnsave __P((caddr_t addr));
117void fnstcw __P((caddr_t addr));
118void fnstsw __P((caddr_t addr));
119void fp_divide_by_0 __P((void));
120void frstor __P((caddr_t addr));
121#ifdef CPU_ENABLE_SSE
122void fxsave __P((caddr_t addr));
123void fxrstor __P((caddr_t addr));
124#endif
125void start_emulating __P((void));
126void stop_emulating __P((void));
127
128#endif /* __GNUC__ */
129
130#ifdef CPU_ENABLE_SSE
131#define GET_FPU_EXSW_PTR(pcb) \
132 (cpu_fxsr ? \
133 &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \
134 &(pcb)->pcb_save.sv_87.sv_ex_sw)
135#else /* CPU_ENABLE_SSE */
136#define GET_FPU_EXSW_PTR(pcb) \
137 (&(pcb)->pcb_save.sv_87.sv_ex_sw)
138#endif /* CPU_ENABLE_SSE */
139
140typedef u_char bool_t;
141
142static int npx_attach __P((device_t dev));
143 void npx_intr __P((void *));
144static void npx_identify __P((driver_t *driver, device_t parent));
145static int npx_probe __P((device_t dev));
146static int npx_probe1 __P((device_t dev));
147static void fpusave __P((union savefpu *));
148static void fpurstor __P((union savefpu *));
149#ifdef I586_CPU
150static long timezero __P((const char *funcname,
151 void (*func)(void *buf, size_t len)));
152#endif /* I586_CPU */
153
154int hw_float; /* XXX currently just alias for npx_exists */
155
156SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
157 CTLFLAG_RD, &hw_float, 0,
158 "Floatingpoint instructions executed in hardware");
159
160#ifndef SMP
161static u_int npx0_imask = SWI_CLOCK_MASK;
162static struct gate_descriptor npx_idt_probeintr;
163static int npx_intrno;
164static volatile u_int npx_intrs_while_probing;
165static volatile u_int npx_traps_while_probing;
166#endif
167
168static bool_t npx_ex16;
169static bool_t npx_exists;
170static bool_t npx_irq13;
171static int npx_irq; /* irq number */
172
173#ifndef SMP
174/*
175 * Special interrupt handlers. Someday intr0-intr15 will be used to count
176 * interrupts. We'll still need a special exception 16 handler. The busy
177 * latch stuff in probeintr() can be moved to npxprobe().
178 */
179inthand_t probeintr;
180__asm(" \n\
181 .text \n\
182 .p2align 2,0x90 \n\
183 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
184" __XSTRING(CNAME(probeintr)) ": \n\
185 ss \n\
186 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
187 pushl %eax \n\
188 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
189 outb %al,$0xa0 # IO_ICU2 \n\
190 outb %al,$0x20 # IO_ICU1 \n\
191 movb $0,%al \n\
192 outb %al,$0xf0 # clear BUSY# latch \n\
193 popl %eax \n\
194 iret \n\
195");
196
197inthand_t probetrap;
198__asm(" \n\
199 .text \n\
200 .p2align 2,0x90 \n\
201 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
202" __XSTRING(CNAME(probetrap)) ": \n\
203 ss \n\
204 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
205 fnclex \n\
206 iret \n\
207");
208#endif /* SMP */
209
210/*
211 * Identify routine. Create a connection point on our parent for probing.
212 */
213static void
214npx_identify(driver, parent)
215 driver_t *driver;
216 device_t parent;
217{
218 device_t child;
219
220 child = BUS_ADD_CHILD(parent, 0, "npx", 0);
221 if (child == NULL)
222 panic("npx_identify");
223}
224
225/*
226 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
227 * whether the device exists or not (XXX should be elsewhere). Set flags
228 * to tell npxattach() what to do. Modify device struct if npx doesn't
229 * need to use interrupts. Return 1 if device exists.
230 */
231static int
232npx_probe(dev)
233 device_t dev;
234{
235#ifdef SMP
236
237 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
238 npx_irq = 13;
239 return npx_probe1(dev);
240
241#else /* SMP */
242
243 int result;
244 u_long save_eflags;
245 u_char save_icu1_mask;
246 u_char save_icu2_mask;
247 struct gate_descriptor save_idt_npxintr;
248 struct gate_descriptor save_idt_npxtrap;
249 /*
250 * This routine is now just a wrapper for npxprobe1(), to install
251 * special npx interrupt and trap handlers, to enable npx interrupts
252 * and to disable other interrupts. Someday isa_configure() will
253 * install suitable handlers and run with interrupts enabled so we
254 * won't need to do so much here.
255 */
256 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
257 npx_irq = 13;
258 npx_intrno = NRSVIDT + npx_irq;
259 save_eflags = read_eflags();
8a8d5d85 260 cpu_disable_intr();
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261 save_icu1_mask = inb(IO_ICU1 + 1);
262 save_icu2_mask = inb(IO_ICU2 + 1);
263 save_idt_npxintr = idt[npx_intrno];
264 save_idt_npxtrap = idt[16];
265 outb(IO_ICU1 + 1, ~IRQ_SLAVE);
266 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
267 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
268 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
269 npx_idt_probeintr = idt[npx_intrno];
8a8d5d85 270 cpu_enable_intr();
984263bc 271 result = npx_probe1(dev);
8a8d5d85 272 cpu_disable_intr();
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273 outb(IO_ICU1 + 1, save_icu1_mask);
274 outb(IO_ICU2 + 1, save_icu2_mask);
275 idt[npx_intrno] = save_idt_npxintr;
276 idt[16] = save_idt_npxtrap;
277 write_eflags(save_eflags);
278 return (result);
279
280#endif /* SMP */
281}
282
283static int
284npx_probe1(dev)
285 device_t dev;
286{
287#ifndef SMP
288 u_short control;
289 u_short status;
290#endif
291
292 /*
293 * Partially reset the coprocessor, if any. Some BIOS's don't reset
294 * it after a warm boot.
295 */
296 outb(0xf1, 0); /* full reset on some systems, NOP on others */
297 outb(0xf0, 0); /* clear BUSY# latch */
298 /*
299 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
300 * instructions. We must set the CR0_MP bit and use the CR0_TS
301 * bit to control the trap, because setting the CR0_EM bit does
302 * not cause WAIT instructions to trap. It's important to trap
303 * WAIT instructions - otherwise the "wait" variants of no-wait
304 * control instructions would degenerate to the "no-wait" variants
305 * after FP context switches but work correctly otherwise. It's
306 * particularly important to trap WAITs when there is no NPX -
307 * otherwise the "wait" variants would always degenerate.
308 *
309 * Try setting CR0_NE to get correct error reporting on 486DX's.
310 * Setting it should fail or do nothing on lesser processors.
311 */
312 load_cr0(rcr0() | CR0_MP | CR0_NE);
313 /*
314 * But don't trap while we're probing.
315 */
316 stop_emulating();
317 /*
318 * Finish resetting the coprocessor, if any. If there is an error
319 * pending, then we may get a bogus IRQ13, but probeintr() will handle
320 * it OK. Bogus halts have never been observed, but we enabled
321 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
322 */
323 fninit();
324
325#ifdef SMP
326 /*
327 * Exception 16 MUST work for SMP.
328 */
329 npx_irq13 = 0;
330 npx_ex16 = hw_float = npx_exists = 1;
331 device_set_desc(dev, "math processor");
332 return (0);
333
334#else /* !SMP */
335 device_set_desc(dev, "math processor");
336
337 /*
338 * Don't use fwait here because it might hang.
339 * Don't use fnop here because it usually hangs if there is no FPU.
340 */
341 DELAY(1000); /* wait for any IRQ13 */
342#ifdef DIAGNOSTIC
343 if (npx_intrs_while_probing != 0)
344 printf("fninit caused %u bogus npx interrupt(s)\n",
345 npx_intrs_while_probing);
346 if (npx_traps_while_probing != 0)
347 printf("fninit caused %u bogus npx trap(s)\n",
348 npx_traps_while_probing);
349#endif
350 /*
351 * Check for a status of mostly zero.
352 */
353 status = 0x5a5a;
354 fnstsw(&status);
355 if ((status & 0xb8ff) == 0) {
356 /*
357 * Good, now check for a proper control word.
358 */
359 control = 0x5a5a;
360 fnstcw(&control);
361 if ((control & 0x1f3f) == 0x033f) {
362 hw_float = npx_exists = 1;
363 /*
364 * We have an npx, now divide by 0 to see if exception
365 * 16 works.
366 */
367 control &= ~(1 << 2); /* enable divide by 0 trap */
368 fldcw(&control);
369 npx_traps_while_probing = npx_intrs_while_probing = 0;
370 fp_divide_by_0();
371 if (npx_traps_while_probing != 0) {
372 /*
373 * Good, exception 16 works.
374 */
375 npx_ex16 = 1;
376 return (0);
377 }
378 if (npx_intrs_while_probing != 0) {
379 int rid;
380 struct resource *r;
381 void *intr;
382 /*
383 * Bad, we are stuck with IRQ13.
384 */
385 npx_irq13 = 1;
386 /*
387 * npxattach would be too late to set npx0_imask
388 */
389 npx0_imask |= (1 << npx_irq);
390
391 /*
392 * We allocate these resources permanently,
393 * so there is no need to keep track of them.
394 */
395 rid = 0;
396 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
397 &rid, IO_NPX, IO_NPX,
398 IO_NPXSIZE, RF_ACTIVE);
399 if (r == 0)
400 panic("npx: can't get ports");
401 rid = 0;
402 r = bus_alloc_resource(dev, SYS_RES_IRQ,
403 &rid, npx_irq, npx_irq,
404 1, RF_ACTIVE);
405 if (r == 0)
406 panic("npx: can't get IRQ");
407 BUS_SETUP_INTR(device_get_parent(dev),
408 dev, r, INTR_TYPE_MISC,
409 npx_intr, 0, &intr);
410 if (intr == 0)
411 panic("npx: can't create intr");
412
413 return (0);
414 }
415 /*
416 * Worse, even IRQ13 is broken. Use emulator.
417 */
418 }
419 }
420 /*
421 * Probe failed, but we want to get to npxattach to initialize the
422 * emulator and say that it has been installed. XXX handle devices
423 * that aren't really devices better.
424 */
425 return (0);
426#endif /* SMP */
427}
428
429/*
430 * Attach routine - announce which it is, and wire into system
431 */
432int
433npx_attach(dev)
434 device_t dev;
435{
436 int flags;
437
438 if (resource_int_value("npx", 0, "flags", &flags) != 0)
439 flags = 0;
440
441 if (flags)
442 device_printf(dev, "flags 0x%x ", flags);
443 if (npx_irq13) {
444 device_printf(dev, "using IRQ 13 interface\n");
445 } else {
446#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE)
447 if (npx_ex16) {
448 if (!(flags & NPX_PREFER_EMULATOR))
449 device_printf(dev, "INT 16 interface\n");
450 else {
451 device_printf(dev, "FPU exists, but flags request "
452 "emulator\n");
453 hw_float = npx_exists = 0;
454 }
455 } else if (npx_exists) {
456 device_printf(dev, "error reporting broken; using 387 emulator\n");
457 hw_float = npx_exists = 0;
458 } else
459 device_printf(dev, "387 emulator\n");
460#else
461 if (npx_ex16) {
462 device_printf(dev, "INT 16 interface\n");
463 if (flags & NPX_PREFER_EMULATOR) {
464 device_printf(dev, "emulator requested, but none compiled "
465 "into kernel, using FPU\n");
466 }
467 } else
468 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
469#endif
470 }
471 npxinit(__INITIAL_NPXCW__);
472
473#ifdef I586_CPU
474 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
475 timezero("i586_bzero()", i586_bzero) <
476 timezero("bzero()", bzero) * 4 / 5) {
477 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
478 bcopy_vector = i586_bcopy;
479 ovbcopy_vector = i586_bcopy;
480 }
481 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
482 bzero = i586_bzero;
483 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
484 copyin_vector = i586_copyin;
485 copyout_vector = i586_copyout;
486 }
487 }
488#endif
489
490 return (0); /* XXX unused */
491}
492
493/*
494 * Initialize floating point unit.
495 */
496void
497npxinit(control)
498 u_short control;
499{
500 static union savefpu dummy;
501
502 if (!npx_exists)
503 return;
504 /*
505 * fninit has the same h/w bugs as fnsave. Use the detoxified
506 * fnsave to throw away any junk in the fpu. npxsave() initializes
af0bff84 507 * the fpu and sets npxthread = NULL as important side effects.
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508 */
509 npxsave(&dummy);
510 stop_emulating();
511#ifdef CPU_ENABLE_SSE
512 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
513 if (cpu_fxsr)
514 fninit();
515#endif
516 fldcw(&control);
b7c628e4 517 fpusave(&curthread->td_pcb->pcb_save);
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518 start_emulating();
519}
520
521/*
522 * Free coprocessor (if we have it).
523 */
524void
85100692 525npxexit(struct proc *p)
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526{
527
a2a5ad0d 528 if (p->p_thread == mdcpu->gd_npxthread)
b7c628e4 529 npxsave(&curthread->td_pcb->pcb_save);
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530#ifdef NPX_DEBUG
531 if (npx_exists) {
532 u_int masked_exceptions;
533
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534 masked_exceptions =
535 curthread->td_pcb->pcb_save.sv_87.sv_env.en_cw
536 & curthread->td_pcb->pcb_save.sv_87.sv_env.en_sw & 0x7f;
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537 /*
538 * Log exceptions that would have trapped with the old
539 * control word (overflow, divide by 0, and invalid operand).
540 */
541 if (masked_exceptions & 0x0d)
542 log(LOG_ERR,
543 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
544 p->p_pid, p->p_comm, masked_exceptions);
545 }
546#endif
547}
548
549/*
550 * The following mechanism is used to ensure that the FPE_... value
551 * that is passed as a trapcode to the signal handler of the user
552 * process does not have more than one bit set.
553 *
554 * Multiple bits may be set if the user process modifies the control
555 * word while a status word bit is already set. While this is a sign
556 * of bad coding, we have no choise than to narrow them down to one
557 * bit, since we must not send a trapcode that is not exactly one of
558 * the FPE_ macros.
559 *
560 * The mechanism has a static table with 127 entries. Each combination
561 * of the 7 FPU status word exception bits directly translates to a
562 * position in this table, where a single FPE_... value is stored.
563 * This FPE_... value stored there is considered the "most important"
564 * of the exception bits and will be sent as the signal code. The
565 * precedence of the bits is based upon Intel Document "Numerical
566 * Applications", Chapter "Special Computational Situations".
567 *
568 * The macro to choose one of these values does these steps: 1) Throw
569 * away status word bits that cannot be masked. 2) Throw away the bits
570 * currently masked in the control word, assuming the user isn't
571 * interested in them anymore. 3) Reinsert status word bit 7 (stack
572 * fault) if it is set, which cannot be masked but must be presered.
573 * 4) Use the remaining bits to point into the trapcode table.
574 *
575 * The 6 maskable bits in order of their preference, as stated in the
576 * above referenced Intel manual:
577 * 1 Invalid operation (FP_X_INV)
578 * 1a Stack underflow
579 * 1b Stack overflow
580 * 1c Operand of unsupported format
581 * 1d SNaN operand.
582 * 2 QNaN operand (not an exception, irrelavant here)
583 * 3 Any other invalid-operation not mentioned above or zero divide
584 * (FP_X_INV, FP_X_DZ)
585 * 4 Denormal operand (FP_X_DNML)
586 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
587 * 6 Inexact result (FP_X_IMP)
588 */
589static char fpetable[128] = {
590 0,
591 FPE_FLTINV, /* 1 - INV */
592 FPE_FLTUND, /* 2 - DNML */
593 FPE_FLTINV, /* 3 - INV | DNML */
594 FPE_FLTDIV, /* 4 - DZ */
595 FPE_FLTINV, /* 5 - INV | DZ */
596 FPE_FLTDIV, /* 6 - DNML | DZ */
597 FPE_FLTINV, /* 7 - INV | DNML | DZ */
598 FPE_FLTOVF, /* 8 - OFL */
599 FPE_FLTINV, /* 9 - INV | OFL */
600 FPE_FLTUND, /* A - DNML | OFL */
601 FPE_FLTINV, /* B - INV | DNML | OFL */
602 FPE_FLTDIV, /* C - DZ | OFL */
603 FPE_FLTINV, /* D - INV | DZ | OFL */
604 FPE_FLTDIV, /* E - DNML | DZ | OFL */
605 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
606 FPE_FLTUND, /* 10 - UFL */
607 FPE_FLTINV, /* 11 - INV | UFL */
608 FPE_FLTUND, /* 12 - DNML | UFL */
609 FPE_FLTINV, /* 13 - INV | DNML | UFL */
610 FPE_FLTDIV, /* 14 - DZ | UFL */
611 FPE_FLTINV, /* 15 - INV | DZ | UFL */
612 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
613 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
614 FPE_FLTOVF, /* 18 - OFL | UFL */
615 FPE_FLTINV, /* 19 - INV | OFL | UFL */
616 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
617 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
618 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
619 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
620 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
621 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
622 FPE_FLTRES, /* 20 - IMP */
623 FPE_FLTINV, /* 21 - INV | IMP */
624 FPE_FLTUND, /* 22 - DNML | IMP */
625 FPE_FLTINV, /* 23 - INV | DNML | IMP */
626 FPE_FLTDIV, /* 24 - DZ | IMP */
627 FPE_FLTINV, /* 25 - INV | DZ | IMP */
628 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
629 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
630 FPE_FLTOVF, /* 28 - OFL | IMP */
631 FPE_FLTINV, /* 29 - INV | OFL | IMP */
632 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
633 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
634 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
635 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
636 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
637 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
638 FPE_FLTUND, /* 30 - UFL | IMP */
639 FPE_FLTINV, /* 31 - INV | UFL | IMP */
640 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
641 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
642 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
643 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
644 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
645 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
646 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
647 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
648 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
649 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
650 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
651 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
652 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
653 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
654 FPE_FLTSUB, /* 40 - STK */
655 FPE_FLTSUB, /* 41 - INV | STK */
656 FPE_FLTUND, /* 42 - DNML | STK */
657 FPE_FLTSUB, /* 43 - INV | DNML | STK */
658 FPE_FLTDIV, /* 44 - DZ | STK */
659 FPE_FLTSUB, /* 45 - INV | DZ | STK */
660 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
661 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
662 FPE_FLTOVF, /* 48 - OFL | STK */
663 FPE_FLTSUB, /* 49 - INV | OFL | STK */
664 FPE_FLTUND, /* 4A - DNML | OFL | STK */
665 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
666 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
667 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
668 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
669 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
670 FPE_FLTUND, /* 50 - UFL | STK */
671 FPE_FLTSUB, /* 51 - INV | UFL | STK */
672 FPE_FLTUND, /* 52 - DNML | UFL | STK */
673 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
674 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
675 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
676 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
677 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
678 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
679 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
680 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
681 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
682 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
683 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
684 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
685 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
686 FPE_FLTRES, /* 60 - IMP | STK */
687 FPE_FLTSUB, /* 61 - INV | IMP | STK */
688 FPE_FLTUND, /* 62 - DNML | IMP | STK */
689 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
690 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
691 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
692 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
693 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
694 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
695 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
696 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
697 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
698 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
699 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
700 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
701 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
702 FPE_FLTUND, /* 70 - UFL | IMP | STK */
703 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
704 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
705 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
706 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
707 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
708 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
709 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
710 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
711 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
712 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
713 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
714 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
715 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
716 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
717 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
718};
719
720/*
721 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
722 *
723 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
724 * depend on longjmp() restoring a usable state. Restoring the state
725 * or examining it might fail if we didn't clear exceptions.
726 *
727 * The error code chosen will be one of the FPE_... macros. It will be
728 * sent as the second argument to old BSD-style signal handlers and as
729 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
730 *
731 * XXX the FP state is not preserved across signal handlers. So signal
732 * handlers cannot afford to do FP unless they preserve the state or
733 * longjmp() out. Both preserving the state and longjmp()ing may be
734 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
735 * solution for signals other than SIGFPE.
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736 *
737 * The MP lock is not held on entry (see i386/i386/exception.s) and
738 * should not be held on exit.
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739 */
740void
741npx_intr(dummy)
742 void *dummy;
743{
744 int code;
745 u_short control;
746 struct intrframe *frame;
747 u_long *exstat;
748
a2a5ad0d 749 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
8a8d5d85 750 get_mplock();
af0bff84 751 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 752 mdcpu->gd_npxthread, curthread, npx_exists);
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753 panic("npxintr from nowhere");
754 }
a2a5ad0d 755 if (mdcpu->gd_npxthread != curthread) {
8a8d5d85 756 get_mplock();
af0bff84 757 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 758 mdcpu->gd_npxthread, curthread, npx_exists);
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759 panic("npxintr from non-current process");
760 }
761
b7c628e4 762 exstat = GET_FPU_EXSW_PTR(curthread->td_pcb);
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763 outb(0xf0, 0);
764 fnstsw(exstat);
765 fnstcw(&control);
766 fnclex();
767
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768 get_mplock();
769
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770 /*
771 * Pass exception to process.
772 */
773 frame = (struct intrframe *)&dummy; /* XXX */
774 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
775 /*
776 * Interrupt is essentially a trap, so we can afford to call
777 * the SIGFPE handler (if any) as soon as the interrupt
778 * returns.
779 *
780 * XXX little or nothing is gained from this, and plenty is
781 * lost - the interrupt frame has to contain the trap frame
782 * (this is otherwise only necessary for the rescheduling trap
783 * in doreti, and the frame for that could easily be set up
784 * just before it is used).
785 */
786 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
787 /*
788 * Encode the appropriate code for detailed information on
789 * this exception.
790 */
791 code =
792 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
793 trapsignal(curproc, SIGFPE, code);
794 } else {
795 /*
796 * Nested interrupt. These losers occur when:
797 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
798 * o immediately after an fnsave or frstor of an
799 * error state.
800 * o a couple of 386 instructions after
801 * "fstpl _memvar" causes a stack overflow.
802 * These are especially nasty when combined with a
803 * trace trap.
804 * o an IRQ13 occurs at the same time as another higher-
805 * priority interrupt.
806 *
807 * Treat them like a true async interrupt.
808 */
809 psignal(curproc, SIGFPE);
810 }
8a8d5d85 811 rel_mplock();
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812}
813
814/*
815 * Implement device not available (DNA) exception
816 *
af0bff84 817 * It would be better to switch FP context here (if curthread != npxthread)
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818 * and not necessarily for every context switch, but it is too hard to
819 * access foreign pcb's.
820 */
821int
822npxdna()
823{
824 u_long *exstat;
825
826 if (!npx_exists)
827 return (0);
a2a5ad0d 828 if (mdcpu->gd_npxthread != NULL) {
af0bff84 829 printf("npxdna: npxthread = %p, curthread = %p\n",
a2a5ad0d 830 mdcpu->gd_npxthread, curthread);
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831 panic("npxdna");
832 }
833 stop_emulating();
834 /*
835 * Record new context early in case frstor causes an IRQ13.
836 */
a2a5ad0d 837 mdcpu->gd_npxthread = curthread;
b7c628e4 838 exstat = GET_FPU_EXSW_PTR(curthread->td_pcb);
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839 *exstat = 0;
840 /*
841 * The following frstor may cause an IRQ13 when the state being
842 * restored has a pending error. The error will appear to have been
843 * triggered by the current (npx) user instruction even when that
844 * instruction is a no-wait instruction that should not trigger an
845 * error (e.g., fnclex). On at least one 486 system all of the
846 * no-wait instructions are broken the same as frstor, so our
847 * treatment does not amplify the breakage. On at least one
848 * 386/Cyrix 387 system, fnclex works correctly while frstor and
849 * fnsave are broken, so our treatment breaks fnclex if it is the
850 * first FPU instruction after a context switch.
851 */
b7c628e4 852 fpurstor(&curthread->td_pcb->pcb_save);
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853
854 return (1);
855}
856
857/*
858 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error
859 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
860 * any IRQ13 to be handled immediately, and then ignore it. This routine is
861 * often called at splhigh so it must not use many system services. In
862 * particular, it's much easier to install a special handler than to
863 * guarantee that it's safe to use npxintr() and its supporting code.
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864 *
865 * WARNING! This call is made during a switch and the MP lock will be
866 * setup for the new target thread rather then the current thread, so we
867 * cannot do anything here that depends on the *_mplock() functions as
868 * we may trip over their assertions.
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869 */
870void
871npxsave(addr)
872 union savefpu *addr;
873{
874#if defined(SMP) || defined(CPU_ENABLE_SSE)
875
876 stop_emulating();
877 fpusave(addr);
878
879 /* fnop(); */
880 start_emulating();
a2a5ad0d 881 mdcpu->gd_npxthread = NULL;
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882
883#else /* SMP or CPU_ENABLE_SSE */
884
885 u_char icu1_mask;
886 u_char icu2_mask;
887 u_char old_icu1_mask;
888 u_char old_icu2_mask;
889 struct gate_descriptor save_idt_npxintr;
8a8d5d85 890 u_long save_eflags;
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892 save_eflags = read_eflags();
893 cpu_disable_intr();
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894 old_icu1_mask = inb(IO_ICU1 + 1);
895 old_icu2_mask = inb(IO_ICU2 + 1);
896 save_idt_npxintr = idt[npx_intrno];
897 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
898 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
899 idt[npx_intrno] = npx_idt_probeintr;
8a8d5d85 900 cpu_enable_intr();
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901 stop_emulating();
902 fnsave(addr);
903 fnop();
904 start_emulating();
a2a5ad0d 905 mdcpu->gd_npxthread = NULL;
8a8d5d85 906 cpu_disable_intr();
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907 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
908 icu2_mask = inb(IO_ICU2 + 1);
909 outb(IO_ICU1 + 1,
910 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
911 outb(IO_ICU2 + 1,
912 (icu2_mask & ~(npx0_imask >> 8))
913 | (old_icu2_mask & (npx0_imask >> 8)));
914 idt[npx_intrno] = save_idt_npxintr;
8a8d5d85 915 write_eflags(save_eflags); /* back to usual state */
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916
917#endif /* SMP */
918}
919
920static void
921fpusave(addr)
922 union savefpu *addr;
923{
924
925#ifdef CPU_ENABLE_SSE
926 if (cpu_fxsr)
927 fxsave(addr);
928 else
929#endif
930 fnsave(addr);
931}
932
933static void
934fpurstor(addr)
935 union savefpu *addr;
936{
937
938#ifdef CPU_ENABLE_SSE
939 if (cpu_fxsr)
940 fxrstor(addr);
941 else
942#endif
943 frstor(addr);
944}
945
946#ifdef I586_CPU
947static long
948timezero(funcname, func)
949 const char *funcname;
950 void (*func) __P((void *buf, size_t len));
951
952{
953 void *buf;
954#define BUFSIZE 1000000
955 long usec;
956 struct timeval finish, start;
957
958 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
959 if (buf == NULL)
960 return (BUFSIZE);
961 microtime(&start);
962 (*func)(buf, BUFSIZE);
963 microtime(&finish);
964 usec = 1000000 * (finish.tv_sec - start.tv_sec) +
965 finish.tv_usec - start.tv_usec;
966 if (usec <= 0)
967 usec = 1;
968 if (bootverbose)
969 printf("%s bandwidth = %ld bytes/sec\n",
970 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec));
971 free(buf, M_TEMP);
972 return (usec);
973}
974#endif /* I586_CPU */
975
976static device_method_t npx_methods[] = {
977 /* Device interface */
978 DEVMETHOD(device_identify, npx_identify),
979 DEVMETHOD(device_probe, npx_probe),
980 DEVMETHOD(device_attach, npx_attach),
981 DEVMETHOD(device_detach, bus_generic_detach),
982 DEVMETHOD(device_shutdown, bus_generic_shutdown),
983 DEVMETHOD(device_suspend, bus_generic_suspend),
984 DEVMETHOD(device_resume, bus_generic_resume),
985
986 { 0, 0 }
987};
988
989static driver_t npx_driver = {
990 "npx",
991 npx_methods,
992 1, /* no softc */
993};
994
995static devclass_t npx_devclass;
996
997/*
998 * We prefer to attach to the root nexus so that the usual case (exception 16)
999 * doesn't describe the processor as being `on isa'.
1000 */
1001DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);