em/emx: Update comment concerning errata number
[dragonfly.git] / sys / dev / netif / em / if_em.c
CommitLineData
78195a76 1/*
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2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
9c80d176 4 * Copyright (c) 2001-2008, Intel Corporation
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5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9c80d176 9 *
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10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
9c80d176 12 *
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13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
9c80d176 16 *
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17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
9c80d176 20 *
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
9c80d176 35 *
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36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
9c80d176 38 *
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39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
9c80d176 42 *
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43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
9c80d176 52 *
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53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
9c80d176 65 *
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66 */
67/*
68 * SERIALIZATION API RULES:
69 *
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
9c80d176 72 * driver.
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73 *
74 * - ifmedia entry points will be serialized by the ifmedia code using the
75 * ifnet serializer.
76 *
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
79 *
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
82 *
83 * - The device driver typically holds the serializer at the time it wishes
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84 * to call if_input.
85 *
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
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90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
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95
96#include "opt_polling.h"
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97
98#include <sys/param.h>
99#include <sys/bus.h>
100#include <sys/endian.h>
9db4b353 101#include <sys/interrupt.h>
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102#include <sys/kernel.h>
103#include <sys/ktr.h>
104#include <sys/malloc.h>
105#include <sys/mbuf.h>
9c80d176 106#include <sys/proc.h>
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107#include <sys/rman.h>
108#include <sys/serialize.h>
109#include <sys/socket.h>
110#include <sys/sockio.h>
111#include <sys/sysctl.h>
9c80d176 112#include <sys/systm.h>
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113
114#include <net/bpf.h>
115#include <net/ethernet.h>
116#include <net/if.h>
117#include <net/if_arp.h>
118#include <net/if_dl.h>
119#include <net/if_media.h>
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120#include <net/ifq_var.h>
121#include <net/vlan/if_vlan_var.h>
b637f170 122#include <net/vlan/if_vlan_ether.h>
87307ba1 123
87307ba1 124#include <netinet/in_systm.h>
9c80d176 125#include <netinet/in.h>
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126#include <netinet/ip.h>
127#include <netinet/tcp.h>
128#include <netinet/udp.h>
984263bc 129
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130#include <bus/pci/pcivar.h>
131#include <bus/pci/pcireg.h>
984263bc 132
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133#include <dev/netif/ig_hal/e1000_api.h>
134#include <dev/netif/ig_hal/e1000_82571.h>
135#include <dev/netif/em/if_em.h>
984263bc 136
9c80d176 137#define EM_NAME "Intel(R) PRO/1000 Network Connection "
6d5e2922 138#define EM_VER " 7.2.4"
9c80d176 139
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140#define _EM_DEVICE(id, ret) \
141 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
142#define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
143#define EM_DEVICE(id) _EM_DEVICE(id, 0)
144#define EM_DEVICE_NULL { 0, 0, 0, NULL }
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145
146static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM),
148 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP),
150 EM_DEVICE(82540EP_LOM),
151 EM_DEVICE(82540EP_LP),
152
153 EM_DEVICE(82541EI),
154 EM_DEVICE(82541ER),
155 EM_DEVICE(82541ER_LOM),
156 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI),
158 EM_DEVICE(82541GI_LF),
159 EM_DEVICE(82541GI_MOBILE),
160
161 EM_DEVICE(82542),
162
163 EM_DEVICE(82543GC_FIBER),
164 EM_DEVICE(82543GC_COPPER),
165
166 EM_DEVICE(82544EI_COPPER),
167 EM_DEVICE(82544EI_FIBER),
168 EM_DEVICE(82544GC_COPPER),
169 EM_DEVICE(82544GC_LOM),
170
171 EM_DEVICE(82545EM_COPPER),
172 EM_DEVICE(82545EM_FIBER),
173 EM_DEVICE(82545GM_COPPER),
174 EM_DEVICE(82545GM_FIBER),
175 EM_DEVICE(82545GM_SERDES),
176
177 EM_DEVICE(82546EB_COPPER),
178 EM_DEVICE(82546EB_FIBER),
179 EM_DEVICE(82546EB_QUAD_COPPER),
180 EM_DEVICE(82546GB_COPPER),
181 EM_DEVICE(82546GB_FIBER),
182 EM_DEVICE(82546GB_SERDES),
183 EM_DEVICE(82546GB_PCIE),
184 EM_DEVICE(82546GB_QUAD_COPPER),
185 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
186
187 EM_DEVICE(82547EI),
188 EM_DEVICE(82547EI_MOBILE),
189 EM_DEVICE(82547GI),
190
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191 EM_EMX_DEVICE(82571EB_COPPER),
192 EM_EMX_DEVICE(82571EB_FIBER),
193 EM_EMX_DEVICE(82571EB_SERDES),
194 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
195 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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198 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
199 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
200 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201
202 EM_EMX_DEVICE(82572EI_COPPER),
203 EM_EMX_DEVICE(82572EI_FIBER),
204 EM_EMX_DEVICE(82572EI_SERDES),
205 EM_EMX_DEVICE(82572EI),
206
207 EM_EMX_DEVICE(82573E),
208 EM_EMX_DEVICE(82573E_IAMT),
209 EM_EMX_DEVICE(82573L),
210
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211 EM_DEVICE(82583V),
212
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213 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
215 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
216 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
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217
218 EM_DEVICE(ICH8_IGP_M_AMT),
219 EM_DEVICE(ICH8_IGP_AMT),
220 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE),
222 EM_DEVICE(ICH8_IFE_GT),
223 EM_DEVICE(ICH8_IFE_G),
224 EM_DEVICE(ICH8_IGP_M),
2d0e5700 225 EM_DEVICE(ICH8_82567V_3),
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226
227 EM_DEVICE(ICH9_IGP_M_AMT),
228 EM_DEVICE(ICH9_IGP_AMT),
229 EM_DEVICE(ICH9_IGP_C),
230 EM_DEVICE(ICH9_IGP_M),
231 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE),
233 EM_DEVICE(ICH9_IFE_GT),
234 EM_DEVICE(ICH9_IFE_G),
235 EM_DEVICE(ICH9_BM),
236
96ced48a 237 EM_EMX_DEVICE(82574L),
2d0e5700 238 EM_EMX_DEVICE(82574LA),
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239
240 EM_DEVICE(ICH10_R_BM_LM),
241 EM_DEVICE(ICH10_R_BM_LF),
242 EM_DEVICE(ICH10_R_BM_V),
243 EM_DEVICE(ICH10_D_BM_LM),
244 EM_DEVICE(ICH10_D_BM_LF),
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245 EM_DEVICE(ICH10_D_BM_V),
246
247 EM_DEVICE(PCH_M_HV_LM),
248 EM_DEVICE(PCH_M_HV_LC),
249 EM_DEVICE(PCH_D_HV_DM),
250 EM_DEVICE(PCH_D_HV_DC),
251
252 EM_DEVICE(PCH2_LV_LM),
253 EM_DEVICE(PCH2_LV_V),
984263bc 254
f647ad3d 255 /* required last entry */
9c80d176 256 EM_DEVICE_NULL
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257};
258
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259static int em_probe(device_t);
260static int em_attach(device_t);
261static int em_detach(device_t);
262static int em_shutdown(device_t);
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263static int em_suspend(device_t);
264static int em_resume(device_t);
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265
266static void em_init(void *);
267static void em_stop(struct adapter *);
f647ad3d 268static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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269static void em_start(struct ifnet *);
270#ifdef DEVICE_POLLING
271static void em_poll(struct ifnet *, enum poll_cmd, int);
272#endif
f647ad3d 273static void em_watchdog(struct ifnet *);
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274static void em_media_status(struct ifnet *, struct ifmediareq *);
275static int em_media_change(struct ifnet *);
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276static void em_timer(void *);
277
278static void em_intr(void *);
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279static void em_intr_mask(void *);
280static void em_intr_body(struct adapter *, boolean_t);
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281static void em_rxeof(struct adapter *, int);
282static void em_txeof(struct adapter *);
9f60d74b 283static void em_tx_collect(struct adapter *);
9c80d176 284static void em_tx_purge(struct adapter *);
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285static void em_enable_intr(struct adapter *);
286static void em_disable_intr(struct adapter *);
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287
288static int em_dma_malloc(struct adapter *, bus_size_t,
289 struct em_dma_alloc *);
290static void em_dma_free(struct adapter *, struct em_dma_alloc *);
291static void em_init_tx_ring(struct adapter *);
292static int em_init_rx_ring(struct adapter *);
293static int em_create_tx_ring(struct adapter *);
294static int em_create_rx_ring(struct adapter *);
295static void em_destroy_tx_ring(struct adapter *, int);
296static void em_destroy_rx_ring(struct adapter *, int);
297static int em_newbuf(struct adapter *, int, int);
298static int em_encap(struct adapter *, struct mbuf **);
299static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
300 struct mbuf *);
002b3a05 301static int em_txcsum_pullup(struct adapter *, struct mbuf **);
9f60d74b 302static int em_txcsum(struct adapter *, struct mbuf *,
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303 uint32_t *, uint32_t *);
304
305static int em_get_hw_info(struct adapter *);
306static int em_is_valid_eaddr(const uint8_t *);
307static int em_alloc_pci_res(struct adapter *);
308static void em_free_pci_res(struct adapter *);
2d0e5700 309static int em_reset(struct adapter *);
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310static void em_setup_ifp(struct adapter *);
311static void em_init_tx_unit(struct adapter *);
312static void em_init_rx_unit(struct adapter *);
313static void em_update_stats(struct adapter *);
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314static void em_set_promisc(struct adapter *);
315static void em_disable_promisc(struct adapter *);
316static void em_set_multi(struct adapter *);
87307ba1 317static void em_update_link_status(struct adapter *);
f647ad3d 318static void em_smartspeed(struct adapter *);
2d0e5700 319static void em_set_itr(struct adapter *, uint32_t);
6d5e2922 320static void em_disable_aspm(struct adapter *);
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321
322/* Hardware workarounds */
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323static int em_82547_fifo_workaround(struct adapter *, int);
324static void em_82547_update_fifo_head(struct adapter *, int);
325static int em_82547_tx_fifo_reset(struct adapter *);
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326static void em_82547_move_tail(void *);
327static void em_82547_move_tail_serialized(struct adapter *);
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328static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
329
f647ad3d 330static void em_print_debug_info(struct adapter *);
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331static void em_print_nvm_info(struct adapter *);
332static void em_print_hw_stats(struct adapter *);
333
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334static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
335static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
d0870c72 336static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
9f60d74b 337static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
9c80d176 338static void em_add_sysctl(struct adapter *adapter);
984263bc 339
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340/* Management and WOL Support */
341static void em_get_mgmt(struct adapter *);
342static void em_rel_mgmt(struct adapter *);
343static void em_get_hw_control(struct adapter *);
344static void em_rel_hw_control(struct adapter *);
345static void em_enable_wol(device_t);
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346
347static device_method_t em_methods[] = {
348 /* Device interface */
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349 DEVMETHOD(device_probe, em_probe),
350 DEVMETHOD(device_attach, em_attach),
351 DEVMETHOD(device_detach, em_detach),
352 DEVMETHOD(device_shutdown, em_shutdown),
353 DEVMETHOD(device_suspend, em_suspend),
354 DEVMETHOD(device_resume, em_resume),
355 { 0, 0 }
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356};
357
358static driver_t em_driver = {
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359 "em",
360 em_methods,
361 sizeof(struct adapter),
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362};
363
364static devclass_t em_devclass;
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365
366DECLARE_DUMMY_MODULE(if_em);
9c80d176 367MODULE_DEPEND(em, ig_hal, 1, 1, 1);
aa2b9d05 368DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
984263bc 369
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370/*
371 * Tunables
372 */
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373static int em_int_throttle_ceil = EM_DEFAULT_ITR;
374static int em_rxd = EM_DEFAULT_RXD;
375static int em_txd = EM_DEFAULT_TXD;
053f3ae6 376static int em_smart_pwr_down = 0;
0d366ee7 377
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378/* Controls whether promiscuous also shows bad packets */
379static int em_debug_sbp = FALSE;
0d366ee7 380
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381static int em_82573_workaround = 1;
382static int em_msi_enable = 1;
05580856 383
d0870c72 384TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
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385TUNABLE_INT("hw.em.rxd", &em_rxd);
386TUNABLE_INT("hw.em.txd", &em_txd);
387TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
9c80d176 388TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
05580856 389TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
053f3ae6 390TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
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391
392/* Global used in WOL setup with multiport cards */
393static int em_global_quad_port_a = 0;
394
395/* Set this to one to display debug statistics */
396static int em_display_debug_stats = 0;
0d366ee7 397
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398#if !defined(KTR_IF_EM)
399#define KTR_IF_EM KTR_ALL
400#endif
401KTR_INFO_MASTER(if_em);
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402KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
403KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
404KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
405KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
406KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
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407#define logif(name) KTR_LOG(if_em_ ## name)
408
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409static int
410em_probe(device_t dev)
411{
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412 const struct em_vendor_info *ent;
413 uint16_t vid, did;
984263bc 414
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415 vid = pci_get_vendor(dev);
416 did = pci_get_device(dev);
984263bc 417
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418 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
419 if (vid == ent->vendor_id && did == ent->device_id) {
420 device_set_desc(dev, ent->desc);
dbcd0c9b 421 device_set_async_attach(dev, TRUE);
96ced48a 422 return (ent->ret);
984263bc 423 }
984263bc 424 }
87307ba1 425 return (ENXIO);
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426}
427
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428static int
429em_attach(device_t dev)
430{
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431 struct adapter *adapter = device_get_softc(dev);
432 struct ifnet *ifp = &adapter->arpcom.ac_if;
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433 int tsize, rsize;
434 int error = 0;
2d0e5700 435 uint16_t eeprom_data, device_id, apme_mask;
87ab432b 436 driver_intr_t *intr_func;
984263bc 437
9c80d176 438 adapter->dev = adapter->osdep.dev = dev;
f647ad3d 439
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440 callout_init_mp(&adapter->timer);
441 callout_init_mp(&adapter->tx_fifo_timer);
af82d4bb 442
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443 /* Determine hardware and mac info */
444 error = em_get_hw_info(adapter);
445 if (error) {
446 device_printf(dev, "Identify hardware failed\n");
447 goto fail;
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448 }
449
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450 /* Setup PCI resources */
451 error = em_alloc_pci_res(adapter);
452 if (error) {
453 device_printf(dev, "Allocation of PCI resources failed\n");
454 goto fail;
455 }
984263bc 456
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457 /*
458 * For ICH8 and family we need to map the flash memory,
459 * and this must happen after the MAC is identified.
460 */
461 if (adapter->hw.mac.type == e1000_ich8lan ||
2d0e5700 462 adapter->hw.mac.type == e1000_ich9lan ||
9c80d176 463 adapter->hw.mac.type == e1000_ich10lan ||
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464 adapter->hw.mac.type == e1000_pchlan ||
465 adapter->hw.mac.type == e1000_pch2lan) {
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466 adapter->flash_rid = EM_BAR_FLASH;
467
468 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
469 &adapter->flash_rid, RF_ACTIVE);
470 if (adapter->flash == NULL) {
471 device_printf(dev, "Mapping of Flash failed\n");
472 error = ENXIO;
473 goto fail;
474 }
475 adapter->osdep.flash_bus_space_tag =
476 rman_get_bustag(adapter->flash);
477 adapter->osdep.flash_bus_space_handle =
478 rman_get_bushandle(adapter->flash);
984263bc 479
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480 /*
481 * This is used in the shared code
482 * XXX this goof is actually not used.
483 */
484 adapter->hw.flash_address = (uint8_t *)adapter->flash;
485 }
0d366ee7 486
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487 /* Do Shared Code initialization */
488 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
489 device_printf(dev, "Setup of Shared code failed\n");
490 error = ENXIO;
491 goto fail;
f647ad3d 492 }
7ea52455 493
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494 e1000_get_bus_info(&adapter->hw);
495
1eca7b82 496 /*
9c80d176 497 * Validate number of transmit and receive descriptors. It
1eca7b82 498 * must not exceed hardware maximum, and must be multiple
9c80d176 499 * of E1000_DBA_ALIGN.
1eca7b82 500 */
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501 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
502 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
503 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
504 em_txd < EM_MIN_TXD) {
1eca7b82 505 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
9c80d176 506 EM_DEFAULT_TXD, em_txd);
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507 adapter->num_tx_desc = EM_DEFAULT_TXD;
508 } else {
509 adapter->num_tx_desc = em_txd;
510 }
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511 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
512 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
513 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
514 em_rxd < EM_MIN_RXD) {
1eca7b82 515 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
9c80d176 516 EM_DEFAULT_RXD, em_rxd);
1eca7b82
SZ
517 adapter->num_rx_desc = EM_DEFAULT_RXD;
518 } else {
519 adapter->num_rx_desc = em_rxd;
520 }
521
9c80d176
SZ
522 adapter->hw.mac.autoneg = DO_AUTO_NEG;
523 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
524 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
525 adapter->rx_buffer_len = MCLBYTES;
e94c2bf4 526
9c80d176
SZ
527 /*
528 * Interrupt throttle rate
529 */
530 if (em_int_throttle_ceil == 0) {
531 adapter->int_throttle_ceil = 0;
532 } else {
533 int throttle = em_int_throttle_ceil;
f647ad3d 534
9c80d176
SZ
535 if (throttle < 0)
536 throttle = EM_DEFAULT_ITR;
0d366ee7 537
9c80d176
SZ
538 /* Recalculate the tunable value to get the exact frequency. */
539 throttle = 1000000000 / 256 / throttle;
664c7645
SZ
540
541 /* Upper 16bits of ITR is reserved and should be zero */
542 if (throttle & 0xffff0000)
543 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
544
9c80d176
SZ
545 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
546 }
984263bc 547
9c80d176
SZ
548 e1000_init_script_state_82541(&adapter->hw, TRUE);
549 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
550
551 /* Copper options */
552 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
553 adapter->hw.phy.mdix = AUTO_ALL_MODES;
554 adapter->hw.phy.disable_polarity_correction = FALSE;
555 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
556 }
557
558 /* Set the frame limits assuming standard ethernet sized frames. */
559 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
560 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
984263bc 561
9c80d176
SZ
562 /* This controls when hardware reports transmit completion status. */
563 adapter->hw.mac.report_tx_early = 1;
984263bc 564
87307ba1 565 /*
9c80d176 566 * Create top level busdma tag
984263bc 567 */
9c80d176
SZ
568 error = bus_dma_tag_create(NULL, 1, 0,
569 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
570 NULL, NULL,
571 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
572 0, &adapter->parent_dtag);
573 if (error) {
574 device_printf(dev, "could not create top level DMA tag\n");
af82d4bb 575 goto fail;
9c80d176 576 }
af82d4bb 577
9c80d176
SZ
578 /*
579 * Allocate Transmit Descriptor ring
580 */
581 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
1eca7b82 582 EM_DBA_ALIGN);
87307ba1
SZ
583 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
584 if (error) {
9c80d176 585 device_printf(dev, "Unable to allocate tx_desc memory\n");
af82d4bb 586 goto fail;
984263bc 587 }
9c80d176 588 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
984263bc 589
9c80d176
SZ
590 /*
591 * Allocate Receive Descriptor ring
592 */
593 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
1eca7b82 594 EM_DBA_ALIGN);
87307ba1
SZ
595 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
596 if (error) {
9ccd8c1f 597 device_printf(dev, "Unable to allocate rx_desc memory\n");
af82d4bb 598 goto fail;
984263bc 599 }
9c80d176
SZ
600 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
601
2d0e5700
SZ
602 /* Allocate multicast array memory. */
603 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
604 M_DEVBUF, M_WAITOK);
605
606 /* Indicate SOL/IDER usage */
607 if (e1000_check_reset_block(&adapter->hw)) {
608 device_printf(dev,
609 "PHY reset is blocked due to SOL/IDER session.\n");
610 }
611
612 /*
613 * Start from a known state, this is important in reading the
614 * nvm and mac from that.
615 */
616 e1000_reset_hw(&adapter->hw);
617
9c80d176
SZ
618 /* Make sure we have a good EEPROM before we read from it */
619 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
620 /*
621 * Some PCI-E parts fail the first check due to
622 * the link being in sleep state, call it again,
623 * if it fails a second time its a real issue.
624 */
625 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
626 device_printf(dev,
627 "The EEPROM Checksum Is Not Valid\n");
628 error = EIO;
629 goto fail;
630 }
631 }
984263bc 632
984263bc 633 /* Copy the permanent MAC address out of the EEPROM */
9c80d176
SZ
634 if (e1000_read_mac_addr(&adapter->hw) < 0) {
635 device_printf(dev, "EEPROM read error while reading MAC"
636 " address\n");
984263bc 637 error = EIO;
af82d4bb 638 goto fail;
984263bc 639 }
9c80d176 640 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
87307ba1 641 device_printf(dev, "Invalid MAC address\n");
984263bc 642 error = EIO;
af82d4bb 643 goto fail;
984263bc
MD
644 }
645
9c80d176
SZ
646 /* Allocate transmit descriptors and buffers */
647 error = em_create_tx_ring(adapter);
648 if (error) {
649 device_printf(dev, "Could not setup transmit structures\n");
650 goto fail;
651 }
652
653 /* Allocate receive descriptors and buffers */
654 error = em_create_rx_ring(adapter);
655 if (error) {
656 device_printf(dev, "Could not setup receive structures\n");
657 goto fail;
658 }
659
660 /* Manually turn off all interrupts */
661 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
662
9c80d176
SZ
663 /* Determine if we have to control management hardware */
664 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
665
666 /*
667 * Setup Wake-on-Lan
668 */
2d0e5700
SZ
669 apme_mask = EM_EEPROM_APME;
670 eeprom_data = 0;
9c80d176
SZ
671 switch (adapter->hw.mac.type) {
672 case e1000_82542:
673 case e1000_82543:
674 break;
675
2d0e5700
SZ
676 case e1000_82573:
677 case e1000_82583:
678 adapter->has_amt = 1;
679 /* FALL THROUGH */
680
9c80d176
SZ
681 case e1000_82546:
682 case e1000_82546_rev_3:
683 case e1000_82571:
2d0e5700 684 case e1000_82572:
9c80d176
SZ
685 case e1000_80003es2lan:
686 if (adapter->hw.bus.func == 1) {
687 e1000_read_nvm(&adapter->hw,
688 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
689 } else {
690 e1000_read_nvm(&adapter->hw,
691 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
692 }
2d0e5700
SZ
693 break;
694
695 case e1000_ich8lan:
696 case e1000_ich9lan:
697 case e1000_ich10lan:
698 case e1000_pchlan:
699 case e1000_pch2lan:
700 apme_mask = E1000_WUC_APME;
701 adapter->has_amt = TRUE;
702 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
9c80d176
SZ
703 break;
704
705 default:
2d0e5700
SZ
706 e1000_read_nvm(&adapter->hw,
707 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9c80d176
SZ
708 break;
709 }
2d0e5700
SZ
710 if (eeprom_data & apme_mask)
711 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
712
9c80d176
SZ
713 /*
714 * We have the eeprom settings, now apply the special cases
715 * where the eeprom may be wrong or the board won't support
716 * wake on lan on a particular port
717 */
718 device_id = pci_get_device(dev);
719 switch (device_id) {
720 case E1000_DEV_ID_82546GB_PCIE:
721 adapter->wol = 0;
722 break;
723
724 case E1000_DEV_ID_82546EB_FIBER:
725 case E1000_DEV_ID_82546GB_FIBER:
726 case E1000_DEV_ID_82571EB_FIBER:
727 /*
728 * Wake events only supported on port A for dual fiber
729 * regardless of eeprom setting
730 */
731 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
732 E1000_STATUS_FUNC_1)
733 adapter->wol = 0;
734 break;
735
736 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
737 case E1000_DEV_ID_82571EB_QUAD_COPPER:
738 case E1000_DEV_ID_82571EB_QUAD_FIBER:
739 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
740 /* if quad port adapter, disable WoL on all but port A */
741 if (em_global_quad_port_a != 0)
742 adapter->wol = 0;
743 /* Reset for multiple quad port adapters */
744 if (++em_global_quad_port_a == 4)
745 em_global_quad_port_a = 0;
746 break;
747 }
748
749 /* XXX disable wol */
750 adapter->wol = 0;
751
2d0e5700
SZ
752 /* Setup OS specific network interface */
753 em_setup_ifp(adapter);
754
755 /* Add sysctl tree, must after em_setup_ifp() */
756 em_add_sysctl(adapter);
757
758 /* Reset the hardware */
759 error = em_reset(adapter);
760 if (error) {
761 device_printf(dev, "Unable to reset the hardware\n");
762 goto fail;
763 }
764
765 /* Initialize statistics */
766 em_update_stats(adapter);
767
768 adapter->hw.mac.get_link_status = 1;
769 em_update_link_status(adapter);
770
9c80d176
SZ
771 /* Do we need workaround for 82544 PCI-X adapter? */
772 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
773 adapter->hw.mac.type == e1000_82544)
f647ad3d 774 adapter->pcix_82544 = TRUE;
87307ba1 775 else
f647ad3d 776 adapter->pcix_82544 = FALSE;
af82d4bb 777
9c80d176
SZ
778 if (adapter->pcix_82544) {
779 /*
780 * 82544 on PCI-X may split one TX segment
781 * into two TX descs, so we double its number
782 * of spare TX desc here.
783 */
784 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
785 } else {
786 adapter->spare_tx_desc = EM_TX_SPARE;
787 }
788
9f60d74b
SZ
789 /*
790 * Keep following relationship between spare_tx_desc, oact_tx_desc
791 * and tx_int_nsegs:
792 * (spare_tx_desc + EM_TX_RESERVED) <=
793 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
794 */
795 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
796 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
797 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
798 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
799 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
800
801 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
802 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
803 adapter->tx_int_nsegs = adapter->oact_tx_desc;
804
2d0e5700
SZ
805 /* Non-AMT based hardware can now take control from firmware */
806 if (adapter->has_manage && !adapter->has_amt &&
807 adapter->hw.mac.type >= e1000_82571)
808 em_get_hw_control(adapter);
809
87ab432b
SZ
810 /*
811 * Missing Interrupt Following ICR read:
812 *
a835687d
SZ
813 * 82571/82572 specification update errata #76
814 * 82573 specification update errata #31
815 * 82574 specification update errata #12
816 * 82583 specification update errata #4
87ab432b
SZ
817 */
818 intr_func = em_intr;
819 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
820 (adapter->hw.mac.type == e1000_82571 ||
821 adapter->hw.mac.type == e1000_82572 ||
822 adapter->hw.mac.type == e1000_82573 ||
823 adapter->hw.mac.type == e1000_82574 ||
824 adapter->hw.mac.type == e1000_82583))
825 intr_func = em_intr_mask;
826
9c80d176 827 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
87ab432b 828 intr_func, adapter, &adapter->intr_tag,
9c80d176 829 ifp->if_serializer);
af82d4bb 830 if (error) {
9c80d176
SZ
831 device_printf(dev, "Failed to register interrupt handler");
832 ether_ifdetach(&adapter->arpcom.ac_if);
af82d4bb
JS
833 goto fail;
834 }
835
a749d1d2 836 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res);
9db4b353 837 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
9c80d176 838 return (0);
af82d4bb
JS
839fail:
840 em_detach(dev);
9c80d176 841 return (error);
984263bc
MD
842}
843
984263bc
MD
844static int
845em_detach(device_t dev)
846{
78195a76 847 struct adapter *adapter = device_get_softc(dev);
984263bc 848
af82d4bb 849 if (device_is_attached(dev)) {
9c80d176 850 struct ifnet *ifp = &adapter->arpcom.ac_if;
cdf89432
SZ
851
852 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 853
af82d4bb 854 em_stop(adapter);
9c80d176
SZ
855
856 e1000_phy_hw_reset(&adapter->hw);
857
858 em_rel_mgmt(adapter);
2d0e5700 859 em_rel_hw_control(adapter);
9c80d176
SZ
860
861 if (adapter->wol) {
862 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
863 E1000_WUC_PME_EN);
864 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
865 em_enable_wol(dev);
866 }
867
868 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
869
cdf89432
SZ
870 lwkt_serialize_exit(ifp->if_serializer);
871
872 ether_ifdetach(ifp);
2d0e5700
SZ
873 } else {
874 em_rel_hw_control(adapter);
7ea52455 875 }
cdf89432
SZ
876 bus_generic_detach(dev);
877
9c80d176
SZ
878 em_free_pci_res(adapter);
879
880 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
881 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
af82d4bb 882
984263bc 883 /* Free Transmit Descriptor ring */
9c80d176 884 if (adapter->tx_desc_base)
9ccd8c1f 885 em_dma_free(adapter, &adapter->txdma);
984263bc 886
984263bc 887 /* Free Receive Descriptor ring */
9c80d176 888 if (adapter->rx_desc_base)
9ccd8c1f 889 em_dma_free(adapter, &adapter->rxdma);
9c80d176
SZ
890
891 /* Free top level busdma tag */
892 if (adapter->parent_dtag != NULL)
893 bus_dma_tag_destroy(adapter->parent_dtag);
984263bc 894
1eca7b82 895 /* Free sysctl tree */
9c80d176 896 if (adapter->sysctl_tree != NULL)
1eca7b82 897 sysctl_ctx_free(&adapter->sysctl_ctx);
984263bc 898
87307ba1 899 return (0);
984263bc
MD
900}
901
984263bc
MD
902static int
903em_shutdown(device_t dev)
904{
9c80d176 905 return em_suspend(dev);
87307ba1
SZ
906}
907
87307ba1
SZ
908static int
909em_suspend(device_t dev)
910{
911 struct adapter *adapter = device_get_softc(dev);
9c80d176 912 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
913
914 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 915
87307ba1 916 em_stop(adapter);
9c80d176
SZ
917
918 em_rel_mgmt(adapter);
2d0e5700 919 em_rel_hw_control(adapter);
9c80d176 920
2d0e5700 921 if (adapter->wol) {
9c80d176
SZ
922 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
923 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
924 em_enable_wol(dev);
2d0e5700 925 }
9c80d176 926
87307ba1 927 lwkt_serialize_exit(ifp->if_serializer);
9c80d176
SZ
928
929 return bus_generic_suspend(dev);
87307ba1
SZ
930}
931
932static int
933em_resume(device_t dev)
934{
935 struct adapter *adapter = device_get_softc(dev);
9c80d176 936 struct ifnet *ifp = &adapter->arpcom.ac_if;
87307ba1
SZ
937
938 lwkt_serialize_enter(ifp->if_serializer);
9c80d176 939
87307ba1 940 em_init(adapter);
9c80d176 941 em_get_mgmt(adapter);
9db4b353 942 if_devstart(ifp);
9c80d176 943
87307ba1
SZ
944 lwkt_serialize_exit(ifp->if_serializer);
945
946 return bus_generic_resume(dev);
984263bc
MD
947}
948
984263bc
MD
949static void
950em_start(struct ifnet *ifp)
951{
f647ad3d 952 struct adapter *adapter = ifp->if_softc;
9c80d176 953 struct mbuf *m_head;
984263bc 954
1eca7b82 955 ASSERT_SERIALIZED(ifp->if_serializer);
78195a76 956
87307ba1
SZ
957 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
958 return;
9c80d176 959
9db4b353
SZ
960 if (!adapter->link_active) {
961 ifq_purge(&ifp->if_snd);
f647ad3d 962 return;
9db4b353 963 }
9c80d176 964
e26dc3e9 965 while (!ifq_is_empty(&ifp->if_snd)) {
9f60d74b
SZ
966 /* Now do we at least have a minimal? */
967 if (EM_IS_OACTIVE(adapter)) {
968 em_tx_collect(adapter);
9c80d176 969 if (EM_IS_OACTIVE(adapter)) {
9c80d176 970 ifp->if_flags |= IFF_OACTIVE;
9f60d74b 971 adapter->no_tx_desc_avail1++;
9c80d176
SZ
972 break;
973 }
974 }
975
976 logif(pkt_txqueue);
9db4b353 977 m_head = ifq_dequeue(&ifp->if_snd, NULL);
f647ad3d
JS
978 if (m_head == NULL)
979 break;
984263bc 980
9c80d176 981 if (em_encap(adapter, &m_head)) {
002b3a05 982 ifp->if_oerrors++;
9f60d74b
SZ
983 em_tx_collect(adapter);
984 continue;
f647ad3d 985 }
984263bc
MD
986
987 /* Send a copy of the frame to the BPF listener */
b637f170 988 ETHER_BPF_MTAP(ifp, m_head);
87307ba1
SZ
989
990 /* Set timeout in case hardware has problems transmitting. */
991 ifp->if_timer = EM_TX_TIMEOUT;
f647ad3d 992 }
984263bc
MD
993}
994
984263bc 995static int
bd4539cc 996em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 997{
f647ad3d 998 struct adapter *adapter = ifp->if_softc;
9c80d176 999 struct ifreq *ifr = (struct ifreq *)data;
1eca7b82 1000 uint16_t eeprom_data = 0;
9c80d176
SZ
1001 int max_frame_size, mask, reinit;
1002 int error = 0;
0d366ee7 1003
9c80d176 1004 ASSERT_SERIALIZED(ifp->if_serializer);
0d366ee7 1005
984263bc 1006 switch (command) {
984263bc 1007 case SIOCSIFMTU:
9c80d176
SZ
1008 switch (adapter->hw.mac.type) {
1009 case e1000_82573:
1eca7b82
SZ
1010 /*
1011 * 82573 only supports jumbo frames
1012 * if ASPM is disabled.
1013 */
9c80d176
SZ
1014 e1000_read_nvm(&adapter->hw,
1015 NVM_INIT_3GIO_3, 1, &eeprom_data);
1016 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1eca7b82
SZ
1017 max_frame_size = ETHER_MAX_LEN;
1018 break;
1019 }
9c80d176
SZ
1020 /* FALL THROUGH */
1021
1022 /* Limit Jumbo Frame size */
1023 case e1000_82571:
1024 case e1000_82572:
1025 case e1000_ich9lan:
1026 case e1000_ich10lan:
2d0e5700 1027 case e1000_pch2lan:
9c80d176 1028 case e1000_82574:
6d5e2922 1029 case e1000_82583:
9c80d176 1030 case e1000_80003es2lan:
1eca7b82 1031 max_frame_size = 9234;
7ea52455 1032 break;
9c80d176 1033
2d0e5700
SZ
1034 case e1000_pchlan:
1035 max_frame_size = 4096;
1036 break;
1037
9c80d176
SZ
1038 /* Adapters that do not support jumbo frames */
1039 case e1000_82542:
1040 case e1000_ich8lan:
7ea52455
SZ
1041 max_frame_size = ETHER_MAX_LEN;
1042 break;
9c80d176 1043
7ea52455
SZ
1044 default:
1045 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1046 break;
1047 }
9c80d176
SZ
1048 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1049 ETHER_CRC_LEN) {
984263bc 1050 error = EINVAL;
9c80d176 1051 break;
984263bc 1052 }
9c80d176
SZ
1053
1054 ifp->if_mtu = ifr->ifr_mtu;
1055 adapter->max_frame_size =
1056 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1057
1058 if (ifp->if_flags & IFF_RUNNING)
1059 em_init(adapter);
984263bc 1060 break;
9c80d176 1061
984263bc 1062 case SIOCSIFFLAGS:
984263bc 1063 if (ifp->if_flags & IFF_UP) {
9c80d176
SZ
1064 if ((ifp->if_flags & IFF_RUNNING)) {
1065 if ((ifp->if_flags ^ adapter->if_flags) &
1066 (IFF_PROMISC | IFF_ALLMULTI)) {
1067 em_disable_promisc(adapter);
1068 em_set_promisc(adapter);
1069 }
1070 } else {
78195a76 1071 em_init(adapter);
87307ba1 1072 }
9c80d176
SZ
1073 } else if (ifp->if_flags & IFF_RUNNING) {
1074 em_stop(adapter);
984263bc 1075 }
87307ba1 1076 adapter->if_flags = ifp->if_flags;
984263bc 1077 break;
9c80d176 1078
984263bc
MD
1079 case SIOCADDMULTI:
1080 case SIOCDELMULTI:
984263bc
MD
1081 if (ifp->if_flags & IFF_RUNNING) {
1082 em_disable_intr(adapter);
1083 em_set_multi(adapter);
9c80d176
SZ
1084 if (adapter->hw.mac.type == e1000_82542 &&
1085 adapter->hw.revision_id == E1000_REVISION_2)
1086 em_init_rx_unit(adapter);
1eca7b82 1087#ifdef DEVICE_POLLING
9c80d176 1088 if (!(ifp->if_flags & IFF_POLLING))
1eca7b82 1089#endif
9c80d176 1090 em_enable_intr(adapter);
984263bc
MD
1091 }
1092 break;
9c80d176 1093
984263bc 1094 case SIOCSIFMEDIA:
87307ba1 1095 /* Check SOL/IDER usage */
9c80d176
SZ
1096 if (e1000_check_reset_block(&adapter->hw)) {
1097 device_printf(adapter->dev, "Media change is"
1098 " blocked due to SOL/IDER session.\n");
87307ba1
SZ
1099 break;
1100 }
9c80d176
SZ
1101 /* FALL THROUGH */
1102
984263bc 1103 case SIOCGIFMEDIA:
984263bc
MD
1104 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1105 break;
9c80d176 1106
984263bc 1107 case SIOCSIFCAP:
9c80d176 1108 reinit = 0;
984263bc
MD
1109 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1110 if (mask & IFCAP_HWCSUM) {
9c80d176 1111 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
1eca7b82 1112 reinit = 1;
984263bc 1113 }
1eca7b82
SZ
1114 if (mask & IFCAP_VLAN_HWTAGGING) {
1115 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1116 reinit = 1;
1117 }
9c80d176 1118 if (reinit && (ifp->if_flags & IFF_RUNNING))
1eca7b82 1119 em_init(adapter);
984263bc 1120 break;
9c80d176 1121
984263bc 1122 default:
1eca7b82
SZ
1123 error = ether_ioctl(ifp, command, data);
1124 break;
984263bc 1125 }
87307ba1 1126 return (error);
984263bc
MD
1127}
1128
984263bc
MD
1129static void
1130em_watchdog(struct ifnet *ifp)
1131{
1eca7b82 1132 struct adapter *adapter = ifp->if_softc;
984263bc 1133
9c80d176
SZ
1134 ASSERT_SERIALIZED(ifp->if_serializer);
1135
1136 /*
1137 * The timer is set to 5 every time start queues a packet.
1138 * Then txeof keeps resetting it as long as it cleans at
1139 * least one descriptor.
1140 * Finally, anytime all descriptors are clean the timer is
1141 * set to 0.
1142 */
1143
9f60d74b
SZ
1144 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1145 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1146 /*
1147 * If we reach here, all TX jobs are completed and
1148 * the TX engine should have been idled for some time.
1149 * We don't need to call if_devstart() here.
1150 */
1151 ifp->if_flags &= ~IFF_OACTIVE;
1152 ifp->if_timer = 0;
1153 return;
1154 }
1155
1eca7b82
SZ
1156 /*
1157 * If we are in this routine because of pause frames, then
984263bc
MD
1158 * don't reset the hardware.
1159 */
9c80d176
SZ
1160 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1161 E1000_STATUS_TXOFF) {
984263bc
MD
1162 ifp->if_timer = EM_TX_TIMEOUT;
1163 return;
1164 }
1165
9c80d176 1166 if (e1000_check_for_link(&adapter->hw) == 0)
f647ad3d 1167 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc 1168
9c80d176
SZ
1169 ifp->if_oerrors++;
1170 adapter->watchdog_events++;
1171
984263bc
MD
1172 em_init(adapter);
1173
9c80d176
SZ
1174 if (!ifq_is_empty(&ifp->if_snd))
1175 if_devstart(ifp);
984263bc
MD
1176}
1177
984263bc 1178static void
9c80d176 1179em_init(void *xsc)
984263bc 1180{
9c80d176
SZ
1181 struct adapter *adapter = xsc;
1182 struct ifnet *ifp = &adapter->arpcom.ac_if;
1183 device_t dev = adapter->dev;
eac00e59 1184 uint32_t pba;
984263bc 1185
87307ba1
SZ
1186 ASSERT_SERIALIZED(ifp->if_serializer);
1187
984263bc
MD
1188 em_stop(adapter);
1189
eac00e59
SZ
1190 /*
1191 * Packet Buffer Allocation (PBA)
1192 * Writing PBA sets the receive portion of the buffer
1193 * the remainder is used for the transmit buffer.
1eca7b82
SZ
1194 *
1195 * Devices before the 82547 had a Packet Buffer of 64K.
1196 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1197 * After the 82547 the buffer was reduced to 40K.
1198 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1199 * Note: default does not leave enough room for Jumbo Frame >10k.
eac00e59 1200 */
9c80d176
SZ
1201 switch (adapter->hw.mac.type) {
1202 case e1000_82547:
1203 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1204 if (adapter->max_frame_size > 8192)
eac00e59 1205 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
7ea52455
SZ
1206 else
1207 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
eac00e59
SZ
1208 adapter->tx_fifo_head = 0;
1209 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1210 adapter->tx_fifo_size =
9c80d176 1211 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
7ea52455 1212 break;
9c80d176 1213
87307ba1 1214 /* Total Packet Buffer on these is 48K */
9c80d176
SZ
1215 case e1000_82571:
1216 case e1000_82572:
1217 case e1000_80003es2lan:
7ea52455
SZ
1218 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1219 break;
9c80d176
SZ
1220
1221 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
7ea52455
SZ
1222 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1223 break;
9c80d176
SZ
1224
1225 case e1000_82574:
2d0e5700 1226 case e1000_82583:
9c80d176 1227 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1eca7b82 1228 break;
9c80d176 1229
2d0e5700
SZ
1230 case e1000_ich8lan:
1231 pba = E1000_PBA_8K;
1232 break;
1233
9c80d176
SZ
1234 case e1000_ich9lan:
1235 case e1000_ich10lan:
1236#define E1000_PBA_10K 0x000A
b0ff1d56
MS
1237 pba = E1000_PBA_10K;
1238 break;
9c80d176 1239
2d0e5700
SZ
1240 case e1000_pchlan:
1241 case e1000_pch2lan:
1242 pba = E1000_PBA_26K;
9c80d176
SZ
1243 break;
1244
7ea52455
SZ
1245 default:
1246 /* Devices before 82547 had a Packet Buffer of 64K. */
9c80d176 1247 if (adapter->max_frame_size > 8192)
7ea52455
SZ
1248 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1249 else
1250 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
eac00e59 1251 }
9c80d176 1252 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
a4a205fa 1253
0d366ee7 1254 /* Get the latest mac address, User can use a LAA */
9c80d176
SZ
1255 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1256
1257 /* Put the address into the Receive Address Array */
1258 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1259
1260 /*
1261 * With the 82571 adapter, RAR[0] may be overwritten
1262 * when the other port is reset, we make a duplicate
1263 * in RAR[14] for that eventuality, this assures
1264 * the interface continues to function.
1265 */
1266 if (adapter->hw.mac.type == e1000_82571) {
1267 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1268 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1269 E1000_RAR_ENTRIES - 1);
1270 }
0d366ee7 1271
2d0e5700
SZ
1272 /* Reset the hardware */
1273 if (em_reset(adapter)) {
1274 device_printf(dev, "Unable to reset the hardware\n");
9c80d176 1275 /* XXX em_stop()? */
984263bc
MD
1276 return;
1277 }
87307ba1 1278 em_update_link_status(adapter);
984263bc 1279
9c80d176
SZ
1280 /* Setup VLAN support, basic and offload if available */
1281 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
984263bc 1282
9c80d176
SZ
1283 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1284 uint32_t ctrl;
1285
1286 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1287 ctrl |= E1000_CTRL_VME;
1288 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
87307ba1
SZ
1289 }
1290
9c80d176
SZ
1291 /* Set hardware offload abilities */
1292 if (ifp->if_capenable & IFCAP_TXCSUM)
1293 ifp->if_hwassist = EM_CSUM_FEATURES;
1294 else
1295 ifp->if_hwassist = 0;
1296
1297 /* Configure for OS presence */
1298 em_get_mgmt(adapter);
1299
984263bc 1300 /* Prepare transmit descriptors and buffers */
9c80d176
SZ
1301 em_init_tx_ring(adapter);
1302 em_init_tx_unit(adapter);
984263bc
MD
1303
1304 /* Setup Multicast table */
1305 em_set_multi(adapter);
1306
1307 /* Prepare receive descriptors and buffers */
9c80d176
SZ
1308 if (em_init_rx_ring(adapter)) {
1309 device_printf(dev, "Could not setup receive structures\n");
984263bc 1310 em_stop(adapter);
984263bc
MD
1311 return;
1312 }
9c80d176 1313 em_init_rx_unit(adapter);
7ea52455 1314
87307ba1 1315 /* Don't lose promiscuous settings */
0d366ee7 1316 em_set_promisc(adapter);
984263bc 1317
984263bc
MD
1318 ifp->if_flags |= IFF_RUNNING;
1319 ifp->if_flags &= ~IFF_OACTIVE;
1320
9c80d176
SZ
1321 callout_reset(&adapter->timer, hz, em_timer, adapter);
1322 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1323
1324 /* MSI/X configuration for 82574 */
1325 if (adapter->hw.mac.type == e1000_82574) {
1326 int tmp;
1327
1328 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1329 tmp |= E1000_CTRL_EXT_PBA_CLR;
1330 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1331 /*
2d0e5700 1332 * XXX MSIX
9c80d176
SZ
1333 * Set the IVAR - interrupt vector routing.
1334 * Each nibble represents a vector, high bit
1335 * is enable, other 3 bits are the MSIX table
1336 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1337 * Link (other) to 2, hence the magic number.
1338 */
1339 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1340 }
1eca7b82
SZ
1341
1342#ifdef DEVICE_POLLING
9c80d176
SZ
1343 /*
1344 * Only enable interrupts if we are not polling, make sure
1345 * they are off otherwise.
1346 */
1eca7b82
SZ
1347 if (ifp->if_flags & IFF_POLLING)
1348 em_disable_intr(adapter);
1349 else
9c80d176
SZ
1350#endif /* DEVICE_POLLING */
1351 em_enable_intr(adapter);
0d366ee7 1352
2d0e5700
SZ
1353 /* AMT based hardware can now take control from firmware */
1354 if (adapter->has_manage && adapter->has_amt &&
1355 adapter->hw.mac.type >= e1000_82571)
1356 em_get_hw_control(adapter);
1357
0d366ee7 1358 /* Don't reset the phy next time init gets called */
9c80d176 1359 adapter->hw.phy.reset_disable = TRUE;
984263bc
MD
1360}
1361
984263bc 1362#ifdef DEVICE_POLLING
f647ad3d
JS
1363
1364static void
984263bc
MD
1365em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1366{
f647ad3d
JS
1367 struct adapter *adapter = ifp->if_softc;
1368 uint32_t reg_icr;
984263bc 1369
78195a76
MD
1370 ASSERT_SERIALIZED(ifp->if_serializer);
1371
9c80d176 1372 switch (cmd) {
9c095379
MD
1373 case POLL_REGISTER:
1374 em_disable_intr(adapter);
1375 break;
9c80d176 1376
9c095379 1377 case POLL_DEREGISTER:
f647ad3d 1378 em_enable_intr(adapter);
9c095379 1379 break;
9c80d176 1380
9c095379 1381 case POLL_AND_CHECK_STATUS:
9c80d176 1382 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
f647ad3d 1383 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
9ccd8c1f 1384 callout_stop(&adapter->timer);
9c80d176 1385 adapter->hw.mac.get_link_status = 1;
87307ba1 1386 em_update_link_status(adapter);
9c80d176 1387 callout_reset(&adapter->timer, hz, em_timer, adapter);
f647ad3d 1388 }
9c80d176 1389 /* FALL THROUGH */
9c095379
MD
1390 case POLL_ONLY:
1391 if (ifp->if_flags & IFF_RUNNING) {
87307ba1
SZ
1392 em_rxeof(adapter, count);
1393 em_txeof(adapter);
1eca7b82 1394
9c095379 1395 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1396 if_devstart(ifp);
9c095379
MD
1397 }
1398 break;
f647ad3d 1399 }
984263bc 1400}
9c095379 1401
984263bc
MD
1402#endif /* DEVICE_POLLING */
1403
984263bc 1404static void
9c80d176 1405em_intr(void *xsc)
984263bc 1406{
87ab432b
SZ
1407 em_intr_body(xsc, TRUE);
1408}
1409
1410static void
1411em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1412{
9c80d176 1413 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1414 uint32_t reg_icr;
984263bc 1415
07855a48 1416 logif(intr_beg);
78195a76
MD
1417 ASSERT_SERIALIZED(ifp->if_serializer);
1418
9c80d176
SZ
1419 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1420
87ab432b
SZ
1421 if (chk_asserted &&
1422 ((adapter->hw.mac.type >= e1000_82571 &&
1423 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1424 reg_icr == 0)) {
07855a48 1425 logif(intr_end);
984263bc 1426 return;
07855a48 1427 }
984263bc 1428
87307ba1 1429 /*
9c80d176
SZ
1430 * XXX: some laptops trigger several spurious interrupts
1431 * on em(4) when in the resume cycle. The ICR register
1432 * reports all-ones value in this case. Processing such
1433 * interrupts would lead to a freeze. I don't know why.
87307ba1
SZ
1434 */
1435 if (reg_icr == 0xffffffff) {
1436 logif(intr_end);
1437 return;
984263bc
MD
1438 }
1439
79938e61 1440 if (ifp->if_flags & IFF_RUNNING) {
9f60d74b 1441 if (reg_icr &
6643d744 1442 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
9f60d74b 1443 em_rxeof(adapter, -1);
6643d744 1444 if (reg_icr & E1000_ICR_TXDW) {
9f60d74b
SZ
1445 em_txeof(adapter);
1446 if (!ifq_is_empty(&ifp->if_snd))
1447 if_devstart(ifp);
1448 }
f647ad3d 1449 }
984263bc 1450
87307ba1
SZ
1451 /* Link status change */
1452 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1453 callout_stop(&adapter->timer);
9c80d176 1454 adapter->hw.mac.get_link_status = 1;
87307ba1 1455 em_update_link_status(adapter);
9c80d176
SZ
1456
1457 /* Deal with TX cruft when link lost */
1458 em_tx_purge(adapter);
1459
1460 callout_reset(&adapter->timer, hz, em_timer, adapter);
87307ba1
SZ
1461 }
1462
1463 if (reg_icr & E1000_ICR_RXO)
1464 adapter->rx_overruns++;
1465
07855a48 1466 logif(intr_end);
984263bc
MD
1467}
1468
984263bc 1469static void
87ab432b
SZ
1470em_intr_mask(void *xsc)
1471{
1472 struct adapter *adapter = xsc;
1473
1474 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1475 /*
1476 * NOTE:
1477 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1478 * so don't check it.
1479 */
1480 em_intr_body(adapter, FALSE);
1481 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1482}
1483
1484static void
984263bc
MD
1485em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1486{
87307ba1 1487 struct adapter *adapter = ifp->if_softc;
1eca7b82 1488 u_char fiber_type = IFM_1000_SX;
984263bc 1489
78195a76
MD
1490 ASSERT_SERIALIZED(ifp->if_serializer);
1491
87307ba1 1492 em_update_link_status(adapter);
984263bc
MD
1493
1494 ifmr->ifm_status = IFM_AVALID;
1495 ifmr->ifm_active = IFM_ETHER;
1496
1497 if (!adapter->link_active)
1498 return;
1499
1500 ifmr->ifm_status |= IFM_ACTIVE;
1501
9c80d176
SZ
1502 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1503 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1504 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
1505 fiber_type = IFM_1000_LX;
1506 ifmr->ifm_active |= fiber_type | IFM_FDX;
984263bc
MD
1507 } else {
1508 switch (adapter->link_speed) {
1509 case 10:
1510 ifmr->ifm_active |= IFM_10_T;
1511 break;
1512 case 100:
1513 ifmr->ifm_active |= IFM_100_TX;
1514 break;
9c80d176 1515
984263bc 1516 case 1000:
7f259627 1517 ifmr->ifm_active |= IFM_1000_T;
984263bc
MD
1518 break;
1519 }
1520 if (adapter->link_duplex == FULL_DUPLEX)
1521 ifmr->ifm_active |= IFM_FDX;
1522 else
1523 ifmr->ifm_active |= IFM_HDX;
1524 }
984263bc
MD
1525}
1526
984263bc
MD
1527static int
1528em_media_change(struct ifnet *ifp)
1529{
87307ba1
SZ
1530 struct adapter *adapter = ifp->if_softc;
1531 struct ifmedia *ifm = &adapter->media;
984263bc 1532
78195a76 1533 ASSERT_SERIALIZED(ifp->if_serializer);
9c095379 1534
87307ba1
SZ
1535 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1536 return (EINVAL);
1537
984263bc
MD
1538 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1539 case IFM_AUTO:
9c80d176
SZ
1540 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1541 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
984263bc 1542 break;
9c80d176 1543
1eca7b82 1544 case IFM_1000_LX:
984263bc 1545 case IFM_1000_SX:
7f259627 1546 case IFM_1000_T:
9c80d176
SZ
1547 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1548 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
984263bc 1549 break;
9c80d176 1550
984263bc 1551 case IFM_100_TX:
9c80d176
SZ
1552 adapter->hw.mac.autoneg = FALSE;
1553 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1554 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1555 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
984263bc 1556 else
9c80d176 1557 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
984263bc 1558 break;
9c80d176 1559
984263bc 1560 case IFM_10_T:
9c80d176
SZ
1561 adapter->hw.mac.autoneg = FALSE;
1562 adapter->hw.phy.autoneg_advertised = 0;
984263bc 1563 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
9c80d176 1564 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
984263bc 1565 else
9c80d176 1566 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
984263bc 1567 break;
9c80d176 1568
984263bc 1569 default:
f647ad3d 1570 if_printf(ifp, "Unsupported media type\n");
9c80d176 1571 break;
984263bc 1572 }
9c80d176 1573
f647ad3d 1574 /*
9c80d176 1575 * As the speed/duplex settings my have changed we need to
f647ad3d
JS
1576 * reset the PHY.
1577 */
9c80d176 1578 adapter->hw.phy.reset_disable = FALSE;
984263bc 1579
78195a76 1580 em_init(adapter);
984263bc 1581
9c80d176 1582 return (0);
9ccd8c1f
JS
1583}
1584
984263bc 1585static int
9c80d176 1586em_encap(struct adapter *adapter, struct mbuf **m_headp)
9ccd8c1f 1587{
9c80d176 1588 bus_dma_segment_t segs[EM_MAX_SCATTER];
1eca7b82 1589 bus_dmamap_t map;
9c80d176
SZ
1590 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1591 struct e1000_tx_desc *ctxd = NULL;
002b3a05 1592 struct mbuf *m_head = *m_headp;
9f60d74b 1593 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
9c80d176 1594 int maxsegs, nsegs, i, j, first, last = 0, error;
984263bc 1595
3752657e 1596 if (m_head->m_len < EM_TXCSUM_MINHL &&
002b3a05
SZ
1597 (m_head->m_flags & EM_CSUM_FEATURES)) {
1598 /*
1599 * Make sure that ethernet header and ip.ip_hl are in
1600 * contiguous memory, since if TXCSUM is enabled, later
1601 * TX context descriptor's setup need to access ip.ip_hl.
1602 */
1603 error = em_txcsum_pullup(adapter, m_headp);
1604 if (error) {
1605 KKASSERT(*m_headp == NULL);
1606 return error;
1607 }
1608 m_head = *m_headp;
1609 }
1610
9c80d176
SZ
1611 txd_upper = txd_lower = 0;
1612 txd_used = 0;
87307ba1
SZ
1613
1614 /*
9c80d176
SZ
1615 * Capture the first descriptor index, this descriptor
1616 * will have the index of the EOP which is the only one
1617 * that now gets a DONE bit writeback.
87307ba1 1618 */
9c80d176
SZ
1619 first = adapter->next_avail_tx_desc;
1620 tx_buffer = &adapter->tx_buffer_area[first];
1621 tx_buffer_mapped = tx_buffer;
1622 map = tx_buffer->map;
87307ba1 1623
9c80d176
SZ
1624 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1625 KASSERT(maxsegs >= adapter->spare_tx_desc,
ed20d0e3 1626 ("not enough spare TX desc"));
9c80d176
SZ
1627 if (adapter->pcix_82544) {
1628 /* Half it; see the comment in em_attach() */
1629 maxsegs >>= 1;
9ccd8c1f 1630 }
9c80d176
SZ
1631 if (maxsegs > EM_MAX_SCATTER)
1632 maxsegs = EM_MAX_SCATTER;
984263bc 1633
9c80d176
SZ
1634 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1635 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1636 if (error) {
1637 if (error == ENOBUFS)
1638 adapter->mbuf_alloc_failed++;
1639 else
1640 adapter->no_tx_dma_setup++;
984263bc 1641
9c80d176
SZ
1642 m_freem(*m_headp);
1643 *m_headp = NULL;
1644 return error;
7ea52455 1645 }
9c80d176 1646 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
984263bc 1647
9c80d176 1648 m_head = *m_headp;
9f60d74b 1649 adapter->tx_nsegs += nsegs;
9c80d176 1650
002b3a05 1651 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
9c80d176 1652 /* TX csum offloading will consume one TX desc */
9f60d74b
SZ
1653 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1654 &txd_upper, &txd_lower);
9c80d176 1655 }
984263bc 1656 i = adapter->next_avail_tx_desc;
87307ba1
SZ
1657
1658 /* Set up our transmit descriptors */
9c80d176 1659 for (j = 0; j < nsegs; j++) {
9ccd8c1f
JS
1660 /* If adapter is 82544 and on PCIX bus */
1661 if(adapter->pcix_82544) {
87307ba1
SZ
1662 DESC_ARRAY desc_array;
1663 uint32_t array_elements, counter;
1664
9c80d176 1665 /*
f647ad3d
JS
1666 * Check the Address and Length combination and
1667 * split the data accordingly
9ccd8c1f 1668 */
9c80d176
SZ
1669 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1670 segs[j].ds_len, &desc_array);
9ccd8c1f 1671 for (counter = 0; counter < array_elements; counter++) {
9c80d176
SZ
1672 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1673
9ccd8c1f 1674 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176
SZ
1675 ctxd = &adapter->tx_desc_base[i];
1676
1677 ctxd->buffer_addr = htole64(
1678 desc_array.descriptor[counter].address);
1679 ctxd->lower.data = htole32(
2af74b85 1680 E1000_TXD_CMD_IFCS | txd_lower |
9c80d176
SZ
1681 desc_array.descriptor[counter].length);
1682 ctxd->upper.data = htole32(txd_upper);
87307ba1
SZ
1683
1684 last = i;
9ccd8c1f
JS
1685 if (++i == adapter->num_tx_desc)
1686 i = 0;
1687
9ccd8c1f 1688 txd_used++;
9c80d176 1689 }
9ccd8c1f 1690 } else {
0d366ee7 1691 tx_buffer = &adapter->tx_buffer_area[i];
9c80d176 1692 ctxd = &adapter->tx_desc_base[i];
9ccd8c1f 1693
9c80d176 1694 ctxd->buffer_addr = htole64(segs[j].ds_addr);
2af74b85 1695 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
9c80d176
SZ
1696 txd_lower | segs[j].ds_len);
1697 ctxd->upper.data = htole32(txd_upper);
984263bc 1698
87307ba1 1699 last = i;
0d366ee7
MD
1700 if (++i == adapter->num_tx_desc)
1701 i = 0;
0d366ee7 1702 }
984263bc 1703 }
9ccd8c1f 1704
984263bc 1705 adapter->next_avail_tx_desc = i;
9c80d176
SZ
1706 if (adapter->pcix_82544) {
1707 KKASSERT(adapter->num_tx_desc_avail > txd_used);
9ccd8c1f 1708 adapter->num_tx_desc_avail -= txd_used;
9c80d176
SZ
1709 } else {
1710 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1711 adapter->num_tx_desc_avail -= nsegs;
1712 }
984263bc 1713
9c80d176 1714 /* Handle VLAN tag */
83790f85 1715 if (m_head->m_flags & M_VLANTAG) {
9c80d176
SZ
1716 /* Set the vlan id. */
1717 ctxd->upper.fields.special =
1718 htole16(m_head->m_pkthdr.ether_vlantag);
9ccd8c1f 1719
f647ad3d 1720 /* Tell hardware to add tag */
9c80d176 1721 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
f647ad3d 1722 }
984263bc
MD
1723
1724 tx_buffer->m_head = m_head;
9c80d176 1725 tx_buffer_mapped->map = tx_buffer->map;
1eca7b82 1726 tx_buffer->map = map;
9ccd8c1f 1727
9f60d74b
SZ
1728 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1729 adapter->tx_nsegs = 0;
4e4e8481
SZ
1730
1731 /*
1732 * Report Status (RS) is turned on
1733 * every tx_int_nsegs descriptors.
1734 */
9f60d74b
SZ
1735 cmd = E1000_TXD_CMD_RS;
1736
b4b0a2b4
SZ
1737 /*
1738 * Keep track of the descriptor, which will
1739 * be written back by hardware.
1740 */
9f60d74b
SZ
1741 adapter->tx_dd[adapter->tx_dd_tail] = last;
1742 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1743 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1744 }
1745
9ccd8c1f 1746 /*
984263bc 1747 * Last Descriptor of Packet needs End Of Packet (EOP)
87307ba1 1748 */
9f60d74b 1749 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
87307ba1
SZ
1750
1751 /*
9c80d176 1752 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
984263bc
MD
1753 * that this frame is available to transmit.
1754 */
9c80d176 1755 if (adapter->hw.mac.type == e1000_82547 &&
984263bc 1756 adapter->link_duplex == HALF_DUPLEX) {
cfefda96 1757 em_82547_move_tail_serialized(adapter);
9ccd8c1f 1758 } else {
9c80d176
SZ
1759 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1760 if (adapter->hw.mac.type == e1000_82547) {
cfefda96 1761 em_82547_update_fifo_head(adapter,
9c80d176 1762 m_head->m_pkthdr.len);
984263bc
MD
1763 }
1764 }
87307ba1 1765 return (0);
984263bc
MD
1766}
1767
9c80d176 1768/*
984263bc 1769 * 82547 workaround to avoid controller hang in half-duplex environment.
87307ba1 1770 * The workaround is to avoid queuing a large packet that would span
9c80d176
SZ
1771 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1772 * in this case. We do that only when FIFO is quiescent.
1773 */
9c095379 1774static void
1eca7b82 1775em_82547_move_tail_serialized(struct adapter *adapter)
9c095379 1776{
9c80d176
SZ
1777 struct e1000_tx_desc *tx_desc;
1778 uint16_t hw_tdt, sw_tdt, length = 0;
1779 bool eop = 0;
984263bc 1780
9c80d176
SZ
1781 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1782
1783 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
984263bc 1784 sw_tdt = adapter->next_avail_tx_desc;
f647ad3d 1785
984263bc
MD
1786 while (hw_tdt != sw_tdt) {
1787 tx_desc = &adapter->tx_desc_base[hw_tdt];
1788 length += tx_desc->lower.flags.length;
1789 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
87307ba1 1790 if (++hw_tdt == adapter->num_tx_desc)
984263bc
MD
1791 hw_tdt = 0;
1792
87307ba1 1793 if (eop) {
984263bc 1794 if (em_82547_fifo_workaround(adapter, length)) {
eac00e59 1795 adapter->tx_fifo_wrk_cnt++;
9ccd8c1f
JS
1796 callout_reset(&adapter->tx_fifo_timer, 1,
1797 em_82547_move_tail, adapter);
1798 break;
984263bc 1799 }
9c80d176 1800 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
9ccd8c1f
JS
1801 em_82547_update_fifo_head(adapter, length);
1802 length = 0;
984263bc 1803 }
9c80d176
SZ
1804 }
1805}
1806
1807static void
1808em_82547_move_tail(void *xsc)
1809{
1810 struct adapter *adapter = xsc;
1811 struct ifnet *ifp = &adapter->arpcom.ac_if;
1812
1813 lwkt_serialize_enter(ifp->if_serializer);
1814 em_82547_move_tail_serialized(adapter);
1815 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1816}
1817
1818static int
1819em_82547_fifo_workaround(struct adapter *adapter, int len)
1820{
1821 int fifo_space, fifo_pkt_len;
1822
1eca7b82 1823 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
984263bc
MD
1824
1825 if (adapter->link_duplex == HALF_DUPLEX) {
eac00e59 1826 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
984263bc
MD
1827
1828 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
f647ad3d 1829 if (em_82547_tx_fifo_reset(adapter))
87307ba1 1830 return (0);
f647ad3d 1831 else
87307ba1 1832 return (1);
984263bc
MD
1833 }
1834 }
87307ba1 1835 return (0);
984263bc
MD
1836}
1837
1838static void
1839em_82547_update_fifo_head(struct adapter *adapter, int len)
1840{
1eca7b82 1841 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
f647ad3d 1842
984263bc
MD
1843 /* tx_fifo_head is always 16 byte aligned */
1844 adapter->tx_fifo_head += fifo_pkt_len;
eac00e59
SZ
1845 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1846 adapter->tx_fifo_head -= adapter->tx_fifo_size;
984263bc
MD
1847}
1848
984263bc
MD
1849static int
1850em_82547_tx_fifo_reset(struct adapter *adapter)
7ea52455 1851{
984263bc
MD
1852 uint32_t tctl;
1853
9c80d176
SZ
1854 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1855 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1856 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1857 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1858 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1859 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1860 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
984263bc 1861 /* Disable TX unit */
9c80d176
SZ
1862 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1863 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1864 tctl & ~E1000_TCTL_EN);
984263bc
MD
1865
1866 /* Reset FIFO pointers */
9c80d176
SZ
1867 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1868 adapter->tx_head_addr);
1869 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1870 adapter->tx_head_addr);
1871 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1872 adapter->tx_head_addr);
1873 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1874 adapter->tx_head_addr);
984263bc
MD
1875
1876 /* Re-enable TX unit */
9c80d176 1877 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
1878 E1000_WRITE_FLUSH(&adapter->hw);
1879
1880 adapter->tx_fifo_head = 0;
eac00e59 1881 adapter->tx_fifo_reset_cnt++;
984263bc 1882
87307ba1 1883 return (TRUE);
eac00e59 1884 } else {
87307ba1 1885 return (FALSE);
984263bc
MD
1886 }
1887}
1888
1889static void
f647ad3d 1890em_set_promisc(struct adapter *adapter)
984263bc 1891{
9c80d176 1892 struct ifnet *ifp = &adapter->arpcom.ac_if;
1eca7b82 1893 uint32_t reg_rctl;
984263bc 1894
9c80d176 1895 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc
MD
1896
1897 if (ifp->if_flags & IFF_PROMISC) {
1898 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
9c80d176
SZ
1899 /* Turn this on if you want to see bad packets */
1900 if (em_debug_sbp)
1901 reg_rctl |= E1000_RCTL_SBP;
1902 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1903 } else if (ifp->if_flags & IFF_ALLMULTI) {
1904 reg_rctl |= E1000_RCTL_MPE;
1905 reg_rctl &= ~E1000_RCTL_UPE;
9c80d176 1906 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc 1907 }
984263bc
MD
1908}
1909
1910static void
f647ad3d 1911em_disable_promisc(struct adapter *adapter)
984263bc 1912{
f647ad3d 1913 uint32_t reg_rctl;
984263bc 1914
9c80d176 1915 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
984263bc 1916
9c80d176
SZ
1917 reg_rctl &= ~E1000_RCTL_UPE;
1918 reg_rctl &= ~E1000_RCTL_MPE;
1919 reg_rctl &= ~E1000_RCTL_SBP;
1920 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
984263bc
MD
1921}
1922
984263bc 1923static void
f647ad3d 1924em_set_multi(struct adapter *adapter)
984263bc 1925{
9c80d176 1926 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 1927 struct ifmultiaddr *ifma;
9c80d176 1928 uint32_t reg_rctl = 0;
2d0e5700 1929 uint8_t *mta;
f647ad3d 1930 int mcnt = 0;
f647ad3d 1931
2d0e5700
SZ
1932 mta = adapter->mta;
1933 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1934
9c80d176
SZ
1935 if (adapter->hw.mac.type == e1000_82542 &&
1936 adapter->hw.revision_id == E1000_REVISION_2) {
1937 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1938 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1939 e1000_pci_clear_mwi(&adapter->hw);
f647ad3d 1940 reg_rctl |= E1000_RCTL_RST;
9c80d176 1941 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d
JS
1942 msec_delay(5);
1943 }
984263bc 1944
441d34b2 1945 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
f647ad3d
JS
1946 if (ifma->ifma_addr->sa_family != AF_LINK)
1947 continue;
1948
1949 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1950 break;
984263bc 1951
f647ad3d 1952 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
9c80d176 1953 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
f647ad3d
JS
1954 mcnt++;
1955 }
1956
1957 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
9c80d176 1958 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1959 reg_rctl |= E1000_RCTL_MPE;
9c80d176 1960 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
7ea52455 1961 } else {
6a5a645e 1962 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
7ea52455 1963 }
f647ad3d 1964
9c80d176
SZ
1965 if (adapter->hw.mac.type == e1000_82542 &&
1966 adapter->hw.revision_id == E1000_REVISION_2) {
1967 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
f647ad3d 1968 reg_rctl &= ~E1000_RCTL_RST;
9c80d176 1969 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
f647ad3d 1970 msec_delay(5);
9c80d176
SZ
1971 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1972 e1000_pci_set_mwi(&adapter->hw);
f647ad3d
JS
1973 }
1974}
984263bc 1975
9c80d176
SZ
1976/*
1977 * This routine checks for link status and updates statistics.
1978 */
984263bc 1979static void
9c80d176 1980em_timer(void *xsc)
984263bc 1981{
9c80d176
SZ
1982 struct adapter *adapter = xsc;
1983 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 1984
78195a76 1985 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1986
87307ba1 1987 em_update_link_status(adapter);
9c80d176
SZ
1988 em_update_stats(adapter);
1989
1990 /* Reset LAA into RAR[0] on 82571 */
1991 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1992 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1993
1994 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
984263bc 1995 em_print_hw_stats(adapter);
9c80d176 1996
984263bc
MD
1997 em_smartspeed(adapter);
1998
9c80d176 1999 callout_reset(&adapter->timer, hz, em_timer, adapter);
984263bc 2000
78195a76 2001 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2002}
2003
2004static void
87307ba1 2005em_update_link_status(struct adapter *adapter)
984263bc 2006{
9c80d176
SZ
2007 struct e1000_hw *hw = &adapter->hw;
2008 struct ifnet *ifp = &adapter->arpcom.ac_if;
2009 device_t dev = adapter->dev;
2010 uint32_t link_check = 0;
2011
2012 /* Get the cached link value or read phy for real */
2013 switch (hw->phy.media_type) {
2014 case e1000_media_type_copper:
2015 if (hw->mac.get_link_status) {
2016 /* Do the work to read phy */
2017 e1000_check_for_link(hw);
2018 link_check = !hw->mac.get_link_status;
2019 if (link_check) /* ESB2 fix */
2020 e1000_cfg_on_link_up(hw);
2021 } else {
2022 link_check = TRUE;
984263bc 2023 }
9c80d176
SZ
2024 break;
2025
2026 case e1000_media_type_fiber:
2027 e1000_check_for_link(hw);
2028 link_check =
2029 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2030 break;
2031
2032 case e1000_media_type_internal_serdes:
2033 e1000_check_for_link(hw);
2034 link_check = adapter->hw.mac.serdes_has_link;
2035 break;
2036
2037 case e1000_media_type_unknown:
2038 default:
2039 break;
2040 }
2041
2042 /* Now check for a transition */
2043 if (link_check && adapter->link_active == 0) {
2044 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2045 &adapter->link_duplex);
cb5a6be6
SZ
2046
2047 /*
2048 * Check if we should enable/disable SPEED_MODE bit on
2049 * 82571/82572
2050 */
2d0e5700
SZ
2051 if (adapter->link_speed != SPEED_1000 &&
2052 (hw->mac.type == e1000_82571 ||
2053 hw->mac.type == e1000_82572)) {
9c80d176
SZ
2054 int tarc0;
2055
2056 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 2057 tarc0 &= ~SPEED_MODE_BIT;
9c80d176 2058 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
984263bc 2059 }
9c80d176
SZ
2060 if (bootverbose) {
2061 device_printf(dev, "Link is up %d Mbps %s\n",
2062 adapter->link_speed,
2063 ((adapter->link_duplex == FULL_DUPLEX) ?
2064 "Full Duplex" : "Half Duplex"));
2065 }
2066 adapter->link_active = 1;
2067 adapter->smartspeed = 0;
2068 ifp->if_baudrate = adapter->link_speed * 1000000;
2069 ifp->if_link_state = LINK_STATE_UP;
2070 if_link_state_change(ifp);
2071 } else if (!link_check && adapter->link_active == 1) {
2072 ifp->if_baudrate = adapter->link_speed = 0;
2073 adapter->link_duplex = 0;
2074 if (bootverbose)
2075 device_printf(dev, "Link is Down\n");
2076 adapter->link_active = 0;
2077#if 0
2078 /* Link down, disable watchdog */
2079 if->if_timer = 0;
2080#endif
2081 ifp->if_link_state = LINK_STATE_DOWN;
2082 if_link_state_change(ifp);
984263bc 2083 }
984263bc
MD
2084}
2085
984263bc 2086static void
9c80d176 2087em_stop(struct adapter *adapter)
984263bc 2088{
9c80d176
SZ
2089 struct ifnet *ifp = &adapter->arpcom.ac_if;
2090 int i;
984263bc 2091
1eca7b82
SZ
2092 ASSERT_SERIALIZED(ifp->if_serializer);
2093
984263bc 2094 em_disable_intr(adapter);
9c80d176 2095
9ccd8c1f
JS
2096 callout_stop(&adapter->timer);
2097 callout_stop(&adapter->tx_fifo_timer);
984263bc 2098
984263bc 2099 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
af82d4bb 2100 ifp->if_timer = 0;
9c80d176
SZ
2101
2102 e1000_reset_hw(&adapter->hw);
2103 if (adapter->hw.mac.type >= e1000_82544)
2104 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2105
2106 for (i = 0; i < adapter->num_tx_desc; i++) {
2107 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2108
2109 if (tx_buffer->m_head != NULL) {
2110 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2111 m_freem(tx_buffer->m_head);
2112 tx_buffer->m_head = NULL;
2113 }
9c80d176
SZ
2114 }
2115
2116 for (i = 0; i < adapter->num_rx_desc; i++) {
2117 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2118
2119 if (rx_buffer->m_head != NULL) {
2120 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2121 m_freem(rx_buffer->m_head);
2122 rx_buffer->m_head = NULL;
2123 }
2124 }
c9ff32cc
SZ
2125
2126 if (adapter->fmp != NULL)
2127 m_freem(adapter->fmp);
2128 adapter->fmp = NULL;
2129 adapter->lmp = NULL;
51e6819f
SZ
2130
2131 adapter->csum_flags = 0;
2132 adapter->csum_ehlen = 0;
2133 adapter->csum_iphlen = 0;
9f60d74b
SZ
2134
2135 adapter->tx_dd_head = 0;
2136 adapter->tx_dd_tail = 0;
2137 adapter->tx_nsegs = 0;
984263bc
MD
2138}
2139
9c80d176
SZ
2140static int
2141em_get_hw_info(struct adapter *adapter)
984263bc
MD
2142{
2143 device_t dev = adapter->dev;
2144
984263bc
MD
2145 /* Save off the information about this board */
2146 adapter->hw.vendor_id = pci_get_vendor(dev);
2147 adapter->hw.device_id = pci_get_device(dev);
f647ad3d
JS
2148 adapter->hw.revision_id = pci_get_revid(dev);
2149 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
9c80d176 2150 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
984263bc 2151
9c80d176
SZ
2152 /* Do Shared Code Init and Setup */
2153 if (e1000_set_mac_type(&adapter->hw))
2154 return ENXIO;
2155 return 0;
984263bc
MD
2156}
2157
1eca7b82 2158static int
9c80d176 2159em_alloc_pci_res(struct adapter *adapter)
1eca7b82 2160{
9c80d176 2161 device_t dev = adapter->dev;
053f3ae6 2162 u_int intr_flags;
84e26aaa 2163 int val, rid, msi_enable;
9c80d176
SZ
2164
2165 /* Enable bus mastering */
2166 pci_enable_busmaster(dev);
1eca7b82 2167
9c80d176
SZ
2168 adapter->memory_rid = EM_BAR_MEM;
2169 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2170 &adapter->memory_rid, RF_ACTIVE);
2171 if (adapter->memory == NULL) {
1eca7b82 2172 device_printf(dev, "Unable to allocate bus resource: memory\n");
9c80d176 2173 return (ENXIO);
1eca7b82
SZ
2174 }
2175 adapter->osdep.mem_bus_space_tag =
9c80d176 2176 rman_get_bustag(adapter->memory);
1eca7b82 2177 adapter->osdep.mem_bus_space_handle =
9c80d176
SZ
2178 rman_get_bushandle(adapter->memory);
2179
2180 /* XXX This is quite goofy, it is not actually used */
1eca7b82
SZ
2181 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2182
9c80d176
SZ
2183 /* Only older adapters use IO mapping */
2184 if (adapter->hw.mac.type > e1000_82543 &&
2185 adapter->hw.mac.type < e1000_82571) {
1eca7b82 2186 /* Figure our where our IO BAR is ? */
9c80d176 2187 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
1eca7b82 2188 val = pci_read_config(dev, rid, 4);
87307ba1 2189 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1eca7b82
SZ
2190 adapter->io_rid = rid;
2191 break;
2192 }
2193 rid += 4;
87307ba1
SZ
2194 /* check for 64bit BAR */
2195 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2196 rid += 4;
1eca7b82 2197 }
9c80d176 2198 if (rid >= PCIR_CARDBUSCIS) {
87307ba1
SZ
2199 device_printf(dev, "Unable to locate IO BAR\n");
2200 return (ENXIO);
9c80d176
SZ
2201 }
2202 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2203 &adapter->io_rid, RF_ACTIVE);
2204 if (adapter->ioport == NULL) {
1eca7b82 2205 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2206 "ioport\n");
2207 return (ENXIO);
1eca7b82 2208 }
87307ba1
SZ
2209 adapter->hw.io_base = 0;
2210 adapter->osdep.io_bus_space_tag =
9c80d176 2211 rman_get_bustag(adapter->ioport);
87307ba1 2212 adapter->osdep.io_bus_space_handle =
9c80d176 2213 rman_get_bushandle(adapter->ioport);
1eca7b82
SZ
2214 }
2215
84e26aaa 2216 /*
a835687d
SZ
2217 * Don't enable MSI-X on 82574, see:
2218 * 82574 specification update errata #15
2219 *
84e26aaa 2220 * Don't enable MSI on PCI/PCI-X chips, see:
a835687d
SZ
2221 * 82540 specification update errata #6
2222 * 82545 specification update errata #4
84e26aaa
SZ
2223 *
2224 * Don't enable MSI on 82571/82572, see:
a835687d 2225 * 82571/82572 specification update errata #63
84e26aaa
SZ
2226 */
2227 msi_enable = em_msi_enable;
2228 if (msi_enable &&
2229 (!pci_is_pcie(dev) ||
2230 adapter->hw.mac.type == e1000_82571 ||
2231 adapter->hw.mac.type == e1000_82572))
2232 msi_enable = 0;
2233
2234 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
053f3ae6
SZ
2235 &adapter->intr_rid, &intr_flags);
2236
87ab432b
SZ
2237 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2238 int unshared;
2239
2240 unshared = device_getenv_int(dev, "irq.unshared", 0);
2241 if (!unshared) {
2242 adapter->flags |= EM_FLAG_SHARED_INTR;
2243 if (bootverbose)
2244 device_printf(dev, "IRQ shared\n");
2245 } else {
2246 intr_flags &= ~RF_SHAREABLE;
2247 if (bootverbose)
2248 device_printf(dev, "IRQ unshared\n");
2249 }
2250 }
2251
9c80d176 2252 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
053f3ae6 2253 &adapter->intr_rid, intr_flags);
9c80d176 2254 if (adapter->intr_res == NULL) {
1eca7b82 2255 device_printf(dev, "Unable to allocate bus resource: "
9c80d176
SZ
2256 "interrupt\n");
2257 return (ENXIO);
1eca7b82
SZ
2258 }
2259
9c80d176 2260 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1eca7b82 2261 adapter->hw.back = &adapter->osdep;
a483bd34 2262 return (0);
1eca7b82
SZ
2263}
2264
2265static void
9c80d176 2266em_free_pci_res(struct adapter *adapter)
1eca7b82 2267{
9c80d176 2268 device_t dev = adapter->dev;
1eca7b82 2269
9c80d176
SZ
2270 if (adapter->intr_res != NULL) {
2271 bus_release_resource(dev, SYS_RES_IRQ,
2272 adapter->intr_rid, adapter->intr_res);
1eca7b82 2273 }
9c80d176 2274
053f3ae6
SZ
2275 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2276 pci_release_msi(dev);
2277
9c80d176
SZ
2278 if (adapter->memory != NULL) {
2279 bus_release_resource(dev, SYS_RES_MEMORY,
2280 adapter->memory_rid, adapter->memory);
1eca7b82
SZ
2281 }
2282
9c80d176
SZ
2283 if (adapter->flash != NULL) {
2284 bus_release_resource(dev, SYS_RES_MEMORY,
2285 adapter->flash_rid, adapter->flash);
1eca7b82
SZ
2286 }
2287
9c80d176
SZ
2288 if (adapter->ioport != NULL) {
2289 bus_release_resource(dev, SYS_RES_IOPORT,
2290 adapter->io_rid, adapter->ioport);
1eca7b82
SZ
2291 }
2292}
2293
984263bc 2294static int
2d0e5700 2295em_reset(struct adapter *adapter)
984263bc 2296{
9c80d176
SZ
2297 device_t dev = adapter->dev;
2298 uint16_t rx_buffer_size;
7ea52455 2299
984263bc
MD
2300 /* When hardware is reset, fifo_head is also reset */
2301 adapter->tx_fifo_head = 0;
2302
87307ba1 2303 /* Set up smart power down as default off on newer adapters. */
1eca7b82 2304 if (!em_smart_pwr_down &&
9c80d176
SZ
2305 (adapter->hw.mac.type == e1000_82571 ||
2306 adapter->hw.mac.type == e1000_82572)) {
1eca7b82
SZ
2307 uint16_t phy_tmp = 0;
2308
87307ba1 2309 /* Speed up time to link by disabling smart power down. */
9c80d176
SZ
2310 e1000_read_phy_reg(&adapter->hw,
2311 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1eca7b82 2312 phy_tmp &= ~IGP02E1000_PM_SPD;
9c80d176
SZ
2313 e1000_write_phy_reg(&adapter->hw,
2314 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1eca7b82
SZ
2315 }
2316
7ea52455 2317 /*
87307ba1
SZ
2318 * These parameters control the automatic generation (Tx) and
2319 * response (Rx) to Ethernet PAUSE frames.
7ea52455
SZ
2320 * - High water mark should allow for at least two frames to be
2321 * received after sending an XOFF.
2322 * - Low water mark works best when it is very near the high water mark.
2323 * This allows the receiver to restart by sending XON when it has
9c80d176
SZ
2324 * drained a bit. Here we use an arbitary value of 1500 which will
2325 * restart after one full frame is pulled from the buffer. There
7ea52455
SZ
2326 * could be several smaller frames in the buffer and if so they will
2327 * not trigger the XON until their total number reduces the buffer
2328 * by 1500.
2329 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2330 */
9c80d176
SZ
2331 rx_buffer_size =
2332 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
7ea52455 2333
9c80d176
SZ
2334 adapter->hw.fc.high_water = rx_buffer_size -
2335 roundup2(adapter->max_frame_size, 1024);
2336 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2337
2338 if (adapter->hw.mac.type == e1000_80003es2lan)
2339 adapter->hw.fc.pause_time = 0xFFFF;
1eca7b82 2340 else
9c80d176 2341 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2d0e5700 2342
9c80d176 2343 adapter->hw.fc.send_xon = TRUE;
2d0e5700 2344
9c80d176 2345 adapter->hw.fc.requested_mode = e1000_fc_full;
7ea52455 2346
2d0e5700
SZ
2347 /* Workaround: no TX flow ctrl for PCH */
2348 if (adapter->hw.mac.type == e1000_pchlan)
2349 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2350
2351 /* Override - settings for PCH2LAN, ya its magic :) */
2352 if (adapter->hw.mac.type == e1000_pch2lan) {
2353 adapter->hw.fc.high_water = 0x5C20;
2354 adapter->hw.fc.low_water = 0x5048;
2355 adapter->hw.fc.pause_time = 0x0650;
2356 adapter->hw.fc.refresh_time = 0x0400;
2357
2358 /* Jumbos need adjusted PBA */
2359 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2360 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2361 else
2362 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2363 }
2364
2365 /* Issue a global reset */
2366 e1000_reset_hw(&adapter->hw);
2367 if (adapter->hw.mac.type >= e1000_82544)
2368 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
6d5e2922 2369 em_disable_aspm(adapter);
2d0e5700 2370
9c80d176
SZ
2371 if (e1000_init_hw(&adapter->hw) < 0) {
2372 device_printf(dev, "Hardware Initialization Failed\n");
87307ba1 2373 return (EIO);
984263bc
MD
2374 }
2375
2d0e5700
SZ
2376 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2377 e1000_get_phy_info(&adapter->hw);
9c80d176 2378 e1000_check_for_link(&adapter->hw);
984263bc 2379
87307ba1 2380 return (0);
984263bc
MD
2381}
2382
984263bc 2383static void
9c80d176 2384em_setup_ifp(struct adapter *adapter)
984263bc 2385{
9c80d176 2386 struct ifnet *ifp = &adapter->arpcom.ac_if;
984263bc 2387
9c80d176
SZ
2388 if_initname(ifp, device_get_name(adapter->dev),
2389 device_get_unit(adapter->dev));
984263bc
MD
2390 ifp->if_softc = adapter;
2391 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c80d176 2392 ifp->if_init = em_init;
984263bc
MD
2393 ifp->if_ioctl = em_ioctl;
2394 ifp->if_start = em_start;
9c095379
MD
2395#ifdef DEVICE_POLLING
2396 ifp->if_poll = em_poll;
2397#endif
984263bc 2398 ifp->if_watchdog = em_watchdog;
e26dc3e9 2399 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
19b1d5b8 2400 ifq_set_ready(&ifp->if_snd);
984263bc 2401
9c80d176 2402 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
984263bc 2403
9c80d176
SZ
2404 if (adapter->hw.mac.type >= e1000_82543)
2405 ifp->if_capabilities = IFCAP_HWCSUM;
e095c7aa 2406
9c80d176
SZ
2407 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2408 ifp->if_capenable = ifp->if_capabilities;
984263bc 2409
9c80d176
SZ
2410 if (ifp->if_capenable & IFCAP_TXCSUM)
2411 ifp->if_hwassist = EM_CSUM_FEATURES;
21fa6062 2412
f647ad3d
JS
2413 /*
2414 * Tell the upper layer(s) we support long frames.
2415 */
2416 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
984263bc 2417
87307ba1 2418 /*
984263bc
MD
2419 * Specify the media types supported by this adapter and register
2420 * callbacks to update media and link information
2421 */
9c80d176
SZ
2422 ifmedia_init(&adapter->media, IFM_IMASK,
2423 em_media_change, em_media_status);
2424 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2425 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2426 u_char fiber_type = IFM_1000_SX; /* default type */
2427
2428 if (adapter->hw.mac.type == e1000_82545)
1eca7b82
SZ
2429 fiber_type = IFM_1000_LX;
2430 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
984263bc 2431 0, NULL);
87307ba1 2432 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
984263bc
MD
2433 } else {
2434 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
87307ba1 2435 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
984263bc 2436 0, NULL);
87307ba1 2437 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
984263bc 2438 0, NULL);
87307ba1 2439 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
984263bc 2440 0, NULL);
9c80d176
SZ
2441 if (adapter->hw.phy.type != e1000_phy_ife) {
2442 ifmedia_add(&adapter->media,
2443 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2444 ifmedia_add(&adapter->media,
2445 IFM_ETHER | IFM_1000_T, 0, NULL);
2446 }
984263bc
MD
2447 }
2448 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2449 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
984263bc
MD
2450}
2451
9c80d176
SZ
2452
2453/*
2454 * Workaround for SmartSpeed on 82541 and 82547 controllers
2455 */
984263bc
MD
2456static void
2457em_smartspeed(struct adapter *adapter)
2458{
f647ad3d
JS
2459 uint16_t phy_tmp;
2460
9c80d176
SZ
2461 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2462 adapter->hw.mac.autoneg == 0 ||
2463 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
984263bc
MD
2464 return;
2465
f647ad3d
JS
2466 if (adapter->smartspeed == 0) {
2467 /*
2468 * If Master/Slave config fault is asserted twice,
9c80d176 2469 * we assume back-to-back
f647ad3d 2470 */
9c80d176 2471 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d
JS
2472 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2473 return;
9c80d176 2474 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
f647ad3d 2475 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
9c80d176
SZ
2476 e1000_read_phy_reg(&adapter->hw,
2477 PHY_1000T_CTRL, &phy_tmp);
f647ad3d
JS
2478 if (phy_tmp & CR_1000T_MS_ENABLE) {
2479 phy_tmp &= ~CR_1000T_MS_ENABLE;
9c80d176
SZ
2480 e1000_write_phy_reg(&adapter->hw,
2481 PHY_1000T_CTRL, phy_tmp);
f647ad3d 2482 adapter->smartspeed++;
9c80d176
SZ
2483 if (adapter->hw.mac.autoneg &&
2484 !e1000_phy_setup_autoneg(&adapter->hw) &&
2485 !e1000_read_phy_reg(&adapter->hw,
2486 PHY_CONTROL, &phy_tmp)) {
2487 phy_tmp |= MII_CR_AUTO_NEG_EN |
2488 MII_CR_RESTART_AUTO_NEG;
2489 e1000_write_phy_reg(&adapter->hw,
2490 PHY_CONTROL, phy_tmp);
f647ad3d
JS
2491 }
2492 }
2493 }
87307ba1 2494 return;
f647ad3d
JS
2495 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2496 /* If still no link, perhaps using 2/3 pair cable */
9c80d176 2497 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
f647ad3d 2498 phy_tmp |= CR_1000T_MS_ENABLE;
9c80d176
SZ
2499 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2500 if (adapter->hw.mac.autoneg &&
2501 !e1000_phy_setup_autoneg(&adapter->hw) &&
2502 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2503 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2504 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
f647ad3d
JS
2505 }
2506 }
9c80d176 2507
f647ad3d
JS
2508 /* Restart process after EM_SMARTSPEED_MAX iterations */
2509 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2510 adapter->smartspeed = 0;
984263bc
MD
2511}
2512
9ccd8c1f
JS
2513static int
2514em_dma_malloc(struct adapter *adapter, bus_size_t size,
87307ba1 2515 struct em_dma_alloc *dma)
9ccd8c1f 2516{
9c80d176
SZ
2517 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2518 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2519 &dma->dma_tag, &dma->dma_map,
2520 &dma->dma_paddr);
2521 if (dma->dma_vaddr == NULL)
2522 return ENOMEM;
2523 else
2524 return 0;
9ccd8c1f
JS
2525}
2526
2527static void
2528em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2529{
9c80d176
SZ
2530 if (dma->dma_tag == NULL)
2531 return;
2532 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2533 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2534 bus_dma_tag_destroy(dma->dma_tag);
984263bc
MD
2535}
2536
984263bc 2537static int
9c80d176 2538em_create_tx_ring(struct adapter *adapter)
984263bc 2539{
9c80d176 2540 device_t dev = adapter->dev;
1eca7b82 2541 struct em_buffer *tx_buffer;
1eca7b82
SZ
2542 int error, i;
2543
87307ba1
SZ
2544 adapter->tx_buffer_area =
2545 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2546 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 2547
9c80d176
SZ
2548 /*
2549 * Create DMA tags for tx buffers
2550 */
2551 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2552 1, 0, /* alignment, bounds */
2553 BUS_SPACE_MAXADDR, /* lowaddr */
2554 BUS_SPACE_MAXADDR, /* highaddr */
2555 NULL, NULL, /* filter, filterarg */
2556 EM_TSO_SIZE, /* maxsize */
2557 EM_MAX_SCATTER, /* nsegments */
2558 EM_MAX_SEGSIZE, /* maxsegsize */
2559 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2560 BUS_DMA_ONEBPAGE, /* flags */
2561 &adapter->txtag);
2562 if (error) {
2563 device_printf(dev, "Unable to allocate TX DMA tag\n");
2564 kfree(adapter->tx_buffer_area, M_DEVBUF);
2565 adapter->tx_buffer_area = NULL;
2566 return error;
2567 }
2568
2569 /*
2570 * Create DMA maps for tx buffers
2571 */
1eca7b82 2572 for (i = 0; i < adapter->num_tx_desc; i++) {
9c80d176
SZ
2573 tx_buffer = &adapter->tx_buffer_area[i];
2574
2575 error = bus_dmamap_create(adapter->txtag,
2576 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2577 &tx_buffer->map);
1eca7b82 2578 if (error) {
9c80d176
SZ
2579 device_printf(dev, "Unable to create TX DMA map\n");
2580 em_destroy_tx_ring(adapter, i);
2581 return error;
1eca7b82 2582 }
1eca7b82 2583 }
9c80d176
SZ
2584 return (0);
2585}
9ccd8c1f 2586
9c80d176
SZ
2587static void
2588em_init_tx_ring(struct adapter *adapter)
2589{
2590 /* Clear the old ring contents */
2591 bzero(adapter->tx_desc_base,
2592 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2593
2594 /* Reset state */
87307ba1
SZ
2595 adapter->next_avail_tx_desc = 0;
2596 adapter->next_tx_to_clean = 0;
984263bc 2597 adapter->num_tx_desc_avail = adapter->num_tx_desc;
984263bc
MD
2598}
2599
984263bc 2600static void
9c80d176 2601em_init_tx_unit(struct adapter *adapter)
984263bc 2602{
9c80d176 2603 uint32_t tctl, tarc, tipg = 0;
9ccd8c1f
JS
2604 uint64_t bus_addr;
2605
984263bc 2606 /* Setup the Base and Length of the Tx Descriptor Ring */
9ccd8c1f 2607 bus_addr = adapter->txdma.dma_paddr;
9c80d176
SZ
2608 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2609 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2610 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2611 (uint32_t)(bus_addr >> 32));
2612 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2613 (uint32_t)bus_addr);
984263bc 2614 /* Setup the HW Tx Head and Tail descriptor pointers */
9c80d176
SZ
2615 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2616 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
984263bc 2617
984263bc 2618 /* Set the default values for the Tx Inter Packet Gap timer */
9c80d176
SZ
2619 switch (adapter->hw.mac.type) {
2620 case e1000_82542:
2621 tipg = DEFAULT_82542_TIPG_IPGT;
2622 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2623 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
984263bc 2624 break;
9c80d176
SZ
2625
2626 case e1000_80003es2lan:
2627 tipg = DEFAULT_82543_TIPG_IPGR1;
2628 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2629 E1000_TIPG_IPGR2_SHIFT;
1eca7b82 2630 break;
9c80d176 2631
984263bc 2632 default:
9c80d176
SZ
2633 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2634 adapter->hw.phy.media_type ==
2635 e1000_media_type_internal_serdes)
2636 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
984263bc 2637 else
9c80d176
SZ
2638 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2639 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2640 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2641 break;
2642 }
2643
2644 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
91e8debf
SZ
2645
2646 /* NOTE: 0 is not allowed for TIDV */
2647 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2648 if(adapter->hw.mac.type >= e1000_82540)
2649 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
984263bc 2650
9c80d176
SZ
2651 if (adapter->hw.mac.type == e1000_82571 ||
2652 adapter->hw.mac.type == e1000_82572) {
2653 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2654 tarc |= SPEED_MODE_BIT;
2655 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2656 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2657 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2658 tarc |= 1;
2659 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2660 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2661 tarc |= 1;
2662 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
1eca7b82
SZ
2663 }
2664
984263bc 2665 /* Program the Transmit Control Register */
9c80d176
SZ
2666 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2667 tctl &= ~E1000_TCTL_CT;
2668 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2669 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2670
2671 if (adapter->hw.mac.type >= e1000_82571)
2672 tctl |= E1000_TCTL_MULR;
1eca7b82 2673
87307ba1 2674 /* This write will effectively turn on the transmit unit. */
9c80d176 2675 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
984263bc
MD
2676}
2677
984263bc 2678static void
9c80d176 2679em_destroy_tx_ring(struct adapter *adapter, int ndesc)
984263bc 2680{
f647ad3d
JS
2681 struct em_buffer *tx_buffer;
2682 int i;
984263bc 2683
9c80d176
SZ
2684 if (adapter->tx_buffer_area == NULL)
2685 return;
984263bc 2686
9c80d176
SZ
2687 for (i = 0; i < ndesc; i++) {
2688 tx_buffer = &adapter->tx_buffer_area[i];
1eca7b82 2689
9c80d176
SZ
2690 KKASSERT(tx_buffer->m_head == NULL);
2691 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
9ccd8c1f 2692 }
9c80d176
SZ
2693 bus_dma_tag_destroy(adapter->txtag);
2694
2695 kfree(adapter->tx_buffer_area, M_DEVBUF);
2696 adapter->tx_buffer_area = NULL;
984263bc
MD
2697}
2698
9c80d176
SZ
2699/*
2700 * The offload context needs to be set when we transfer the first
2701 * packet of a particular protocol (TCP/UDP). This routine has been
002b3a05 2702 * enhanced to deal with inserted VLAN headers.
51e6819f
SZ
2703 *
2704 * If the new packet's ether header length, ip header length and
2705 * csum offloading type are same as the previous packet, we should
2706 * avoid allocating a new csum context descriptor; mainly to take
2707 * advantage of the pipeline effect of the TX data read request.
9f60d74b
SZ
2708 *
2709 * This function returns number of TX descrptors allocated for
2710 * csum context.
9c80d176 2711 */
9f60d74b 2712static int
9c80d176
SZ
2713em_txcsum(struct adapter *adapter, struct mbuf *mp,
2714 uint32_t *txd_upper, uint32_t *txd_lower)
984263bc 2715{
9c80d176 2716 struct e1000_context_desc *TXD;
984263bc 2717 struct em_buffer *tx_buffer;
9c80d176 2718 struct ether_vlan_header *eh;
51e6819f
SZ
2719 struct ip *ip;
2720 int curr_txd, ehdrlen, csum_flags;
9c80d176
SZ
2721 uint32_t cmd, hdr_len, ip_hlen;
2722 uint16_t etype;
9c80d176 2723
9c80d176
SZ
2724 /*
2725 * Determine where frame payload starts.
2726 * Jump over vlan headers if already present,
2727 * helpful for QinQ too.
2728 */
252dfd0d 2729 KASSERT(mp->m_len >= ETHER_HDR_LEN,
ed20d0e3 2730 ("em_txcsum_pullup is not called (eh)?"));
9c80d176
SZ
2731 eh = mtod(mp, struct ether_vlan_header *);
2732 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
252dfd0d 2733 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
ed20d0e3 2734 ("em_txcsum_pullup is not called (evh)?"));
9c80d176
SZ
2735 etype = ntohs(eh->evl_proto);
2736 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
984263bc 2737 } else {
9c80d176
SZ
2738 etype = ntohs(eh->evl_encap_proto);
2739 ehdrlen = ETHER_HDR_LEN;
984263bc
MD
2740 }
2741
1eca7b82 2742 /*
002b3a05 2743 * We only support TCP/UDP for IPv4 for the moment.
9c80d176 2744 * TODO: Support SCTP too when it hits the tree.
984263bc 2745 */
51e6819f 2746 if (etype != ETHERTYPE_IP)
9f60d74b 2747 return 0;
002b3a05 2748
51e6819f 2749 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE,
ed20d0e3 2750 ("em_txcsum_pullup is not called (eh+ip_vhl)?"));
9c80d176 2751
51e6819f
SZ
2752 /* NOTE: We could only safely access ip.ip_vhl part */
2753 ip = (struct ip *)(mp->m_data + ehdrlen);
2754 ip_hlen = ip->ip_hl << 2;
984263bc 2755
51e6819f
SZ
2756 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2757
2758 if (adapter->csum_ehlen == ehdrlen &&
2759 adapter->csum_iphlen == ip_hlen &&
2760 adapter->csum_flags == csum_flags) {
2761 /*
2762 * Same csum offload context as the previous packets;
2763 * just return.
2764 */
2765 *txd_upper = adapter->csum_txd_upper;
2766 *txd_lower = adapter->csum_txd_lower;
9f60d74b 2767 return 0;
984263bc
MD
2768 }
2769
51e6819f
SZ
2770 /*
2771 * Setup a new csum offload context.
2772 */
2773
2774 curr_txd = adapter->next_avail_tx_desc;
2775 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2776 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2777
2778 cmd = 0;
2779
2780 /* Setup of IP header checksum. */
2781 if (csum_flags & CSUM_IP) {
2782 /*
2783 * Start offset for header checksum calculation.
2784 * End offset for header checksum calculation.
2785 * Offset of place to put the checksum.
2786 */
2787 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2788 TXD->lower_setup.ip_fields.ipcse =
2789 htole16(ehdrlen + ip_hlen - 1);
2790 TXD->lower_setup.ip_fields.ipcso =
2791 ehdrlen + offsetof(struct ip, ip_sum);
2792 cmd |= E1000_TXD_CMD_IP;
2793 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2794 }
2795 hdr_len = ehdrlen + ip_hlen;
2796
2797 if (csum_flags & CSUM_TCP) {
002b3a05
SZ
2798 /*
2799 * Start offset for payload checksum calculation.
2800 * End offset for payload checksum calculation.
2801 * Offset of place to put the checksum.
2802 */
2803 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2804 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2805 TXD->upper_setup.tcp_fields.tucso =
2806 hdr_len + offsetof(struct tcphdr, th_sum);
2807 cmd |= E1000_TXD_CMD_TCP;
2808 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
51e6819f 2809 } else if (csum_flags & CSUM_UDP) {
002b3a05
SZ
2810 /*
2811 * Start offset for header checksum calculation.
2812 * End offset for header checksum calculation.
2813 * Offset of place to put the checksum.
2814 */
2815 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2816 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2817 TXD->upper_setup.tcp_fields.tucso =
2818 hdr_len + offsetof(struct udphdr, uh_sum);
2819 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
9c80d176
SZ
2820 }
2821
2822 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2823 E1000_TXD_DTYP_D; /* Data descr */
51e6819f
SZ
2824
2825 /* Save the information for this csum offloading context */
2826 adapter->csum_ehlen = ehdrlen;
2827 adapter->csum_iphlen = ip_hlen;
2828 adapter->csum_flags = csum_flags;
2829 adapter->csum_txd_upper = *txd_upper;
2830 adapter->csum_txd_lower = *txd_lower;
2831
9c80d176
SZ
2832 TXD->tcp_seg_setup.data = htole32(0);
2833 TXD->cmd_and_length =
2af74b85 2834 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
984263bc
MD
2835
2836 if (++curr_txd == adapter->num_tx_desc)
2837 curr_txd = 0;
2838
9c80d176 2839 KKASSERT(adapter->num_tx_desc_avail > 0);
984263bc 2840 adapter->num_tx_desc_avail--;
9c80d176 2841
984263bc 2842 adapter->next_avail_tx_desc = curr_txd;
9f60d74b 2843 return 1;
984263bc
MD
2844}
2845
002b3a05
SZ
2846static int
2847em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0)
2848{
2849 struct mbuf *m = *m0;
2850 struct ether_header *eh;
2851 int len;
2852
2853 adapter->tx_csum_try_pullup++;
2854
2855 len = ETHER_HDR_LEN + EM_IPVHL_SIZE;
2856
2857 if (__predict_false(!M_WRITABLE(m))) {
2858 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2859 adapter->tx_csum_drop1++;
2860 m_freem(m);
2861 *m0 = NULL;
2862 return ENOBUFS;
2863 }
2864 eh = mtod(m, struct ether_header *);
2865
2866 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2867 len += EVL_ENCAPLEN;
2868
3752657e 2869 if (m->m_len < len) {
002b3a05
SZ
2870 adapter->tx_csum_drop2++;
2871 m_freem(m);
2872 *m0 = NULL;
2873 return ENOBUFS;
2874 }
2875 return 0;
2876 }
2877
2878 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2879 adapter->tx_csum_pullup1++;
2880 m = m_pullup(m, ETHER_HDR_LEN);
2881 if (m == NULL) {
2882 adapter->tx_csum_pullup1_failed++;
2883 *m0 = NULL;
2884 return ENOBUFS;
2885 }
2886 *m0 = m;
2887 }
2888 eh = mtod(m, struct ether_header *);
2889
2890 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2891 len += EVL_ENCAPLEN;
2892
3752657e 2893 if (m->m_len < len) {
002b3a05
SZ
2894 adapter->tx_csum_pullup2++;
2895 m = m_pullup(m, len);
2896 if (m == NULL) {
2897 adapter->tx_csum_pullup2_failed++;
2898 *m0 = NULL;
2899 return ENOBUFS;
2900 }
2901 *m0 = m;
2902 }
2903 return 0;
2904}
2905
984263bc 2906static void
87307ba1 2907em_txeof(struct adapter *adapter)
984263bc 2908{
9c80d176 2909 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2910 struct em_buffer *tx_buffer;
2911 int first, num_avail;
2912
2913 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2914 return;
984263bc 2915
f647ad3d
JS
2916 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2917 return;
984263bc 2918
9c80d176 2919 num_avail = adapter->num_tx_desc_avail;
87307ba1 2920 first = adapter->next_tx_to_clean;
9c80d176 2921
9f60d74b 2922 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
4e499730 2923 struct e1000_tx_desc *tx_desc;
9f60d74b 2924 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
984263bc 2925
9f60d74b 2926 tx_desc = &adapter->tx_desc_base[dd_idx];
9f60d74b
SZ
2927 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2928 EM_INC_TXDD_IDX(adapter->tx_dd_head);
984263bc 2929
9f60d74b
SZ
2930 if (++dd_idx == adapter->num_tx_desc)
2931 dd_idx = 0;
9c80d176 2932
9f60d74b 2933 while (first != dd_idx) {
edbfa193
SZ
2934 logif(pkt_txclean);
2935
9f60d74b
SZ
2936 num_avail++;
2937
4e499730 2938 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
2939 if (tx_buffer->m_head) {
2940 ifp->if_opackets++;
2941 bus_dmamap_unload(adapter->txtag,
2942 tx_buffer->map);
2943 m_freem(tx_buffer->m_head);
2944 tx_buffer->m_head = NULL;
2945 }
2946
2947 if (++first == adapter->num_tx_desc)
2948 first = 0;
2949 }
87307ba1
SZ
2950 } else {
2951 break;
2952 }
f647ad3d 2953 }
9f60d74b
SZ
2954 adapter->next_tx_to_clean = first;
2955 adapter->num_tx_desc_avail = num_avail;
2956
2957 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2958 adapter->tx_dd_head = 0;
2959 adapter->tx_dd_tail = 0;
2960 }
2961
2962 if (!EM_IS_OACTIVE(adapter)) {
2963 ifp->if_flags &= ~IFF_OACTIVE;
2964
2965 /* All clean, turn off the timer */
2966 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2967 ifp->if_timer = 0;
2968 }
2969}
2970
2971static void
2972em_tx_collect(struct adapter *adapter)
2973{
2974 struct ifnet *ifp = &adapter->arpcom.ac_if;
9f60d74b
SZ
2975 struct em_buffer *tx_buffer;
2976 int tdh, first, num_avail, dd_idx = -1;
2977
2978 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2979 return;
2980
2981 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2982 if (tdh == adapter->next_tx_to_clean)
2983 return;
2984
2985 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2986 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2987
2988 num_avail = adapter->num_tx_desc_avail;
2989 first = adapter->next_tx_to_clean;
2990
2991 while (first != tdh) {
edbfa193
SZ
2992 logif(pkt_txclean);
2993
9f60d74b
SZ
2994 num_avail++;
2995
4e499730 2996 tx_buffer = &adapter->tx_buffer_area[first];
9f60d74b
SZ
2997 if (tx_buffer->m_head) {
2998 ifp->if_opackets++;
2999 bus_dmamap_unload(adapter->txtag,
3000 tx_buffer->map);
3001 m_freem(tx_buffer->m_head);
3002 tx_buffer->m_head = NULL;
3003 }
3004
3005 if (first == dd_idx) {
3006 EM_INC_TXDD_IDX(adapter->tx_dd_head);
3007 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3008 adapter->tx_dd_head = 0;
3009 adapter->tx_dd_tail = 0;
3010 dd_idx = -1;
3011 } else {
3012 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3013 }
3014 }
3015
3016 if (++first == adapter->num_tx_desc)
3017 first = 0;
3018 }
3019 adapter->next_tx_to_clean = first;
9c80d176 3020 adapter->num_tx_desc_avail = num_avail;
984263bc 3021
9f60d74b 3022 if (!EM_IS_OACTIVE(adapter)) {
9c80d176 3023 ifp->if_flags &= ~IFF_OACTIVE;
afa68aa1 3024
9c80d176
SZ
3025 /* All clean, turn off the timer */
3026 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3027 ifp->if_timer = 0;
3028 }
3029}
984263bc 3030
9c80d176
SZ
3031/*
3032 * When Link is lost sometimes there is work still in the TX ring
3033 * which will result in a watchdog, rather than allow that do an
3034 * attempted cleanup and then reinit here. Note that this has been
3035 * seens mostly with fiber adapters.
3036 */
3037static void
3038em_tx_purge(struct adapter *adapter)
3039{
3040 struct ifnet *ifp = &adapter->arpcom.ac_if;
3041
3042 if (!adapter->link_active && ifp->if_timer) {
9f60d74b 3043 em_tx_collect(adapter);
9c80d176
SZ
3044 if (ifp->if_timer) {
3045 if_printf(ifp, "Link lost, TX pending, reinit\n");
f647ad3d 3046 ifp->if_timer = 0;
9c80d176
SZ
3047 em_init(adapter);
3048 }
f647ad3d 3049 }
984263bc
MD
3050}
3051
984263bc 3052static int
9c80d176 3053em_newbuf(struct adapter *adapter, int i, int init)
984263bc 3054{
9c80d176
SZ
3055 struct mbuf *m;
3056 bus_dma_segment_t seg;
3057 bus_dmamap_t map;
9ccd8c1f 3058 struct em_buffer *rx_buffer;
9c80d176
SZ
3059 int error, nseg;
3060
3061 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3062 if (m == NULL) {
3063 adapter->mbuf_cluster_failed++;
3064 if (init) {
3065 if_printf(&adapter->arpcom.ac_if,
3066 "Unable to allocate RX mbuf\n");
984263bc 3067 }
9c80d176 3068 return (ENOBUFS);
984263bc 3069 }
9c80d176 3070 m->m_len = m->m_pkthdr.len = MCLBYTES;
87307ba1 3071
9c80d176
SZ
3072 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3073 m_adj(m, ETHER_ALIGN);
9ccd8c1f 3074
9c80d176
SZ
3075 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3076 adapter->rx_sparemap, m,
3077 &seg, 1, &nseg, BUS_DMA_NOWAIT);
9ccd8c1f 3078 if (error) {
9c80d176
SZ
3079 m_freem(m);
3080 if (init) {
3081 if_printf(&adapter->arpcom.ac_if,
3082 "Unable to load RX mbuf\n");
3083 }
87307ba1 3084 return (error);
9ccd8c1f 3085 }
984263bc 3086
9c80d176
SZ
3087 rx_buffer = &adapter->rx_buffer_area[i];
3088 if (rx_buffer->m_head != NULL)
3089 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3090
3091 map = rx_buffer->map;
3092 rx_buffer->map = adapter->rx_sparemap;
3093 adapter->rx_sparemap = map;
3094
3095 rx_buffer->m_head = m;
3096
3097 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
87307ba1 3098 return (0);
984263bc
MD
3099}
3100
984263bc 3101static int
9c80d176 3102em_create_rx_ring(struct adapter *adapter)
984263bc 3103{
9c80d176 3104 device_t dev = adapter->dev;
9ccd8c1f 3105 struct em_buffer *rx_buffer;
9c80d176
SZ
3106 int i, error;
3107
3108 adapter->rx_buffer_area =
3109 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3110 M_DEVBUF, M_WAITOK | M_ZERO);
9ccd8c1f 3111
9c80d176
SZ
3112 /*
3113 * Create DMA tag for rx buffers
3114 */
3115 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3116 1, 0, /* alignment, bounds */
3117 BUS_SPACE_MAXADDR, /* lowaddr */
3118 BUS_SPACE_MAXADDR, /* highaddr */
3119 NULL, NULL, /* filter, filterarg */
3120 MCLBYTES, /* maxsize */
3121 1, /* nsegments */
3122 MCLBYTES, /* maxsegsize */
3123 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3124 &adapter->rxtag);
87307ba1 3125 if (error) {
9c80d176
SZ
3126 device_printf(dev, "Unable to allocate RX DMA tag\n");
3127 kfree(adapter->rx_buffer_area, M_DEVBUF);
3128 adapter->rx_buffer_area = NULL;
3129 return error;
3130 }
3131
3132 /*
3133 * Create spare DMA map for rx buffers
3134 */
3135 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3136 &adapter->rx_sparemap);
3137 if (error) {
3138 device_printf(dev, "Unable to create spare RX DMA map\n");
3139 bus_dma_tag_destroy(adapter->rxtag);
3140 kfree(adapter->rx_buffer_area, M_DEVBUF);
3141 adapter->rx_buffer_area = NULL;
3142 return error;
9ccd8c1f 3143 }
9c80d176
SZ
3144
3145 /*
3146 * Create DMA maps for rx buffers
3147 */
3148 for (i = 0; i < adapter->num_rx_desc; i++) {
3149 rx_buffer = &adapter->rx_buffer_area[i];
3150
3151 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
9ccd8c1f 3152 &rx_buffer->map);
87307ba1 3153 if (error) {
9c80d176
SZ
3154 device_printf(dev, "Unable to create RX DMA map\n");
3155 em_destroy_rx_ring(adapter, i);
3156 return error;
9ccd8c1f 3157 }
984263bc 3158 }
87307ba1 3159 return (0);
984263bc
MD
3160}
3161
984263bc 3162static int
9c80d176 3163em_init_rx_ring(struct adapter *adapter)
984263bc 3164{
9c80d176 3165 int i, error;
984263bc 3166
9c80d176 3167 /* Reset descriptor ring */
87307ba1 3168 bzero(adapter->rx_desc_base,
9c80d176 3169 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
87307ba1 3170
9c80d176
SZ
3171 /* Allocate new ones. */
3172 for (i = 0; i < adapter->num_rx_desc; i++) {
3173 error = em_newbuf(adapter, i, 1);
3174 if (error)
3175 return (error);
3176 }
984263bc
MD
3177
3178 /* Setup our descriptor pointers */
f647ad3d 3179 adapter->next_rx_desc_to_check = 0;
87307ba1
SZ
3180
3181 return (0);
984263bc
MD
3182}
3183
984263bc 3184static void
9c80d176 3185em_init_rx_unit(struct adapter *adapter)
984263bc 3186{
9c80d176 3187 struct ifnet *ifp = &adapter->arpcom.ac_if;
f647ad3d 3188 uint64_t bus_addr;
2d0e5700 3189 uint32_t rctl;
984263bc 3190
87307ba1
SZ
3191 /*
3192 * Make sure receives are disabled while setting
3193 * up the descriptor ring
3194 */
9c80d176
SZ
3195 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3196 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
984263bc 3197
9c80d176 3198 if (adapter->hw.mac.type >= e1000_82540) {
2d0e5700
SZ
3199 uint32_t itr;
3200
9c80d176
SZ
3201 /*
3202 * Set the interrupt throttling rate. Value is calculated
3203 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3204 */
2d0e5700
SZ
3205 if (adapter->int_throttle_ceil)
3206 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3207 else
3208 itr = 0;
3209 em_set_itr(adapter, itr);
f647ad3d 3210 }
984263bc 3211
9c80d176
SZ
3212 /* Disable accelerated ackknowledge */
3213 if (adapter->hw.mac.type == e1000_82574) {
3214 E1000_WRITE_REG(&adapter->hw,
3215 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3216 }
3217
2d0e5700
SZ
3218 /* Receive Checksum Offload for TCP and UDP */
3219 if (ifp->if_capenable & IFCAP_RXCSUM) {
3220 uint32_t rxcsum;
3221
3222 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3223 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3224 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3225 }
3226
3227 /*
3228 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3229 * long latencies are observed, like Lenovo X60. This
3230 * change eliminates the problem, but since having positive
3231 * values in RDTR is a known source of problems on other
3232 * platforms another solution is being sought.
3233 */
3234 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3235 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3236 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3237 }
3238
3239 /*
3240 * Setup the Base and Length of the Rx Descriptor Ring
3241 */
9ccd8c1f 3242 bus_addr = adapter->rxdma.dma_paddr;
9c80d176
SZ
3243 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3244 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3245 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3246 (uint32_t)(bus_addr >> 32));
3247 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3248 (uint32_t)bus_addr);
984263bc 3249
2d0e5700
SZ
3250 /*
3251 * Setup the HW Rx Head and Tail Descriptor Pointers
3252 */
3253 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3254 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3255
3256 /* Set early receive threshold on appropriate hw */
3257 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3258 (adapter->hw.mac.type == e1000_pch2lan) ||
3259 (adapter->hw.mac.type == e1000_ich10lan)) &&
3260 (ifp->if_mtu > ETHERMTU)) {
3261 uint32_t rxdctl;
3262
3263 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3264 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3265 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13));
3266<