em/emx: Update comment concerning errata number
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
8434a83b 68#include "opt_rss.h"
e6cde6e6 69#include "opt_emx.h"
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70
71#include <sys/param.h>
72#include <sys/bus.h>
73#include <sys/endian.h>
74#include <sys/interrupt.h>
75#include <sys/kernel.h>
76#include <sys/ktr.h>
77#include <sys/malloc.h>
78#include <sys/mbuf.h>
79#include <sys/proc.h>
80#include <sys/rman.h>
81#include <sys/serialize.h>
bc197380 82#include <sys/serialize2.h>
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83#include <sys/socket.h>
84#include <sys/sockio.h>
85#include <sys/sysctl.h>
86#include <sys/systm.h>
87
88#include <net/bpf.h>
89#include <net/ethernet.h>
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/if_dl.h>
93#include <net/if_media.h>
94#include <net/ifq_var.h>
89d8e73d 95#include <net/toeplitz.h>
9cc86e17 96#include <net/toeplitz2.h>
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97#include <net/vlan/if_vlan_var.h>
98#include <net/vlan/if_vlan_ether.h>
b3a7093f 99#include <net/if_poll.h>
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100
101#include <netinet/in_systm.h>
102#include <netinet/in.h>
103#include <netinet/ip.h>
104#include <netinet/tcp.h>
105#include <netinet/udp.h>
106
107#include <bus/pci/pcivar.h>
108#include <bus/pci/pcireg.h>
109
110#include <dev/netif/ig_hal/e1000_api.h>
111#include <dev/netif/ig_hal/e1000_82571.h>
112#include <dev/netif/emx/if_emx.h>
113
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114#ifdef EMX_RSS_DEBUG
115#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116do { \
89d8e73d 117 if (sc->rss_debug >= lvl) \
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118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119} while (0)
120#else /* !EMX_RSS_DEBUG */
121#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122#endif /* EMX_RSS_DEBUG */
123
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124#define EMX_TX_SERIALIZE 1
125#define EMX_RX_SERIALIZE 2
126
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127#define EMX_NAME "Intel(R) PRO/1000 "
128
129#define EMX_DEVICE(id) \
130 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
131#define EMX_DEVICE_NULL { 0, 0, NULL }
132
133static const struct emx_device {
134 uint16_t vid;
135 uint16_t did;
136 const char *desc;
137} emx_devices[] = {
138 EMX_DEVICE(82571EB_COPPER),
139 EMX_DEVICE(82571EB_FIBER),
140 EMX_DEVICE(82571EB_SERDES),
141 EMX_DEVICE(82571EB_SERDES_DUAL),
142 EMX_DEVICE(82571EB_SERDES_QUAD),
143 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 144 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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145 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
146 EMX_DEVICE(82571EB_QUAD_FIBER),
147 EMX_DEVICE(82571PT_QUAD_COPPER),
148
149 EMX_DEVICE(82572EI_COPPER),
150 EMX_DEVICE(82572EI_FIBER),
151 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82572EI),
153
154 EMX_DEVICE(82573E),
155 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(82573L),
157
158 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
160 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
161 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
162
163 EMX_DEVICE(82574L),
2d0e5700 164 EMX_DEVICE(82574LA),
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165
166 /* required last entry */
167 EMX_DEVICE_NULL
168};
169
170static int emx_probe(device_t);
171static int emx_attach(device_t);
172static int emx_detach(device_t);
173static int emx_shutdown(device_t);
174static int emx_suspend(device_t);
175static int emx_resume(device_t);
176
177static void emx_init(void *);
178static void emx_stop(struct emx_softc *);
179static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
180static void emx_start(struct ifnet *);
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181#ifdef IFPOLL_ENABLE
182static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
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183#endif
184static void emx_watchdog(struct ifnet *);
185static void emx_media_status(struct ifnet *, struct ifmediareq *);
186static int emx_media_change(struct ifnet *);
187static void emx_timer(void *);
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188static void emx_serialize(struct ifnet *, enum ifnet_serialize);
189static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
190static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
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191#ifdef INVARIANTS
192static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 boolean_t);
194#endif
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195
196static void emx_intr(void *);
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197static void emx_intr_mask(void *);
198static void emx_intr_body(struct emx_softc *, boolean_t);
c39e3a1f 199static void emx_rxeof(struct emx_softc *, int, int);
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200static void emx_txeof(struct emx_softc *);
201static void emx_tx_collect(struct emx_softc *);
202static void emx_tx_purge(struct emx_softc *);
203static void emx_enable_intr(struct emx_softc *);
204static void emx_disable_intr(struct emx_softc *);
205
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206static int emx_dma_alloc(struct emx_softc *);
207static void emx_dma_free(struct emx_softc *);
5330213c 208static void emx_init_tx_ring(struct emx_softc *);
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209static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
210static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 211static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 212static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 213static void emx_destroy_tx_ring(struct emx_softc *, int);
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214static void emx_destroy_rx_ring(struct emx_softc *,
215 struct emx_rxdata *, int);
216static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 217static int emx_encap(struct emx_softc *, struct mbuf **);
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218static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
219static int emx_txcsum(struct emx_softc *, struct mbuf *,
220 uint32_t *, uint32_t *);
221
222static int emx_is_valid_eaddr(const uint8_t *);
2d0e5700 223static int emx_reset(struct emx_softc *);
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224static void emx_setup_ifp(struct emx_softc *);
225static void emx_init_tx_unit(struct emx_softc *);
226static void emx_init_rx_unit(struct emx_softc *);
227static void emx_update_stats(struct emx_softc *);
228static void emx_set_promisc(struct emx_softc *);
229static void emx_disable_promisc(struct emx_softc *);
230static void emx_set_multi(struct emx_softc *);
231static void emx_update_link_status(struct emx_softc *);
232static void emx_smartspeed(struct emx_softc *);
2d0e5700 233static void emx_set_itr(struct emx_softc *, uint32_t);
6d5e2922 234static void emx_disable_aspm(struct emx_softc *);
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235
236static void emx_print_debug_info(struct emx_softc *);
237static void emx_print_nvm_info(struct emx_softc *);
238static void emx_print_hw_stats(struct emx_softc *);
239
240static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
241static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
242static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
243static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
244static void emx_add_sysctl(struct emx_softc *);
245
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246static void emx_serialize_skipmain(struct emx_softc *);
247static void emx_deserialize_skipmain(struct emx_softc *);
248
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249/* Management and WOL Support */
250static void emx_get_mgmt(struct emx_softc *);
251static void emx_rel_mgmt(struct emx_softc *);
252static void emx_get_hw_control(struct emx_softc *);
253static void emx_rel_hw_control(struct emx_softc *);
254static void emx_enable_wol(device_t);
255
256static device_method_t emx_methods[] = {
257 /* Device interface */
258 DEVMETHOD(device_probe, emx_probe),
259 DEVMETHOD(device_attach, emx_attach),
260 DEVMETHOD(device_detach, emx_detach),
261 DEVMETHOD(device_shutdown, emx_shutdown),
262 DEVMETHOD(device_suspend, emx_suspend),
263 DEVMETHOD(device_resume, emx_resume),
264 { 0, 0 }
265};
266
267static driver_t emx_driver = {
268 "emx",
269 emx_methods,
270 sizeof(struct emx_softc),
271};
272
273static devclass_t emx_devclass;
274
275DECLARE_DUMMY_MODULE(if_emx);
276MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
aa2b9d05 277DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
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278
279/*
280 * Tunables
281 */
282static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
283static int emx_rxd = EMX_DEFAULT_RXD;
284static int emx_txd = EMX_DEFAULT_TXD;
704b6287 285static int emx_smart_pwr_down = 0;
724cbff8 286static int emx_rxr = 0;
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287
288/* Controls whether promiscuous also shows bad packets */
b4d8c36b 289static int emx_debug_sbp = 0;
5330213c 290
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291static int emx_82573_workaround = 1;
292static int emx_msi_enable = 1;
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293
294TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
295TUNABLE_INT("hw.emx.rxd", &emx_rxd);
724cbff8 296TUNABLE_INT("hw.emx.rxr", &emx_rxr);
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297TUNABLE_INT("hw.emx.txd", &emx_txd);
298TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
299TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
300TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
704b6287 301TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
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302
303/* Global used in WOL setup with multiport cards */
304static int emx_global_quad_port_a = 0;
305
306/* Set this to one to display debug statistics */
307static int emx_display_debug_stats = 0;
308
309#if !defined(KTR_IF_EMX)
310#define KTR_IF_EMX KTR_ALL
311#endif
312KTR_INFO_MASTER(if_emx);
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313KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
314KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
315KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
316KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
317KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
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318#define logif(name) KTR_LOG(if_emx_ ## name)
319
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320static __inline void
321emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
322{
323 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 324 /* DD bit must be cleared */
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325 rxd->rxd_staterr = 0;
326}
327
328static __inline void
329emx_rxcsum(uint32_t staterr, struct mbuf *mp)
330{
331 /* Ignore Checksum bit is set */
332 if (staterr & E1000_RXD_STAT_IXSM)
333 return;
334
335 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
336 E1000_RXD_STAT_IPCS)
337 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
338
339 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
340 E1000_RXD_STAT_TCPCS) {
341 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
342 CSUM_PSEUDO_HDR |
343 CSUM_FRAG_NOT_CHECKED;
344 mp->m_pkthdr.csum_data = htons(0xffff);
345 }
346}
347
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348static __inline struct pktinfo *
349emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
350 uint32_t mrq, uint32_t hash, uint32_t staterr)
351{
352 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
353 case EMX_RXDMRQ_IPV4_TCP:
354 pi->pi_netisr = NETISR_IP;
355 pi->pi_flags = 0;
356 pi->pi_l3proto = IPPROTO_TCP;
357 break;
358
359 case EMX_RXDMRQ_IPV6_TCP:
360 pi->pi_netisr = NETISR_IPV6;
361 pi->pi_flags = 0;
362 pi->pi_l3proto = IPPROTO_TCP;
363 break;
364
365 case EMX_RXDMRQ_IPV4:
366 if (staterr & E1000_RXD_STAT_IXSM)
367 return NULL;
368
369 if ((staterr &
370 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
371 E1000_RXD_STAT_TCPCS) {
372 pi->pi_netisr = NETISR_IP;
373 pi->pi_flags = 0;
374 pi->pi_l3proto = IPPROTO_UDP;
375 break;
376 }
377 /* FALL THROUGH */
378 default:
379 return NULL;
380 }
381
382 m->m_flags |= M_HASH;
383 m->m_pkthdr.hash = toeplitz_hash(hash);
384 return pi;
385}
386
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387static int
388emx_probe(device_t dev)
389{
390 const struct emx_device *d;
391 uint16_t vid, did;
392
393 vid = pci_get_vendor(dev);
394 did = pci_get_device(dev);
395
396 for (d = emx_devices; d->desc != NULL; ++d) {
397 if (vid == d->vid && did == d->did) {
398 device_set_desc(dev, d->desc);
399 device_set_async_attach(dev, TRUE);
400 return 0;
401 }
402 }
403 return ENXIO;
404}
405
406static int
407emx_attach(device_t dev)
408{
409 struct emx_softc *sc = device_get_softc(dev);
410 struct ifnet *ifp = &sc->arpcom.ac_if;
d01335e8 411 int error = 0, i, throttle, msi_enable;
704b6287 412 u_int intr_flags;
2d0e5700 413 uint16_t eeprom_data, device_id, apme_mask;
4cb541ae 414 driver_intr_t *intr_func;
5330213c 415
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416 lwkt_serialize_init(&sc->main_serialize);
417 lwkt_serialize_init(&sc->tx_serialize);
418 for (i = 0; i < EMX_NRX_RING; ++i)
419 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
420
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421 i = 0;
422 sc->serializes[i++] = &sc->main_serialize;
423 sc->serializes[i++] = &sc->tx_serialize;
424 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
425 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
426 KKASSERT(i == EMX_NSERIALIZE);
427
c2022416 428 callout_init_mp(&sc->timer);
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429
430 sc->dev = sc->osdep.dev = dev;
431
432 /*
433 * Determine hardware and mac type
434 */
435 sc->hw.vendor_id = pci_get_vendor(dev);
436 sc->hw.device_id = pci_get_device(dev);
437 sc->hw.revision_id = pci_get_revid(dev);
438 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
439 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
440
441 if (e1000_set_mac_type(&sc->hw))
442 return ENXIO;
443
444 /* Enable bus mastering */
445 pci_enable_busmaster(dev);
446
447 /*
448 * Allocate IO memory
449 */
450 sc->memory_rid = EMX_BAR_MEM;
451 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
452 &sc->memory_rid, RF_ACTIVE);
453 if (sc->memory == NULL) {
454 device_printf(dev, "Unable to allocate bus resource: memory\n");
455 error = ENXIO;
456 goto fail;
457 }
458 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
459 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
460
461 /* XXX This is quite goofy, it is not actually used */
462 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
463
464 /*
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465 * Don't enable MSI-X on 82574, see:
466 * 82574 specification update errata #15
467 *
d01335e8 468 * Don't enable MSI on 82571/82572, see:
a835687d 469 * 82571/82572 specification update errata #63
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470 */
471 msi_enable = emx_msi_enable;
472 if (msi_enable &&
473 (sc->hw.mac.type == e1000_82571 ||
474 sc->hw.mac.type == e1000_82572))
475 msi_enable = 0;
476
477 /*
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478 * Allocate interrupt
479 */
d01335e8 480 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
7fb43956 481 &sc->intr_rid, &intr_flags);
704b6287 482
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483 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
484 int unshared;
485
486 unshared = device_getenv_int(dev, "irq.unshared", 0);
487 if (!unshared) {
488 sc->flags |= EMX_FLAG_SHARED_INTR;
489 if (bootverbose)
490 device_printf(dev, "IRQ shared\n");
491 } else {
492 intr_flags &= ~RF_SHAREABLE;
493 if (bootverbose)
494 device_printf(dev, "IRQ unshared\n");
495 }
496 }
497
5330213c 498 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
704b6287 499 intr_flags);
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500 if (sc->intr_res == NULL) {
501 device_printf(dev, "Unable to allocate bus resource: "
502 "interrupt\n");
503 error = ENXIO;
504 goto fail;
505 }
506
507 /* Save PCI command register for Shared Code */
508 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
509 sc->hw.back = &sc->osdep;
510
511 /* Do Shared Code initialization */
512 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
513 device_printf(dev, "Setup of Shared code failed\n");
514 error = ENXIO;
515 goto fail;
516 }
517 e1000_get_bus_info(&sc->hw);
518
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519 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
520 sc->hw.phy.autoneg_wait_to_complete = FALSE;
521 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
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522
523 /*
524 * Interrupt throttle rate
525 */
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526 throttle = device_getenv_int(dev, "int_throttle_ceil",
527 emx_int_throttle_ceil);
528 if (throttle == 0) {
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529 sc->int_throttle_ceil = 0;
530 } else {
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531 if (throttle < 0)
532 throttle = EMX_DEFAULT_ITR;
533
534 /* Recalculate the tunable value to get the exact frequency. */
535 throttle = 1000000000 / 256 / throttle;
536
537 /* Upper 16bits of ITR is reserved and should be zero */
538 if (throttle & 0xffff0000)
539 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
540
541 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
542 }
543
544 e1000_init_script_state_82541(&sc->hw, TRUE);
545 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
546
547 /* Copper options */
548 if (sc->hw.phy.media_type == e1000_media_type_copper) {
549 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
550 sc->hw.phy.disable_polarity_correction = FALSE;
551 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
552 }
553
554 /* Set the frame limits assuming standard ethernet sized frames. */
555 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
556 sc->min_frame_size = ETHER_MIN_LEN;
557
558 /* This controls when hardware reports transmit completion status. */
559 sc->hw.mac.report_tx_early = 1;
560
65c7a6af 561 /* Calculate # of RX rings */
724cbff8 562 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
a317449e 563 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
65c7a6af 564
071699f8
SZ
565 /* Allocate RX/TX rings' busdma(9) stuffs */
566 error = emx_dma_alloc(sc);
567 if (error)
e5b3bcc4 568 goto fail;
e5b3bcc4 569
2d0e5700
SZ
570 /* Allocate multicast array memory. */
571 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
572 M_DEVBUF, M_WAITOK);
573
574 /* Indicate SOL/IDER usage */
575 if (e1000_check_reset_block(&sc->hw)) {
576 device_printf(dev,
577 "PHY reset is blocked due to SOL/IDER session.\n");
578 }
579
580 /*
581 * Start from a known state, this is important in reading the
582 * nvm and mac from that.
583 */
584 e1000_reset_hw(&sc->hw);
585
5330213c
SZ
586 /* Make sure we have a good EEPROM before we read from it */
587 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
588 /*
589 * Some PCI-E parts fail the first check due to
590 * the link being in sleep state, call it again,
591 * if it fails a second time its a real issue.
592 */
593 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
594 device_printf(dev,
595 "The EEPROM Checksum Is Not Valid\n");
596 error = EIO;
597 goto fail;
598 }
599 }
600
5330213c
SZ
601 /* Copy the permanent MAC address out of the EEPROM */
602 if (e1000_read_mac_addr(&sc->hw) < 0) {
603 device_printf(dev, "EEPROM read error while reading MAC"
604 " address\n");
605 error = EIO;
606 goto fail;
607 }
608 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
609 device_printf(dev, "Invalid MAC address\n");
610 error = EIO;
611 goto fail;
612 }
613
5330213c
SZ
614 /* Determine if we have to control management hardware */
615 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
616
617 /*
618 * Setup Wake-on-Lan
619 */
2d0e5700
SZ
620 apme_mask = EMX_EEPROM_APME;
621 eeprom_data = 0;
5330213c 622 switch (sc->hw.mac.type) {
2d0e5700
SZ
623 case e1000_82573:
624 sc->has_amt = 1;
625 /* FALL THROUGH */
626
5330213c 627 case e1000_82571:
2d0e5700 628 case e1000_82572:
5330213c
SZ
629 case e1000_80003es2lan:
630 if (sc->hw.bus.func == 1) {
631 e1000_read_nvm(&sc->hw,
632 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
633 } else {
634 e1000_read_nvm(&sc->hw,
635 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
636 }
5330213c
SZ
637 break;
638
639 default:
2d0e5700
SZ
640 e1000_read_nvm(&sc->hw,
641 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
5330213c
SZ
642 break;
643 }
2d0e5700
SZ
644 if (eeprom_data & apme_mask)
645 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
646
5330213c
SZ
647 /*
648 * We have the eeprom settings, now apply the special cases
649 * where the eeprom may be wrong or the board won't support
650 * wake on lan on a particular port
651 */
652 device_id = pci_get_device(dev);
653 switch (device_id) {
654 case E1000_DEV_ID_82571EB_FIBER:
655 /*
656 * Wake events only supported on port A for dual fiber
657 * regardless of eeprom setting
658 */
659 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
660 E1000_STATUS_FUNC_1)
661 sc->wol = 0;
662 break;
663
664 case E1000_DEV_ID_82571EB_QUAD_COPPER:
665 case E1000_DEV_ID_82571EB_QUAD_FIBER:
666 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
667 /* if quad port sc, disable WoL on all but port A */
668 if (emx_global_quad_port_a != 0)
669 sc->wol = 0;
670 /* Reset for multiple quad port adapters */
671 if (++emx_global_quad_port_a == 4)
672 emx_global_quad_port_a = 0;
673 break;
674 }
675
676 /* XXX disable wol */
677 sc->wol = 0;
678
2d0e5700
SZ
679 /* Setup OS specific network interface */
680 emx_setup_ifp(sc);
681
682 /* Add sysctl tree, must after em_setup_ifp() */
683 emx_add_sysctl(sc);
684
685 /* Reset the hardware */
686 error = emx_reset(sc);
687 if (error) {
688 device_printf(dev, "Unable to reset the hardware\n");
689 goto fail;
690 }
691
692 /* Initialize statistics */
693 emx_update_stats(sc);
694
695 sc->hw.mac.get_link_status = 1;
696 emx_update_link_status(sc);
697
5330213c
SZ
698 sc->spare_tx_desc = EMX_TX_SPARE;
699
700 /*
701 * Keep following relationship between spare_tx_desc, oact_tx_desc
702 * and tx_int_nsegs:
703 * (spare_tx_desc + EMX_TX_RESERVED) <=
704 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
705 */
706 sc->oact_tx_desc = sc->num_tx_desc / 8;
707 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
708 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
709 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
710 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
711
712 sc->tx_int_nsegs = sc->num_tx_desc / 16;
713 if (sc->tx_int_nsegs < sc->oact_tx_desc)
714 sc->tx_int_nsegs = sc->oact_tx_desc;
715
2d0e5700
SZ
716 /* Non-AMT based hardware can now take control from firmware */
717 if (sc->has_manage && !sc->has_amt)
718 emx_get_hw_control(sc);
719
4cb541ae
SZ
720 /*
721 * Missing Interrupt Following ICR read:
722 *
a835687d
SZ
723 * 82571/82572 specification update errata #76
724 * 82573 specification update errata #31
725 * 82574 specification update errata #12
4cb541ae
SZ
726 */
727 intr_func = emx_intr;
728 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
729 (sc->hw.mac.type == e1000_82571 ||
730 sc->hw.mac.type == e1000_82572 ||
731 sc->hw.mac.type == e1000_82573 ||
732 sc->hw.mac.type == e1000_82574))
733 intr_func = emx_intr_mask;
734
735 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
6d435846 736 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ
737 if (error) {
738 device_printf(dev, "Failed to register interrupt handler");
739 ether_ifdetach(&sc->arpcom.ac_if);
740 goto fail;
741 }
742
704b6287 743 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
5330213c
SZ
744 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
745 return (0);
746fail:
747 emx_detach(dev);
748 return (error);
749}
750
751static int
752emx_detach(device_t dev)
753{
754 struct emx_softc *sc = device_get_softc(dev);
755
756 if (device_is_attached(dev)) {
757 struct ifnet *ifp = &sc->arpcom.ac_if;
758
6d435846 759 ifnet_serialize_all(ifp);
5330213c
SZ
760
761 emx_stop(sc);
762
763 e1000_phy_hw_reset(&sc->hw);
764
765 emx_rel_mgmt(sc);
2d0e5700 766 emx_rel_hw_control(sc);
5330213c
SZ
767
768 if (sc->wol) {
769 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
770 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
771 emx_enable_wol(dev);
772 }
773
774 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
775
6d435846 776 ifnet_deserialize_all(ifp);
5330213c
SZ
777
778 ether_ifdetach(ifp);
2d0e5700
SZ
779 } else {
780 emx_rel_hw_control(sc);
5330213c
SZ
781 }
782 bus_generic_detach(dev);
783
784 if (sc->intr_res != NULL) {
785 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
786 sc->intr_res);
787 }
788
7fb43956 789 if (sc->intr_type == PCI_INTR_TYPE_MSI)
704b6287
SZ
790 pci_release_msi(dev);
791
5330213c
SZ
792 if (sc->memory != NULL) {
793 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
794 sc->memory);
795 }
796
071699f8 797 emx_dma_free(sc);
5330213c
SZ
798
799 /* Free sysctl tree */
800 if (sc->sysctl_tree != NULL)
801 sysctl_ctx_free(&sc->sysctl_ctx);
802
803 return (0);
804}
805
806static int
807emx_shutdown(device_t dev)
808{
809 return emx_suspend(dev);
810}
811
812static int
813emx_suspend(device_t dev)
814{
815 struct emx_softc *sc = device_get_softc(dev);
816 struct ifnet *ifp = &sc->arpcom.ac_if;
817
6d435846 818 ifnet_serialize_all(ifp);
5330213c
SZ
819
820 emx_stop(sc);
821
822 emx_rel_mgmt(sc);
2d0e5700 823 emx_rel_hw_control(sc);
5330213c 824
2d0e5700 825 if (sc->wol) {
5330213c
SZ
826 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
827 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
828 emx_enable_wol(dev);
2d0e5700 829 }
5330213c 830
6d435846 831 ifnet_deserialize_all(ifp);
5330213c
SZ
832
833 return bus_generic_suspend(dev);
834}
835
836static int
837emx_resume(device_t dev)
838{
839 struct emx_softc *sc = device_get_softc(dev);
840 struct ifnet *ifp = &sc->arpcom.ac_if;
841
6d435846 842 ifnet_serialize_all(ifp);
5330213c
SZ
843
844 emx_init(sc);
845 emx_get_mgmt(sc);
846 if_devstart(ifp);
847
6d435846 848 ifnet_deserialize_all(ifp);
5330213c
SZ
849
850 return bus_generic_resume(dev);
851}
852
853static void
854emx_start(struct ifnet *ifp)
855{
856 struct emx_softc *sc = ifp->if_softc;
857 struct mbuf *m_head;
858
6d435846 859 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ
860
861 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
862 return;
863
864 if (!sc->link_active) {
865 ifq_purge(&ifp->if_snd);
866 return;
867 }
868
869 while (!ifq_is_empty(&ifp->if_snd)) {
870 /* Now do we at least have a minimal? */
871 if (EMX_IS_OACTIVE(sc)) {
872 emx_tx_collect(sc);
873 if (EMX_IS_OACTIVE(sc)) {
874 ifp->if_flags |= IFF_OACTIVE;
875 sc->no_tx_desc_avail1++;
876 break;
877 }
878 }
879
880 logif(pkt_txqueue);
881 m_head = ifq_dequeue(&ifp->if_snd, NULL);
882 if (m_head == NULL)
883 break;
884
885 if (emx_encap(sc, &m_head)) {
886 ifp->if_oerrors++;
887 emx_tx_collect(sc);
888 continue;
889 }
890
891 /* Send a copy of the frame to the BPF listener */
892 ETHER_BPF_MTAP(ifp, m_head);
893
894 /* Set timeout in case hardware has problems transmitting. */
895 ifp->if_timer = EMX_TX_TIMEOUT;
896 }
897}
898
899static int
900emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
901{
902 struct emx_softc *sc = ifp->if_softc;
903 struct ifreq *ifr = (struct ifreq *)data;
904 uint16_t eeprom_data = 0;
905 int max_frame_size, mask, reinit;
906 int error = 0;
907
2c9effcf 908 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
909
910 switch (command) {
911 case SIOCSIFMTU:
912 switch (sc->hw.mac.type) {
913 case e1000_82573:
914 /*
915 * 82573 only supports jumbo frames
916 * if ASPM is disabled.
917 */
918 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
919 &eeprom_data);
920 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
921 max_frame_size = ETHER_MAX_LEN;
922 break;
923 }
924 /* FALL THROUGH */
925
926 /* Limit Jumbo Frame size */
927 case e1000_82571:
928 case e1000_82572:
929 case e1000_82574:
930 case e1000_80003es2lan:
931 max_frame_size = 9234;
932 break;
933
934 default:
935 max_frame_size = MAX_JUMBO_FRAME_SIZE;
936 break;
937 }
938 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
939 ETHER_CRC_LEN) {
940 error = EINVAL;
941 break;
942 }
943
944 ifp->if_mtu = ifr->ifr_mtu;
945 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
946 ETHER_CRC_LEN;
947
948 if (ifp->if_flags & IFF_RUNNING)
949 emx_init(sc);
950 break;
951
952 case SIOCSIFFLAGS:
953 if (ifp->if_flags & IFF_UP) {
954 if ((ifp->if_flags & IFF_RUNNING)) {
955 if ((ifp->if_flags ^ sc->if_flags) &
956 (IFF_PROMISC | IFF_ALLMULTI)) {
957 emx_disable_promisc(sc);
958 emx_set_promisc(sc);
959 }
960 } else {
961 emx_init(sc);
962 }
963 } else if (ifp->if_flags & IFF_RUNNING) {
964 emx_stop(sc);
965 }
966 sc->if_flags = ifp->if_flags;
967 break;
968
969 case SIOCADDMULTI:
970 case SIOCDELMULTI:
971 if (ifp->if_flags & IFF_RUNNING) {
972 emx_disable_intr(sc);
973 emx_set_multi(sc);
b3a7093f
SZ
974#ifdef IFPOLL_ENABLE
975 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ
976#endif
977 emx_enable_intr(sc);
978 }
979 break;
980
981 case SIOCSIFMEDIA:
982 /* Check SOL/IDER usage */
983 if (e1000_check_reset_block(&sc->hw)) {
984 device_printf(sc->dev, "Media change is"
985 " blocked due to SOL/IDER session.\n");
986 break;
987 }
988 /* FALL THROUGH */
989
990 case SIOCGIFMEDIA:
991 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
992 break;
993
994 case SIOCSIFCAP:
995 reinit = 0;
996 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
997 if (mask & IFCAP_HWCSUM) {
998 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
999 reinit = 1;
1000 }
1001 if (mask & IFCAP_VLAN_HWTAGGING) {
1002 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1003 reinit = 1;
1004 }
13890b61 1005 if (mask & IFCAP_RSS)
8434a83b 1006 ifp->if_capenable ^= IFCAP_RSS;
5330213c
SZ
1007 if (reinit && (ifp->if_flags & IFF_RUNNING))
1008 emx_init(sc);
1009 break;
1010
1011 default:
1012 error = ether_ioctl(ifp, command, data);
1013 break;
1014 }
1015 return (error);
1016}
1017
1018static void
1019emx_watchdog(struct ifnet *ifp)
1020{
1021 struct emx_softc *sc = ifp->if_softc;
1022
2c9effcf 1023 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1024
1025 /*
1026 * The timer is set to 5 every time start queues a packet.
1027 * Then txeof keeps resetting it as long as it cleans at
1028 * least one descriptor.
1029 * Finally, anytime all descriptors are clean the timer is
1030 * set to 0.
1031 */
1032
1033 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1034 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1035 /*
1036 * If we reach here, all TX jobs are completed and
1037 * the TX engine should have been idled for some time.
1038 * We don't need to call if_devstart() here.
1039 */
1040 ifp->if_flags &= ~IFF_OACTIVE;
1041 ifp->if_timer = 0;
1042 return;
1043 }
1044
1045 /*
1046 * If we are in this routine because of pause frames, then
1047 * don't reset the hardware.
1048 */
1049 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1050 ifp->if_timer = EMX_TX_TIMEOUT;
1051 return;
1052 }
1053
1054 if (e1000_check_for_link(&sc->hw) == 0)
1055 if_printf(ifp, "watchdog timeout -- resetting\n");
1056
1057 ifp->if_oerrors++;
1058 sc->watchdog_events++;
1059
1060 emx_init(sc);
1061
1062 if (!ifq_is_empty(&ifp->if_snd))
1063 if_devstart(ifp);
1064}
1065
1066static void
1067emx_init(void *xsc)
1068{
1069 struct emx_softc *sc = xsc;
1070 struct ifnet *ifp = &sc->arpcom.ac_if;
1071 device_t dev = sc->dev;
1072 uint32_t pba;
3f939c23 1073 int i;
5330213c 1074
2c9effcf 1075 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1076
1077 emx_stop(sc);
1078
1079 /*
1080 * Packet Buffer Allocation (PBA)
1081 * Writing PBA sets the receive portion of the buffer
1082 * the remainder is used for the transmit buffer.
1083 */
1084 switch (sc->hw.mac.type) {
1085 /* Total Packet Buffer on these is 48K */
1086 case e1000_82571:
1087 case e1000_82572:
1088 case e1000_80003es2lan:
1089 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1090 break;
1091
1092 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1093 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1094 break;
1095
1096 case e1000_82574:
1097 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1098 break;
1099
1100 default:
1101 /* Devices before 82547 had a Packet Buffer of 64K. */
1102 if (sc->max_frame_size > 8192)
1103 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1104 else
1105 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1106 }
1107 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1108
1109 /* Get the latest mac address, User can use a LAA */
1110 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1111
1112 /* Put the address into the Receive Address Array */
1113 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1114
1115 /*
1116 * With the 82571 sc, RAR[0] may be overwritten
1117 * when the other port is reset, we make a duplicate
1118 * in RAR[14] for that eventuality, this assures
1119 * the interface continues to function.
1120 */
1121 if (sc->hw.mac.type == e1000_82571) {
1122 e1000_set_laa_state_82571(&sc->hw, TRUE);
1123 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1124 E1000_RAR_ENTRIES - 1);
1125 }
1126
1127 /* Initialize the hardware */
2d0e5700
SZ
1128 if (emx_reset(sc)) {
1129 device_printf(dev, "Unable to reset the hardware\n");
5330213c
SZ
1130 /* XXX emx_stop()? */
1131 return;
1132 }
1133 emx_update_link_status(sc);
1134
1135 /* Setup VLAN support, basic and offload if available */
1136 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1137
1138 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1139 uint32_t ctrl;
1140
1141 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1142 ctrl |= E1000_CTRL_VME;
1143 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1144 }
1145
1146 /* Set hardware offload abilities */
1147 if (ifp->if_capenable & IFCAP_TXCSUM)
1148 ifp->if_hwassist = EMX_CSUM_FEATURES;
1149 else
1150 ifp->if_hwassist = 0;
1151
1152 /* Configure for OS presence */
1153 emx_get_mgmt(sc);
1154
1155 /* Prepare transmit descriptors and buffers */
1156 emx_init_tx_ring(sc);
1157 emx_init_tx_unit(sc);
1158
1159 /* Setup Multicast table */
1160 emx_set_multi(sc);
1161
1162 /* Prepare receive descriptors and buffers */
13890b61 1163 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
1164 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1165 device_printf(dev,
1166 "Could not setup receive structures\n");
1167 emx_stop(sc);
1168 return;
1169 }
5330213c
SZ
1170 }
1171 emx_init_rx_unit(sc);
1172
1173 /* Don't lose promiscuous settings */
1174 emx_set_promisc(sc);
1175
1176 ifp->if_flags |= IFF_RUNNING;
1177 ifp->if_flags &= ~IFF_OACTIVE;
1178
1179 callout_reset(&sc->timer, hz, emx_timer, sc);
1180 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1181
1182 /* MSI/X configuration for 82574 */
1183 if (sc->hw.mac.type == e1000_82574) {
1184 int tmp;
1185
1186 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1187 tmp |= E1000_CTRL_EXT_PBA_CLR;
1188 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1189 /*
2d0e5700 1190 * XXX MSIX
5330213c
SZ
1191 * Set the IVAR - interrupt vector routing.
1192 * Each nibble represents a vector, high bit
1193 * is enable, other 3 bits are the MSIX table
1194 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1195 * Link (other) to 2, hence the magic number.
1196 */
1197 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1198 }
1199
b3a7093f 1200#ifdef IFPOLL_ENABLE
5330213c
SZ
1201 /*
1202 * Only enable interrupts if we are not polling, make sure
1203 * they are off otherwise.
1204 */
b3a7093f 1205 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ
1206 emx_disable_intr(sc);
1207 else
b3a7093f 1208#endif /* IFPOLL_ENABLE */
5330213c
SZ
1209 emx_enable_intr(sc);
1210
2d0e5700
SZ
1211 /* AMT based hardware can now take control from firmware */
1212 if (sc->has_manage && sc->has_amt)
1213 emx_get_hw_control(sc);
1214
5330213c
SZ
1215 /* Don't reset the phy next time init gets called */
1216 sc->hw.phy.reset_disable = TRUE;
1217}
1218
5330213c
SZ
1219static void
1220emx_intr(void *xsc)
1221{
4cb541ae
SZ
1222 emx_intr_body(xsc, TRUE);
1223}
1224
1225static void
1226emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1227{
5330213c
SZ
1228 struct ifnet *ifp = &sc->arpcom.ac_if;
1229 uint32_t reg_icr;
1230
1231 logif(intr_beg);
6d435846 1232 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ
1233
1234 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1235
4cb541ae 1236 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
5330213c
SZ
1237 logif(intr_end);
1238 return;
1239 }
1240
1241 /*
1242 * XXX: some laptops trigger several spurious interrupts
df50f778 1243 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ
1244 * reports all-ones value in this case. Processing such
1245 * interrupts would lead to a freeze. I don't know why.
1246 */
1247 if (reg_icr == 0xffffffff) {
1248 logif(intr_end);
1249 return;
1250 }
1251
1252 if (ifp->if_flags & IFF_RUNNING) {
1253 if (reg_icr &
3f939c23
SZ
1254 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1255 int i;
1256
13890b61 1257 for (i = 0; i < sc->rx_ring_cnt; ++i) {
6d435846
SZ
1258 lwkt_serialize_enter(
1259 &sc->rx_data[i].rx_serialize);
3f939c23 1260 emx_rxeof(sc, i, -1);
6d435846
SZ
1261 lwkt_serialize_exit(
1262 &sc->rx_data[i].rx_serialize);
1263 }
3f939c23 1264 }
6446af7b 1265 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1266 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ
1267 emx_txeof(sc);
1268 if (!ifq_is_empty(&ifp->if_snd))
1269 if_devstart(ifp);
6d435846 1270 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ
1271 }
1272 }
1273
1274 /* Link status change */
1275 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1276 emx_serialize_skipmain(sc);
6d435846 1277
5330213c
SZ
1278 callout_stop(&sc->timer);
1279 sc->hw.mac.get_link_status = 1;
1280 emx_update_link_status(sc);
1281
1282 /* Deal with TX cruft when link lost */
1283 emx_tx_purge(sc);
1284
1285 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1286
bca7c435 1287 emx_deserialize_skipmain(sc);
5330213c
SZ
1288 }
1289
1290 if (reg_icr & E1000_ICR_RXO)
1291 sc->rx_overruns++;
1292
1293 logif(intr_end);
1294}
1295
1296static void
4cb541ae
SZ
1297emx_intr_mask(void *xsc)
1298{
1299 struct emx_softc *sc = xsc;
1300
1301 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1302 /*
1303 * NOTE:
1304 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1305 * so don't check it.
1306 */
1307 emx_intr_body(sc, FALSE);
1308 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1309}
1310
1311static void
5330213c
SZ
1312emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1313{
1314 struct emx_softc *sc = ifp->if_softc;
1315
2c9effcf 1316 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1317
1318 emx_update_link_status(sc);
1319
1320 ifmr->ifm_status = IFM_AVALID;
1321 ifmr->ifm_active = IFM_ETHER;
1322
1323 if (!sc->link_active)
1324 return;
1325
1326 ifmr->ifm_status |= IFM_ACTIVE;
1327
1328 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1329 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1330 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1331 } else {
1332 switch (sc->link_speed) {
1333 case 10:
1334 ifmr->ifm_active |= IFM_10_T;
1335 break;
1336 case 100:
1337 ifmr->ifm_active |= IFM_100_TX;
1338 break;
1339
1340 case 1000:
1341 ifmr->ifm_active |= IFM_1000_T;
1342 break;
1343 }
1344 if (sc->link_duplex == FULL_DUPLEX)
1345 ifmr->ifm_active |= IFM_FDX;
1346 else
1347 ifmr->ifm_active |= IFM_HDX;
1348 }
1349}
1350
1351static int
1352emx_media_change(struct ifnet *ifp)
1353{
1354 struct emx_softc *sc = ifp->if_softc;
1355 struct ifmedia *ifm = &sc->media;
1356
2c9effcf 1357 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1358
1359 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1360 return (EINVAL);
1361
1362 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1363 case IFM_AUTO:
1364 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1365 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1366 break;
1367
1368 case IFM_1000_LX:
1369 case IFM_1000_SX:
1370 case IFM_1000_T:
1371 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1372 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1373 break;
1374
1375 case IFM_100_TX:
1376 sc->hw.mac.autoneg = FALSE;
1377 sc->hw.phy.autoneg_advertised = 0;
1378 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1379 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1380 else
1381 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1382 break;
1383
1384 case IFM_10_T:
1385 sc->hw.mac.autoneg = FALSE;
1386 sc->hw.phy.autoneg_advertised = 0;
1387 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1388 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1389 else
1390 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1391 break;
1392
1393 default:
1394 if_printf(ifp, "Unsupported media type\n");
1395 break;
1396 }
1397
1398 /*
1399 * As the speed/duplex settings my have changed we need to
1400 * reset the PHY.
1401 */
1402 sc->hw.phy.reset_disable = FALSE;
1403
1404 emx_init(sc);
1405
1406 return (0);
1407}
1408
1409static int
1410emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1411{
1412 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1413 bus_dmamap_t map;
323e5ecd 1414 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ
1415 struct e1000_tx_desc *ctxd = NULL;
1416 struct mbuf *m_head = *m_headp;
1417 uint32_t txd_upper, txd_lower, cmd = 0;
1418 int maxsegs, nsegs, i, j, first, last = 0, error;
1419
3752657e 1420 if (m_head->m_len < EMX_TXCSUM_MINHL &&
5330213c
SZ
1421 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1422 /*
1423 * Make sure that ethernet header and ip.ip_hl are in
1424 * contiguous memory, since if TXCSUM is enabled, later
1425 * TX context descriptor's setup need to access ip.ip_hl.
1426 */
1427 error = emx_txcsum_pullup(sc, m_headp);
1428 if (error) {
1429 KKASSERT(*m_headp == NULL);
1430 return error;
1431 }
1432 m_head = *m_headp;
1433 }
1434
1435 txd_upper = txd_lower = 0;
1436
1437 /*
1438 * Capture the first descriptor index, this descriptor
1439 * will have the index of the EOP which is the only one
1440 * that now gets a DONE bit writeback.
1441 */
1442 first = sc->next_avail_tx_desc;
323e5ecd 1443 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
1444 tx_buffer_mapped = tx_buffer;
1445 map = tx_buffer->map;
1446
1447 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
ed20d0e3 1448 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
5330213c
SZ
1449 if (maxsegs > EMX_MAX_SCATTER)
1450 maxsegs = EMX_MAX_SCATTER;
1451
1452 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1453 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1454 if (error) {
1455 if (error == ENOBUFS)
1456 sc->mbuf_alloc_failed++;
1457 else
1458 sc->no_tx_dma_setup++;
1459
1460 m_freem(*m_headp);
1461 *m_headp = NULL;
1462 return error;
1463 }
1464 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1465
1466 m_head = *m_headp;
1467 sc->tx_nsegs += nsegs;
1468
1469 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1470 /* TX csum offloading will consume one TX desc */
1471 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1472 }
1473 i = sc->next_avail_tx_desc;
1474
1475 /* Set up our transmit descriptors */
1476 for (j = 0; j < nsegs; j++) {
323e5ecd 1477 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1478 ctxd = &sc->tx_desc_base[i];
1479
1480 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1481 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1482 txd_lower | segs[j].ds_len);
1483 ctxd->upper.data = htole32(txd_upper);
1484
1485 last = i;
1486 if (++i == sc->num_tx_desc)
1487 i = 0;
5330213c
SZ
1488 }
1489
1490 sc->next_avail_tx_desc = i;
1491
1492 KKASSERT(sc->num_tx_desc_avail > nsegs);
1493 sc->num_tx_desc_avail -= nsegs;
1494
1495 /* Handle VLAN tag */
1496 if (m_head->m_flags & M_VLANTAG) {
1497 /* Set the vlan id. */
1498 ctxd->upper.fields.special =
1499 htole16(m_head->m_pkthdr.ether_vlantag);
1500
1501 /* Tell hardware to add tag */
1502 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1503 }
1504
1505 tx_buffer->m_head = m_head;
1506 tx_buffer_mapped->map = tx_buffer->map;
1507 tx_buffer->map = map;
1508
1509 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1510 sc->tx_nsegs = 0;
4e4e8481
SZ
1511
1512 /*
1513 * Report Status (RS) is turned on
1514 * every tx_int_nsegs descriptors.
1515 */
5330213c
SZ
1516 cmd = E1000_TXD_CMD_RS;
1517
b4b0a2b4
SZ
1518 /*
1519 * Keep track of the descriptor, which will
1520 * be written back by hardware.
1521 */
5330213c
SZ
1522 sc->tx_dd[sc->tx_dd_tail] = last;
1523 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1524 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1525 }
1526
1527 /*
1528 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ
1529 */
1530 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1531
1532 /*
5330213c
SZ
1533 * Advance the Transmit Descriptor Tail (TDT), this tells
1534 * the E1000 that this frame is available to transmit.
1535 */
1536 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1537
1538 return (0);
1539}
1540
1541static void
1542emx_set_promisc(struct emx_softc *sc)
1543{
1544 struct ifnet *ifp = &sc->arpcom.ac_if;
1545 uint32_t reg_rctl;
1546
1547 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1548
1549 if (ifp->if_flags & IFF_PROMISC) {
1550 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1551 /* Turn this on if you want to see bad packets */
1552 if (emx_debug_sbp)
1553 reg_rctl |= E1000_RCTL_SBP;
1554 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1555 } else if (ifp->if_flags & IFF_ALLMULTI) {
1556 reg_rctl |= E1000_RCTL_MPE;
1557 reg_rctl &= ~E1000_RCTL_UPE;
1558 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1559 }
1560}
1561
1562static void
1563emx_disable_promisc(struct emx_softc *sc)
1564{
1565 uint32_t reg_rctl;
1566
1567 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1568
1569 reg_rctl &= ~E1000_RCTL_UPE;
1570 reg_rctl &= ~E1000_RCTL_MPE;
1571 reg_rctl &= ~E1000_RCTL_SBP;
1572 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1573}
1574
1575static void
1576emx_set_multi(struct emx_softc *sc)
1577{
1578 struct ifnet *ifp = &sc->arpcom.ac_if;
1579 struct ifmultiaddr *ifma;
1580 uint32_t reg_rctl = 0;
2d0e5700 1581 uint8_t *mta;
5330213c
SZ
1582 int mcnt = 0;
1583
2d0e5700
SZ
1584 mta = sc->mta;
1585 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1586
441d34b2 1587 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ
1588 if (ifma->ifma_addr->sa_family != AF_LINK)
1589 continue;
1590
1591 if (mcnt == EMX_MCAST_ADDR_MAX)
1592 break;
1593
1594 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1595 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1596 mcnt++;
1597 }
1598
1599 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1600 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1601 reg_rctl |= E1000_RCTL_MPE;
1602 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1603 } else {
6a5a645e 1604 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
5330213c
SZ
1605 }
1606}
1607
1608/*
1609 * This routine checks for link status and updates statistics.
1610 */
1611static void
1612emx_timer(void *xsc)
1613{
1614 struct emx_softc *sc = xsc;
1615 struct ifnet *ifp = &sc->arpcom.ac_if;
1616
6d435846 1617 ifnet_serialize_all(ifp);
5330213c
SZ
1618
1619 emx_update_link_status(sc);
1620 emx_update_stats(sc);
1621
1622 /* Reset LAA into RAR[0] on 82571 */
1623 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1624 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1625
1626 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1627 emx_print_hw_stats(sc);
1628
1629 emx_smartspeed(sc);
1630
1631 callout_reset(&sc->timer, hz, emx_timer, sc);
1632
6d435846 1633 ifnet_deserialize_all(ifp);
5330213c
SZ
1634}
1635
1636static void
1637emx_update_link_status(struct emx_softc *sc)
1638{
1639 struct e1000_hw *hw = &sc->hw;
1640 struct ifnet *ifp = &sc->arpcom.ac_if;
1641 device_t dev = sc->dev;
1642 uint32_t link_check = 0;
1643
1644 /* Get the cached link value or read phy for real */
1645 switch (hw->phy.media_type) {
1646 case e1000_media_type_copper:
1647 if (hw->mac.get_link_status) {
1648 /* Do the work to read phy */
1649 e1000_check_for_link(hw);
1650 link_check = !hw->mac.get_link_status;
1651 if (link_check) /* ESB2 fix */
1652 e1000_cfg_on_link_up(hw);
1653 } else {
1654 link_check = TRUE;
1655 }
1656 break;
1657
1658 case e1000_media_type_fiber:
1659 e1000_check_for_link(hw);
1660 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1661 break;
1662
1663 case e1000_media_type_internal_serdes:
1664 e1000_check_for_link(hw);
1665 link_check = sc->hw.mac.serdes_has_link;
1666 break;
1667
1668 case e1000_media_type_unknown:
1669 default:
1670 break;
1671 }
1672
1673 /* Now check for a transition */
1674 if (link_check && sc->link_active == 0) {
1675 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1676 &sc->link_duplex);
1677
1678 /*
1679 * Check if we should enable/disable SPEED_MODE bit on
1680 * 82571EB/82572EI
1681 */
2d0e5700
SZ
1682 if (sc->link_speed != SPEED_1000 &&
1683 (hw->mac.type == e1000_82571 ||
1684 hw->mac.type == e1000_82572)) {
5330213c
SZ
1685 int tarc0;
1686
1687 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 1688 tarc0 &= ~EMX_TARC_SPEED_MODE;
5330213c
SZ
1689 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1690 }
1691 if (bootverbose) {
1692 device_printf(dev, "Link is up %d Mbps %s\n",
1693 sc->link_speed,
1694 ((sc->link_duplex == FULL_DUPLEX) ?
1695 "Full Duplex" : "Half Duplex"));
1696 }
1697 sc->link_active = 1;
1698 sc->smartspeed = 0;
1699 ifp->if_baudrate = sc->link_speed * 1000000;
1700 ifp->if_link_state = LINK_STATE_UP;
1701 if_link_state_change(ifp);
1702 } else if (!link_check && sc->link_active == 1) {
1703 ifp->if_baudrate = sc->link_speed = 0;
1704 sc->link_duplex = 0;
1705 if (bootverbose)
1706 device_printf(dev, "Link is Down\n");
1707 sc->link_active = 0;
1708#if 0
1709 /* Link down, disable watchdog */
1710 if->if_timer = 0;
1711#endif
1712 ifp->if_link_state = LINK_STATE_DOWN;
1713 if_link_state_change(ifp);
1714 }
1715}
1716
1717static void
1718emx_stop(struct emx_softc *sc)
1719{
1720 struct ifnet *ifp = &sc->arpcom.ac_if;
1721 int i;
1722
2c9effcf 1723 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1724
1725 emx_disable_intr(sc);
1726
1727 callout_stop(&sc->timer);
1728
1729 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1730 ifp->if_timer = 0;
1731
3f939c23
SZ
1732 /*
1733 * Disable multiple receive queues.
1734 *
1735 * NOTE:
1736 * We should disable multiple receive queues before
1737 * resetting the hardware.
1738 */
1739 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1740
5330213c
SZ
1741 e1000_reset_hw(&sc->hw);
1742 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1743
1744 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1745 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1746
1747 if (tx_buffer->m_head != NULL) {
1748 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1749 m_freem(tx_buffer->m_head);
1750 tx_buffer->m_head = NULL;
1751 }
1752 }
1753
13890b61 1754 for (i = 0; i < sc->rx_ring_cnt; ++i)
3f939c23 1755 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ
1756
1757 sc->csum_flags = 0;
1758 sc->csum_ehlen = 0;
1759 sc->csum_iphlen = 0;
1760
1761 sc->tx_dd_head = 0;
1762 sc->tx_dd_tail = 0;
1763 sc->tx_nsegs = 0;
1764}
1765
1766static int
2d0e5700 1767emx_reset(struct emx_softc *sc)
5330213c
SZ
1768{
1769 device_t dev = sc->dev;
1770 uint16_t rx_buffer_size;
1771
5330213c
SZ
1772 /* Set up smart power down as default off on newer adapters. */
1773 if (!emx_smart_pwr_down &&
1774 (sc->hw.mac.type == e1000_82571 ||
1775 sc->hw.mac.type == e1000_82572)) {
1776 uint16_t phy_tmp = 0;
1777
1778 /* Speed up time to link by disabling smart power down. */
1779 e1000_read_phy_reg(&sc->hw,
1780 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1781 phy_tmp &= ~IGP02E1000_PM_SPD;
1782 e1000_write_phy_reg(&sc->hw,
1783 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1784 }
1785
1786 /*
1787 * These parameters control the automatic generation (Tx) and
1788 * response (Rx) to Ethernet PAUSE frames.
1789 * - High water mark should allow for at least two frames to be
1790 * received after sending an XOFF.
1791 * - Low water mark works best when it is very near the high water mark.
1792 * This allows the receiver to restart by sending XON when it has
1793 * drained a bit. Here we use an arbitary value of 1500 which will
1794 * restart after one full frame is pulled from the buffer. There
1795 * could be several smaller frames in the buffer and if so they will
1796 * not trigger the XON until their total number reduces the buffer
1797 * by 1500.
1798 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1799 */
1800 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1801
1802 sc->hw.fc.high_water = rx_buffer_size -
1803 roundup2(sc->max_frame_size, 1024);
1804 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1805
1806 if (sc->hw.mac.type == e1000_80003es2lan)
1807 sc->hw.fc.pause_time = 0xFFFF;
1808 else
1809 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1810 sc->hw.fc.send_xon = TRUE;
1811 sc->hw.fc.requested_mode = e1000_fc_full;
1812
2d0e5700
SZ
1813 /* Issue a global reset */
1814 e1000_reset_hw(&sc->hw);
1815 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
6d5e2922 1816 emx_disable_aspm(sc);
2d0e5700 1817
5330213c
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1818 if (e1000_init_hw(&sc->hw) < 0) {
1819 device_printf(dev, "Hardware Initialization Failed\n");
1820 return (EIO);
1821 }
1822
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SZ
1823 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1824 e1000_get_phy_info(&sc->hw);
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1825 e1000_check_for_link(&sc->hw);
1826
1827 return (0);
1828}
1829
1830static void
1831emx_setup_ifp(struct emx_softc *sc)
1832{
1833 struct ifnet *ifp = &sc->arpcom.ac_if;
1834
1835 if_initname(ifp, device_get_name(sc->dev),
1836 device_get_unit(sc->dev));
1837 ifp->if_softc = sc;
1838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1839 ifp->if_init = emx_init;
1840 ifp->if_ioctl = emx_ioctl;
1841 ifp->if_start = emx_start;
b3a7093f
SZ
1842#ifdef IFPOLL_ENABLE
1843 ifp->if_qpoll = emx_qpoll;
5330213c
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1844#endif
1845 ifp->if_watchdog = emx_watchdog;
6d435846
SZ
1846 ifp->if_serialize = emx_serialize;
1847 ifp->if_deserialize = emx_deserialize;
1848 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ
1849#ifdef INVARIANTS
1850 ifp->if_serialize_assert = emx_serialize_assert;
1851#endif
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1852 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1853 ifq_set_ready(&ifp->if_snd);
1854
ae474cfa 1855 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ
1856
1857 ifp->if_capabilities = IFCAP_HWCSUM |
1858 IFCAP_VLAN_HWTAGGING |
1859 IFCAP_VLAN_MTU;
8434a83b
SZ
1860 if (sc->rx_ring_cnt > 1)
1861 ifp->if_capabilities |= IFCAP_RSS;
5330213c
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1862 ifp->if_capenable = ifp->if_capabilities;
1863 ifp->if_hwassist = EMX_CSUM_FEATURES;
1864
1865 /*
1866 * Tell the upper layer(s) we support long frames.
1867 */
1868 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1869
1870 /*
1871 * Specify the media types supported by this sc and register
1872 * callbacks to update media and link information
1873 */
1874 ifmedia_init(&sc->media, IFM_IMASK,
1875 emx_media_change, emx_media_status);
1876 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1877 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1878 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1879 0, NULL);
1880 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1881 } else {
1882 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1883 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1884 0, NULL);
1885 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1886 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1887 0, NULL);
1888 if (sc->hw.phy.type != e1000_phy_ife) {
1889 ifmedia_add(&sc->media,
1890 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1891 ifmedia_add(&sc->media,
1892 IFM_ETHER | IFM_1000_T, 0, NULL);
1893 }
1894 }
1895 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1896 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1897}
1898
1899/*
1900 * Workaround for SmartSpeed on 82541 and 82547 controllers
1901 */
1902static void
1903emx_smartspeed(struct emx_softc *sc)
1904{
1905 uint16_t phy_tmp;
1906
1907 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1908 sc->hw.mac.autoneg == 0 ||
1909 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1910 return;
1911
1912 if (sc->smartspeed == 0) {
1913 /*
1914 * If Master/Slave config fault is asserted twice,
1915 * we assume back-to-back
1916 */
1917 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1918 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1919 return;
1920 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1921 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1922 e1000_read_phy_reg(&sc->hw,
1923 PHY_1000T_CTRL, &phy_tmp);
1924 if (phy_tmp & CR_1000T_MS_ENABLE) {
1925 phy_tmp &= ~CR_1000T_MS_ENABLE;
1926 e1000_write_phy_reg(&sc->hw,
1927 PHY_1000T_CTRL, phy_tmp);
1928 sc->smartspeed++;
1929 if (sc->hw.mac.autoneg &&
1930 !e1000_phy_setup_autoneg(&sc->hw) &&
1931 !e1000_read_phy_reg(&sc->hw,
1932 PHY_CONTROL, &phy_tmp)) {
1933 phy_tmp |= MII_CR_AUTO_NEG_EN |
1934 MII_CR_RESTART_AUTO_NEG;
1935 e1000_write_phy_reg(&sc->hw,
1936 PHY_CONTROL, phy_tmp);
1937 }
1938 }
1939 }
1940 return;
1941 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1942 /* If still no link, perhaps using 2/3 pair cable */
1943 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1944 phy_tmp |= CR_1000T_MS_ENABLE;
1945 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1946 if (sc->hw.mac.autoneg &&
1947 !e1000_phy_setup_autoneg(&sc->hw) &&
1948 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1949 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1950 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1951 }
1952 }
1953
1954 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1955 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1956 sc->smartspeed = 0;
1957}
1958
1959static int
5330213c
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1960emx_create_tx_ring(struct emx_softc *sc)
1961{
1962 device_t dev = sc->dev;
323e5ecd 1963 struct emx_txbuf *tx_buffer;
b4d8c36b 1964 int error, i, tsize, ntxd;
bdca134f
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1965
1966 /*
1967 * Validate number of transmit descriptors. It must not exceed
1968 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1969 */
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1970 ntxd = device_getenv_int(dev, "txd", emx_txd);
1971 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1972 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
bdca134f 1973 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
b4d8c36b 1974 EMX_DEFAULT_TXD, ntxd);
bdca134f
SZ
1975 sc->num_tx_desc = EMX_DEFAULT_TXD;
1976 } else {
b4d8c36b 1977 sc->num_tx_desc = ntxd;
bdca134f
SZ
1978 }
1979
1980 /*
1981 * Allocate Transmit Descriptor ring
1982 */
1983 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1984 EMX_DBA_ALIGN);
a596084c
SZ
1985 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1986 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1987 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1988 &sc->tx_desc_paddr);
1989 if (sc->tx_desc_base == NULL) {
bdca134f 1990 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 1991 return ENOMEM;
bdca134f 1992 }
5330213c 1993
323e5ecd
SZ
1994 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1995 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
1996
1997 /*
1998 * Create DMA tags for tx buffers
1999 */
2000 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2001 1, 0, /* alignment, bounds */
2002 BUS_SPACE_MAXADDR, /* lowaddr */
2003 BUS_SPACE_MAXADDR, /* highaddr */
2004 NULL, NULL, /* filter, filterarg */
2005 EMX_TSO_SIZE, /* maxsize */
2006 EMX_MAX_SCATTER, /* nsegments */
2007 EMX_MAX_SEGSIZE, /* maxsegsize */
2008 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2009 BUS_DMA_ONEBPAGE, /* flags */
2010 &sc->txtag);
2011 if (error) {
2012 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
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2013 kfree(sc->tx_buf, M_DEVBUF);
2014 sc->tx_buf = NULL;
5330213c
SZ
2015 return error;
2016 }
2017
2018 /*
2019 * Create DMA maps for tx buffers
2020 */
2021 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 2022 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2023
2024 error = bus_dmamap_create(sc->txtag,
2025 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2026 &tx_buffer->map);
2027 if (error) {
2028 device_printf(dev, "Unable to create TX DMA map\n");
2029 emx_destroy_tx_ring(sc, i);
2030 return error;
2031 }
2032 }
2033 return (0);
2034}
2035
2036static void
2037emx_init_tx_ring(struct emx_softc *sc)
2038{
2039 /* Clear the old ring contents */
2040 bzero(sc->tx_desc_base,
2041 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2042
2043 /* Reset state */
2044 sc->next_avail_tx_desc = 0;
2045 sc->next_tx_to_clean = 0;
2046 sc->num_tx_desc_avail = sc->num_tx_desc;
2047}
2048
2049static void
2050emx_init_tx_unit(struct emx_softc *sc)
2051{
2052 uint32_t tctl, tarc, tipg = 0;
2053 uint64_t bus_addr;
2054
2055 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 2056 bus_addr = sc->tx_desc_paddr;
5330213c
SZ
2057 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2058 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2059 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2060 (uint32_t)(bus_addr >> 32));
2061 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2062 (uint32_t)bus_addr);
2063 /* Setup the HW Tx Head and Tail descriptor pointers */
2064 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2065 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2066
2067 /* Set the default values for the Tx Inter Packet Gap timer */
2068 switch (sc->hw.mac.type) {
2069 case e1000_80003es2lan:
2070 tipg = DEFAULT_82543_TIPG_IPGR1;
2071 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2072 E1000_TIPG_IPGR2_SHIFT;
2073 break;
2074
2075 default:
2076 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2077 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2078 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2079 else
2080 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2081 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2082 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2083 break;
2084 }
2085
2086 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2087
2088 /* NOTE: 0 is not allowed for TIDV */
2089 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2090 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2091
2092 if (sc->hw.mac.type == e1000_82571 ||
2093 sc->hw.mac.type == e1000_82572) {
2094 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2095 tarc |= EMX_TARC_SPEED_MODE;
2096 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2097 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2098 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2099 tarc |= 1;
2100 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2101 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2102 tarc |= 1;
2103 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2104 }
2105
2106 /* Program the Transmit Control Register */
2107 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2108 tctl &= ~E1000_TCTL_CT;
2109 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2110 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2111 tctl |= E1000_TCTL_MULR;
2112
2113 /* This write will effectively turn on the transmit unit. */
2114 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2115}
2116
2117static void
2118emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2119{
323e5ecd 2120 struct emx_txbuf *tx_buffer;
5330213c
SZ
2121 int i;
2122
bdca134f 2123 /* Free Transmit Descriptor ring */
a596084c
SZ
2124 if (sc->tx_desc_base) {
2125 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2126 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2127 sc->tx_desc_dmap);
2128 bus_dma_tag_destroy(sc->tx_desc_dtag);
2129
2130 sc->tx_desc_base = NULL;
2131 }
bdca134f 2132
323e5ecd 2133 if (sc->tx_buf == NULL)
5330213c
SZ
2134 return;
2135
2136 for (i = 0; i < ndesc; i++) {
323e5ecd 2137 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2138
2139 KKASSERT(tx_buffer->m_head == NULL);
2140 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2141 }
2142 bus_dma_tag_destroy(sc->txtag);
2143
323e5ecd
SZ
2144 kfree(sc->tx_buf, M_DEVBUF);
2145 sc->tx_buf = NULL;
5330213c
SZ
2146}
2147
2148/*
2149 * The offload context needs to be set when we transfer the first
2150 * packet of a particular protocol (TCP/UDP). This routine has been
2151 * enhanced to deal with inserted VLAN headers.
2152 *
2153 * If the new packet's ether header length, ip header length and
2154 * csum offloading type are same as the previous packet, we should
2155 * avoid allocating a new csum context descriptor; mainly to take
2156 * advantage of the pipeline effect of the TX data read request.
2157 *
2158 * This function returns number of TX descrptors allocated for
2159 * csum context.
2160 */
2161static int
2162emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2163 uint32_t *txd_upper, uint32_t *txd_lower)
2164{
2165 struct e1000_context_desc *TXD;
323e5ecd 2166 struct emx_txbuf *tx_buffer;
5330213c
SZ
2167 struct ether_vlan_header *eh;
2168 struct ip *ip;
2169 int curr_txd, ehdrlen, csum_flags;
2170 uint32_t cmd, hdr_len, ip_hlen;
2171 uint16_t etype;
2172
2173 /*
2174 * Determine where frame payload starts.
2175 * Jump over vlan headers if already present,
2176 * helpful for QinQ too.
2177 */
2178 KASSERT(mp->m_len >= ETHER_HDR_LEN,
ed20d0e3 2179 ("emx_txcsum_pullup is not called (eh)?"));
5330213c
SZ
2180 eh = mtod(mp, struct ether_vlan_header *);
2181 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2182 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
ed20d0e3 2183 ("emx_txcsum_pullup is not called (evh)?"));
5330213c
SZ
2184 etype = ntohs(eh->evl_proto);
2185 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2186 } else {
2187 etype = ntohs(eh->evl_encap_proto);
2188 ehdrlen = ETHER_HDR_LEN;
2189 }
2190
2191 /*
2192 * We only support TCP/UDP for IPv4 for the moment.
2193 * TODO: Support SCTP too when it hits the tree.
2194 */
2195 if (etype != ETHERTYPE_IP)
2196 return 0;
2197
2198 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
ed20d0e3 2199 ("emx_txcsum_pullup is not called (eh+ip_vhl)?"));
5330213c
SZ
2200
2201 /* NOTE: We could only safely access ip.ip_vhl part */
2202 ip = (struct ip *)(mp->m_data + ehdrlen);
2203 ip_hlen = ip->ip_hl << 2;
2204
2205 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2206
2207 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2208 sc->csum_flags == csum_flags) {
2209 /*
2210 * Same csum offload context as the previous packets;
2211 * just return.
2212 */
2213 *txd_upper = sc->csum_txd_upper;
2214 *txd_lower = sc->csum_txd_lower;
2215 return 0;
2216 }
2217
2218 /*
2219 * Setup a new csum offload context.
2220 */
2221
2222 curr_txd = sc->next_avail_tx_desc;
323e5ecd 2223 tx_buffer = &sc->tx_buf[curr_txd];
5330213c
SZ
2224 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2225
2226 cmd = 0;
2227
2228 /* Setup of IP header checksum. */
2229 if (csum_flags & CSUM_IP) {
2230 /*
2231 * Start offset for header checksum calculation.
2232 * End offset for header checksum calculation.
2233 * Offset of place to put the checksum.
2234 */
2235 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2236 TXD->lower_setup.ip_fields.ipcse =
2237 htole16(ehdrlen + ip_hlen - 1);
2238 TXD->lower_setup.ip_fields.ipcso =
2239 ehdrlen + offsetof(struct ip, ip_sum);
2240 cmd |= E1000_TXD_CMD_IP;
2241 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2242 }
2243 hdr_len = ehdrlen + ip_hlen;
2244
2245 if (csum_flags & CSUM_TCP) {
2246 /*
2247 * Start offset for payload checksum calculation.
2248 * End offset for payload checksum calculation.
2249 * Offset of place to put the checksum.
2250 */
2251 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2252 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2253 TXD->upper_setup.tcp_fields.tucso =
2254 hdr_len + offsetof(struct tcphdr, th_sum);
2255 cmd |= E1000_TXD_CMD_TCP;
2256 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2257 } else if (csum_flags & CSUM_UDP) {
2258 /*
2259 * Start offset for header checksum calculation.
2260 * End offset for header checksum calculation.
2261 * Offset of place to put the checksum.
2262 */
2263 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2264 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2265 TXD->upper_setup.tcp_fields.tucso =
2266 hdr_len + offsetof(struct udphdr, uh_sum);
2267 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2268 }
2269
2270 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2271 E1000_TXD_DTYP_D; /* Data descr */
2272
2273 /* Save the information for this csum offloading context */
2274 sc->csum_ehlen = ehdrlen;
2275 sc->csum_iphlen = ip_hlen;
2276 sc->csum_flags = csum_flags;
2277 sc->csum_txd_upper = *txd_upper;
2278 sc->csum_txd_lower = *txd_lower;
2279
2280 TXD->tcp_seg_setup.data = htole32(0);
2281 TXD->cmd_and_length =
2282 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ
2283
2284 if (++curr_txd == sc->num_tx_desc)
2285 curr_txd = 0;
2286
2287 KKASSERT(sc->num_tx_desc_avail > 0);
2288 sc->num_tx_desc_avail--;
2289
2290 sc->next_avail_tx_desc = curr_txd;
2291 return 1;
2292}
2293
2294static int
2295emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2296{
2297 struct mbuf *m = *m0;
2298 struct ether_header *eh;
2299 int len;
2300
2301 sc->tx_csum_try_pullup++;
2302
2303 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2304
2305 if (__predict_false(!M_WRITABLE(m))) {
2306 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2307 sc->tx_csum_drop1++;
2308 m_freem(m);
2309 *m0 = NULL;
2310 return ENOBUFS;
2311 }
2312 eh = mtod(m, struct ether_header *);
2313
2314 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2315 len += EVL_ENCAPLEN;
2316
3752657e 2317 if (m->m_len < len) {
5330213c
SZ
2318 sc->tx_csum_drop2++;
2319 m_freem(m);
2320 *m0 = NULL;
2321 return ENOBUFS;
2322 }
2323 return 0;
2324 }
2325
2326 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2327 sc->tx_csum_pullup1++;
2328 m = m_pullup(m, ETHER_HDR_LEN);
2329 if (m == NULL) {
2330 sc->tx_csum_pullup1_failed++;
2331 *m0 = NULL;
2332 return ENOBUFS;
2333 }
2334 *m0 = m;
2335 }
2336 eh = mtod(m, struct ether_header *);
2337
2338 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2339 len += EVL_ENCAPLEN;
2340
3752657e 2341 if (m->m_len < len) {
5330213c
SZ
2342 sc->tx_csum_pullup2++;
2343 m = m_pullup(m, len);
2344 if (m == NULL) {
2345 sc->tx_csum_pullup2_failed++;
2346 *m0 = NULL;
2347 return ENOBUFS;
2348 }
2349 *m0 = m;
2350 }
2351 return 0;
2352}
2353
2354static void
2355emx_txeof(struct emx_softc *sc)
2356{
2357 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2358 struct emx_txbuf *tx_buffer;
5330213c
SZ
2359 int first, num_avail;
2360
2361 if (sc->tx_dd_head == sc->tx_dd_tail)
2362 return;
2363
2364 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2365 return;
2366
2367 num_avail = sc->num_tx_desc_avail;
2368 first = sc->next_tx_to_clean;
2369
2370 while (sc->tx_dd_head != sc->tx_dd_tail) {
2371 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2372 struct e1000_tx_desc *tx_desc;
5330213c
SZ
2373
2374 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ
2375 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2376 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2377
2378 if (++dd_idx == sc->num_tx_desc)
2379 dd_idx = 0;
2380
2381 while (first != dd_idx) {
2382 logif(pkt_txclean);
2383
5330213c
SZ
2384 num_avail++;
2385
323e5ecd 2386 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2387 if (tx_buffer->m_head) {
2388 ifp->if_opackets++;
2389 bus_dmamap_unload(sc->txtag,
2390 tx_buffer->map);
2391 m_freem(tx_buffer->m_head);
2392 tx_buffer->m_head = NULL;
2393 }
2394
2395 if (++first == sc->num_tx_desc)
2396 first = 0;
2397 }
2398 } else {
2399 break;
2400 }
2401 }
2402 sc->next_tx_to_clean = first;
2403 sc->num_tx_desc_avail = num_avail;
2404
2405 if (sc->tx_dd_head == sc->tx_dd_tail) {
2406 sc->tx_dd_head = 0;
2407 sc->tx_dd_tail = 0;
2408 }
2409
2410 if (!EMX_IS_OACTIVE(sc)) {
2411 ifp->if_flags &= ~IFF_OACTIVE;
2412
2413 /* All clean, turn off the timer */
2414 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2415 ifp->if_timer = 0;
2416 }
2417}
2418
2419static void
2420emx_tx_collect(struct emx_softc *sc)
2421{
2422 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2423 struct emx_txbuf *tx_buffer;
5330213c
SZ
2424 int tdh, first, num_avail, dd_idx = -1;
2425
2426 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2427 return;
2428
2429 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2430 if (tdh == sc->next_tx_to_clean)
2431 return;
2432
2433 if (sc->tx_dd_head != sc->tx_dd_tail)
2434 dd_idx = sc->tx_dd[sc->tx_dd_head];
2435
2436 num_avail = sc->num_tx_desc_avail;
2437 first = sc->next_tx_to_clean;
2438
2439 while (first != tdh) {
2440 logif(pkt_txclean);
2441
5330213c
SZ
2442 num_avail++;
2443
323e5ecd 2444 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2445 if (tx_buffer->m_head) {
2446 ifp->if_opackets++;
2447 bus_dmamap_unload(sc->txtag,
2448 tx_buffer->map);
2449 m_freem(tx_buffer->m_head);
2450 tx_buffer->m_head = NULL;
2451 }
2452
2453 if (first == dd_idx) {
2454 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2455 if (sc->tx_dd_head == sc->tx_dd_tail) {
2456 sc->tx_dd_head = 0;
2457 sc->tx_dd_tail = 0;
2458 dd_idx = -1;
2459 } else {
2460 dd_idx = sc->tx_dd[sc->tx_dd_head];
2461 }
2462 }
2463
2464 if (++first == sc->num_tx_desc)
2465 first = 0;
2466 }
2467 sc->next_tx_to_clean = first;
2468 sc->num_tx_desc_avail = num_avail;
2469
2470 if (!EMX_IS_OACTIVE(sc)) {
2471 ifp->if_flags &= ~IFF_OACTIVE;
2472
2473 /* All clean, turn off the timer */
2474 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2475 ifp->if_timer = 0;
2476 }
2477}
2478
2479/*
2480 * When Link is lost sometimes there is work still in the TX ring
2481 * which will result in a watchdog, rather than allow that do an
2482 * attempted cleanup and then reinit here. Note that this has been
2483 * seens mostly with fiber adapters.
2484 */
2485static void
2486emx_tx_purge(struct emx_softc *sc)
2487{
2488 struct ifnet *ifp = &sc->arpcom.ac_if;
2489
2490 if (!sc->link_active && ifp->if_timer) {
2491 emx_tx_collect(sc);
2492 if (ifp->if_timer) {
2493 if_printf(ifp, "Link lost, TX pending, reinit\n");
2494 ifp->if_timer = 0;
2495 emx_init(sc);
2496 }
2497 }
2498}
2499
2500static int
c39e3a1f 2501emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ
2502{
2503 struct mbuf *m;
2504 bus_dma_segment_t seg;
2505 bus_dmamap_t map;
323e5ecd 2506 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2507 int error, nseg;
2508
2509 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2510 if (m == NULL) {
c39e3a1f 2511 rdata->mbuf_cluster_failed++;
5330213c
SZ
2512 if (init) {
2513 if_printf(&sc->arpcom.ac_if,
2514 "Unable to allocate RX mbuf\n");
2515 }
2516 return (ENOBUFS);
2517 }
2518 m->m_len = m->m_pkthdr.len = MCLBYTES;
2519
2520 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2521 m_adj(m, ETHER_ALIGN);
2522
c39e3a1f
SZ
2523 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2524 rdata->rx_sparemap, m,
5330213c
SZ
2525 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2526 if (error) {
2527 m_freem(m);
2528 if (init) {
2529 if_printf(&sc->arpcom.ac_if,
2530 "Unable to load RX mbuf\n");
2531 }
2532 return (error);
2533 }
2534
323e5ecd 2535 rx_buffer = &rdata->rx_buf[i];
5330213c 2536 if (rx_buffer->m_head != NULL)
c39e3a1f 2537 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ
2538
2539 map = rx_buffer->map;
c39e3a1f
SZ
2540 rx_buffer->map = rdata->rx_sparemap;
2541 rdata->rx_sparemap = map;
5330213c
SZ
2542
2543 rx_buffer->m_head = m;
235b9d30 2544 rx_buffer->paddr = seg.ds_addr;
5330213c 2545
235b9d30 2546 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ
2547 return (0);
2548}
2549
2550static int
c39e3a1f 2551emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2552{
2553 device_t dev = sc->dev;
323e5ecd 2554 struct emx_rxbuf *rx_buffer;
b4d8c36b 2555 int i, error, rsize, nrxd;
bdca134f
SZ
2556
2557 /*
2558 * Validate number of receive descriptors. It must not exceed
2559 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2560 */
b4d8c36b
SZ
2561 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2562 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2563 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
bdca134f 2564 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
b4d8c36b 2565 EMX_DEFAULT_RXD, nrxd);
c39e3a1f 2566 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2567 } else {
b4d8c36b 2568 rdata->num_rx_desc = nrxd;
bdca134f
SZ
2569 }
2570
2571 /*
2572 * Allocate Receive Descriptor ring
2573 */
235b9d30 2574 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2575 EMX_DBA_ALIGN);
235b9d30 2576 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2577 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ
2578 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2579 &rdata->rx_desc_paddr);
235b9d30 2580 if (rdata->rx_desc == NULL) {
bdca134f 2581 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2582 return ENOMEM;
bdca134f 2583 }
5330213c 2584
323e5ecd
SZ
2585 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2586 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2587
2588 /*
2589 * Create DMA tag for rx buffers
2590 */
2591 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2592 1, 0, /* alignment, bounds */
2593 BUS_SPACE_MAXADDR, /* lowaddr */
2594 BUS_SPACE_MAXADDR, /* highaddr */
2595 NULL, NULL, /* filter, filterarg */
2596 MCLBYTES, /* maxsize */
2597 1, /* nsegments */
2598 MCLBYTES, /* maxsegsize */
2599 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2600 &rdata->rxtag);
5330213c
SZ
2601 if (error) {
2602 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ
2603 kfree(rdata->rx_buf, M_DEVBUF);
2604 rdata->rx_buf = NULL;
5330213c
SZ
2605 return error;
2606 }
2607
2608 /*
2609 * Create spare DMA map for rx buffers
2610 */
c39e3a1f
SZ
2611 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2612 &rdata->rx_sparemap);
5330213c
SZ
2613 if (error) {
2614 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2615 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ
2616 kfree(rdata->rx_buf, M_DEVBUF);
2617 rdata->rx_buf = NULL;
5330213c
SZ
2618 return error;
2619 }
2620
2621 /*
2622 * Create DMA maps for rx buffers
2623 */
c39e3a1f 2624 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2625 rx_buffer = &rdata->rx_buf[i];
5330213c 2626
c39e3a1f 2627 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ
2628 &rx_buffer->map);
2629 if (error) {
2630 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2631 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ
2632 return error;
2633 }
2634 }
2635 return (0);
2636}
2637
c39e3a1f
SZ
2638static void
2639emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2640{
2641 int i;
2642
2643 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2644 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ
2645
2646 if (rx_buffer->m_head != NULL) {
2647 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2648 m_freem(rx_buffer->m_head);
2649 rx_buffer->m_head = NULL;
2650 }
2651 }
2652
2653 if (rdata->fmp != NULL)
2654 m_freem(rdata->fmp);
2655 rdata->fmp = NULL;
2656 rdata->lmp = NULL;
2657}
2658
5330213c 2659static int
c39e3a1f 2660emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2661{
2662 int i, error;
2663
2664 /* Reset descriptor ring */
235b9d30 2665 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ
2666
2667 /* Allocate new ones. */
c39e3a1f
SZ
2668 for (i = 0; i < rdata->num_rx_desc; i++) {
2669 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ
2670 if (error)
2671 return (error);
2672 }
2673
2674 /* Setup our descriptor pointers */
c39e3a1f 2675 rdata->next_rx_desc_to_check = 0;
5330213c
SZ
2676
2677 return (0);
2678}
2679
2680static void
2681emx_init_rx_unit(struct emx_softc *sc)
2682{
2683 struct ifnet *ifp = &sc->arpcom.ac_if;
2684 uint64_t bus_addr;
2d0e5700 2685 uint32_t rctl, itr, rfctl;
3f939c23 2686 int i;
5330213c
SZ
2687
2688 /*
2689 * Make sure receives are disabled while setting
2690 * up the descriptor ring
2691 */
2692 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2693 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2694
2695 /*
2696 * Set the interrupt throttling rate. Value is calculated
2697 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2698 */
2d0e5700
SZ
2699 if (sc->int_throttle_ceil)
2700 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2701 else
2702 itr = 0;
2703 emx_set_itr(sc, itr);
5330213c 2704
235b9d30
SZ
2705 /* Use extended RX descriptor */
2706 rfctl = E1000_RFCTL_EXTEN;
2707
5330213c 2708 /* Disable accelerated ackknowledge */
235b9d30
SZ
2709 if (sc->hw.mac.type == e1000_82574)
2710 rfctl |= E1000_RFCTL_ACK_DIS;
2711
2712 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c 2713
65c7a6af
SZ
2714 /*
2715 * Receive Checksum Offload for TCP and UDP
2716 *
2717 * Checksum offloading is also enabled if multiple receive
2718 * queue is to be supported, since we need it to figure out
2719 * packet type.
2720 */
13890b61
SZ
2721 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2722 sc->rx_ring_cnt > 1) {
2d0e5700
SZ
2723 uint32_t rxcsum;
2724
5330213c 2725 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ
2726
2727 /*
2728 * NOTE:
2729 * PCSD must be enabled to enable multiple
2730 * receive queues.
2731 */
2732 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2733 E1000_RXCSUM_PCSD;
5330213c
SZ
2734 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2735 }
2736
2737 /*
65c7a6af 2738 * Configure multiple receive queue (RSS)
3f939c23 2739 */
13890b61 2740 if (sc->rx_ring_cnt > 1) {
89d8e73d
SZ
2741 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2742 uint32_t reta;
2743
13890b61
SZ
2744 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2745 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
89d8e73d 2746
65c7a6af
SZ
2747 /*
2748 * NOTE:
2749 * When we reach here, RSS has already been disabled
2750 * in emx_stop(), so we could safely configure RSS key
2751 * and redirect table.
2752 */
3f939c23 2753
65c7a6af
SZ
2754 /*
2755 * Configure RSS key
2756 */
89d8e73d
SZ
2757 toeplitz_get_key(key, sizeof(key));
2758 for (i = 0; i < EMX_NRSSRK; ++i) {
2759 uint32_t rssrk;
2760
2761 rssrk = EMX_RSSRK_VAL(key, i);
2762 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2763
2764 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2765 }
3f939c23 2766
65c7a6af 2767 /*
89d8e73d
SZ
2768 * Configure RSS redirect table in following fashion:
2769 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2770 */
89d8e73d
SZ
2771 reta = 0;
2772 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2773 uint32_t q;
2774
13890b61 2775 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
89d8e73d
SZ
2776 reta |= q << (8 * i);
2777 }
2778 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2779
65c7a6af
SZ
2780 for (i = 0; i < EMX_NRETA; ++i)
2781 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2782
65c7a6af
SZ
2783 /*
2784 * Enable multiple receive queues.
2785 * Enable IPv4 RSS standard hash functions.
2786 * Disable RSS interrupt.
2787 */
2788 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2789 E1000_MRQC_ENABLE_RSS_2Q |
2790 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2791 E1000_MRQC_RSS_FIELD_IPV4);
2792 }
3f939c23
SZ
2793
2794 /*
5330213c
SZ
2795 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2796 * long latencies are observed, like Lenovo X60. This
2797 * change eliminates the problem, but since having positive
2798 * values in RDTR is a known source of problems on other
2799 * platforms another solution is being sought.
2800 */
2801 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2802 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2803 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2804 }
2805
13890b61 2806 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2d0e5700
SZ
2807 struct emx_rxdata *rdata = &sc->rx_data[i];
2808
2809 /*
2810 * Setup the Base and Length of the Rx Descriptor Ring
2811 */
2812 bus_addr = rdata->rx_desc_paddr;
2813 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2814 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2815 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2816 (uint32_t)(bus_addr >> 32));
2817 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2818 (uint32_t)bus_addr);
2819
2820 /*
2821 * Setup the HW Rx Head and Tail Descriptor Pointers
2822 */
3f939c23
SZ
2823 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2824 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2825 sc->rx_data[i].num_rx_desc - 1);
2826 }
2827
2d0e5700
SZ
2828 /* Setup the Receive Control Register */
2829 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2830 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2831 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2832 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2833
2834 /* Make sure VLAN Filters are off */
2835 rctl &= ~E1000_RCTL_VFE;
2836
2837 /* Don't store bad paket */
2838 rctl &= ~E1000_RCTL_SBP;
2839
2840 /* MCLBYTES */
2841 rctl |= E1000_RCTL_SZ_2048;
2842
2843 if (ifp->if_mtu > ETHERMTU)
2844 rctl |= E1000_RCTL_LPE;
2845 else
2846 rctl &= ~E1000_RCTL_LPE;
2847
3f939c23
SZ
2848 /* Enable Receives */
2849 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ
2850}
2851
2852static void
c39e3a1f 2853emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2854{
323e5ecd 2855 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2856 int i;
2857
bdca134f 2858 /* Free Receive Descriptor ring */
235b9d30 2859 if (rdata->rx_desc) {
c39e3a1f 2860 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2861 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ
2862 rdata->rx_desc_dmap);
2863 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2864
235b9d30 2865 rdata->rx_desc = NULL;
a596084c 2866 }
bdca134f 2867
323e5ecd 2868 if (rdata->rx_buf == NULL)
5330213c
SZ
2869 return;
2870
2871 for (i = 0; i < ndesc; i++) {
323e5ecd 2872 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ
2873
2874 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2875 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2876 }
c39e3a1f
SZ
2877 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2878 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2879
323e5ecd
SZ
2880 kfree(rdata->rx_buf, M_DEVBUF);
2881 rdata->rx_buf = NULL;
5330213c
SZ
2882}
2883
2884static void
c39e3a1f 2885emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2886{
c39e3a1f 2887 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2888 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2889 uint32_t staterr;
235b9d30 2890 emx_rxdesc_t *current_desc;
5330213c
SZ
2891 struct mbuf *mp;
2892 int i;
5330213c 2893
c39e3a1f 2894 i = rdata->next_rx_desc_to_check;
235b9d30
SZ
2895 current_desc = &rdata->rx_desc[i];
2896 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2897
235b9d30 2898 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ
2899 return;
2900
235b9d30 2901 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2902 struct pktinfo *pi = NULL, pi0;
235b9d30 2903 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2904 struct mbuf *m = NULL;
0acc29d6 2905 int eop, len;
5330213c
SZ
2906
2907 logif(pkt_receive);
2908
235b9d30 2909 mp = rx_buf->m_head;
5330213c
SZ
2910
2911 /*
2912 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2913 * needs to access the last received byte in the mbuf.
2914 */
235b9d30 2915 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ
2916 BUS_DMASYNC_POSTREAD);
2917
0acc29d6 2918 len = le16toh(current_desc->rxd_length);
235b9d30 2919 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ
2920 count--;
2921 eop = 1;
5330213c
SZ
2922 } else {
2923 eop = 0;
5330213c
SZ
2924 }
2925
235b9d30
SZ
2926 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2927 uint16_t vlan = 0;
3f939c23 2928 uint32_t mrq, rss_hash;
235b9d30
SZ
2929
2930 /*
2931 * Save several necessary information,
2932 * before emx_newbuf() destroy it.
2933 */
2934 if ((staterr & E1000_RXD_STAT_VP) && eop)
2935 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2936
3f939c23
SZ
2937 mrq = le32toh(current_desc->rxd_mrq);
2938 rss_hash = le32toh(current_desc->rxd_rss);
2939
2940 EMX_RSS_DPRINTF(sc, 10,
2941 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2942 ring_idx, mrq, rss_hash);
2943
c39e3a1f 2944 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ
2945 ifp->if_iqdrops++;
2946 goto discard;
2947 }
2948
2949 /* Assign correct length to the current fragment */
2950 mp->m_len = len;
2951
c39e3a1f 2952 if (rdata->fmp == NULL) {
5330213c 2953 mp->m_pkthdr.len = len;
c39e3a1f
SZ
2954 rdata->fmp = mp; /* Store the first mbuf */
2955 rdata->lmp = mp;
5330213c
SZ
2956 } else {
2957 /*
2958 * Chain mbuf's together
2959 */
c39e3a1f
SZ
2960 rdata->lmp->m_next = mp;
2961 rdata->lmp = rdata->lmp->m_next;
2962 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ
2963 }
2964
2965 if (eop) {
c39e3a1f 2966 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ
2967 ifp->if_ipackets++;
2968
235b9d30
SZ
2969 if (ifp->if_capenable & IFCAP_RXCSUM)
2970 emx_rxcsum(staterr, rdata->fmp);
5330213c 2971
235b9d30 2972 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2973 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2974 vlan;
c39e3a1f 2975 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2976 }
c39e3a1f
SZ
2977 m = rdata->fmp;
2978 rdata->fmp = NULL;
2979 rdata->lmp = NULL;
3f939c23 2980
9cc86e17
SZ
2981 if (ifp->if_capenable & IFCAP_RSS) {
2982 pi = emx_rssinfo(m, &pi0, mrq,
2983 rss_hash, staterr);
2984 }
3f939c23
SZ
2985#ifdef EMX_RSS_DEBUG
2986 rdata->rx_pkts++;
2987#endif
5330213c
SZ
2988 }
2989 } else {
2990 ifp->if_ierrors++;
2991discard:
235b9d30 2992 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ
2993 if (rdata->fmp != NULL) {
2994 m_freem(rdata->fmp);
2995 rdata->fmp = NULL;
2996 rdata->lmp = NULL;
5330213c
SZ
2997 }
2998 m = NULL;
2999 }
3000
5330213c 3001 if (m != NULL)
eda7db08 3002 ether_input_pkt(ifp, m, pi);
5330213c
SZ
3003
3004 /* Advance our pointers to the next descriptor. */
c39e3a1f 3005 if (++i == rdata->num_rx_desc)
5330213c 3006 i = 0;
235b9d30
SZ
3007
3008 current_desc = &rdata->rx_desc[i];
3009 staterr = le32toh(current_desc->rxd_staterr);
5330213c 3010 }
c39e3a1f 3011 rdata->next_rx_desc_to_check = i;
5330213c 3012
3f939c23 3013 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 3014 if (--i < 0)
c39e3a1f 3015 i = rdata->num_rx_desc - 1;
3f939c23 3016 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ
3017}
3018
3019static void
5330213c
SZ
3020emx_enable_intr(struct emx_softc *sc)
3021{
2d0e5700
SZ
3022 uint32_t ims_mask = IMS_ENABLE_MASK;
3023
6d435846 3024 lwkt_serialize_handler_enable(&sc->main_serialize);
2d0e5700
SZ
3025
3026#if 0
3027 if (sc->hw.mac.type == e1000_82574) {
3028 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3029 ims_mask |= EM_MSIX_MASK;
3030 }
3031#endif
3032 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
5330213c
SZ
3033}
3034
3035static void
3036emx_disable_intr(struct emx_softc *sc)
3037{
2d0e5700
SZ
3038 if (sc->hw.mac.type == e1000_82574)
3039 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
5330213c 3040 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2d0e5700 3041
6d435846 3042 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ
3043}
3044
3045/*
3046 * Bit of a misnomer, what this really means is
3047 * to enable OS management of the system... aka
3048 * to disable special hardware management features
3049 */
3050static void
3051emx_get_mgmt(struct emx_softc *sc)
3052{
3053 /* A shared code workaround */
3054 if (sc->has_manage) {
3055 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3056 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3057
3058 /* disable hardware interception of ARP */
3059 manc &= ~(E1000_MANC_ARP_EN);
3060
3061 /* enable receiving management packets to the host */
3062 manc |= E1000_MANC_EN_MNG2HOST;
3063#define E1000_MNG2HOST_PORT_623 (1 << 5)
3064#define E1000_MNG2HOST_PORT_664 (1 << 6)
3065 manc2h |= E1000_MNG2HOST_PORT_623;
3066 manc2h |= E1000_MNG2HOST_PORT_664;
3067 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3068
3069 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3070 }
3071}
3072
3073/*
3074 * Give control back to hardware management
3075 * controller if there is one.
3076 */
3077static void
3078emx_rel_mgmt(struct emx_softc *sc)
3079{
3080 if (sc->has_manage) {
3081 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3082
3083 /* re-enable hardware interception of ARP */
3084 manc |= E1000_MANC_ARP_EN;
3085 manc &= ~E1000_MANC_EN_MNG2HOST;
3086
3087 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3088 }
3089}
3090
3091/*
3092 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3093 * For ASF and Pass Through versions of f/w this means that
3094 * the driver is loaded. For AMT version (only with 82573)
3095 * of the f/w this means that the network i/f is open.
3096 */
3097static void
3098emx_get_hw_control(struct emx_softc *sc)
3099{
5330213c 3100 /* Let firmware know the driver has taken over */
2d0e5700
SZ
3101 if (sc->hw.mac.type == e1000_82573) {
3102 uint32_t swsm;
3103
5330213c
SZ
3104 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3105 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3106 swsm | E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3107 } else {
3108 uint32_t ctrl_ext;
5330213c 3109
5330213c
SZ
3110 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3111 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3112 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
5330213c 3113 }
2d0e5700 3114 sc->control_hw = 1;
5330213c
SZ
3115}
3116
3117/*
3118 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3119 * For ASF and Pass Through versions of f/w this means that the
3120 * driver is no longer loaded. For AMT version (only with 82573)
3121 * of the f/w this means that the network i/f is closed.
3122 */
3123static void
3124emx_rel_hw_control(struct emx_softc *sc)
3125{
2d0e5700
SZ
3126 if (!sc->control_hw)
3127 return;
3128 sc->control_hw = 0;
5330213c
SZ
3129
3130 /* Let firmware taken over control of h/w */
2d0e5700
SZ
3131 if (sc->hw.mac.type == e1000_82573) {
3132 uint32_t swsm;
3133
5330213c
SZ
3134 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3135 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3136 swsm & ~E1000_SWSM_DRV_LOAD);
2d0e5700
SZ
3137 } else {
3138 uint32_t ctrl_ext;
5330213c 3139
5330213c
SZ
3140 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3141 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3142 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
5330213c
SZ
3143 }
3144}
3145
3146static int
3147emx_is_valid_eaddr(const uint8_t *addr)
3148{
3149 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3150
3151 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3152 return (FALSE);
3153
3154 return (TRUE);
3155}
3156
3157/*
3158 * Enable PCI Wake On Lan capability
3159 */
3160void
3161emx_enable_wol(device_t dev)
3162{
3163 uint16_t cap, status;
3164 uint8_t id;
3165
3166 /* First find the capabilities pointer*/
3167 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3168
3169 /* Read the PM Capabilities */
3170 id = pci_read_config(dev, cap, 1);
3171 if (id != PCIY_PMG) /* Something wrong */
3172 return;
3173
3174 /*
3175 * OK, we have the power capabilities,
3176 * so now get the status register
3177 */
3178 cap += PCIR_POWER_STATUS;
3179 status = pci_read_config(dev, cap, 2);
3180 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3181 pci_write_config(dev, cap, status, 2);
3182}
3183
3184static void
3185emx_update_stats(struct emx_softc *sc)
3186{
3187 struct ifnet *ifp = &sc->arpcom.ac_if;
3188
3189 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3190 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3191 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3192 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3193 }
3194 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3195 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3196 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3197 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3198
3199 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3200 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3201 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3202 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3203 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3204 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3205 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3206 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3207 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3208 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3209 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3210 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3211 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3212 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3213 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3214 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3215 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3216 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3217 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3218 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3219
3220 /* For the 64-bit byte counters the low dword must be read first. */
3221 /* Both registers clear on the read of the high dword */
3222
3223 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3224 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3225
3226 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3227 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3228 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3229 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3230 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3231
3232 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3233 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3234
3235 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3236 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3237 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3238 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3239 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3240 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3241 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3242 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3243 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3244 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3245
3246 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3247 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3248 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3249 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3250 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3251 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3252
3253 ifp->if_collisions = sc->stats.colc;
3254
3255 /* Rx Errors */
3256 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3257 sc->stats.crcerrs + sc->stats.algnerrc +
3258 sc->stats.ruc + sc->stats.roc +
3259 sc->stats.mpc + sc->stats.cexterr;
3260
3261 /* Tx Errors */
3262 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3263 sc->watchdog_events;
3264}
3265
3266static void
3267emx_print_debug_info(struct emx_softc *sc)
3268{
3269 device_t dev = sc->dev;
3270 uint8_t *hw_addr = sc->hw.hw_addr;
3271
3272 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3273 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3274 E1000_READ_REG(&sc->hw, E1000_CTRL),
3275 E1000_READ_REG(&sc->hw, E1000_RCTL));
3276 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3277 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3278 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3279 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3280 sc->hw.fc.high_water, sc->hw.fc.low_water);
3281 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3282 E1000_READ_REG(&sc->hw, E1000_TIDV),
3283 E1000_READ_REG(&sc->hw, E1000_TADV));
3284 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3285 E1000_READ_REG(&sc->hw, E1000_RDTR),
3286 E1000_READ_REG(&sc->hw, E1000_RADV));
3287 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3288 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3289 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3290 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3291 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3292 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3293 device_printf(dev, "Num Tx descriptors avail = %d\n",
3294 sc->num_tx_desc_avail);
3295 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3296 sc->no_tx_desc_avail1);
3297 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3298 sc->no_tx_desc_avail2);
3299 device_printf(dev, "Std mbuf failed = %ld\n",
3300 sc->mbuf_alloc_failed);
3301 device_printf(dev, "Std mbuf cluster failed = %ld\n",
c39e3a1f 3302 sc->rx_data[0].mbuf_cluster_failed);
5330213c
SZ
3303 device_printf(dev, "Driver dropped packets = %ld\n",
3304 sc->dropped_pkts);
3305 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3306 sc->no_tx_dma_setup);
3307
3308 device_printf(dev, "TXCSUM try pullup = %lu\n",
3309 sc->tx_csum_try_pullup);
3310 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3311 sc->tx_csum_pullup1);
3312 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3313 sc->tx_csum_pullup1_failed);
3314 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3315 sc->tx_csum_pullup2);
3316 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3317 sc->tx_csum_pullup2_failed);
3318 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3319 sc->tx_csum_drop1);
3320 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3321 sc->tx_csum_drop2);
3322}
3323
3324static void
3325emx_print_hw_stats(struct emx_softc *sc)
3326{
3327 device_t dev = sc->dev;
3328
3329 device_printf(dev, "Excessive collisions = %lld\n",
3330 (long long)sc->stats.ecol);
3331#if (DEBUG_HW > 0) /* Dont output these errors normally */
3332 device_printf(dev, "Symbol errors = %lld\n",
3333 (long long)sc->stats.symerrs);
3334#endif
3335 device_printf(dev, "Sequence errors = %lld\n",
3336 (long long)sc->stats.sec);
3337 device_printf(dev, "Defer count = %lld\n",
3338 (long long)sc->stats.dc);
3339 device_printf(dev, "Missed Packets = %lld\n",
3340 (long long)sc->stats.mpc);
3341 device_printf(dev, "Receive No Buffers = %lld\n",
3342 (long long)sc->stats.rnbc);
3343 /* RLEC is inaccurate on some hardware, calculate our own. */
3344 device_printf(dev, "Receive Length Errors = %lld\n",
3345 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3346 device_printf(dev, "Receive errors = %lld\n",
3347 (long long)sc->stats.rxerrc);
3348 device_printf(dev, "Crc errors = %lld\n",
3349 (long long)sc->stats.crcerrs);
3350 device_printf(dev, "Alignment errors = %lld\n",
3351 (long long)sc->stats.algnerrc);
3352 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3353 (long long)sc->stats.cexterr);
3354 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3355 device_printf(dev, "watchdog timeouts = %ld\n",
3356 sc->watchdog_events);
3357 device_printf(dev, "XON Rcvd = %lld\n",
3358 (long long)sc->stats.xonrxc);
3359 device_printf(dev, "XON Xmtd = %lld\n",
3360 (long long)sc->stats.xontxc);
3361 device_printf(dev, "XOFF Rcvd = %lld\n",
3362 (long long)sc->stats.xoffrxc);
3363 device_printf(dev, "XOFF Xmtd = %lld\n",
3364 (long long)sc->stats.xofftxc);
3365 device_printf(dev, "Good Packets Rcvd = %lld\n",
3366 (long long)sc->stats.gprc);
3367 device_printf(dev, "Good Packets Xmtd = %lld\n",
3368 (long long)sc->stats.gptc);
3369}
3370
3371static void
3372emx_print_nvm_info(struct emx_softc *sc)
3373{
3374 uint16_t eeprom_data;
3375 int i, j, row = 0;
3376
3377 /* Its a bit crude, but it gets the job done */
3378 kprintf("\nInterface EEPROM Dump:\n");
3379 kprintf("Offset\n0x0000 ");
3380 for (i = 0, j = 0; i < 32; i++, j++) {
3381 if (j == 8) { /* Make the offset block */
3382 j = 0; ++row;
3383 kprintf("\n0x00%x0 ",row);
3384 }
3385 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3386 kprintf("%04x ", eeprom_data);
3387 }
3388 kprintf("\n");
3389}
3390
3391static int
3392emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3393{
3394 struct emx_softc *sc;
3395 struct ifnet *ifp;
3396 int error, result;
3397
3398 result = -1;
3399 error = sysctl_handle_int(oidp, &result, 0, req);
3400 if (error || !req->newptr)
3401 return (error);
3402
3403 sc = (struct emx_softc *)arg1;
3404 ifp = &sc->arpcom.ac_if;
3405
6d435846 3406 ifnet_serialize_all(ifp);
5330213c
SZ
3407
3408 if (result == 1)
3409 emx_print_debug_info(sc);
3410
3411 /*
3412 * This value will cause a hex dump of the
3413 * first 32 16-bit words of the EEPROM to
3414 * the screen.
3415 */
3416 if (result == 2)
3417 emx_print_nvm_info(sc);
3418
6d435846 3419 ifnet_deserialize_all(ifp);
5330213c
SZ
3420
3421 return (error);
3422}
3423
3424static int
3425emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3426{
3427 int error, result;
3428
3429 result = -1;
3430 error = sysctl_handle_int(oidp, &result, 0, req);
3431 if (error || !req->newptr)
3432 return (error);
3433
3434 if (result == 1) {
3435 struct emx_softc *sc = (struct emx_softc *)arg1;
3436 struct ifnet *ifp = &sc->arpcom.ac_if;
3437
6d435846 3438 ifnet_serialize_all(ifp);
5330213c 3439 emx_print_hw_stats(sc);
6d435846 3440 ifnet_deserialize_all(ifp);
5330213c
SZ
3441 }
3442 return (error);
3443}
3444
3445static void
3446emx_add_sysctl(struct emx_softc *sc)
3447{
3f939c23
SZ
3448#ifdef EMX_RSS_DEBUG
3449 char rx_pkt[32];
3450 int i;
3451#endif
5330213c
SZ
3452
3453 sysctl_ctx_init(&sc->sysctl_ctx);
3454 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3455 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3456 device_get_nameunit(sc->dev),
3457 CTLFLAG_RD, 0, "");
3458 if (sc->sysctl_tree == NULL) {
3459 device_printf(sc->dev, "can't add sysctl node\n");
3460 return;
3461 }
3462
3463 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3464 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3465 emx_sysctl_debug_info, "I", "Debug Information");
3466
3467 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3468 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3469 emx_sysctl_stats, "I", "Statistics");
3470
3471 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ
3472 OID_AUTO, "rxd", CTLFLAG_RD,
3473 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3474 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3475 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3476
5330213c
SZ
3477 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3478 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3479 sc, 0, emx_sysctl_int_throttle, "I",
3480 "interrupt throttling rate");
3481 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3482 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3483 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3484 "# segments per TX interrupt");
3f939c23 3485
8434a83b 3486 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
13890b61
SZ
3487 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3488 &sc->rx_ring_cnt, 0, "RX ring count");
8434a83b 3489
3f939c23
SZ
3490#ifdef EMX_RSS_DEBUG
3491 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3492 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3493 0, "RSS debug level");
65c7a6af 3494 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3495 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3496 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3497 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3498 rx_pkt, CTLFLAG_RW,
3f939c23
SZ
3499 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3500 }
3501#endif
5330213c
SZ
3502}
3503
3504static int
3505emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3506{
3507 struct emx_softc *sc = (void *)arg1;
3508 struct ifnet *ifp = &sc->arpcom.ac_if;
3509 int error, throttle;
3510
3511 throttle = sc->int_throttle_ceil;
3512 error = sysctl_handle_int(oidp, &throttle, 0, req);
3513 if (error || req->newptr == NULL)
3514 return error;
3515 if (throttle < 0 || throttle > 1000000000 / 256)
3516 return EINVAL;
3517
3518 if (throttle) {
3519 /*
3520 * Set the interrupt throttling rate in 256ns increments,
3521 * recalculate sysctl value assignment to get exact frequency.
3522 */
3523 throttle = 1000000000 / 256 / throttle;
3524
3525 /* Upper 16bits of ITR is reserved and should be zero */
3526 if (throttle & 0xffff0000)
3527 return EINVAL;
3528 }
3529
6d435846 3530 ifnet_serialize_all(ifp);
5330213c
SZ
3531
3532 if (throttle)
3533 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3534 else
3535 sc->int_throttle_ceil = 0;
3536
3537 if (ifp->if_flags & IFF_RUNNING)
2d0e5700 3538 emx_set_itr(sc, throttle);
5330213c 3539
6d435846 3540 ifnet_deserialize_all(ifp);
5330213c
SZ
3541
3542 if (bootverbose) {
3543 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3544 sc->int_throttle_ceil);
3545 }
3546 return 0;
3547}
3548
3549static int
3550emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3551{
3552 struct emx_softc *sc = (void *)arg1;
3553 struct ifnet *ifp = &sc->arpcom.ac_if;
3554 int error, segs;
3555
3556 segs = sc->tx_int_nsegs;
3557 error = sysctl_handle_int(oidp, &segs, 0, req);
3558 if (error || req->newptr == NULL)
3559 return error;
3560 if (segs <= 0)
3561 return EINVAL;
3562
6d435846 3563 ifnet_serialize_all(ifp);
5330213c
SZ
3564
3565 /*
3566 * Don't allow int_tx_nsegs to become:
3567 * o Less the oact_tx_desc
3568 * o Too large that no TX desc will cause TX interrupt to
3569 * be generated (OACTIVE will never recover)
3570 * o Too small that will cause tx_dd[] overflow
3571 */
3572 if (segs < sc->oact_tx_desc ||
3573 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3574 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3575 error = EINVAL;
3576 } else {
3577 error = 0;
3578 sc->tx_int_nsegs = segs;
3579 }
3580
6d435846 3581 ifnet_deserialize_all(ifp);
5330213c
SZ
3582
3583 return error;
3584}
071699f8
SZ
3585
3586static int
3587emx_dma_alloc(struct emx_softc *sc)
3588{
3f939c23 3589 int error, i;
071699f8
SZ
3590
3591 /*
3592 * Create top level busdma tag
3593 */
3594 error = bus_dma_tag_create(NULL, 1, 0,
3595 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3596 NULL, NULL,
3597 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3598 0, &sc->parent_dtag);
3599 if (error) {
3600 device_printf(sc->dev, "could not create top level DMA tag\n");
3601 return error;
3602 }
3603
3604 /*
3605 * Allocate transmit descriptors ring and buffers
3606 */
3607 error = emx_create_tx_ring(sc);
3608 if (error) {
3609 device_printf(sc->dev, "Could not setup transmit structures\n");
3610 return error;
3611 }
3612
3613 /*
3614 * Allocate receive descriptors ring and buffers
3615 */
65c7a6af 3616 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3617 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3618 if (error) {
3619 device_printf(sc->dev,
3620 "Could not setup receive structures\n");
3621 return error;
3622 }
071699f8
SZ
3623 }
3624 return 0;
3625}
3626
3627static void
3628emx_dma_free(struct emx_softc *sc)
3629{
3f939c23
SZ
3630 int i;
3631
071699f8 3632 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3633
65c7a6af 3634 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3635 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3636 sc->rx_data[i].num_rx_desc);
3637 }
071699f8
SZ
3638
3639 /* Free top level busdma tag */
3640 if (sc->parent_dtag != NULL)
3641 bus_dma_tag_destroy(sc->parent_dtag);
3642}
6d435846
SZ
3643
3644static void
3645emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3646{
3647 struct emx_softc *sc = ifp->if_softc;
6d435846 3648
8f594b38
SZ
3649 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3650 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3651}
3652
3653static void
3654emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3655{
3656 struct emx_softc *sc = ifp->if_softc;
6d435846 3657
8f594b38
SZ
3658 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3659 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ
3660}
3661
3662static int
3663emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3664{
3665 struct emx_softc *sc = ifp->if_softc;
6d435846 3666
8f594b38
SZ
3667 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3668 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846 3669}
bca7c435
SZ
3670
3671static void
3672emx_serialize_skipmain(struct emx_softc *sc)
3673{
3674 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3675}
3676
3677static void
3678emx_deserialize_skipmain(struct emx_softc *sc)
3679{
3680 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3681}
2c9effcf
SZ
3682
3683#ifdef INVARIANTS
3684
3685static void
3686emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
8f594b38 3687 boolean_t serialized)
2c9effcf
SZ
3688{
3689 struct emx_softc *sc = ifp->if_softc;
2c9effcf 3690
8f594b38
SZ
3691 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3692 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
2c9effcf
SZ
3693}
3694
3695#endif /* INVARIANTS */
b3a7093f
SZ
3696
3697#ifdef IFPOLL_ENABLE
3698
3699static void
3700emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3701{
3702 struct emx_softc *sc = ifp->if_softc;
3703 uint32_t reg_icr;
3704
3705 ASSERT_SERIALIZED(&sc->main_serialize);
3706
3707 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3708 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3cbe4103
SZ
3709 emx_serialize_skipmain(sc);
3710
3711 callout_stop(&sc->timer);
3712 sc->hw.mac.get_link_status = 1;
3713 emx_update_link_status(sc);
3714 callout_reset(&sc->timer, hz, emx_timer, sc);
3715
3716 emx_deserialize_skipmain(sc);
b3a7093f
SZ
3717 }
3718}
3719
3720static void
3721emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3722{
3723 struct emx_softc *sc = ifp->if_softc;
3724
3725 ASSERT_SERIALIZED(&sc->tx_serialize);
3726
3727 emx_txeof(sc);
3728 if (!ifq_is_empty(&ifp->if_snd))
3729 if_devstart(ifp);
3730}