kernel: Use NULL for DRIVER_MODULE()'s evh & arg (which are pointers).
[dragonfly.git] / sys / dev / disk / mpt / mpt_pci.c
CommitLineData
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1/*-
2 * PCI specific probe and attach routines for LSI Fusion Adapters
984263bc
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3 * FreeBSD Version.
4 *
d751f32e 5 * Copyright (c) 2000, 2001 by Greg Ansley
984263bc 6 * Partially derived from Matt Jacob's ISP driver.
d751f32e
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7 * Copyright (c) 1997, 1998, 1999, 2000, 2001, 2002 by Matthew Jacob
8 * Feral Software
9 * All rights reserved.
984263bc
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10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice immediately at the beginning of the file, without modification,
16 * this list of conditions, and the following disclaimer.
17 * 2. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
d751f32e
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32/*-
33 * Copyright (c) 2002, 2006 by Matthew Jacob
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are
38 * met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
42 * substantially similar to the "NO WARRANTY" disclaimer below
43 * ("Disclaimer") and any redistribution must be conditioned upon including
44 * a substantially similar Disclaimer requirement for further binary
45 * redistribution.
46 * 3. Neither the names of the above listed copyright holders nor the names
47 * of any contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
60 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 * Support from Chris Ellsworth in order to make SAS adapters work
63 * is gratefully acknowledged.
64 *
65 * Support from LSI-Logic has also gone a great deal toward making this a
66 * workable subsystem and is gratefully acknowledged.
67 */
984263bc 68/*
d751f32e
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69 * Copyright (c) 2004, Avid Technology, Inc. and its contributors.
70 * Copyright (c) 2005, WHEEL Sp. z o.o.
71 * Copyright (c) 2004, 2005 Justin T. Gibbs
72 * All rights reserved.
73 *
74 * Redistribution and use in source and binary forms, with or without
75 * modification, are permitted provided that the following conditions are
76 * met:
77 * 1. Redistributions of source code must retain the above copyright
78 * notice, this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
80 * substantially similar to the "NO WARRANTY" disclaimer below
81 * ("Disclaimer") and any redistribution must be conditioned upon including
82 * a substantially similar Disclaimer requirement for further binary
83 * redistribution.
84 * 3. Neither the names of the above listed copyright holders nor the names
85 * of any contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
87 *
88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
91 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
92 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
98 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af04f7 99 *
6d259fc1 100 * $FreeBSD: src/sys/dev/mpt/mpt_pci.c,v 1.61 2011/04/22 09:59:16 marius Exp $
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101 */
102
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103#include <dev/disk/mpt/mpt.h>
104#include <dev/disk/mpt/mpt_cam.h>
105#include <dev/disk/mpt/mpt_raid.h>
984263bc 106
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107#ifndef PCI_VENDOR_LSI
108#define PCI_VENDOR_LSI 0x1000
109#endif
984263bc 110
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111#ifndef PCI_PRODUCT_LSI_FC909
112#define PCI_PRODUCT_LSI_FC909 0x0620
113#endif
114
115#ifndef PCI_PRODUCT_LSI_FC909A
116#define PCI_PRODUCT_LSI_FC909A 0x0621
117#endif
118
119#ifndef PCI_PRODUCT_LSI_FC919
120#define PCI_PRODUCT_LSI_FC919 0x0624
121#endif
122
123#ifndef PCI_PRODUCT_LSI_FC929
124#define PCI_PRODUCT_LSI_FC929 0x0622
125#endif
126
127#ifndef PCI_PRODUCT_LSI_FC929X
128#define PCI_PRODUCT_LSI_FC929X 0x0626
129#endif
130
131#ifndef PCI_PRODUCT_LSI_FC919X
132#define PCI_PRODUCT_LSI_FC919X 0x0628
133#endif
134
135#ifndef PCI_PRODUCT_LSI_FC7X04X
136#define PCI_PRODUCT_LSI_FC7X04X 0x0640
137#endif
138
139#ifndef PCI_PRODUCT_LSI_FC646
140#define PCI_PRODUCT_LSI_FC646 0x0646
141#endif
142
143#ifndef PCI_PRODUCT_LSI_1030
144#define PCI_PRODUCT_LSI_1030 0x0030
145#endif
146
147#ifndef PCI_PRODUCT_LSI_SAS1064
148#define PCI_PRODUCT_LSI_SAS1064 0x0050
149#endif
150
151#ifndef PCI_PRODUCT_LSI_SAS1064A
152#define PCI_PRODUCT_LSI_SAS1064A 0x005C
153#endif
154
155#ifndef PCI_PRODUCT_LSI_SAS1064E
156#define PCI_PRODUCT_LSI_SAS1064E 0x0056
157#endif
158
159#ifndef PCI_PRODUCT_LSI_SAS1066
160#define PCI_PRODUCT_LSI_SAS1066 0x005E
161#endif
162
163#ifndef PCI_PRODUCT_LSI_SAS1066E
164#define PCI_PRODUCT_LSI_SAS1066E 0x005A
165#endif
166
167#ifndef PCI_PRODUCT_LSI_SAS1068
168#define PCI_PRODUCT_LSI_SAS1068 0x0054
169#endif
170
171#ifndef PCI_PRODUCT_LSI_SAS1068E
172#define PCI_PRODUCT_LSI_SAS1068E 0x0058
173#endif
174
175#ifndef PCI_PRODUCT_LSI_SAS1078
176#define PCI_PRODUCT_LSI_SAS1078 0x0062
177#endif
178
179#ifndef PCI_PRODUCT_LSI_SAS1078DE
180#define PCI_PRODUCT_LSI_SAS1078DE 0x007C
181#endif
984263bc 182
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183#ifndef PCIM_CMD_SERRESPEN
184#define PCIM_CMD_SERRESPEN 0x0100
185#endif
186
187
188
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189static int mpt_pci_probe(device_t);
190static int mpt_pci_attach(device_t);
191static void mpt_free_bus_resources(struct mpt_softc *mpt);
192static int mpt_pci_detach(device_t);
193static int mpt_pci_shutdown(device_t);
194static int mpt_dma_mem_alloc(struct mpt_softc *mpt);
195static void mpt_dma_mem_free(struct mpt_softc *mpt);
196static void mpt_read_config_regs(struct mpt_softc *mpt);
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197static void mpt_pci_intr(void *);
198
199static device_method_t mpt_methods[] = {
200 /* Device interface */
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201 DEVMETHOD(device_probe, mpt_pci_probe),
202 DEVMETHOD(device_attach, mpt_pci_attach),
203 DEVMETHOD(device_detach, mpt_pci_detach),
204 DEVMETHOD(device_shutdown, mpt_pci_shutdown),
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205 { 0, 0 }
206};
207
208static driver_t mpt_driver = {
d751f32e 209 "mpt", mpt_methods, sizeof(struct mpt_softc)
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210};
211static devclass_t mpt_devclass;
aa2b9d05 212DRIVER_MODULE(mpt, pci, mpt_driver, mpt_devclass, NULL, NULL);
d751f32e 213MODULE_DEPEND(mpt, pci, 1, 1, 1);
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214MODULE_VERSION(mpt, 1);
215
984263bc 216static int
d751f32e 217mpt_pci_probe(device_t dev)
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218{
219 char *desc;
220
d751f32e 221 if (pci_get_vendor(dev) != PCI_VENDOR_LSI) {
984263bc 222 return (ENXIO);
d751f32e 223 }
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224
225 switch ((pci_get_device(dev) & ~1)) {
d751f32e 226 case PCI_PRODUCT_LSI_FC909:
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227 desc = "LSILogic FC909 FC Adapter";
228 break;
d751f32e 229 case PCI_PRODUCT_LSI_FC909A:
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230 desc = "LSILogic FC909A FC Adapter";
231 break;
d751f32e 232 case PCI_PRODUCT_LSI_FC919:
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233 desc = "LSILogic FC919 FC Adapter";
234 break;
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235 case PCI_PRODUCT_LSI_FC929:
236 desc = "Dual LSILogic FC929 FC Adapter";
984263bc 237 break;
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238 case PCI_PRODUCT_LSI_FC919X:
239 desc = "LSILogic FC919 FC PCI-X Adapter";
d30c73c7 240 break;
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241 case PCI_PRODUCT_LSI_FC929X:
242 desc = "Dual LSILogic FC929X 2Gb/s FC PCI-X Adapter";
243 break;
244 case PCI_PRODUCT_LSI_FC646:
245 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-Express Adapter";
246 break;
247 case PCI_PRODUCT_LSI_FC7X04X:
248 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-X Adapter";
249 break;
250 case PCI_PRODUCT_LSI_1030:
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251 desc = "LSILogic 1030 Ultra4 Adapter";
252 break;
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253 case PCI_PRODUCT_LSI_SAS1064:
254 case PCI_PRODUCT_LSI_SAS1064A:
255 case PCI_PRODUCT_LSI_SAS1064E:
256 case PCI_PRODUCT_LSI_SAS1066:
257 case PCI_PRODUCT_LSI_SAS1066E:
258 case PCI_PRODUCT_LSI_SAS1068:
259 case PCI_PRODUCT_LSI_SAS1068E:
260 case PCI_PRODUCT_LSI_SAS1078:
261 case PCI_PRODUCT_LSI_SAS1078DE:
262 desc = "LSILogic SAS/SATA Adapter";
263 break;
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MD
264 default:
265 return (ENXIO);
266 }
267
268 device_set_desc(dev, desc);
269 return (0);
270}
271
984263bc 272static void
d751f32e 273mpt_set_options(struct mpt_softc *mpt)
984263bc
MD
274{
275 int bitmap;
276
277 bitmap = 0;
2545bca0 278 if (kgetenv_int("mpt_disable", &bitmap)) {
984263bc
MD
279 if (bitmap & (1 << mpt->unit)) {
280 mpt->disabled = 1;
281 }
282 }
d751f32e 283 bitmap = 0;
2545bca0 284 if (kgetenv_int("mpt_debug", &bitmap)) {
d751f32e
MD
285 if (bitmap & (1 << mpt->unit)) {
286 mpt->verbose = MPT_PRT_DEBUG;
287 }
288 }
289 bitmap = 0;
2545bca0 290 if (kgetenv_int("mpt_debug1", &bitmap)) {
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291 if (bitmap & (1 << mpt->unit)) {
292 mpt->verbose = MPT_PRT_DEBUG1;
293 }
294 }
295 bitmap = 0;
2545bca0 296 if (kgetenv_int("mpt_debug2", &bitmap)) {
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297 if (bitmap & (1 << mpt->unit)) {
298 mpt->verbose = MPT_PRT_DEBUG2;
299 }
300 }
301 bitmap = 0;
2545bca0 302 if (kgetenv_int("mpt_debug3", &bitmap)) {
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MD
303 if (bitmap & (1 << mpt->unit)) {
304 mpt->verbose = MPT_PRT_DEBUG3;
305 }
306 }
984263bc 307
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308 mpt->cfg_role = MPT_ROLE_DEFAULT;
309 bitmap = 0;
2545bca0 310 if (kgetenv_int("mpt_nil_role", &bitmap)) {
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311 if (bitmap & (1 << mpt->unit)) {
312 mpt->cfg_role = 0;
313 }
314 mpt->do_cfg_role = 1;
315 }
316 bitmap = 0;
2545bca0 317 if (kgetenv_int("mpt_tgt_role", &bitmap)) {
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318 if (bitmap & (1 << mpt->unit)) {
319 mpt->cfg_role |= MPT_ROLE_TARGET;
320 }
321 mpt->do_cfg_role = 1;
322 }
984263bc 323 bitmap = 0;
2545bca0 324 if (kgetenv_int("mpt_ini_role", &bitmap)) {
984263bc 325 if (bitmap & (1 << mpt->unit)) {
d751f32e 326 mpt->cfg_role |= MPT_ROLE_INITIATOR;
984263bc 327 }
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328 mpt->do_cfg_role = 1;
329 }
330 mpt->msi_enable = 0;
331}
d751f32e 332
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333
334static void
d751f32e 335mpt_link_peer(struct mpt_softc *mpt)
984263bc 336{
d751f32e 337 struct mpt_softc *mpt2;
984263bc
MD
338
339 if (mpt->unit == 0) {
340 return;
341 }
984263bc
MD
342 /*
343 * XXX: depends on probe order
344 */
d751f32e 345 mpt2 = (struct mpt_softc *)devclass_get_softc(mpt_devclass,mpt->unit-1);
984263bc
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346
347 if (mpt2 == NULL) {
348 return;
349 }
350 if (pci_get_vendor(mpt2->dev) != pci_get_vendor(mpt->dev)) {
351 return;
352 }
353 if (pci_get_device(mpt2->dev) != pci_get_device(mpt->dev)) {
354 return;
355 }
356 mpt->mpt2 = mpt2;
357 mpt2->mpt2 = mpt;
d751f32e
MD
358 if (mpt->verbose >= MPT_PRT_DEBUG) {
359 mpt_prt(mpt, "linking with peer (mpt%d)\n",
984263bc
MD
360 device_get_unit(mpt2->dev));
361 }
362}
363
d751f32e
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364static void
365mpt_unlink_peer(struct mpt_softc *mpt)
366{
367 if (mpt->mpt2) {
368 mpt->mpt2->mpt2 = NULL;
369 }
370}
371
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372
373static int
d751f32e 374mpt_pci_attach(device_t dev)
984263bc 375{
d751f32e
MD
376 struct mpt_softc *mpt;
377 int iqd;
378 uint32_t data, cmd;
6d259fc1 379 int mpt_io_bar, mpt_mem_bar;
984263bc
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380
381 /* Allocate the softc structure */
d751f32e 382 mpt = (struct mpt_softc*)device_get_softc(dev);
984263bc
MD
383 if (mpt == NULL) {
384 device_printf(dev, "cannot allocate softc\n");
385 return (ENOMEM);
386 }
d751f32e 387 memset(mpt, 0, sizeof(struct mpt_softc));
984263bc 388 switch ((pci_get_device(dev) & ~1)) {
d751f32e
MD
389 case PCI_PRODUCT_LSI_FC909:
390 case PCI_PRODUCT_LSI_FC909A:
391 case PCI_PRODUCT_LSI_FC919:
392 case PCI_PRODUCT_LSI_FC929:
393 case PCI_PRODUCT_LSI_FC919X:
394 case PCI_PRODUCT_LSI_FC646:
395 case PCI_PRODUCT_LSI_FC7X04X:
984263bc
MD
396 mpt->is_fc = 1;
397 break;
d751f32e
MD
398 case PCI_PRODUCT_LSI_SAS1064:
399 case PCI_PRODUCT_LSI_SAS1064A:
400 case PCI_PRODUCT_LSI_SAS1064E:
401 case PCI_PRODUCT_LSI_SAS1066:
402 case PCI_PRODUCT_LSI_SAS1066E:
403 case PCI_PRODUCT_LSI_SAS1068:
404 case PCI_PRODUCT_LSI_SAS1068E:
405 case PCI_PRODUCT_LSI_SAS1078:
406 case PCI_PRODUCT_LSI_SAS1078DE:
407 mpt->is_sas = 1;
408 break;
984263bc 409 default:
d751f32e 410 mpt->is_spi = 1;
984263bc
MD
411 break;
412 }
413 mpt->dev = dev;
414 mpt->unit = device_get_unit(dev);
d751f32e
MD
415 mpt->raid_resync_rate = MPT_RAID_RESYNC_RATE_DEFAULT;
416 mpt->raid_mwce_setting = MPT_RAID_MWCE_DEFAULT;
417 mpt->raid_queue_depth = MPT_RAID_QUEUE_DEPTH_DEFAULT;
418 mpt->verbose = MPT_PRT_NONE;
419 mpt->role = MPT_ROLE_NONE;
6d259fc1 420 mpt->mpt_ini_id = MPT_INI_ID_NONE;
984263bc 421 mpt_set_options(mpt);
d751f32e
MD
422 if (mpt->verbose == MPT_PRT_NONE) {
423 mpt->verbose = MPT_PRT_WARN;
424 /* Print INFO level (if any) if bootverbose is set */
425 mpt->verbose += (bootverbose != 0)? 1 : 0;
426 }
984263bc
MD
427 /* Make sure memory access decoders are enabled */
428 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
429 if ((cmd & PCIM_CMD_MEMEN) == 0) {
430 device_printf(dev, "Memory accesses disabled");
d751f32e 431 return (ENXIO);
984263bc
MD
432 }
433
434 /*
435 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
436 */
437 cmd |=
438 PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN |
439 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
440 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
441
442 /*
443 * Make sure we've disabled the ROM.
444 */
445 data = pci_read_config(dev, PCIR_BIOS, 4);
6d259fc1 446 data &= ~PCIM_BIOS_ENABLE;
984263bc
MD
447 pci_write_config(dev, PCIR_BIOS, data, 4);
448
984263bc
MD
449 /*
450 * Is this part a dual?
451 * If so, link with our partner (around yet)
452 */
d751f32e
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453 if ((pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC929 ||
454 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC646 ||
455 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC7X04X ||
456 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_1030) {
984263bc
MD
457 mpt_link_peer(mpt);
458 }
459
6d259fc1
SW
460 /*
461 * Figure out which are the I/O and MEM Bars
462 */
463 data = pci_read_config(dev, PCIR_BAR(0), 4);
464 if (PCI_BAR_IO(data)) {
465 /* BAR0 is IO, BAR1 is memory */
466 mpt_io_bar = 0;
467 mpt_mem_bar = 1;
468 } else {
469 /* BAR0 is memory, BAR1 is IO */
470 mpt_mem_bar = 0;
471 mpt_io_bar = 1;
472 }
473
d751f32e
MD
474 /*
475 * Set up register access. PIO mode is required for
476 * certain reset operations (but must be disabled for
477 * some cards otherwise).
478 */
6d259fc1
SW
479 mpt->pci_pio_rid = PCIR_BAR(mpt_io_bar);
480 mpt->pci_pio_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
481 &mpt->pci_pio_rid, RF_ACTIVE);
d751f32e
MD
482 if (mpt->pci_pio_reg == NULL) {
483 device_printf(dev, "unable to map registers in PIO mode\n");
484 goto bad;
485 }
486 mpt->pci_pio_st = rman_get_bustag(mpt->pci_pio_reg);
487 mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg);
488
984263bc 489 /* Allocate kernel virtual memory for the 9x9's Mem0 region */
6d259fc1
SW
490 mpt->pci_mem_rid = PCIR_BAR(mpt_mem_bar);
491 mpt->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
492 &mpt->pci_mem_rid, RF_ACTIVE);
984263bc 493 if (mpt->pci_reg == NULL) {
d751f32e
MD
494 device_printf(dev, "Unable to memory map registers.\n");
495 if (mpt->is_sas) {
496 device_printf(dev, "Giving Up.\n");
497 goto bad;
498 }
499 device_printf(dev, "Falling back to PIO mode.\n");
500 mpt->pci_st = mpt->pci_pio_st;
501 mpt->pci_sh = mpt->pci_pio_sh;
502 } else {
503 mpt->pci_st = rman_get_bustag(mpt->pci_reg);
504 mpt->pci_sh = rman_get_bushandle(mpt->pci_reg);
984263bc 505 }
984263bc
MD
506
507 /* Get a handle to the interrupt */
508 iqd = 0;
d751f32e
MD
509 if (mpt->msi_enable) {
510 /*
511 * First try to alloc an MSI-X message. If that
512 * fails, then try to alloc an MSI message instead.
513 */
514 if (pci_msix_count(dev) == 1) {
515 mpt->pci_msi_count = 1;
516 if (pci_alloc_msix(dev, &mpt->pci_msi_count) == 0) {
517 iqd = 1;
518 } else {
519 mpt->pci_msi_count = 0;
520 }
521 }
522 if (iqd == 0 && pci_msi_count(dev) == 1) {
523 mpt->pci_msi_count = 1;
524 if (pci_alloc_msi(dev, &mpt->pci_msi_count) == 0) {
525 iqd = 1;
526 } else {
527 mpt->pci_msi_count = 0;
528 }
529 }
530 }
531 mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd,
532 RF_ACTIVE | RF_SHAREABLE);
984263bc
MD
533 if (mpt->pci_irq == NULL) {
534 device_printf(dev, "could not allocate interrupt\n");
535 goto bad;
536 }
537
984263bc
MD
538 MPT_LOCK_SETUP(mpt);
539
540 /* Disable interrupts at the part */
541 mpt_disable_ints(mpt);
542
d751f32e 543 /* Register the interrupt handler */
6d259fc1 544 if (mpt_setup_intr(dev, mpt->pci_irq, 0, NULL, mpt_pci_intr,
d751f32e
MD
545 mpt, &mpt->ih)) {
546 device_printf(dev, "could not setup interrupt\n");
547 goto bad;
548 }
549
984263bc 550 /* Allocate dma memory */
6d259fc1 551/* XXX JGibbs -Should really be done based on IOCFacts. */
984263bc 552 if (mpt_dma_mem_alloc(mpt)) {
d751f32e 553 mpt_prt(mpt, "Could not allocate DMA memory\n");
984263bc
MD
554 goto bad;
555 }
556
557 /*
558 * Save the PCI config register values
559 *
560 * Hard resets are known to screw up the BAR for diagnostic
561 * memory accesses (Mem1).
562 *
6d259fc1 563 * Using Mem1 is known to make the chip stop responding to
984263bc
MD
564 * configuration space transfers, so we need to save it now
565 */
566
567 mpt_read_config_regs(mpt);
568
d751f32e
MD
569 /*
570 * Disable PIO until we need it
571 */
572 if (mpt->is_sas) {
573 pci_disable_io(dev, SYS_RES_IOPORT);
574 }
575
984263bc
MD
576 /* Initialize the hardware */
577 if (mpt->disabled == 0) {
d751f32e 578 if (mpt_attach(mpt) != 0) {
984263bc
MD
579 goto bad;
580 }
d751f32e
MD
581 } else {
582 mpt_prt(mpt, "device disabled at user request\n");
583 goto bad;
984263bc
MD
584 }
585
d751f32e
MD
586 mpt->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, mpt_pci_shutdown,
587 dev, SHUTDOWN_PRI_DEFAULT);
588
589 if (mpt->eh == NULL) {
590 mpt_prt(mpt, "shutdown event registration failed\n");
591 (void) mpt_detach(mpt);
592 goto bad;
593 }
984263bc
MD
594 return (0);
595
596bad:
597 mpt_dma_mem_free(mpt);
598 mpt_free_bus_resources(mpt);
d751f32e
MD
599 mpt_unlink_peer(mpt);
600
601 MPT_LOCK_DESTROY(mpt);
984263bc
MD
602
603 /*
604 * but return zero to preserve unit numbering
605 */
606 return (0);
607}
608
609/*
610 * Free bus resources
611 */
612static void
d751f32e 613mpt_free_bus_resources(struct mpt_softc *mpt)
984263bc
MD
614{
615 if (mpt->ih) {
616 bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih);
617 mpt->ih = 0;
618 }
619
620 if (mpt->pci_irq) {
d751f32e
MD
621 bus_release_resource(mpt->dev, SYS_RES_IRQ,
622 mpt->pci_msi_count ? 1 : 0, mpt->pci_irq);
984263bc
MD
623 mpt->pci_irq = 0;
624 }
625
d751f32e
MD
626 if (mpt->pci_msi_count) {
627 pci_release_msi(mpt->dev);
628 mpt->pci_msi_count = 0;
629 }
630
631 if (mpt->pci_pio_reg) {
632 bus_release_resource(mpt->dev, SYS_RES_IOPORT, mpt->pci_pio_rid,
633 mpt->pci_pio_reg);
634 mpt->pci_pio_reg = 0;
635 }
984263bc 636 if (mpt->pci_reg) {
d751f32e 637 bus_release_resource(mpt->dev, SYS_RES_MEMORY, mpt->pci_mem_rid,
984263bc
MD
638 mpt->pci_reg);
639 mpt->pci_reg = 0;
640 }
641 MPT_LOCK_DESTROY(mpt);
642}
643
644
645/*
646 * Disconnect ourselves from the system.
647 */
648static int
d751f32e 649mpt_pci_detach(device_t dev)
984263bc 650{
d751f32e 651 struct mpt_softc *mpt;
984263bc 652
d751f32e 653 mpt = (struct mpt_softc*)device_get_softc(dev);
984263bc
MD
654
655 if (mpt) {
656 mpt_disable_ints(mpt);
d751f32e
MD
657 mpt_detach(mpt);
658 mpt_reset(mpt, /*reinit*/FALSE);
984263bc
MD
659 mpt_dma_mem_free(mpt);
660 mpt_free_bus_resources(mpt);
d751f32e
MD
661 mpt_raid_free_mem(mpt);
662 if (mpt->eh != NULL) {
663 EVENTHANDLER_DEREGISTER(shutdown_post_sync, mpt->eh);
664 }
984263bc
MD
665 }
666 return(0);
667}
668
669
670/*
671 * Disable the hardware
672 */
673static int
d751f32e 674mpt_pci_shutdown(device_t dev)
984263bc 675{
d751f32e 676 struct mpt_softc *mpt;
984263bc 677
d751f32e 678 mpt = (struct mpt_softc *)device_get_softc(dev);
984263bc 679 if (mpt) {
d751f32e
MD
680 int r;
681 r = mpt_shutdown(mpt);
682 return (r);
984263bc
MD
683 }
684 return(0);
685}
686
984263bc 687static int
d751f32e 688mpt_dma_mem_alloc(struct mpt_softc *mpt)
984263bc 689{
984263bc 690 size_t len;
d751f32e 691 struct mpt_map_info mi;
984263bc
MD
692
693 /* Check if we alreay have allocated the reply memory */
3641b7ca 694 if (mpt->reply_phys != 0) {
984263bc
MD
695 return 0;
696 }
697
d751f32e 698 len = sizeof (request_t) * MPT_MAX_REQUESTS(mpt);
2545bca0 699 mpt->request_pool = (request_t *)kmalloc(len, M_DEVBUF, M_WAITOK|M_ZERO);
d751f32e
MD
700 if (mpt->request_pool == NULL) {
701 mpt_prt(mpt, "cannot allocate request pool\n");
702 return (1);
703 }
984263bc
MD
704
705 /*
d751f32e 706 * Create a parent dma tag for this device.
984263bc 707 *
d751f32e
MD
708 * Align at byte boundaries,
709 * Limit to 32-bit addressing for request/reply queues.
984263bc 710 */
6d259fc1 711 if (mpt_dma_tag_create(mpt, /*parent*/NULL,
d751f32e
MD
712 /*alignment*/1, /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
713 /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL,
714 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
6d259fc1
SW
715 /*nsegments*/BUS_SPACE_UNRESTRICTED,
716 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, /*flags*/0,
984263bc 717 &mpt->parent_dmat) != 0) {
d751f32e 718 mpt_prt(mpt, "cannot create parent dma tag\n");
984263bc
MD
719 return (1);
720 }
721
722 /* Create a child tag for reply buffers */
d751f32e
MD
723 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0,
724 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
725 NULL, NULL, 2 * PAGE_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0,
984263bc 726 &mpt->reply_dmat) != 0) {
d751f32e 727 mpt_prt(mpt, "cannot create a dma tag for replies\n");
984263bc
MD
728 return (1);
729 }
730
6d259fc1 731 /* Allocate some DMA accessible memory for replies */
984263bc
MD
732 if (bus_dmamem_alloc(mpt->reply_dmat, (void **)&mpt->reply,
733 BUS_DMA_NOWAIT, &mpt->reply_dmap) != 0) {
d751f32e
MD
734 mpt_prt(mpt, "cannot allocate %lu bytes of reply memory\n",
735 (u_long) (2 * PAGE_SIZE));
984263bc
MD
736 return (1);
737 }
738
d751f32e
MD
739 mi.mpt = mpt;
740 mi.error = 0;
984263bc
MD
741
742 /* Load and lock it into "bus space" */
743 bus_dmamap_load(mpt->reply_dmat, mpt->reply_dmap, mpt->reply,
d751f32e 744 2 * PAGE_SIZE, mpt_map_rquest, &mi, 0);
984263bc 745
d751f32e
MD
746 if (mi.error) {
747 mpt_prt(mpt, "error %d loading dma map for DMA reply queue\n",
748 mi.error);
984263bc
MD
749 return (1);
750 }
d751f32e 751 mpt->reply_phys = mi.phys;
984263bc 752
984263bc
MD
753 return (0);
754}
755
756
757
6d259fc1 758/* Deallocate memory that was allocated by mpt_dma_mem_alloc
984263bc
MD
759 */
760static void
d751f32e 761mpt_dma_mem_free(struct mpt_softc *mpt)
984263bc 762{
984263bc
MD
763
764 /* Make sure we aren't double destroying */
765 if (mpt->reply_dmat == 0) {
d751f32e 766 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n");
984263bc
MD
767 return;
768 }
6d259fc1 769
984263bc
MD
770 bus_dmamap_unload(mpt->reply_dmat, mpt->reply_dmap);
771 bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap);
772 bus_dma_tag_destroy(mpt->reply_dmat);
773 bus_dma_tag_destroy(mpt->parent_dmat);
774 mpt->reply_dmat = 0;
2545bca0 775 kfree(mpt->request_pool, M_DEVBUF);
984263bc
MD
776 mpt->request_pool = 0;
777
778}
779
780
781
782/* Reads modifiable (via PCI transactions) config registers */
783static void
d751f32e 784mpt_read_config_regs(struct mpt_softc *mpt)
984263bc
MD
785{
786 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
787 mpt->pci_cfg.LatencyTimer_LineSize =
788 pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2);
d751f32e
MD
789 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4);
790 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4);
791 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4);
792 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4);
793 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4);
984263bc
MD
794 mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4);
795 mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1);
796 mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4);
797}
798
799/* Sets modifiable config registers */
800void
d751f32e 801mpt_set_config_regs(struct mpt_softc *mpt)
984263bc 802{
d751f32e 803 uint32_t val;
984263bc
MD
804
805#define MPT_CHECK(reg, offset, size) \
806 val = pci_read_config(mpt->dev, offset, size); \
807 if (mpt->pci_cfg.reg != val) { \
d751f32e 808 mpt_prt(mpt, \
984263bc
MD
809 "Restoring " #reg " to 0x%X from 0x%X\n", \
810 mpt->pci_cfg.reg, val); \
811 }
812
d751f32e 813 if (mpt->verbose >= MPT_PRT_DEBUG) {
984263bc
MD
814 MPT_CHECK(Command, PCIR_COMMAND, 2);
815 MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2);
d751f32e
MD
816 MPT_CHECK(IO_BAR, PCIR_BAR(0), 4);
817 MPT_CHECK(Mem0_BAR[0], PCIR_BAR(1), 4);
818 MPT_CHECK(Mem0_BAR[1], PCIR_BAR(2), 4);
819 MPT_CHECK(Mem1_BAR[0], PCIR_BAR(3), 4);
820 MPT_CHECK(Mem1_BAR[1], PCIR_BAR(4), 4);
984263bc
MD
821 MPT_CHECK(ROM_BAR, PCIR_BIOS, 4);
822 MPT_CHECK(IntLine, PCIR_INTLINE, 1);
823 MPT_CHECK(PMCSR, 0x44, 4);
824 }
825#undef MPT_CHECK
826
827 pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
828 pci_write_config(mpt->dev, PCIR_CACHELNSZ,
829 mpt->pci_cfg.LatencyTimer_LineSize, 2);
d751f32e
MD
830 pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4);
831 pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4);
832 pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4);
833 pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4);
834 pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4);
984263bc
MD
835 pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4);
836 pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1);
837 pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4);
838}
839
840static void
841mpt_pci_intr(void *arg)
842{
d751f32e
MD
843 struct mpt_softc *mpt;
844
845 mpt = (struct mpt_softc *)arg;
984263bc 846 MPT_LOCK(mpt);
d751f32e 847 mpt_intr(mpt);
984263bc
MD
848 MPT_UNLOCK(mpt);
849}