kernel: Use NULL for DRIVER_MODULE()'s evh & arg (which are pointers).
[dragonfly.git] / sys / dev / sound / isa / mss.c
CommitLineData
558a398b 1/*-
984263bc 2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
558a398b 3 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
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4 * Copyright Luigi Rizzo, 1997,1998
5 * Copyright by Hannu Savolainen 1994, 1995
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
1de703da 28 *
558a398b 29 * $FreeBSD: src/sys/dev/sound/isa/mss.c,v 1.95.2.3 2006/04/04 17:30:59 ariff Exp $
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30 */
31
32#include <dev/sound/pcm/sound.h>
33
cad195a6 34SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/isa/mss.c,v 1.11 2007/06/16 20:07:18 dillon Exp $");
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35
36/* board-specific include files */
37#include <dev/sound/isa/mss.h>
38#include <dev/sound/isa/sb.h>
39#include <dev/sound/chip.h>
40
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41#include <bus/isa/isavar.h>
42
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43#include "mixer_if.h"
44
45#define MSS_DEFAULT_BUFSZ (4096)
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46#define MSS_INDEXED_REGS 0x20
47#define OPL_INDEXED_REGS 0x19
48
49struct mss_info;
50
51struct mss_chinfo {
52 struct mss_info *parent;
53 struct pcm_channel *channel;
54 struct snd_dbuf *buffer;
55 int dir;
56 u_int32_t fmt, blksz;
57};
58
59struct mss_info {
60 struct resource *io_base; /* primary I/O address for the board */
61 int io_rid;
62 struct resource *conf_base; /* and the opti931 also has a config space */
63 int conf_rid;
64 struct resource *irq;
65 int irq_rid;
66 struct resource *drq1; /* play */
67 int drq1_rid;
68 struct resource *drq2; /* rec */
69 int drq2_rid;
70 void *ih;
71 bus_dma_tag_t parent_dmat;
cad195a6 72 sndlock_t lock;
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73
74 char mss_indexed_regs[MSS_INDEXED_REGS];
75 char opl_indexed_regs[OPL_INDEXED_REGS];
76 int bd_id; /* used to hold board-id info, eg. sb version,
77 * mss codec type, etc. etc.
78 */
79 int opti_offset; /* offset from config_base for opti931 */
80 u_long bd_flags; /* board-specific flags */
81 int optibase; /* base address for OPTi9xx config */
82 struct resource *indir; /* Indirect register index address */
83 int indir_rid;
84 int password; /* password for opti9xx cards */
85 int passwdreg; /* password register */
86 unsigned int bufsize;
87 struct mss_chinfo pch, rch;
88};
89
90static int mss_probe(device_t dev);
91static int mss_attach(device_t dev);
92
93static driver_intr_t mss_intr;
94
95/* prototypes for local functions */
96static int mss_detect(device_t dev, struct mss_info *mss);
97static int opti_detect(device_t dev, struct mss_info *mss);
98static char *ymf_test(device_t dev, struct mss_info *mss);
99static void ad_unmute(struct mss_info *mss);
100
101/* mixer set funcs */
102static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
103static int mss_set_recsrc(struct mss_info *mss, int mask);
104
105/* io funcs */
106static int ad_wait_init(struct mss_info *mss, int x);
107static int ad_read(struct mss_info *mss, int reg);
108static void ad_write(struct mss_info *mss, int reg, u_char data);
109static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
110static void ad_enter_MCE(struct mss_info *mss);
111static void ad_leave_MCE(struct mss_info *mss);
112
113/* OPTi-specific functions */
114static void opti_write(struct mss_info *mss, u_char reg,
115 u_char data);
116static u_char opti_read(struct mss_info *mss, u_char reg);
117static int opti_init(device_t dev, struct mss_info *mss);
118
119/* io primitives */
120static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
121static u_char conf_rd(struct mss_info *mss, u_char reg);
122
123static int pnpmss_probe(device_t dev);
124static int pnpmss_attach(device_t dev);
125
126static driver_intr_t opti931_intr;
127
128static u_int32_t mss_fmt[] = {
129 AFMT_U8,
130 AFMT_STEREO | AFMT_U8,
131 AFMT_S16_LE,
132 AFMT_STEREO | AFMT_S16_LE,
133 AFMT_MU_LAW,
134 AFMT_STEREO | AFMT_MU_LAW,
135 AFMT_A_LAW,
136 AFMT_STEREO | AFMT_A_LAW,
137 0
138};
139static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
140
141static u_int32_t guspnp_fmt[] = {
142 AFMT_U8,
143 AFMT_STEREO | AFMT_U8,
144 AFMT_S16_LE,
145 AFMT_STEREO | AFMT_S16_LE,
146 AFMT_A_LAW,
147 AFMT_STEREO | AFMT_A_LAW,
148 0
149};
150static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
151
152static u_int32_t opti931_fmt[] = {
153 AFMT_U8,
154 AFMT_STEREO | AFMT_U8,
155 AFMT_S16_LE,
156 AFMT_STEREO | AFMT_S16_LE,
157 0
158};
159static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
160
161#define MD_AD1848 0x91
162#define MD_AD1845 0x92
163#define MD_CS42XX 0xA1
558a398b 164#define MD_CS423X 0xA2
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165#define MD_OPTI930 0xB0
166#define MD_OPTI931 0xB1
167#define MD_OPTI925 0xB2
168#define MD_OPTI924 0xB3
169#define MD_GUSPNP 0xB8
170#define MD_GUSMAX 0xB9
171#define MD_YM0020 0xC1
172#define MD_VIVO 0xD1
173
174#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
175
176#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
177
178static void
179mss_lock(struct mss_info *mss)
180{
181 snd_mtxlock(mss->lock);
182}
183
184static void
185mss_unlock(struct mss_info *mss)
186{
187 snd_mtxunlock(mss->lock);
188}
189
190static int
191port_rd(struct resource *port, int off)
192{
193 if (port)
194 return bus_space_read_1(rman_get_bustag(port),
195 rman_get_bushandle(port),
196 off);
197 else
198 return -1;
199}
200
201static void
202port_wr(struct resource *port, int off, u_int8_t data)
203{
204 if (port)
205 bus_space_write_1(rman_get_bustag(port),
206 rman_get_bushandle(port),
207 off, data);
208}
209
210static int
211io_rd(struct mss_info *mss, int reg)
212{
213 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
214 return port_rd(mss->io_base, reg);
215}
216
217static void
218io_wr(struct mss_info *mss, int reg, u_int8_t data)
219{
220 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
221 port_wr(mss->io_base, reg, data);
222}
223
224static void
225conf_wr(struct mss_info *mss, u_char reg, u_char value)
226{
227 port_wr(mss->conf_base, 0, reg);
228 port_wr(mss->conf_base, 1, value);
229}
230
231static u_char
232conf_rd(struct mss_info *mss, u_char reg)
233{
234 port_wr(mss->conf_base, 0, reg);
235 return port_rd(mss->conf_base, 1);
236}
237
238static void
239opti_wr(struct mss_info *mss, u_char reg, u_char value)
240{
241 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
242 port_wr(mss->conf_base, mss->opti_offset + 1, value);
243}
244
245static u_char
246opti_rd(struct mss_info *mss, u_char reg)
247{
248 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
249 return port_rd(mss->conf_base, mss->opti_offset + 1);
250}
251
252static void
253gus_wr(struct mss_info *mss, u_char reg, u_char value)
254{
255 port_wr(mss->conf_base, 3, reg);
256 port_wr(mss->conf_base, 5, value);
257}
258
259static u_char
260gus_rd(struct mss_info *mss, u_char reg)
261{
262 port_wr(mss->conf_base, 3, reg);
263 return port_rd(mss->conf_base, 5);
264}
265
266static void
267mss_release_resources(struct mss_info *mss, device_t dev)
268{
269 if (mss->irq) {
270 if (mss->ih)
271 bus_teardown_intr(dev, mss->irq, mss->ih);
272 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
273 mss->irq);
274 mss->irq = 0;
275 }
276 if (mss->drq2) {
277 if (mss->drq2 != mss->drq1) {
278 isa_dma_release(rman_get_start(mss->drq2));
279 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
280 mss->drq2);
281 }
282 mss->drq2 = 0;
283 }
284 if (mss->drq1) {
285 isa_dma_release(rman_get_start(mss->drq1));
286 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
287 mss->drq1);
288 mss->drq1 = 0;
289 }
290 if (mss->io_base) {
291 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
292 mss->io_base);
293 mss->io_base = 0;
294 }
295 if (mss->conf_base) {
296 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
297 mss->conf_base);
298 mss->conf_base = 0;
299 }
300 if (mss->indir) {
301 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
302 mss->indir);
303 mss->indir = 0;
304 }
305 if (mss->parent_dmat) {
306 bus_dma_tag_destroy(mss->parent_dmat);
307 mss->parent_dmat = 0;
308 }
309 if (mss->lock) snd_mtxfree(mss->lock);
310
efda3bd0 311 kfree(mss, M_DEVBUF);
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312}
313
314static int
315mss_alloc_resources(struct mss_info *mss, device_t dev)
316{
317 int pdma, rdma, ok = 1;
318 if (!mss->io_base)
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319 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
320 &mss->io_rid, RF_ACTIVE);
984263bc 321 if (!mss->irq)
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322 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
323 &mss->irq_rid, RF_ACTIVE);
984263bc 324 if (!mss->drq1)
558a398b
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325 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
326 &mss->drq1_rid,
327 RF_ACTIVE);
984263bc 328 if (mss->conf_rid >= 0 && !mss->conf_base)
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329 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
330 &mss->conf_rid,
331 RF_ACTIVE);
984263bc 332 if (mss->drq2_rid >= 0 && !mss->drq2)
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333 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
334 &mss->drq2_rid,
335 RF_ACTIVE);
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336
337 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
338 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
339 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
340
341 if (ok) {
342 pdma = rman_get_start(mss->drq1);
343 isa_dma_acquire(pdma);
344 isa_dmainit(pdma, mss->bufsize);
345 mss->bd_flags &= ~BD_F_DUPLEX;
346 if (mss->drq2) {
347 rdma = rman_get_start(mss->drq2);
348 isa_dma_acquire(rdma);
349 isa_dmainit(rdma, mss->bufsize);
350 mss->bd_flags |= BD_F_DUPLEX;
351 } else mss->drq2 = mss->drq1;
352 }
353 return ok;
354}
355
356/*
357 * The various mixers use a variety of bitmasks etc. The Voxware
358 * driver had a very nice technique to describe a mixer and interface
359 * to it. A table defines, for each channel, which register, bits,
360 * offset, polarity to use. This procedure creates the new value
361 * using the table and the old value.
362 */
363
364static void
365change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
366{
367 u_char mask;
368 int shift;
369
e3869ec7 370 DEB(kprintf("ch_bits dev %d ch %d val %d old 0x%02x "
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371 "r %d p %d bit %d off %d\n",
372 dev, chn, newval, *regval,
373 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
374 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
375
376 if ( (*t)[dev][chn].polarity == 1) /* reverse */
377 newval = 100 - newval ;
378
379 mask = (1 << (*t)[dev][chn].nbits) - 1;
380 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
381 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
382
383 *regval &= ~(mask << shift); /* Filter out the previous value */
384 *regval |= (newval & mask) << shift; /* Set the new value */
385}
386
387/* -------------------------------------------------------------------- */
388/* only one source can be set... */
389static int
390mss_set_recsrc(struct mss_info *mss, int mask)
391{
392 u_char recdev;
393
394 switch (mask) {
395 case SOUND_MASK_LINE:
396 case SOUND_MASK_LINE3:
397 recdev = 0;
398 break;
399
400 case SOUND_MASK_CD:
401 case SOUND_MASK_LINE1:
402 recdev = 0x40;
403 break;
404
405 case SOUND_MASK_IMIX:
406 recdev = 0xc0;
407 break;
408
409 case SOUND_MASK_MIC:
410 default:
411 mask = SOUND_MASK_MIC;
412 recdev = 0x80;
413 }
414 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
415 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
416 return mask;
417}
418
419/* there are differences in the mixer depending on the actual sound card. */
420static int
421mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
422{
423 int regoffs;
424 mixer_tab *mix_d;
425 u_char old, val;
426
427 switch (mss->bd_id) {
428 case MD_OPTI931:
429 mix_d = &opti931_devices;
430 break;
431 case MD_OPTI930:
432 mix_d = &opti930_devices;
433 break;
434 default:
435 mix_d = &mix_devices;
436 }
437
438 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
e3869ec7 439 DEB(kprintf("nbits = 0 for dev %d\n", dev));
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440 return -1;
441 }
442
443 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
444
445 /* Set the left channel */
446
447 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
448 old = val = ad_read(mss, regoffs);
449 /* if volume is 0, mute chan. Otherwise, unmute. */
450 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
451 change_bits(mix_d, &val, dev, LEFT_CHN, left);
452 ad_write(mss, regoffs, val);
453
e3869ec7 454 DEB(kprintf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
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455 dev, regoffs, old, val));
456
457 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
458 /* Set the right channel */
459 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
460 old = val = ad_read(mss, regoffs);
461 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
462 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
463 ad_write(mss, regoffs, val);
464
e3869ec7 465 DEB(kprintf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
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466 dev, regoffs, old, val));
467 }
468 return 0; /* success */
469}
470
471/* -------------------------------------------------------------------- */
472
473static int
474mssmix_init(struct snd_mixer *m)
475{
476 struct mss_info *mss = mix_getdevinfo(m);
477
478 mix_setdevs(m, MODE2_MIXER_DEVICES);
479 mix_setrecdevs(m, MSS_REC_DEVICES);
480 switch(mss->bd_id) {
481 case MD_OPTI930:
482 mix_setdevs(m, OPTI930_MIXER_DEVICES);
483 break;
484
485 case MD_OPTI931:
486 mix_setdevs(m, OPTI931_MIXER_DEVICES);
487 mss_lock(mss);
488 ad_write(mss, 20, 0x88);
489 ad_write(mss, 21, 0x88);
490 mss_unlock(mss);
491 break;
492
493 case MD_AD1848:
494 mix_setdevs(m, MODE1_MIXER_DEVICES);
495 break;
496
497 case MD_GUSPNP:
498 case MD_GUSMAX:
499 /* this is only necessary in mode 3 ... */
500 mss_lock(mss);
501 ad_write(mss, 22, 0x88);
502 ad_write(mss, 23, 0x88);
503 mss_unlock(mss);
504 break;
505 }
506 return 0;
507}
508
509static int
510mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
511{
512 struct mss_info *mss = mix_getdevinfo(m);
513
514 mss_lock(mss);
515 mss_mixer_set(mss, dev, left, right);
516 mss_unlock(mss);
517
518 return left | (right << 8);
519}
520
521static int
522mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
523{
524 struct mss_info *mss = mix_getdevinfo(m);
525
526 mss_lock(mss);
527 src = mss_set_recsrc(mss, src);
528 mss_unlock(mss);
529 return src;
530}
531
532static kobj_method_t mssmix_mixer_methods[] = {
533 KOBJMETHOD(mixer_init, mssmix_init),
534 KOBJMETHOD(mixer_set, mssmix_set),
535 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
536 { 0, 0 }
537};
538MIXER_DECLARE(mssmix_mixer);
539
540/* -------------------------------------------------------------------- */
541
542static int
543ymmix_init(struct snd_mixer *m)
544{
545 struct mss_info *mss = mix_getdevinfo(m);
546
547 mssmix_init(m);
548 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
549 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
550 /* Set master volume */
551 mss_lock(mss);
552 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
553 conf_wr(mss, OPL3SAx_VOLUMER, 7);
554 mss_unlock(mss);
555
556 return 0;
557}
558
559static int
560ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
561{
562 struct mss_info *mss = mix_getdevinfo(m);
563 int t, l, r;
564
565 mss_lock(mss);
566 switch (dev) {
567 case SOUND_MIXER_VOLUME:
568 if (left) t = 15 - (left * 15) / 100;
569 else t = 0x80; /* mute */
570 conf_wr(mss, OPL3SAx_VOLUMEL, t);
571 if (right) t = 15 - (right * 15) / 100;
572 else t = 0x80; /* mute */
573 conf_wr(mss, OPL3SAx_VOLUMER, t);
574 break;
575
576 case SOUND_MIXER_MIC:
577 t = left;
578 if (left) t = 31 - (left * 31) / 100;
579 else t = 0x80; /* mute */
580 conf_wr(mss, OPL3SAx_MIC, t);
581 break;
582
583 case SOUND_MIXER_BASS:
584 l = (left * 7) / 100;
585 r = (right * 7) / 100;
586 t = (r << 4) | l;
587 conf_wr(mss, OPL3SAx_BASS, t);
588 break;
589
590 case SOUND_MIXER_TREBLE:
591 l = (left * 7) / 100;
592 r = (right * 7) / 100;
593 t = (r << 4) | l;
594 conf_wr(mss, OPL3SAx_TREBLE, t);
595 break;
596
597 default:
598 mss_mixer_set(mss, dev, left, right);
599 }
600 mss_unlock(mss);
601
602 return left | (right << 8);
603}
604
605static int
606ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
607{
608 struct mss_info *mss = mix_getdevinfo(m);
609 mss_lock(mss);
610 src = mss_set_recsrc(mss, src);
611 mss_unlock(mss);
612 return src;
613}
614
615static kobj_method_t ymmix_mixer_methods[] = {
616 KOBJMETHOD(mixer_init, ymmix_init),
617 KOBJMETHOD(mixer_set, ymmix_set),
618 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
619 { 0, 0 }
620};
621MIXER_DECLARE(ymmix_mixer);
622
623/* -------------------------------------------------------------------- */
624/*
625 * XXX This might be better off in the gusc driver.
626 */
627static void
628gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
629{
630 static const unsigned char irq_bits[16] = {
631 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
632 };
633 static const unsigned char dma_bits[8] = {
634 0, 1, 0, 2, 0, 3, 4, 5
635 };
636 device_t parent = device_get_parent(dev);
637 unsigned char irqctl, dmactl;
984263bc 638
b6d92ffb 639 crit_enter();
984263bc
MD
640
641 port_wr(alt, 0x0f, 0x05);
642 port_wr(alt, 0x00, 0x0c);
643 port_wr(alt, 0x0b, 0x00);
644
645 port_wr(alt, 0x0f, 0x00);
646
647 irqctl = irq_bits[isa_get_irq(parent)];
648 /* Share the IRQ with the MIDI driver. */
649 irqctl |= 0x40;
650 dmactl = dma_bits[isa_get_drq(parent)];
651 if (device_get_flags(parent) & DV_F_DUAL_DMA)
652 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
653 << 3;
654
655 /*
656 * Set the DMA and IRQ control latches.
657 */
658 port_wr(alt, 0x00, 0x0c);
659 port_wr(alt, 0x0b, dmactl | 0x80);
660 port_wr(alt, 0x00, 0x4c);
661 port_wr(alt, 0x0b, irqctl);
662
663 port_wr(alt, 0x00, 0x0c);
664 port_wr(alt, 0x0b, dmactl);
665 port_wr(alt, 0x00, 0x4c);
666 port_wr(alt, 0x0b, irqctl);
667
668 port_wr(mss->conf_base, 2, 0);
669 port_wr(alt, 0x00, 0x0c);
670 port_wr(mss->conf_base, 2, 0);
671
b6d92ffb 672 crit_exit();
984263bc
MD
673}
674
675static int
676mss_init(struct mss_info *mss, device_t dev)
677{
678 u_char r6, r9;
679 struct resource *alt;
680 int rid, tmp;
681
682 mss->bd_flags |= BD_F_MCE_BIT;
683 switch(mss->bd_id) {
684 case MD_OPTI931:
685 /*
686 * The MED3931 v.1.0 allocates 3 bytes for the config
687 * space, whereas v.2.0 allocates 4 bytes. What I know
688 * for sure is that the upper two ports must be used,
689 * and they should end on a boundary of 4 bytes. So I
690 * need the following trick.
691 */
692 mss->opti_offset =
693 (rman_get_start(mss->conf_base) & ~3) + 2
694 - rman_get_start(mss->conf_base);
e3869ec7 695 BVDDB(kprintf("mss_init: opti_offset=%d\n", mss->opti_offset));
984263bc
MD
696 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
697 ad_write(mss, 10, 2); /* enable interrupts */
698 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
699 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
700 break;
701
702 case MD_GUSPNP:
703 case MD_GUSMAX:
704 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
705 DELAY(1000 * 30);
706 /* release reset and enable DAC */
707 gus_wr(mss, 0x4c /* _URSTI */, 3);
708 DELAY(1000 * 30);
709 /* end of reset */
710
711 rid = 0;
558a398b
SS
712 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
713 RF_ACTIVE);
984263bc 714 if (alt == NULL) {
e3869ec7 715 kprintf("XXX couldn't init GUS PnP/MAX\n");
984263bc
MD
716 break;
717 }
718 port_wr(alt, 0, 0xC); /* enable int and dma */
719 if (mss->bd_id == MD_GUSMAX)
720 gusmax_setup(mss, dev, alt);
721 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
722
723 /*
724 * unmute left & right line. Need to go in mode3, unmute,
725 * and back to mode 2
726 */
727 tmp = ad_read(mss, 0x0c);
728 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
729 ad_write(mss, 0x19, 0); /* unmute left */
730 ad_write(mss, 0x1b, 0); /* unmute right */
731 ad_write(mss, 0x0c, tmp); /* restore old mode */
732
733 /* send codec interrupts on irq1 and only use that one */
734 gus_wr(mss, 0x5a, 0x4f);
735
736 /* enable access to hidden regs */
737 tmp = gus_rd(mss, 0x5b /* IVERI */);
738 gus_wr(mss, 0x5b, tmp | 1);
e3869ec7 739 BVDDB(kprintf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
984263bc
MD
740 break;
741
742 case MD_YM0020:
743 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
744 r6 = conf_rd(mss, OPL3SAx_DMACONF);
745 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
e3869ec7 746 BVDDB(kprintf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
984263bc
MD
747 /* yamaha - set volume to max */
748 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
749 conf_wr(mss, OPL3SAx_VOLUMER, 0);
750 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
751 break;
752 }
753 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
754 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
755 ad_enter_MCE(mss);
756 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
757 ad_leave_MCE(mss);
758 ad_write(mss, 10, 2); /* int enable */
759 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
760 /* the following seem required on the CS4232 */
761 ad_unmute(mss);
762 return 0;
763}
764
765
766/*
767 * main irq handler for the CS423x. The OPTi931 code is
768 * a separate one.
769 * The correct way to operate for a device with multiple internal
770 * interrupt sources is to loop on the status register and ack
771 * interrupts until all interrupts are served and none are reported. At
772 * this point the IRQ line to the ISA IRQ controller should go low
773 * and be raised at the next interrupt.
774 *
775 * Since the ISA IRQ controller is sent EOI _before_ passing control
776 * to the isr, it might happen that we serve an interrupt early, in
777 * which case the status register at the next interrupt should just
778 * say that there are no more interrupts...
779 */
780
781static void
782mss_intr(void *arg)
783{
784 struct mss_info *mss = arg;
785 u_char c = 0, served = 0;
786 int i;
787
e3869ec7 788 DEB(kprintf("mss_intr\n"));
984263bc
MD
789 mss_lock(mss);
790 ad_read(mss, 11); /* fake read of status bits */
791
792 /* loop until there are interrupts, but no more than 10 times. */
793 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
794 /* get exact reason for full-duplex boards */
795 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
796 c &= ~served;
797 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
798 served |= 0x10;
558a398b 799 mss_unlock(mss);
984263bc 800 chn_intr(mss->pch.channel);
558a398b 801 mss_lock(mss);
984263bc
MD
802 }
803 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
804 served |= 0x20;
558a398b 805 mss_unlock(mss);
984263bc 806 chn_intr(mss->rch.channel);
558a398b 807 mss_lock(mss);
984263bc
MD
808 }
809 /* now ack the interrupt */
810 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
811 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
812 }
813 if (i == 10) {
e3869ec7 814 BVDDB(kprintf("mss_intr: irq, but not from mss\n"));
984263bc 815 } else if (served == 0) {
e3869ec7 816 BVDDB(kprintf("mss_intr: unexpected irq with reason %x\n", c));
984263bc
MD
817 /*
818 * this should not happen... I have no idea what to do now.
819 * maybe should do a sanity check and restart dmas ?
820 */
821 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
822 }
823 mss_unlock(mss);
824}
825
826/*
827 * AD_WAIT_INIT waits if we are initializing the board and
828 * we cannot modify its settings
829 */
830static int
831ad_wait_init(struct mss_info *mss, int x)
832{
833 int arg = x, n = 0; /* to shut up the compiler... */
834 for (; x > 0; x--)
835 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
836 else return n;
e3869ec7 837 kprintf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
984263bc
MD
838 return n;
839}
840
841static int
842ad_read(struct mss_info *mss, int reg)
843{
844 int x;
845
846 ad_wait_init(mss, 201000);
847 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
848 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
849 x = io_rd(mss, MSS_IDATA);
e3869ec7 850 /* kprintf("ad_read %d, %x\n", reg, x); */
984263bc
MD
851 return x;
852}
853
854static void
855ad_write(struct mss_info *mss, int reg, u_char data)
856{
857 int x;
858
e3869ec7 859 /* kprintf("ad_write %d, %x\n", reg, data); */
984263bc
MD
860 ad_wait_init(mss, 1002000);
861 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
862 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
863 io_wr(mss, MSS_IDATA, data);
864}
865
866static void
867ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
868{
869 ad_write(mss, reg+1, cnt & 0xff);
870 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
871}
872
873static void
874wait_for_calibration(struct mss_info *mss)
875{
876 int t;
877
878 /*
879 * Wait until the auto calibration process has finished.
880 *
881 * 1) Wait until the chip becomes ready (reads don't return 0x80).
882 * 2) Wait until the ACI bit of I11 gets on
883 * 3) Wait until the ACI bit of I11 gets off
884 */
885
886 t = ad_wait_init(mss, 1000000);
e3869ec7 887 if (t & MSS_IDXBUSY) kprintf("mss: Auto calibration timed out(1).\n");
984263bc
MD
888
889 /*
890 * The calibration mode for chips that support it is set so that
891 * we never see ACI go on.
892 */
893 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
894 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
895 } else {
896 /*
897 * XXX This should only be enabled for cards that *really*
898 * need it. Are there any?
899 */
900 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
901 }
902 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
903}
904
905static void
906ad_unmute(struct mss_info *mss)
907{
908 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
909 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
910}
911
912static void
913ad_enter_MCE(struct mss_info *mss)
914{
915 int prev;
916
917 mss->bd_flags |= BD_F_MCE_BIT;
918 ad_wait_init(mss, 203000);
919 prev = io_rd(mss, MSS_INDEX);
920 prev &= ~MSS_TRD;
921 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
922}
923
924static void
925ad_leave_MCE(struct mss_info *mss)
926{
927 u_char prev;
928
929 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
e3869ec7 930 DEB(kprintf("--- hey, leave_MCE: MCE bit was not set!\n"));
984263bc
MD
931 return;
932 }
933
934 ad_wait_init(mss, 1000000);
935
936 mss->bd_flags &= ~BD_F_MCE_BIT;
937
938 prev = io_rd(mss, MSS_INDEX);
939 prev &= ~MSS_TRD;
940 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
941 wait_for_calibration(mss);
942}
943
944static int
945mss_speed(struct mss_chinfo *ch, int speed)
946{
947 struct mss_info *mss = ch->parent;
948 /*
949 * In the CS4231, the low 4 bits of I8 are used to hold the
950 * sample rate. Only a fixed number of values is allowed. This
951 * table lists them. The speed-setting routines scans the table
952 * looking for the closest match. This is the only supported method.
953 *
954 * In the CS4236, there is an alternate metod (which we do not
955 * support yet) which provides almost arbitrary frequency setting.
956 * In the AD1845, it looks like the sample rate can be
957 * almost arbitrary, and written directly to a register.
958 * In the OPTi931, there is a SB command which provides for
959 * almost arbitrary frequency setting.
960 *
961 */
962 ad_enter_MCE(mss);
963 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
964 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
965 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
966 /* XXX must also do something in I27 for the ad1845 */
967 } else {
968 int i, sel = 0; /* assume entry 0 does not contain -1 */
969 static int speeds[] =
970 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
971 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
972
558a398b 973#define abs(i) (i < 0 ? -i : i)
984263bc
MD
974 for (i = 1; i < 16; i++)
975 if (speeds[i] > 0 &&
976 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
558a398b 977#undef abs
984263bc
MD
978 speed = speeds[sel];
979 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
558a398b 980 ad_wait_init(mss, 10000);
984263bc
MD
981 }
982 ad_leave_MCE(mss);
983
984 return speed;
985}
986
987/*
988 * mss_format checks that the format is supported (or defaults to AFMT_U8)
989 * and returns the bit setting for the 1848 register corresponding to
990 * the desired format.
991 *
992 * fixed lr970724
993 */
994
995static int
996mss_format(struct mss_chinfo *ch, u_int32_t format)
997{
998 struct mss_info *mss = ch->parent;
999 int i, arg = format & ~AFMT_STEREO;
1000
1001 /*
1002 * The data format uses 3 bits (just 2 on the 1848). For each
1003 * bit setting, the following array returns the corresponding format.
1004 * The code scans the array looking for a suitable format. In
1005 * case it is not found, default to AFMT_U8 (not such a good
1006 * choice, but let's do it for compatibility...).
1007 */
1008
1009 static int fmts[] =
1010 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1011 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1012
1013 ch->fmt = format;
1014 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1015 arg = i << 1;
1016 if (format & AFMT_STEREO) arg |= 1;
1017 arg <<= 4;
1018 ad_enter_MCE(mss);
1019 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
558a398b
SS
1020 ad_wait_init(mss, 10000);
1021 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1022 ad_write(mss, 28, arg); /* capture mode */
1023 ad_wait_init(mss, 10000);
1024 }
984263bc
MD
1025 ad_leave_MCE(mss);
1026 return format;
1027}
1028
1029static int
1030mss_trigger(struct mss_chinfo *ch, int go)
1031{
1032 struct mss_info *mss = ch->parent;
1033 u_char m;
1034 int retry, wr, cnt, ss;
1035
1036 ss = 1;
1037 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0;
1038 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1039
1040 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1041 m = ad_read(mss, 9);
1042 switch (go) {
1043 case PCMTRIG_START:
1044 cnt = (ch->blksz / ss) - 1;
1045
e3869ec7 1046 DEB(if (m & 4) kprintf("OUCH! reg 9 0x%02x\n", m););
984263bc
MD
1047 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1048 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1049 break;
1050
1051 case PCMTRIG_STOP:
1052 case PCMTRIG_ABORT: /* XXX check this... */
1053 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1054#if 0
1055 /*
1056 * try to disable DMA by clearing count registers. Not sure it
1057 * is needed, and it might cause false interrupts when the
1058 * DMA is re-enabled later.
1059 */
1060 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1061#endif
1062 }
1063 /* on the OPTi931 the enable bit seems hard to set... */
1064 for (retry = 10; retry > 0; retry--) {
1065 ad_write(mss, 9, m);
1066 if (ad_read(mss, 9) == m) break;
1067 }
e3869ec7 1068 if (retry == 0) BVDDB(kprintf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
984263bc
MD
1069 m, ad_read(mss, 9)));
1070 return 0;
1071}
1072
1073
1074/*
1075 * the opti931 seems to miss interrupts when working in full
1076 * duplex, so we try some heuristics to catch them.
1077 */
1078static void
1079opti931_intr(void *arg)
1080{
1081 struct mss_info *mss = (struct mss_info *)arg;
1082 u_char masked = 0, i11, mc11, c = 0;
1083 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1084 int loops = 10;
1085
1086#if 0
1087 reason = io_rd(mss, MSS_STATUS);
1088 if (!(reason & 1)) {/* no int, maybe a shared line ? */
e3869ec7 1089 DEB(kprintf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
984263bc
MD
1090 return;
1091 }
1092#endif
1093 mss_lock(mss);
1094 i11 = ad_read(mss, 11); /* XXX what's for ? */
1095 again:
1096
1097 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1098 mc11 &= 0x0c;
1099 if (c & 0x10) {
e3869ec7 1100 DEB(kprintf("Warning: CD interrupt\n");)
984263bc
MD
1101 mc11 |= 0x10;
1102 }
1103 if (c & 0x20) {
e3869ec7 1104 DEB(kprintf("Warning: MPU interrupt\n");)
984263bc
MD
1105 mc11 |= 0x20;
1106 }
e3869ec7 1107 if (mc11 & masked) BVDDB(kprintf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
984263bc
MD
1108 mc11, masked));
1109 masked |= mc11;
1110 /*
1111 * the nice OPTi931 sets the IRQ line before setting the bits in
1112 * mc11. So, on some occasions I have to retry (max 10 times).
1113 */
1114 if (mc11 == 0) { /* perhaps can return ... */
1115 reason = io_rd(mss, MSS_STATUS);
1116 if (reason & 1) {
e3869ec7 1117 DEB(kprintf("one more try...\n");)
984263bc 1118 if (--loops) goto again;
558a398b 1119 else BVDDB(kprintf("intr, but mc11 not set\n");)
984263bc 1120 }
e3869ec7 1121 if (loops == 0) BVDDB(kprintf("intr, nothing in mcir11 0x%02x\n", mc11));
984263bc
MD
1122 mss_unlock(mss);
1123 return;
1124 }
1125
558a398b
SS
1126 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1127 mss_unlock(mss);
1128 chn_intr(mss->rch.channel);
1129 mss_lock(mss);
1130 }
1131 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1132 mss_unlock(mss);
1133 chn_intr(mss->pch.channel);
1134 mss_lock(mss);
1135 }
984263bc
MD
1136 opti_wr(mss, 11, ~mc11); /* ack */
1137 if (--loops) goto again;
1138 mss_unlock(mss);
e3869ec7 1139 DEB(kprintf("xxx too many loops\n");)
984263bc
MD
1140}
1141
1142/* -------------------------------------------------------------------- */
1143/* channel interface */
1144static void *
1145msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1146{
1147 struct mss_info *mss = devinfo;
1148 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1149
1150 ch->parent = mss;
1151 ch->channel = c;
1152 ch->buffer = b;
1153 ch->dir = dir;
558a398b
SS
1154 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) != 0)
1155 return NULL;
1156 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
984263bc
MD
1157 return ch;
1158}
1159
1160static int
1161msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1162{
1163 struct mss_chinfo *ch = data;
1164 struct mss_info *mss = ch->parent;
1165
1166 mss_lock(mss);
1167 mss_format(ch, format);
1168 mss_unlock(mss);
1169 return 0;
1170}
1171
1172static int
1173msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1174{
1175 struct mss_chinfo *ch = data;
1176 struct mss_info *mss = ch->parent;
1177 int r;
1178
1179 mss_lock(mss);
1180 r = mss_speed(ch, speed);
1181 mss_unlock(mss);
1182
1183 return r;
1184}
1185
1186static int
1187msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1188{
1189 struct mss_chinfo *ch = data;
1190
1191 ch->blksz = blocksize;
1192 sndbuf_resize(ch->buffer, 2, ch->blksz);
1193
1194 return ch->blksz;
1195}
1196
1197static int
1198msschan_trigger(kobj_t obj, void *data, int go)
1199{
1200 struct mss_chinfo *ch = data;
1201 struct mss_info *mss = ch->parent;
1202
1203 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
1204 return 0;
1205
558a398b 1206 sndbuf_dma(ch->buffer, go);
984263bc
MD
1207 mss_lock(mss);
1208 mss_trigger(ch, go);
1209 mss_unlock(mss);
1210 return 0;
1211}
1212
1213static int
1214msschan_getptr(kobj_t obj, void *data)
1215{
1216 struct mss_chinfo *ch = data;
558a398b 1217 return sndbuf_dmaptr(ch->buffer);
984263bc
MD
1218}
1219
1220static struct pcmchan_caps *
1221msschan_getcaps(kobj_t obj, void *data)
1222{
1223 struct mss_chinfo *ch = data;
1224
1225 switch(ch->parent->bd_id) {
1226 case MD_OPTI931:
1227 return &opti931_caps;
1228 break;
1229
1230 case MD_GUSPNP:
1231 case MD_GUSMAX:
1232 return &guspnp_caps;
1233 break;
1234
1235 default:
1236 return &mss_caps;
1237 break;
1238 }
1239}
1240
1241static kobj_method_t msschan_methods[] = {
1242 KOBJMETHOD(channel_init, msschan_init),
1243 KOBJMETHOD(channel_setformat, msschan_setformat),
1244 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1245 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1246 KOBJMETHOD(channel_trigger, msschan_trigger),
1247 KOBJMETHOD(channel_getptr, msschan_getptr),
1248 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1249 { 0, 0 }
1250};
1251CHANNEL_DECLARE(msschan);
1252
1253/* -------------------------------------------------------------------- */
1254
1255/*
1256 * mss_probe() is the probe routine. Note, it is not necessary to
1257 * go through this for PnP devices, since they are already
1258 * indentified precisely using their PnP id.
1259 *
1260 * The base address supplied in the device refers to the old MSS
1261 * specs where the four 4 registers in io space contain configuration
1262 * information. Some boards (as an example, early MSS boards)
1263 * has such a block of registers, whereas others (generally CS42xx)
1264 * do not. In order to distinguish between the two and do not have
1265 * to supply two separate probe routines, the flags entry in isa_device
1266 * has a bit to mark this.
1267 *
1268 */
1269
1270static int
1271mss_probe(device_t dev)
1272{
1273 u_char tmp, tmpx;
1274 int flags, irq, drq, result = ENXIO, setres = 0;
1275 struct mss_info *mss;
1276
1277 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1278
7522187f 1279 mss = kmalloc(sizeof *mss, M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
1280 mss->io_rid = 0;
1281 mss->conf_rid = -1;
1282 mss->irq_rid = 0;
1283 mss->drq1_rid = 0;
1284 mss->drq2_rid = -1;
1285 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1286 0, ~0, 8, RF_ACTIVE);
1287 if (!mss->io_base) {
e3869ec7 1288 BVDDB(kprintf("mss_probe: no address given, try 0x%x\n", 0x530));
984263bc
MD
1289 mss->io_rid = 0;
1290 /* XXX verify this */
1291 setres = 1;
1292 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1293 0x530, 8);
1294 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1295 0, ~0, 8, RF_ACTIVE);
1296 }
1297 if (!mss->io_base) goto no;
1298
1299 /* got irq/dma regs? */
1300 flags = device_get_flags(dev);
1301 irq = isa_get_irq(dev);
1302 drq = isa_get_drq(dev);
1303
1304 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1305
1306 /*
1307 * Check if the IO port returns valid signature. The original MS
1308 * Sound system returns 0x04 while some cards
1309 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1310 */
1311
1312 device_set_desc(dev, "MSS");
1313 tmpx = tmp = io_rd(mss, 3);
1314 if (tmp == 0xff) { /* Bus float */
e3869ec7 1315 BVDDB(kprintf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
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MD
1316 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1317 goto mss_probe_end;
1318 }
1319 tmp &= 0x3f;
1320 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
e3869ec7 1321 BVDDB(kprintf("No MSS signature detected on port 0x%lx (0x%x)\n",
984263bc
MD
1322 rman_get_start(mss->io_base), tmpx));
1323 goto no;
1324 }
984263bc 1325 if (irq > 11) {
e3869ec7 1326 kprintf("MSS: Bad IRQ %d\n", irq);
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MD
1327 goto no;
1328 }
1329 if (!(drq == 0 || drq == 1 || drq == 3)) {
e3869ec7 1330 kprintf("MSS: Bad DMA %d\n", drq);
984263bc
MD
1331 goto no;
1332 }
1333 if (tmpx & 0x80) {
1334 /* 8-bit board: only drq1/3 and irq7/9 */
1335 if (drq == 0) {
e3869ec7 1336 kprintf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
984263bc
MD
1337 goto no;
1338 }
1339 if (!(irq == 7 || irq == 9)) {
e3869ec7 1340 kprintf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
984263bc
MD
1341 irq);
1342 goto no;
1343 }
1344 }
1345 mss_probe_end:
1346 result = mss_detect(dev, mss);
1347 no:
1348 mss_release_resources(mss, dev);
1349#if 0
1350 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1351 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1352#endif
1353 return result;
1354}
1355
1356static int
1357mss_detect(device_t dev, struct mss_info *mss)
1358{
1359 int i;
1360 u_char tmp = 0, tmp1, tmp2;
1361 char *name, *yamaha;
1362
1363 if (mss->bd_id != 0) {
1364 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1365 device_get_desc(dev));
1366 return 0;
1367 }
1368
1369 name = "AD1848";
1370 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1371
1372 if (opti_detect(dev, mss)) {
1373 switch (mss->bd_id) {
1374 case MD_OPTI924:
1375 name = "OPTi924";
1376 break;
1377 case MD_OPTI930:
1378 name = "OPTi930";
1379 break;
1380 }
e3869ec7 1381 kprintf("Found OPTi device %s\n", name);
984263bc
MD
1382 if (opti_init(dev, mss) == 0) goto gotit;
1383 }
1384
1385 /*
1386 * Check that the I/O address is in use.
1387 *
1388 * bit 7 of the base I/O port is known to be 0 after the chip has
1389 * performed its power on initialization. Just assume this has
1390 * happened before the OS is starting.
1391 *
1392 * If the I/O address is unused, it typically returns 0xff.
1393 */
1394
1395 for (i = 0; i < 10; i++)
1396 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1397 else break;
1398
558a398b 1399 if (i >= 10) { /* Not an AD1848 */
e3869ec7 1400 BVDDB(kprintf("mss_detect, busy still set (0x%02x)\n", tmp));
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MD
1401 goto no;
1402 }
1403 /*
1404 * Test if it's possible to change contents of the indirect
1405 * registers. Registers 0 and 1 are ADC volume registers. The bit
1406 * 0x10 is read only so try to avoid using it.
1407 */
1408
1409 ad_write(mss, 0, 0xaa);
1410 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1411 tmp1 = ad_read(mss, 0);
1412 tmp2 = ad_read(mss, 1);
1413 if (tmp1 != 0xaa || tmp2 != 0x45) {
e3869ec7 1414 BVDDB(kprintf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
984263bc
MD
1415 goto no;
1416 }
1417
1418 ad_write(mss, 0, 0x45);
1419 ad_write(mss, 1, 0xaa);
1420 tmp1 = ad_read(mss, 0);
1421 tmp2 = ad_read(mss, 1);
1422 if (tmp1 != 0x45 || tmp2 != 0xaa) {
e3869ec7 1423 BVDDB(kprintf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
984263bc
MD
1424 goto no;
1425 }
1426
1427 /*
1428 * The indirect register I12 has some read only bits. Lets try to
1429 * change them.
1430 */
1431
1432 tmp = ad_read(mss, 12);
1433 ad_write(mss, 12, (~tmp) & 0x0f);
1434 tmp1 = ad_read(mss, 12);
1435
1436 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
e3869ec7 1437 BVDDB(kprintf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
984263bc
MD
1438 goto no;
1439 }
1440
1441 /*
1442 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1443 * 0x01=RevB
1444 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1445 */
1446
e3869ec7 1447 BVDDB(kprintf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
984263bc
MD
1448
1449 /*
1450 * The original AD1848/CS4248 has just 16 indirect registers. This
1451 * means that I0 and I16 should return the same value (etc.). Ensure
1452 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1453 * with new parts.
1454 */
1455
1456 ad_write(mss, 12, 0); /* Mode2=disabled */
1457#if 0
1458 for (i = 0; i < 16; i++) {
1459 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
e3869ec7 1460 BVDDB(kprintf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
984263bc
MD
1461 i, tmp1, tmp2));
1462 /*
1463 * note - this seems to fail on the 4232 on I11. So we just break
1464 * rather than fail. (which makes this test pointless - cg)
1465 */
1466 break; /* return 0; */
1467 }
1468 }
1469#endif
1470 /*
1471 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1472 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1473 *
1474 * On the OPTi931, however, I12 is readonly and only contains the
1475 * chip revision ID (as in the CS4231A). The upper bits return 0.
1476 */
1477
1478 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1479
1480 tmp1 = ad_read(mss, 12);
1481 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1482 if ((tmp1 & 0xf0) == 0x00) {
e3869ec7 1483 BVDDB(kprintf("this should be an OPTi931\n");)
984263bc
MD
1484 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1485 /*
1486 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1487 * We want to check that this is really a CS4231
1488 * Verify that setting I0 doesn't change I16.
1489 */
1490 ad_write(mss, 16, 0); /* Set I16 to known value */
1491 ad_write(mss, 0, 0x45);
1492 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1493
1494 ad_write(mss, 0, 0xaa);
1495 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
e3869ec7 1496 BVDDB(kprintf("mss_detect error - step H(%x)\n", tmp1));
984263bc
MD
1497 goto no;
1498 }
1499 /* Verify that some bits of I25 are read only. */
1500 tmp1 = ad_read(mss, 25); /* Original bits */
1501 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1502 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1503 int id;
1504
1505 /* It's at least CS4231 */
1506 name = "CS4231";
1507 mss->bd_id = MD_CS42XX;
1508
1509 /*
1510 * It could be an AD1845 or CS4231A as well.
1511 * CS4231 and AD1845 report the same revision info in I25
1512 * while the CS4231A reports different.
1513 */
1514
1515 id = ad_read(mss, 25) & 0xe7;
1516 /*
1517 * b7-b5 = version number;
1518 * 100 : all CS4231
1519 * 101 : CS4231A
1520 *
1521 * b2-b0 = chip id;
1522 */
1523 switch (id) {
1524
1525 case 0xa0:
1526 name = "CS4231A";
1527 mss->bd_id = MD_CS42XX;
1528 break;
1529
1530 case 0xa2:
1531 name = "CS4232";
1532 mss->bd_id = MD_CS42XX;
1533 break;
1534
1535 case 0xb2:
1536 /* strange: the 4231 data sheet says b4-b3 are XX
1537 * so this should be the same as 0xa2
1538 */
1539 name = "CS4232A";
1540 mss->bd_id = MD_CS42XX;
1541 break;
1542
1543 case 0x80:
1544 /*
1545 * It must be a CS4231 or AD1845. The register I23
1546 * of CS4231 is undefined and it appears to be read
1547 * only. AD1845 uses I23 for setting sample rate.
1548 * Assume the chip is AD1845 if I23 is changeable.
1549 */
1550
1551 tmp = ad_read(mss, 23);
1552
1553 ad_write(mss, 23, ~tmp);
1554 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1555 name = "AD1845";
1556 mss->bd_id = MD_AD1845;
1557 }
1558 ad_write(mss, 23, tmp); /* Restore */
1559
1560 yamaha = ymf_test(dev, mss);
1561 if (yamaha) {
1562 mss->bd_id = MD_YM0020;
1563 name = yamaha;
1564 }
1565 break;
1566
1567 case 0x83: /* CS4236 */
1568 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1569 name = "CS4236";
1570 mss->bd_id = MD_CS42XX;
1571 break;
1572
1573 default: /* Assume CS4231 */
e3869ec7 1574 BVDDB(kprintf("unknown id 0x%02x, assuming CS4231\n", id);)
984263bc
MD
1575 mss->bd_id = MD_CS42XX;
1576 }
1577 }
1578 ad_write(mss, 25, tmp1); /* Restore bits */
1579gotit:
e3869ec7 1580 BVDDB(kprintf("mss_detect() - Detected %s\n", name));
984263bc
MD
1581 device_set_desc(dev, name);
1582 device_set_flags(dev,
1583 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1584 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1585 return 0;
1586no:
1587 return ENXIO;
1588}
1589
1590static int
1591opti_detect(device_t dev, struct mss_info *mss)
1592{
1593 int c;
1594 static const struct opticard {
1595 int boardid;
1596 int passwdreg;
1597 int password;
1598 int base;
1599 int indir_reg;
1600 } cards[] = {
1601 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1602 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1603 { 0 },
1604 };
1605 mss->conf_rid = 3;
1606 mss->indir_rid = 4;
1607 for (c = 0; cards[c].base; c++) {
1608 mss->optibase = cards[c].base;
1609 mss->password = cards[c].password;
1610 mss->passwdreg = cards[c].passwdreg;
1611 mss->bd_id = cards[c].boardid;
1612
1613 if (cards[c].indir_reg)
1614 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1615 &mss->indir_rid, cards[c].indir_reg,
1616 cards[c].indir_reg+1, 1, RF_ACTIVE);
1617
1618 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1619 &mss->conf_rid, mss->optibase, mss->optibase+9,
1620 9, RF_ACTIVE);
1621
1622 if (opti_read(mss, 1) != 0xff) {
1623 return 1;
1624 } else {
1625 if (mss->indir)
1626 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1627 mss->indir = NULL;
1628 if (mss->conf_base)
1629 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1630 mss->conf_base = NULL;
1631 }
1632 }
1633 return 0;
1634}
1635
1636static char *
1637ymf_test(device_t dev, struct mss_info *mss)
1638{
1639 static int ports[] = {0x370, 0x310, 0x538};
1640 int p, i, j, version;
1641 static char *chipset[] = {
1642 NULL, /* 0 */
1643 "OPL3-SA2 (YMF711)", /* 1 */
1644 "OPL3-SA3 (YMF715)", /* 2 */
1645 "OPL3-SA3 (YMF715)", /* 3 */
1646 "OPL3-SAx (YMF719)", /* 4 */
1647 "OPL3-SAx (YMF719)", /* 5 */
1648 "OPL3-SAx (YMF719)", /* 6 */
1649 "OPL3-SAx (YMF719)", /* 7 */
1650 };
1651
1652 for (p = 0; p < 3; p++) {
1653 mss->conf_rid = 1;
1654 mss->conf_base = bus_alloc_resource(dev,
1655 SYS_RES_IOPORT,
1656 &mss->conf_rid,
1657 ports[p], ports[p] + 1, 2,
1658 RF_ACTIVE);
1659 if (!mss->conf_base) return 0;
1660
1661 /* Test the index port of the config registers */
1662 i = port_rd(mss->conf_base, 0);
1663 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1664 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1665 port_wr(mss->conf_base, 0, i);
1666 if (!j) {
1667 bus_release_resource(dev, SYS_RES_IOPORT,
1668 mss->conf_rid, mss->conf_base);
984263bc
MD
1669 mss->conf_base = 0;
1670 continue;
1671 }
1672 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1673 return chipset[version];
1674 }
1675 return NULL;
1676}
1677
1678static int
1679mss_doattach(device_t dev, struct mss_info *mss)
1680{
1681 int pdma, rdma, flags = device_get_flags(dev);
1682 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1683
1684 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1685 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1686 if (!mss_alloc_resources(mss, dev)) goto no;
1687 mss_init(mss, dev);
1688 pdma = rman_get_start(mss->drq1);
1689 rdma = rman_get_start(mss->drq2);
1690 if (flags & DV_F_TRUE_MSS) {
1691 /* has IRQ/DMA registers, set IRQ and DMA addr */
984263bc
MD
1692 static char interrupt_bits[12] =
1693 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
984263bc
MD
1694 static char pdma_bits[4] = {1, 2, -1, 3};
1695 static char valid_rdma[4] = {1, 0, -1, 0};
1696 char bits;
1697
1698 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1699 goto no;
984263bc
MD
1700 io_wr(mss, 0, bits | 0x40); /* config port */
1701 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
984263bc
MD
1702 /* Write IRQ+DMA setup */
1703 if (pdma_bits[pdma] == -1) goto no;
1704 bits |= pdma_bits[pdma];
1705 if (pdma != rdma) {
1706 if (rdma == valid_rdma[pdma]) bits |= 4;
1707 else {
e3869ec7 1708 kprintf("invalid dual dma config %d:%d\n", pdma, rdma);
984263bc
MD
1709 goto no;
1710 }
1711 }
1712 io_wr(mss, 0, bits);
e3869ec7 1713 kprintf("drq/irq conf %x\n", io_rd(mss, 0));
984263bc
MD
1714 }
1715 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1716 switch (mss->bd_id) {
1717 case MD_OPTI931:
558a398b 1718 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
984263bc
MD
1719 break;
1720 default:
558a398b 1721 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
984263bc
MD
1722 }
1723 if (pdma == rdma)
1724 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1725 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1726 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1727 /*highaddr*/BUS_SPACE_MAXADDR,
1728 /*filter*/NULL, /*filterarg*/NULL,
1729 /*maxsize*/mss->bufsize, /*nsegments*/1,
558a398b
SS
1730 /*maxsegz*/0x3ffff, /*flags*/0,
1731 &mss->parent_dmat) != 0) {
984263bc
MD
1732 device_printf(dev, "unable to create dma tag\n");
1733 goto no;
1734 }
1735
1736 if (pdma != rdma)
f8c7a42d 1737 ksnprintf(status2, SND_STATUSLEN, ":%d", rdma);
984263bc
MD
1738 else
1739 status2[0] = '\0';
1740
f8c7a42d 1741 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
984263bc
MD
1742 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1743
1744 if (pcm_register(dev, mss, 1, 1)) goto no;
1745 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1746 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1747 pcm_setstatus(dev, status);
1748
1749 return 0;
1750no:
1751 mss_release_resources(mss, dev);
1752 return ENXIO;
1753}
1754
1755static int
1756mss_detach(device_t dev)
1757{
1758 int r;
1759 struct mss_info *mss;
1760
1761 r = pcm_unregister(dev);
1762 if (r)
1763 return r;
1764
1765 mss = pcm_getdevinfo(dev);
1766 mss_release_resources(mss, dev);
1767
1768 return 0;
1769}
1770
1771static int
1772mss_attach(device_t dev)
1773{
1774 struct mss_info *mss;
1775 int flags = device_get_flags(dev);
1776
7522187f 1777 mss = kmalloc(sizeof *mss, M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
1778 mss->io_rid = 0;
1779 mss->conf_rid = -1;
1780 mss->irq_rid = 0;
1781 mss->drq1_rid = 0;
1782 mss->drq2_rid = -1;
1783 if (flags & DV_F_DUAL_DMA) {
1784 bus_set_resource(dev, SYS_RES_DRQ, 1,
1785 flags & DV_F_DRQ_MASK, 1);
1786 mss->drq2_rid = 1;
1787 }
1788 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1789 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1790 return mss_doattach(dev, mss);
1791}
1792
1793/*
1794 * mss_resume() is the code to allow a laptop to resume using the sound
1795 * card.
1796 *
1797 * This routine re-sets the state of the board to the state before going
1798 * to sleep. According to the yamaha docs this is the right thing to do,
1799 * but getting DMA restarted appears to be a bit of a trick, so the device
1800 * has to be closed and re-opened to be re-used, but there is no skipping
1801 * problem, and volume, bass/treble and most other things are restored
1802 * properly.
1803 *
1804 */
1805
1806static int
1807mss_resume(device_t dev)
1808{
1809 /*
1810 * Restore the state taken below.
1811 */
1812 struct mss_info *mss;
1813 int i;
1814
1815 mss = pcm_getdevinfo(dev);
1816
558a398b 1817 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
984263bc
MD
1818 /* This works on a Toshiba Libretto 100CT. */
1819 for (i = 0; i < MSS_INDEXED_REGS; i++)
1820 ad_write(mss, i, mss->mss_indexed_regs[i]);
1821 for (i = 0; i < OPL_INDEXED_REGS; i++)
1822 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1823 mss_intr(mss);
1824 }
558a398b
SS
1825
1826 if (mss->bd_id == MD_CS423X) {
1827 /* Needed on IBM Thinkpad 600E */
1828 mss_lock(mss);
1829 mss_format(&mss->pch, mss->pch.channel->format);
1830 mss_speed(&mss->pch, mss->pch.channel->speed);
1831 mss_unlock(mss);
1832 }
1833
984263bc
MD
1834 return 0;
1835
1836}
1837
1838/*
1839 * mss_suspend() is the code that gets called right before a laptop
1840 * suspends.
1841 *
1842 * This code saves the state of the sound card right before shutdown
1843 * so it can be restored above.
1844 *
1845 */
1846
1847static int
1848mss_suspend(device_t dev)
1849{
1850 int i;
1851 struct mss_info *mss;
1852
1853 mss = pcm_getdevinfo(dev);
1854
558a398b 1855 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
984263bc
MD
1856 {
1857 /* this stops playback. */
1858 conf_wr(mss, 0x12, 0x0c);
1859 for(i = 0; i < MSS_INDEXED_REGS; i++)
1860 mss->mss_indexed_regs[i] = ad_read(mss, i);
1861 for(i = 0; i < OPL_INDEXED_REGS; i++)
1862 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1863 mss->opl_indexed_regs[0x12] = 0x0;
1864 }
1865 return 0;
1866}
1867
1868static device_method_t mss_methods[] = {
1869 /* Device interface */
1870 DEVMETHOD(device_probe, mss_probe),
1871 DEVMETHOD(device_attach, mss_attach),
1872 DEVMETHOD(device_detach, mss_detach),
1873 DEVMETHOD(device_suspend, mss_suspend),
1874 DEVMETHOD(device_resume, mss_resume),
1875
1876 { 0, 0 }
1877};
1878
1879static driver_t mss_driver = {
1880 "pcm",
1881 mss_methods,
1882 PCM_SOFTC_SIZE,
1883};
1884
aa2b9d05 1885DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, NULL, NULL);
558a398b 1886MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc
MD
1887MODULE_VERSION(snd_mss, 1);
1888
1889static int
1890azt2320_mss_mode(struct mss_info *mss, device_t dev)
1891{
1892 struct resource *sbport;
1893 int i, ret, rid;
1894
1895 rid = 0;
1896 ret = -1;
558a398b 1897 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
984263bc
MD
1898 if (sbport) {
1899 for (i = 0; i < 1000; i++) {
1900 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1901 DELAY((i > 100) ? 1000 : 10);
1902 else {
1903 port_wr(sbport, SBDSP_CMD, 0x09);
1904 break;
1905 }
1906 }
1907 for (i = 0; i < 1000; i++) {
1908 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1909 DELAY((i > 100) ? 1000 : 10);
1910 else {
1911 port_wr(sbport, SBDSP_CMD, 0x00);
1912 ret = 0;
1913 break;
1914 }
1915 }
1916 DELAY(1000);
1917 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1918 }
1919 return ret;
1920}
1921
1922static struct isa_pnp_id pnpmss_ids[] = {
1923 {0x0000630e, "CS423x"}, /* CSC0000 */
1924 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1925 {0x01000000, "CMI8330"}, /* @@@0001 */
1926 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1927 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1928 {0x1093143e, "OPTi931"}, /* OPT9310 */
1929 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1930 {0x0000143e, "OPTi924"}, /* OPT0924 */
1931 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1932 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1933#if 0
1934 {0x0000561e, "GusPnP"}, /* GRV0000 */
1935#endif
1936 {0},
1937};
1938
1939static int
1940pnpmss_probe(device_t dev)
1941{
1942 u_int32_t lid, vid;
1943
1944 lid = isa_get_logicalid(dev);
1945 vid = isa_get_vendorid(dev);
1946 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1947 return ENXIO;
1948 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1949}
1950
1951static int
1952pnpmss_attach(device_t dev)
1953{
1954 struct mss_info *mss;
1955
7522187f 1956 mss = kmalloc(sizeof *mss, M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
1957 mss->io_rid = 0;
1958 mss->conf_rid = -1;
1959 mss->irq_rid = 0;
1960 mss->drq1_rid = 0;
1961 mss->drq2_rid = 1;
1962 mss->bd_id = MD_CS42XX;
1963
1964 switch (isa_get_logicalid(dev)) {
1965 case 0x0000630e: /* CSC0000 */
1966 case 0x0001630e: /* CSC0100 */
1967 mss->bd_flags |= BD_F_MSS_OFFSET;
558a398b 1968 mss->bd_id = MD_CS423X;
984263bc
MD
1969 break;
1970
1971 case 0x2100a865: /* YHM0021 */
1972 mss->io_rid = 1;
1973 mss->conf_rid = 4;
1974 mss->bd_id = MD_YM0020;
1975 break;
1976
1977 case 0x1110d315: /* ENS1011 */
1978 mss->io_rid = 1;
1979 mss->bd_id = MD_VIVO;
1980 break;
1981
1982 case 0x1093143e: /* OPT9310 */
1983 mss->bd_flags |= BD_F_MSS_OFFSET;
1984 mss->conf_rid = 3;
1985 mss->bd_id = MD_OPTI931;
1986 break;
1987
1988 case 0x5092143e: /* OPT9250 XXX guess */
1989 mss->io_rid = 1;
1990 mss->conf_rid = 3;
1991 mss->bd_id = MD_OPTI925;
1992 break;
1993
1994 case 0x0000143e: /* OPT0924 */
1995 mss->password = 0xe5;
1996 mss->passwdreg = 3;
1997 mss->optibase = 0xf0c;
1998 mss->io_rid = 2;
1999 mss->conf_rid = 3;
2000 mss->bd_id = MD_OPTI924;
2001 mss->bd_flags |= BD_F_924PNP;
558a398b
SS
2002 if(opti_init(dev, mss) != 0) {
2003 kfree(mss, M_DEVBUF);
984263bc 2004 return ENXIO;
558a398b 2005 }
984263bc
MD
2006 break;
2007
2008 case 0x1022b839: /* NMX2210 */
2009 mss->io_rid = 1;
2010 break;
2011
2012 case 0x01005407: /* AZT0001 */
2013 /* put into MSS mode first (snatched from NetBSD) */
558a398b
SS
2014 if (azt2320_mss_mode(mss, dev) == -1) {
2015 kfree(mss, M_DEVBUF);
984263bc 2016 return ENXIO;
558a398b 2017 }
984263bc
MD
2018
2019 mss->bd_flags |= BD_F_MSS_OFFSET;
2020 mss->io_rid = 2;
2021 break;
2022
2023#if 0
2024 case 0x0000561e: /* GRV0000 */
2025 mss->bd_flags |= BD_F_MSS_OFFSET;
2026 mss->io_rid = 2;
2027 mss->conf_rid = 1;
2028 mss->drq1_rid = 1;
2029 mss->drq2_rid = 0;
2030 mss->bd_id = MD_GUSPNP;
2031 break;
2032#endif
2033 case 0x01000000: /* @@@0001 */
2034 mss->drq2_rid = -1;
2035 break;
2036
2037 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2038 default:
2039 mss->bd_flags |= BD_F_MSS_OFFSET;
2040 break;
2041 }
2042 return mss_doattach(dev, mss);
2043}
2044
2045static int
2046opti_init(device_t dev, struct mss_info *mss)
2047{
2048 int flags = device_get_flags(dev);
2049 int basebits = 0;
2050
2051 if (!mss->conf_base) {
2052 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2053 mss->optibase, 0x9);
2054
2055 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2056 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2057 0x9, RF_ACTIVE);
2058 }
2059
2060 if (!mss->conf_base)
2061 return ENXIO;
2062
2063 if (!mss->io_base)
2064 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2065 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2066
2067 if (!mss->io_base) /* No hint specified, use 0x530 */
2068 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2069 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2070
2071 if (!mss->io_base)
2072 return ENXIO;
2073
2074 switch (rman_get_start(mss->io_base)) {
2075 case 0x530:
2076 basebits = 0x0;
2077 break;
2078 case 0xe80:
2079 basebits = 0x10;
2080 break;
2081 case 0xf40:
2082 basebits = 0x20;
2083 break;
2084 case 0x604:
2085 basebits = 0x30;
2086 break;
2087 default:
e3869ec7 2088 kprintf("opti_init: invalid MSS base address!\n");
984263bc
MD
2089 return ENXIO;
2090 }
2091
2092
2093 switch (mss->bd_id) {
2094 case MD_OPTI924:
2095 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2096 opti_write(mss, 2, 0x00); /* Disable CD */
2097 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2098 opti_write(mss, 4, 0xf0);
2099 opti_write(mss, 5, 0x00);
2100 opti_write(mss, 6, 0x02); /* MPU stuff */
2101 break;
2102
2103 case MD_OPTI930:
2104 opti_write(mss, 1, 0x00 | basebits);
2105 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2106 opti_write(mss, 4, 0x52); /* Empty FIFO */
2107 opti_write(mss, 5, 0x3c); /* Mode 2 */
2108 opti_write(mss, 6, 0x02); /* Enable MSS */
2109 break;
2110 }
2111
2112 if (mss->bd_flags & BD_F_924PNP) {
2113 u_int32_t irq = isa_get_irq(dev);
2114 u_int32_t drq = isa_get_drq(dev);
2115 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2116 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2117 if (flags & DV_F_DUAL_DMA) {
2118 bus_set_resource(dev, SYS_RES_DRQ, 1,
2119 flags & DV_F_DRQ_MASK, 1);
2120 mss->drq2_rid = 1;
2121 }
2122 }
2123
2124 /* OPTixxx has I/DRQ registers */
2125
2126 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2127
2128 return 0;
2129}
2130
2131static void
2132opti_write(struct mss_info *mss, u_char reg, u_char val)
2133{
2134 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2135
2136 switch(mss->bd_id) {
2137 case MD_OPTI924:
2138 if (reg > 7) { /* Indirect register */
2139 port_wr(mss->conf_base, mss->passwdreg, reg);
2140 port_wr(mss->conf_base, mss->passwdreg,
2141 mss->password);
2142 port_wr(mss->conf_base, 9, val);
2143 return;
2144 }
2145 port_wr(mss->conf_base, reg, val);
2146 break;
2147
2148 case MD_OPTI930:
2149 port_wr(mss->indir, 0, reg);
2150 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2151 port_wr(mss->indir, 1, val);
2152 break;
2153 }
2154}
2155
2156u_char
2157opti_read(struct mss_info *mss, u_char reg)
2158{
2159 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2160
2161 switch(mss->bd_id) {
2162 case MD_OPTI924:
2163 if (reg > 7) { /* Indirect register */
2164 port_wr(mss->conf_base, mss->passwdreg, reg);
2165 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2166 return(port_rd(mss->conf_base, 9));
2167 }
2168 return(port_rd(mss->conf_base, reg));
2169 break;
2170
2171 case MD_OPTI930:
2172 port_wr(mss->indir, 0, reg);
2173 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2174 return port_rd(mss->indir, 1);
2175 break;
2176 }
2177 return -1;
2178}
2179
2180static device_method_t pnpmss_methods[] = {
2181 /* Device interface */
2182 DEVMETHOD(device_probe, pnpmss_probe),
2183 DEVMETHOD(device_attach, pnpmss_attach),
2184 DEVMETHOD(device_detach, mss_detach),
2185 DEVMETHOD(device_suspend, mss_suspend),
2186 DEVMETHOD(device_resume, mss_resume),
2187
2188 { 0, 0 }
2189};
2190
2191static driver_t pnpmss_driver = {
2192 "pcm",
2193 pnpmss_methods,
2194 PCM_SOFTC_SIZE,
2195};
2196
aa2b9d05
SW
2197DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, NULL, NULL);
2198DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, NULL, NULL);
558a398b 2199MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc
MD
2200MODULE_VERSION(snd_pnpmss, 1);
2201
2202static int
2203guspcm_probe(device_t dev)
2204{
2205 struct sndcard_func *func;
2206
2207 func = device_get_ivars(dev);
2208 if (func == NULL || func->func != SCF_PCM)
2209 return ENXIO;
2210
2211 device_set_desc(dev, "GUS CS4231");
2212 return 0;
2213}
2214
2215static int
2216guspcm_attach(device_t dev)
2217{
2218 device_t parent = device_get_parent(dev);
2219 struct mss_info *mss;
2220 int base, flags;
2221 unsigned char ctl;
2222
7522187f 2223 mss = kmalloc(sizeof *mss, M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
2224 mss->bd_flags = BD_F_MSS_OFFSET;
2225 mss->io_rid = 2;
2226 mss->conf_rid = 1;
2227 mss->irq_rid = 0;
2228 mss->drq1_rid = 1;
2229 mss->drq2_rid = -1;
2230
2231 if (isa_get_logicalid(parent) == 0)
2232 mss->bd_id = MD_GUSMAX;
2233 else {
2234 mss->bd_id = MD_GUSPNP;
2235 mss->drq2_rid = 0;
2236 goto skip_setup;
2237 }
2238
2239 flags = device_get_flags(parent);
2240 if (flags & DV_F_DUAL_DMA)
2241 mss->drq2_rid = 0;
2242
2243 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2244 0, ~0, 8, RF_ACTIVE);
2245
2246 if (mss->conf_base == NULL) {
2247 mss_release_resources(mss, dev);
2248 return ENXIO;
2249 }
2250
2251 base = isa_get_port(parent);
2252
2253 ctl = 0x40; /* CS4231 enable */
2254 if (isa_get_drq(dev) > 3)
2255 ctl |= 0x10; /* 16-bit dma channel 1 */
2256 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2257 ctl |= 0x20; /* 16-bit dma channel 2 */
2258 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2259 port_wr(mss->conf_base, 6, ctl);
2260
2261skip_setup:
2262 return mss_doattach(dev, mss);
2263}
2264
2265static device_method_t guspcm_methods[] = {
2266 DEVMETHOD(device_probe, guspcm_probe),
2267 DEVMETHOD(device_attach, guspcm_attach),
2268 DEVMETHOD(device_detach, mss_detach),
2269
2270 { 0, 0 }
2271};
2272
2273static driver_t guspcm_driver = {
2274 "pcm",
2275 guspcm_methods,
2276 PCM_SOFTC_SIZE,
2277};
2278
aa2b9d05 2279DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, NULL, NULL);
558a398b 2280MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc
MD
2281MODULE_VERSION(snd_guspcm, 1);
2282
2283