kernel: Remove some old ISA only drivers.
[dragonfly.git] / share / man / man4 / ahc.4
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1.\"
2.\" Copyright (c) 1995, 1996, 1997, 1998, 2000
3.\" Justin T. Gibbs. All rights reserved.
4.\"
5.\" Redistribution and use in source and binary forms, with or without
6.\" modification, are permitted provided that the following conditions
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63c20666 27.\" $FreeBSD: src/share/man/man4/ahc.4,v 1.38.2.1 2006/06/05 19:30:28 brueffer Exp $
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b1e426a6 29.Dd September 26, 2007
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30.Dt AHC 4
31.Os
32.Sh NAME
33.Nm ahc
e842db4d 34.Nd Adaptec PCI SCSI host adapter driver
984263bc 35.Sh SYNOPSIS
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36To compile this driver into the kernel,
37place the following lines in your
38kernel configuration file:
39.Bd -ragged -offset indent
40.Cd "device scbus"
41.Cd "device ahc"
63c20666 42.Cd "device pci"
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43.Pp
44To allow PCI adapters to use memory mapped I/O if enabled:
45.Cd options AHC_ALLOW_MEMIO
46.Pp
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47To compile in debugging code:
48.Cd options AHC_DEBUG
49.Cd options AHC_DEBUG_OPTS=<bitmask of options>
50.Cd options AHC_REG_PRETTY_PRINT
51.Pp
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52To configure one or more controllers to assume the target role:
53.Cd options AHC_TMODE_ENABLE <bitmask of units>
63c20666 54.Ed
984263bc 55.Pp
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56Alternatively, to load the driver as a
57module at boot time, place the following lines in
58.Xr loader.conf 5 :
59.Bd -literal -offset indent
60ahc_load="YES"
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61ahc_pci_load="YES"
62.Ed
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63.Sh DESCRIPTION
64This driver provides access to the
65.Tn SCSI
63c20666 66bus(es) connected to the Adaptec AIC77xx and AIC78xx
984263bc 67host adapter chips.
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68.Pp
69Driver features include support for twin and wide busses,
70fast, ultra or ultra2 synchronous transfers depending on controller type,
71tagged queueing, SCB paging, and target mode.
72.Pp
73Memory mapped I/O can be enabled for PCI devices with the
74.Dq Dv AHC_ALLOW_MEMIO
75configuration option.
76Memory mapped I/O is more efficient than the alternative, programmed I/O.
77Most PCI BIOSes will map devices so that either technique for communicating
78with the card is available.
79In some cases,
80usually when the PCI device is sitting behind a PCI->PCI bridge,
81the BIOS may fail to properly initialize the chip for memory mapped I/O.
82The typical symptom of this problem is a system hang if memory mapped I/O
83is attempted.
84Most modern motherboards perform the initialization correctly and work fine
85with this option enabled.
86.Pp
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87The
88.Dv AHC_DEBUG_OPTS
89option is used to control which diagnostic messages are printed to the
90console when
91.Dv AHC_DEBUG
92is enabled.
93Logically OR the following bits together:
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94.Bl -column -offset indent ".Em Value" ".Em Function"
95.It Em Value Ta Em Function
96.It 0x0001 Ta Show miscellaneous information
97.It 0x0002 Ta Show sense data
98.It 0x0004 Ta Show Serial EEPROM contents
99.It 0x0008 Ta Show bus termination settings
100.It 0x0010 Ta Show host memory usage
101.It 0x0020 Ta Show SCSI protocol messages
102.\".It 0x0040 XXX: AHC_SHOW_DV
103.It 0x0080 Ta Show selection timeouts
104.It 0x0200 Ta Show Queue Full status
105.It 0x0400 Ta Show SCB queue status
106.It 0x0800 Ta Show inbound packet information
107.\".It 0x1000 XXX: AHC_SHOW_MASKED_ERRORS
108.It 0x2000 Ta Enable extra diagnostic code in the firmware
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109.El
110.Pp
111The
112.Dv AHC_REG_PRETTY_PRINT
113option compiles in support for human-readable bit definitions for each register
114that is printed by the debugging code.
115.Pp
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116Individual controllers may be configured to operate in the target role
117through the
118.Dq Dv AHC_TMODE_ENABLE
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119configuration option.
120The value assigned to this option should be a bitmap
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121of all units where target mode is desired.
122For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
63c20666 123A value of 0x8a enables it for units 1, 3, and 7.
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124.Pp
125Per target configuration performed in the
126.Tn SCSI-Select
e842db4d 127menu, accessible at boot, is honored by this driver.
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128This includes synchronous/asynchronous transfers,
129maximum synchronous negotiation rate,
130wide transfers,
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131disconnection
132and the host adapter's SCSI ID.
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133For systems that store non-volatile settings in a system specific manner
134rather than a serial eeprom directly connected to the aic7xxx controller,
135the
136.Tn BIOS
137must be enabled for the driver to access this information.
e842db4d 138This restriction applies to many motherboard configurations.
984263bc 139.Pp
e842db4d 140Note that I/O addresses are determined automatically by the probe routines.
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141.Pp
142Performance and feature sets vary throughout the aic7xxx product line.
143The following table provides a comparison of the different chips supported
144by the
145.Nm
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146driver.
147Note that wide and twin channel features, although always supported
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148by a particular chip, may be disabled in a particular motherboard or card
149design.
1b722dce 150.Bd -ragged -compact
e842db4d 151.Bl -column "aic7850 " "MIPS " "PCI/32 " "MaxSync " "MaxWidth " "SCBs " "1 2 3 4 5 6 7 8 "
1b722dce 152.It Em Chip Ta Em MIPS Ta Em Bus Ta Em MaxSync Ta Em MaxWidth Ta Em SCBs Ta Em Features
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153.It aic7850 Ta 10 Ta PCI/32 Ta 10MHz Ta 8Bit Ta 3
154.It aic7860 Ta 10 Ta PCI/32 Ta 20MHz Ta 8Bit Ta 3
155.It aic7870 Ta 10 Ta PCI/32 Ta 10MHz Ta 16Bit Ta 16
156.It aic7880 Ta 10 Ta PCI/32 Ta 20MHz Ta 16Bit Ta 16
157.It aic7890 Ta 20 Ta PCI/32 Ta 40MHz Ta 16Bit Ta 16 Ta " 3 4 5 6 7 8"
158.It aic7891 Ta 20 Ta PCI/64 Ta 40MHz Ta 16Bit Ta 16 Ta " 3 4 5 6 7 8"
159.It aic7892 Ta 20 Ta PCI/64 Ta 80MHz Ta 16Bit Ta 16 Ta " 3 4 5 6 7 8"
160.It aic7895 Ta 15 Ta PCI/32 Ta 20MHz Ta 16Bit Ta 16 Ta " 2 3 4 5"
161.It aic7895C Ta 15 Ta PCI/32 Ta 20MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 8"
162.It aic7896 Ta 20 Ta PCI/32 Ta 40MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 6 7 8"
163.It aic7897 Ta 20 Ta PCI/64 Ta 40MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 6 7 8"
164.It aic7899 Ta 20 Ta PCI/64 Ta 80MHz Ta 16Bit Ta 16 Ta " 2 3 4 5 6 7 8"
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165.El
166.Pp
167.Bl -enum -compact
168.It
169Multiplexed Twin Channel Device - One controller servicing two busses.
170.It
171Multi-function Twin Channel Device - Two controllers on one chip.
172.It
173Command Channel Secondary DMA Engine - Allows scatter gather list and
174SCB prefetch.
175.It
17664 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
177.It
178Block Move Instruction Support - Doubles the speed of certain sequencer
179operations.
180.It
181.Sq Bayonet
182style Scatter Gather Engine - Improves S/G prefetch performance.
183.It
184Queuing Registers - Allows queueing of new transactions without pausing the
185sequencer.
186.It
187Multiple Target IDs - Allows the controller to respond to selection as a
188target on multiple SCSI IDs.
189.El
190.Ed
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191.Sh HARDWARE
192The
193.Nm
194driver supports the following
195.Tn SCSI
196host adapter chips and
197.Tn SCSI
198controller cards:
199.Pp
200.Bl -bullet -compact
201.It
202Adaptec
203.Tn AIC7770
204host adapter chip
205.It
206Adaptec
207.Tn AIC7850
208host adapter chip
209.It
210Adaptec
211.Tn AIC7860
212host adapter chip
213.It
214Adaptec
215.Tn AIC7870
216host adapter chip
217.It
218Adaptec
219.Tn AIC7880
220host adapter chip
221.It
222Adaptec
223.Tn AIC7890
224host adapter chip
225.It
226Adaptec
227.Tn AIC7891
228host adapter chip
229.It
230Adaptec
231.Tn AIC7892
232host adapter chip
233.It
234Adaptec
235.Tn AIC7895
236host adapter chip
237.It
238Adaptec
239.Tn AIC7896
240host adapter chip
241.It
242Adaptec
243.Tn AIC7897
244host adapter chip
245.It
246Adaptec
247.Tn AIC7899
248host adapter chip
249.It
250Adaptec
251.Tn 274X(W)
252.It
253Adaptec
254.Tn 274X(T)
255.It
256Adaptec
257.Tn 284X
258.It
259Adaptec
260.Tn 2910
261.It
262Adaptec
263.Tn 2915
264.It
265Adaptec
266.Tn 2920
267.It
268Adaptec
269.Tn 2930C
270.It
271Adaptec
272.Tn 2930U2
273.It
274Adaptec
275.Tn 2940
276.It
277Adaptec
278.Tn 2940J
279.It
280Adaptec
281.Tn 2940N
282.It
283Adaptec
284.Tn 2940U
285.It
286Adaptec
287.Tn 2940AU
288.It
289Adaptec
290.Tn 2940UW
291.It
292Adaptec
293.Tn 2940UW Dual
294.It
295Adaptec
296.Tn 2940UW Pro
297.It
298Adaptec
299.Tn 2940U2W
300.It
301Adaptec
302.Tn 2940U2B
303.It
304Adaptec
305.Tn 2950U2W
306.It
307Adaptec
308.Tn 2950U2B
309.It
310Adaptec
311.Tn 19160B
312.It
313Adaptec
314.Tn 29160B
315.It
316Adaptec
317.Tn 29160N
318.It
319Adaptec
320.Tn 3940
321.It
322Adaptec
323.Tn 3940U
324.It
325Adaptec
326.Tn 3940AU
327.It
328Adaptec
329.Tn 3940UW
330.It
331Adaptec
332.Tn 3940AUW
333.It
334Adaptec
335.Tn 3940U2W
336.It
337Adaptec
338.Tn 3950U2
339.It
340Adaptec
341.Tn 3960
342.It
343Adaptec
344.Tn 39160
345.It
346Adaptec
347.Tn 3985
348.It
349Adaptec
350.Tn 4944UW
351.It
352NEC PC-9821Xt13 (PC-98)
353.It
354NEC RvII26 (PC-98)
355.It
356NEC PC-9821X-B02L/B09 (PC-98)
357.It
358NEC SV-98/2-B03 (PC-98)
359.It
360Many motherboards with on-board
361.Tn SCSI
362support
363.El
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364.Sh SCSI CONTROL BLOCKS (SCBs)
365Every transaction sent to a device on the SCSI bus is assigned a
366.Sq SCSI Control Block
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367(SCB).
368The SCB contains all of the information required by the
369controller to process a transaction.
370The chip feature table lists
371the number of SCBs that can be stored in on-chip memory.
372All chips
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373with model numbers greater than or equal to 7870 allow for the on chip
374SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
375Very few Adaptec controller configurations have external SRAM.
376.Pp
377If external SRAM is not available, SCBs are a limited resource.
3f5e28f4 378Using the SCBs in a straight forward manner would only allow the driver to
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379handle as many concurrent transactions as there are physical SCBs.
380To fully utilize the SCSI bus and the devices on it,
381requires much more concurrency.
382The solution to this problem is
383.Em SCB Paging ,
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384a concept similar to memory paging.
385SCB paging takes advantage of
984263bc 386the fact that devices usually disconnect from the SCSI bus for long
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387periods of time without talking to the controller.
388The SCBs for disconnected transactions are only of use to the controller
389when the transfer is resumed.
390When the host queues another transaction
984263bc 391for the controller to execute, the controller firmware will use a
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392free SCB if one is available.
393Otherwise, the state of the most recently
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394disconnected (and therefore most likely to stay disconnected) SCB is
395saved, via dma, to host memory, and the local SCB reused to start
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396the new transaction.
397This allows the controller to queue up to
398255 transactions regardless of the amount of SCB space.
399Since the
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400local SCB space serves as a cache for disconnected transactions, the
401more SCB space available, the less host bus traffic consumed saving
402and restoring SCB data.
ac561d34 403.Sh SEE ALSO
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404.Xr cd 4 ,
405.Xr da 4 ,
406.Xr sa 4 ,
407.Xr scsi 4
408.Sh HISTORY
409The
410.Nm
411driver appeared in
412.Fx 2.0 .
413.Sh AUTHORS
414The
415.Nm
416driver, the
417.Tn AIC7xxx
418sequencer-code assembler,
419and the firmware running on the aic7xxx chips was written by
420.An Justin T. Gibbs .
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421.Sh BUGS
422Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
423.Tn AIC7870
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424Rev B in synchronous mode at 10MHz.
425Controllers with this problem have a
42642 MHz clock crystal on them and run slightly above 10MHz.
427This confuses the drive and hangs the bus.
428Setting a maximum synchronous negotiation rate of 8MHz in the
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429.Tn SCSI-Select
430utility will allow normal operation.
431.Pp
432Although the Ultra2 and Ultra160 products have sufficient instruction
433ram space to support both the initiator and target roles concurrently,
434this configuration is disabled in favor of allowing the target role
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435to respond on multiple target ids.
436A method for configuring dual role mode should be provided.
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437.Pp
438Tagged Queuing is not supported in target mode.
439.Pp
440Reselection in target mode fails to function correctly on all high
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441voltage differential boards as shipped by Adaptec.
442Information on
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443how to modify HVD board to work correctly in target mode is available
444from Adaptec.