[dragonfly.git] / sys / dev / netif / bnx / if_bnxvar.h

/*
 * Copyright (c) 2001 Wind River Systems
 * Copyright (c) 1997, 1998, 1999, 2001
 *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Bill Paul.
 * 4. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
 */

#ifndef _IF_BNXVAR_H_
#define _IF_BNXVAR_H_

/*
 * Tigon general information block. This resides in host memory
 * and contains the status counters, ring control blocks and
 * producer pointers.
 */

struct bnx_gib {
	struct bge_stats	bnx_stats;
	struct bge_rcb		bnx_tx_rcb[16];
	struct bge_rcb		bnx_std_rx_rcb;
	struct bge_rcb		bnx_jumbo_rx_rcb;
	struct bge_rcb		bnx_mini_rx_rcb;
	struct bge_rcb		bnx_return_rcb;
};

#define BNX_MIN_FRAMELEN	60
#define BNX_MAX_FRAMELEN	1536
#define BNX_JUMBO_FRAMELEN	9018
#define BNX_JUMBO_MTU		(BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)

#define BNX_TIMEOUT		5000
#define BNX_FIRMWARE_TIMEOUT	100000
#define BNX_TXCONS_UNSET	0xFFFF	/* impossible value */

/*
 * Other utility macros.
 */
#define BNX_INC(x, y)		(x) = ((x) + 1) % (y)

/*
 * Register access macros. The Tigon always uses memory mapped register
 * accesses and all registers must be accessed with 32 bit operations.
 */

#define CSR_WRITE_4(sc, reg, val)	\
	bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)

#define CSR_READ_4(sc, reg)		\
	bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)

#define BNX_SETBIT(sc, reg, x)	\
	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

#define BNX_CLRBIT(sc, reg, x)	\
	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

#define BNX_MEMWIN_READ(sc, x, val)				\
do {								\
	pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR,	\
	    (0xFFFF0000 & x), 4);				\
	val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF));	\
} while(0)

#define BNX_MEMWIN_WRITE(sc, x, val)				\
do {								\
	pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR,	\
	    (0xFFFF0000 & x), 4);				\
	CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val);	\
} while(0)

#define RCB_WRITE_4(sc, rcb, offset, val)			\
	bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle,	\
			  rcb + offsetof(struct bge_rcb, offset), val)

/*
 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
 * values are tuneable. They control the actual amount of buffers
 * allocated for the standard, mini and jumbo receive rings.
 */

#define BNX_SSLOTS	256
#define BNX_MSLOTS	256
#define BNX_JSLOTS	384

#define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN)
#define BNX_JLEN (BNX_JRAWLEN + \
	(sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t)))
#define BNX_JPAGESZ PAGE_SIZE
#define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ)
#define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID)

struct bnx_softc;

struct bnx_jslot {
	struct bnx_softc	*bnx_sc;
	void			*bnx_buf;
	bus_addr_t		bnx_paddr;
	int			bnx_inuse;
	int			bnx_slot;
	SLIST_ENTRY(bnx_jslot)	jslot_link;
};

/*
 * Ring structures. Most of these reside in host memory and we tell
 * the NIC where they are via the ring control blocks. The exceptions
 * are the tx and command rings, which live in NIC memory and which
 * we access via the shared memory window.
 */
struct bnx_ring_data {
	struct bge_rx_bd	*bnx_rx_std_ring;
	bus_addr_t		bnx_rx_std_ring_paddr;
	struct bge_rx_bd	*bnx_rx_jumbo_ring;
	bus_addr_t		bnx_rx_jumbo_ring_paddr;
	struct bge_rx_bd	*bnx_rx_return_ring;
	bus_addr_t		bnx_rx_return_ring_paddr;
	struct bge_tx_bd	*bnx_tx_ring;
	bus_addr_t		bnx_tx_ring_paddr;
	struct bge_status_block	*bnx_status_block;
	bus_addr_t		bnx_status_block_paddr;
	void			*bnx_jumbo_buf;
	struct bnx_gib		bnx_info;
};

struct bnx_rxchain {
	struct mbuf	*bnx_mbuf;
	bus_addr_t	bnx_paddr;
};

/*
 * Mbuf pointers. We need these to keep track of the virtual addresses
 * of our mbuf chains since we can only convert from physical to virtual,
 * not the other way around.
 */
struct bnx_chain_data {
	bus_dma_tag_t		bnx_parent_tag;
	bus_dma_tag_t		bnx_rx_std_ring_tag;
	bus_dma_tag_t		bnx_rx_jumbo_ring_tag;
	bus_dma_tag_t		bnx_rx_return_ring_tag;
	bus_dma_tag_t		bnx_tx_ring_tag;
	bus_dma_tag_t		bnx_status_tag;
	bus_dma_tag_t		bnx_jumbo_tag;
	bus_dma_tag_t		bnx_tx_mtag;	/* TX mbuf DMA tag */
	bus_dma_tag_t		bnx_rx_mtag;	/* RX mbuf DMA tag */
	bus_dmamap_t		bnx_rx_tmpmap;
	bus_dmamap_t		bnx_tx_dmamap[BGE_TX_RING_CNT];
	bus_dmamap_t		bnx_rx_std_dmamap[BGE_STD_RX_RING_CNT];
	bus_dmamap_t		bnx_rx_std_ring_map;
	bus_dmamap_t		bnx_rx_jumbo_ring_map;
	bus_dmamap_t		bnx_tx_ring_map;
	bus_dmamap_t		bnx_rx_return_ring_map;
	bus_dmamap_t		bnx_status_map;
	bus_dmamap_t		bnx_jumbo_map;
	struct mbuf		*bnx_tx_chain[BGE_TX_RING_CNT];
	struct bnx_rxchain	bnx_rx_std_chain[BGE_STD_RX_RING_CNT];
	struct bnx_rxchain	bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
	/* Stick the jumbo mem management stuff here too. */
	struct bnx_jslot	bnx_jslots[BNX_JSLOTS];
};

struct bnx_softc {
	struct arpcom		arpcom;		/* interface info */
	device_t		bnx_dev;
	device_t		bnx_miibus;
	bus_space_handle_t	bnx_bhandle;
	bus_space_tag_t		bnx_btag;
	void			*bnx_intrhand;
	struct resource		*bnx_irq;
	int			bnx_irq_type;
	int			bnx_irq_rid;
	struct resource		*bnx_res;
	struct ifmedia		bnx_ifmedia;	/* TBI media info */
	int			bnx_pciecap;
	uint32_t		bnx_status_tag;
	uint32_t		bnx_flags;	/* BNX_FLAG_ */
#define BNX_FLAG_TBI		0x00000001
#define BNX_FLAG_JUMBO		0x00000002
#define BNX_FLAG_ONESHOT_MSI	0x00000004
#define BNX_FLAG_5717_PLUS	0x00000008
#define BNX_FLAG_MII_SERDES	0x00000010
#define BNX_FLAG_CPMU		0x00000020
#define BNX_FLAG_57765_PLUS	0x00000040
#define BNX_FLAG_57765_FAMILY	0x00000080
#define BNX_FLAG_STATUSTAG_BUG	0x00000100
#define BNX_FLAG_TSO		0x00000200
#define BNX_FLAG_NO_EEPROM	0x10000000
#define BNX_FLAG_SHORTDMA	0x40000000

	uint32_t		bnx_chipid;
	uint32_t		bnx_asicrev;
	uint32_t		bnx_chiprev;
	struct bnx_ring_data	bnx_ldata;	/* rings */
	struct bnx_chain_data	bnx_cdata;	/* mbufs */
	uint16_t		bnx_tx_saved_considx;
	uint16_t		bnx_rx_saved_considx;
	uint16_t		bnx_return_ring_cnt;
	uint16_t		bnx_std;	/* current std ring head */
	uint16_t		bnx_jumbo;	/* current jumo ring head */
	SLIST_HEAD(__bnx_jfreehead, bnx_jslot)	bnx_jfree_listhead;
	struct lwkt_serialize	bnx_jslot_serializer;
	uint32_t		bnx_rx_coal_ticks;
	uint32_t		bnx_tx_coal_ticks;
	uint32_t		bnx_rx_coal_bds;
	uint32_t		bnx_tx_coal_bds;
	uint32_t		bnx_rx_coal_bds_int;
	uint32_t		bnx_tx_coal_bds_int;
	uint32_t		bnx_tx_prodidx;
	uint32_t		bnx_tx_buf_ratio;
	uint32_t		bnx_mi_mode;
	int			bnx_force_defrag;
	int			bnx_if_flags;
	int			bnx_txcnt;
	int			bnx_link;
	int			bnx_link_evt;
	int			bnx_stat_cpuid;
	struct callout		bnx_stat_timer;

	uint16_t		bnx_rx_check_considx;
	uint16_t		bnx_tx_check_considx;
	boolean_t		bnx_intr_maylose;
	int			bnx_intr_cpuid;
	struct callout		bnx_intr_timer;

	struct sysctl_ctx_list	bnx_sysctl_ctx;
	struct sysctl_oid	*bnx_sysctl_tree;

	int			bnx_phyno;
	uint32_t		bnx_coal_chg;
#define BNX_RX_COAL_TICKS_CHG		0x01
#define BNX_TX_COAL_TICKS_CHG		0x02
#define BNX_RX_COAL_BDS_CHG		0x04
#define BNX_TX_COAL_BDS_CHG		0x08
#define BNX_RX_COAL_BDS_INT_CHG		0x40
#define BNX_TX_COAL_BDS_INT_CHG		0x80

	void			(*bnx_link_upd)(struct bnx_softc *, uint32_t);
	uint32_t		bnx_link_chg;

#define BNX_TSO_NSTATS		45
	u_long			bnx_tsosegs[BNX_TSO_NSTATS];
};

#define BNX_NSEG_NEW		40
#define BNX_NSEG_SPARE		33	/* enough for 64K TSO segment */
#define BNX_NSEG_RSVD		4

/* RX coalesce ticks, unit: us */
#define BNX_RX_COAL_TICKS_MIN	0
#define BNX_RX_COAL_TICKS_DEF	160
#define BNX_RX_COAL_TICKS_MAX	1023

/* TX coalesce ticks, unit: us */
#define BNX_TX_COAL_TICKS_MIN	0
#define BNX_TX_COAL_TICKS_DEF	1023
#define BNX_TX_COAL_TICKS_MAX	1023

/* RX coalesce BDs */
#define BNX_RX_COAL_BDS_MIN	1
#define BNX_RX_COAL_BDS_DEF	80
#define BNX_RX_COAL_BDS_MAX	255

/* TX coalesce BDs */
#define BNX_TX_COAL_BDS_MIN	1
#define BNX_TX_COAL_BDS_DEF	128
#define BNX_TX_COAL_BDS_MAX	255

#endif	/* !_IF_BNXVAR_H_ */
Commit	Line	Data
6c8d8ecc SZ	1	/*
	2	* Copyright (c) 2001 Wind River Systems
	3	* Copyright (c) 1997, 1998, 1999, 2001
	4	* Bill Paul <wpaul@windriver.com>. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	* 1. Redistributions of source code must retain the above copyright
	10	* notice, this list of conditions and the following disclaimer.
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	* 3. All advertising materials mentioning features or use of this software
	15	* must display the following acknowledgement:
	16	* This product includes software developed by Bill Paul.
	17	* 4. Neither the name of the author nor the names of any co-contributors
	18	* may be used to endorse or promote products derived from this software
	19	* without specific prior written permission.
	20	*
	21	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
	22	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	23	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	24	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
	25	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	26	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	27	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	28	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	29	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	30	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	31	* THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	* $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
	34	* $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
	35	*/
	36
	37	#ifndef _IF_BNXVAR_H_
	38	#define _IF_BNXVAR_H_
	39
	40	/*
	41	* Tigon general information block. This resides in host memory
	42	* and contains the status counters, ring control blocks and
	43	* producer pointers.
	44	*/
	45
	46	struct bnx_gib {
	47	struct bge_stats bnx_stats;
	48	struct bge_rcb bnx_tx_rcb[16];
	49	struct bge_rcb bnx_std_rx_rcb;
	50	struct bge_rcb bnx_jumbo_rx_rcb;
	51	struct bge_rcb bnx_mini_rx_rcb;
	52	struct bge_rcb bnx_return_rcb;
	53	};
	54
	55	#define BNX_MIN_FRAMELEN 60
	56	#define BNX_MAX_FRAMELEN 1536
	57	#define BNX_JUMBO_FRAMELEN 9018
	58	#define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
	59
	60	#define BNX_TIMEOUT 5000
	61	#define BNX_FIRMWARE_TIMEOUT 100000
	62	#define BNX_TXCONS_UNSET 0xFFFF /* impossible value */
	63
	64	/*
65	* Other utility macros.
66	*/
67	#define BNX_INC(x, y) (x) = ((x) + 1) % (y)
68
69	/*
70	* Register access macros. The Tigon always uses memory mapped register
71	* accesses and all registers must be accessed with 32 bit operations.
72	*/
73
74	#define CSR_WRITE_4(sc, reg, val) \
75	bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
76
77	#define CSR_READ_4(sc, reg) \
78	bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
79
80	#define BNX_SETBIT(sc, reg, x) \
81	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| x))
82
83	#define BNX_CLRBIT(sc, reg, x) \
84	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
85
86	#define BNX_MEMWIN_READ(sc, x, val) \
87	do { \
88	pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
89	(0xFFFF0000 & x), 4); \
90	val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
91	} while(0)
92
93	#define BNX_MEMWIN_WRITE(sc, x, val) \
94	do { \
95	pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
96	(0xFFFF0000 & x), 4); \
97	CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
98	} while(0)
99
100	#define RCB_WRITE_4(sc, rcb, offset, val) \
101	bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \
102	rcb + offsetof(struct bge_rcb, offset), val)
103
104	/*
105	* Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
106	* values are tuneable. They control the actual amount of buffers
107	* allocated for the standard, mini and jumbo receive rings.
108	*/
109
110	#define BNX_SSLOTS 256
111	#define BNX_MSLOTS 256
112	#define BNX_JSLOTS 384
113
114	#define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN)
115	#define BNX_JLEN (BNX_JRAWLEN + \
116	(sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t)))
117	#define BNX_JPAGESZ PAGE_SIZE
118	#define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ)
119	#define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID)
120
121	struct bnx_softc;
122
123	struct bnx_jslot {
124	struct bnx_softc *bnx_sc;
125	void *bnx_buf;
126	bus_addr_t bnx_paddr;
127	int bnx_inuse;
128	int bnx_slot;
129	SLIST_ENTRY(bnx_jslot) jslot_link;
130	};
131
132	/*
133	* Ring structures. Most of these reside in host memory and we tell
134	* the NIC where they are via the ring control blocks. The exceptions
135	* are the tx and command rings, which live in NIC memory and which
136	* we access via the shared memory window.
137	*/
138	struct bnx_ring_data {
139	struct bge_rx_bd *bnx_rx_std_ring;
140	bus_addr_t bnx_rx_std_ring_paddr;
141	struct bge_rx_bd *bnx_rx_jumbo_ring;
142	bus_addr_t bnx_rx_jumbo_ring_paddr;
143	struct bge_rx_bd *bnx_rx_return_ring;
144	bus_addr_t bnx_rx_return_ring_paddr;
145	struct bge_tx_bd *bnx_tx_ring;
146	bus_addr_t bnx_tx_ring_paddr;
147	struct bge_status_block *bnx_status_block;
148	bus_addr_t bnx_status_block_paddr;
149	void *bnx_jumbo_buf;
150	struct bnx_gib bnx_info;
151	};
152
153	struct bnx_rxchain {
154	struct mbuf *bnx_mbuf;
155	bus_addr_t bnx_paddr;
156	};
157
158	/*
159	* Mbuf pointers. We need these to keep track of the virtual addresses
160	* of our mbuf chains since we can only convert from physical to virtual,
161	* not the other way around.
162	*/
163	struct bnx_chain_data {
164	bus_dma_tag_t bnx_parent_tag;
165	bus_dma_tag_t bnx_rx_std_ring_tag;
166	bus_dma_tag_t bnx_rx_jumbo_ring_tag;
167	bus_dma_tag_t bnx_rx_return_ring_tag;
168	bus_dma_tag_t bnx_tx_ring_tag;
169	bus_dma_tag_t bnx_status_tag;
170	bus_dma_tag_t bnx_jumbo_tag;
171	bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */
172	bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */
173	bus_dmamap_t bnx_rx_tmpmap;
174	bus_dmamap_t bnx_tx_dmamap[BGE_TX_RING_CNT];
175	bus_dmamap_t bnx_rx_std_dmamap[BGE_STD_RX_RING_CNT];
176	bus_dmamap_t bnx_rx_std_ring_map;
177	bus_dmamap_t bnx_rx_jumbo_ring_map;
178	bus_dmamap_t bnx_tx_ring_map;
179	bus_dmamap_t bnx_rx_return_ring_map;
180	bus_dmamap_t bnx_status_map;
181	bus_dmamap_t bnx_jumbo_map;
182	struct mbuf *bnx_tx_chain[BGE_TX_RING_CNT];
183	struct bnx_rxchain bnx_rx_std_chain[BGE_STD_RX_RING_CNT];
184	struct bnx_rxchain bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
185	/* Stick the jumbo mem management stuff here too. */
186	struct bnx_jslot bnx_jslots[BNX_JSLOTS];
187	};
188
189	struct bnx_softc {
190	struct arpcom arpcom; /* interface info */
191	device_t bnx_dev;
192	device_t bnx_miibus;
193	bus_space_handle_t bnx_bhandle;
194	bus_space_tag_t bnx_btag;
195	void *bnx_intrhand;
196	struct resource *bnx_irq;
197	int bnx_irq_type;
198	int bnx_irq_rid;
199	struct resource *bnx_res;
200	struct ifmedia bnx_ifmedia; /* TBI media info */
201	int bnx_pciecap;
202	uint32_t bnx_status_tag;
203	uint32_t bnx_flags; /* BNX_FLAG_ */
204	#define BNX_FLAG_TBI 0x00000001
205	#define BNX_FLAG_JUMBO 0x00000002
206	#define BNX_FLAG_ONESHOT_MSI 0x00000004
207	#define BNX_FLAG_5717_PLUS 0x00000008
208	#define BNX_FLAG_MII_SERDES 0x00000010
209	#define BNX_FLAG_CPMU 0x00000020
f368d0d9 SZ	210	#define BNX_FLAG_57765_PLUS 0x00000040
f368d0d9 SZ	211	#define BNX_FLAG_57765_FAMILY 0x00000080
df9ccc98	212	#define BNX_FLAG_STATUSTAG_BUG 0x00000100
66deb1c1	213	#define BNX_FLAG_TSO 0x00000200
6c8d8ecc SZ	214	#define BNX_FLAG_NO_EEPROM 0x10000000
	215	#define BNX_FLAG_SHORTDMA 0x40000000
	216
	217	uint32_t bnx_chipid;
	218	uint32_t bnx_asicrev;
	219	uint32_t bnx_chiprev;
	220	struct bnx_ring_data bnx_ldata; /* rings */
	221	struct bnx_chain_data bnx_cdata; /* mbufs */
	222	uint16_t bnx_tx_saved_considx;
	223	uint16_t bnx_rx_saved_considx;
6c8d8ecc SZ	224	uint16_t bnx_return_ring_cnt;
	225	uint16_t bnx_std; /* current std ring head */
	226	uint16_t bnx_jumbo; /* current jumo ring head */
	227	SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead;
	228	struct lwkt_serialize bnx_jslot_serializer;
	229	uint32_t bnx_rx_coal_ticks;
	230	uint32_t bnx_tx_coal_ticks;
	231	uint32_t bnx_rx_coal_bds;
	232	uint32_t bnx_tx_coal_bds;
	233	uint32_t bnx_rx_coal_bds_int;
	234	uint32_t bnx_tx_coal_bds_int;
	235	uint32_t bnx_tx_prodidx;
	236	uint32_t bnx_tx_buf_ratio;
	237	uint32_t bnx_mi_mode;
	238	int bnx_force_defrag;
	239	int bnx_if_flags;
	240	int bnx_txcnt;
	241	int bnx_link;
	242	int bnx_link_evt;
8ca0f604	243	int bnx_stat_cpuid;
6c8d8ecc SZ	244	struct callout bnx_stat_timer;
6c8d8ecc SZ	245
df9ccc98 SZ	246	uint16_t bnx_rx_check_considx;
	247	uint16_t bnx_tx_check_considx;
	248	boolean_t bnx_intr_maylose;
	249	int bnx_intr_cpuid;
	250	struct callout bnx_intr_timer;
	251
6c8d8ecc SZ	252	struct sysctl_ctx_list bnx_sysctl_ctx;
	253	struct sysctl_oid *bnx_sysctl_tree;
	254
	255	int bnx_phyno;
	256	uint32_t bnx_coal_chg;
	257	#define BNX_RX_COAL_TICKS_CHG 0x01
	258	#define BNX_TX_COAL_TICKS_CHG 0x02
	259	#define BNX_RX_COAL_BDS_CHG 0x04
	260	#define BNX_TX_COAL_BDS_CHG 0x08
	261	#define BNX_RX_COAL_BDS_INT_CHG 0x40
	262	#define BNX_TX_COAL_BDS_INT_CHG 0x80
	263
	264	void (bnx_link_upd)(struct bnx_softc , uint32_t);
	265	uint32_t bnx_link_chg;
66deb1c1 SZ	266
	267	#define BNX_TSO_NSTATS 45
	268	u_long bnx_tsosegs[BNX_TSO_NSTATS];
6c8d8ecc SZ	269	};
6c8d8ecc SZ	270
66deb1c1	271	#define BNX_NSEG_NEW 40
adea0b8c SZ	272	#define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */
adea0b8c SZ	273	#define BNX_NSEG_RSVD 4
6c8d8ecc SZ	274
	275	/* RX coalesce ticks, unit: us */
	276	#define BNX_RX_COAL_TICKS_MIN 0
	277	#define BNX_RX_COAL_TICKS_DEF 160
	278	#define BNX_RX_COAL_TICKS_MAX 1023
	279
	280	/* TX coalesce ticks, unit: us */
	281	#define BNX_TX_COAL_TICKS_MIN 0
	282	#define BNX_TX_COAL_TICKS_DEF 1023
	283	#define BNX_TX_COAL_TICKS_MAX 1023
	284
	285	/* RX coalesce BDs */
	286	#define BNX_RX_COAL_BDS_MIN 1
	287	#define BNX_RX_COAL_BDS_DEF 80
	288	#define BNX_RX_COAL_BDS_MAX 255
	289
	290	/* TX coalesce BDs */
	291	#define BNX_TX_COAL_BDS_MIN 1
	292	#define BNX_TX_COAL_BDS_DEF 128
	293	#define BNX_TX_COAL_BDS_MAX 255
	294
	295	#endif /* !_IF_BNXVAR_H_ */