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x86_64/ioapic_abi: Augment intr_disable/intr_enable w/ assertions
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
CommitLineData
c8fe38ae
MD		 1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
47#include <sys/interrupt.h>
48#include <sys/bus.h>
981239a7 49#include <sys/rman.h>
95874ffd 50#include <sys/thread2.h>
c8fe38ae
MD		 51
52#include <machine/smp.h>
53#include <machine/segments.h>
54#include <machine/md_var.h>
57a9c56b 55#include <machine/intr_machdep.h>
c8fe38ae
MD		 56#include <machine/globaldata.h>
57
104463f2 58#include <machine_base/isa/isa_intr.h>
61452645 59#include <machine_base/icu/icu.h>
6b809ec7 60#include <machine_base/icu/icu_var.h>
61452645 61#include <machine_base/apic/ioapic.h>
929c940f 62#include <machine_base/apic/ioapic_abi.h>
77f86d14 63#include <machine_base/apic/ioapic_ipl.h>
9a4bd8f3 64#include <machine_base/apic/apicreg.h>
c8fe38ae 65
95874ffd
SZ		 66#include <dev/acpica5/acpi_sci_var.h>
67
451af8d9
SZ		 68#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
69
c8fe38ae 70extern inthand_t
9e0e3f85
SZ		 71 IDTVEC(ioapic_intr0),
72 IDTVEC(ioapic_intr1),
73 IDTVEC(ioapic_intr2),
74 IDTVEC(ioapic_intr3),
75 IDTVEC(ioapic_intr4),
76 IDTVEC(ioapic_intr5),
77 IDTVEC(ioapic_intr6),
78 IDTVEC(ioapic_intr7),
79 IDTVEC(ioapic_intr8),
80 IDTVEC(ioapic_intr9),
81 IDTVEC(ioapic_intr10),
82 IDTVEC(ioapic_intr11),
83 IDTVEC(ioapic_intr12),
84 IDTVEC(ioapic_intr13),
85 IDTVEC(ioapic_intr14),
86 IDTVEC(ioapic_intr15),
87 IDTVEC(ioapic_intr16),
88 IDTVEC(ioapic_intr17),
89 IDTVEC(ioapic_intr18),
90 IDTVEC(ioapic_intr19),
91 IDTVEC(ioapic_intr20),
92 IDTVEC(ioapic_intr21),
93 IDTVEC(ioapic_intr22),
94 IDTVEC(ioapic_intr23),
95 IDTVEC(ioapic_intr24),
96 IDTVEC(ioapic_intr25),
97 IDTVEC(ioapic_intr26),
98 IDTVEC(ioapic_intr27),
99 IDTVEC(ioapic_intr28),
100 IDTVEC(ioapic_intr29),
101 IDTVEC(ioapic_intr30),
102 IDTVEC(ioapic_intr31),
103 IDTVEC(ioapic_intr32),
104 IDTVEC(ioapic_intr33),
105 IDTVEC(ioapic_intr34),
106 IDTVEC(ioapic_intr35),
107 IDTVEC(ioapic_intr36),
108 IDTVEC(ioapic_intr37),
109 IDTVEC(ioapic_intr38),
110 IDTVEC(ioapic_intr39),
111 IDTVEC(ioapic_intr40),
112 IDTVEC(ioapic_intr41),
113 IDTVEC(ioapic_intr42),
114 IDTVEC(ioapic_intr43),
115 IDTVEC(ioapic_intr44),
116 IDTVEC(ioapic_intr45),
117 IDTVEC(ioapic_intr46),
118 IDTVEC(ioapic_intr47),
119 IDTVEC(ioapic_intr48),
120 IDTVEC(ioapic_intr49),
121 IDTVEC(ioapic_intr50),
122 IDTVEC(ioapic_intr51),
123 IDTVEC(ioapic_intr52),
124 IDTVEC(ioapic_intr53),
125 IDTVEC(ioapic_intr54),
126 IDTVEC(ioapic_intr55),
127 IDTVEC(ioapic_intr56),
128 IDTVEC(ioapic_intr57),
129 IDTVEC(ioapic_intr58),
130 IDTVEC(ioapic_intr59),
131 IDTVEC(ioapic_intr60),
132 IDTVEC(ioapic_intr61),
133 IDTVEC(ioapic_intr62),
134 IDTVEC(ioapic_intr63),
135 IDTVEC(ioapic_intr64),
136 IDTVEC(ioapic_intr65),
137 IDTVEC(ioapic_intr66),
138 IDTVEC(ioapic_intr67),
139 IDTVEC(ioapic_intr68),
140 IDTVEC(ioapic_intr69),
141 IDTVEC(ioapic_intr70),
142 IDTVEC(ioapic_intr71),
143 IDTVEC(ioapic_intr72),
144 IDTVEC(ioapic_intr73),
145 IDTVEC(ioapic_intr74),
146 IDTVEC(ioapic_intr75),
147 IDTVEC(ioapic_intr76),
148 IDTVEC(ioapic_intr77),
149 IDTVEC(ioapic_intr78),
150 IDTVEC(ioapic_intr79),
151 IDTVEC(ioapic_intr80),
152 IDTVEC(ioapic_intr81),
153 IDTVEC(ioapic_intr82),
154 IDTVEC(ioapic_intr83),
155 IDTVEC(ioapic_intr84),
156 IDTVEC(ioapic_intr85),
157 IDTVEC(ioapic_intr86),
158 IDTVEC(ioapic_intr87),
159 IDTVEC(ioapic_intr88),
160 IDTVEC(ioapic_intr89),
161 IDTVEC(ioapic_intr90),
162 IDTVEC(ioapic_intr91),
163 IDTVEC(ioapic_intr92),
164 IDTVEC(ioapic_intr93),
165 IDTVEC(ioapic_intr94),
166 IDTVEC(ioapic_intr95),
167 IDTVEC(ioapic_intr96),
168 IDTVEC(ioapic_intr97),
169 IDTVEC(ioapic_intr98),
170 IDTVEC(ioapic_intr99),
171 IDTVEC(ioapic_intr100),
172 IDTVEC(ioapic_intr101),
173 IDTVEC(ioapic_intr102),
174 IDTVEC(ioapic_intr103),
175 IDTVEC(ioapic_intr104),
176 IDTVEC(ioapic_intr105),
177 IDTVEC(ioapic_intr106),
178 IDTVEC(ioapic_intr107),
179 IDTVEC(ioapic_intr108),
180 IDTVEC(ioapic_intr109),
181 IDTVEC(ioapic_intr110),
182 IDTVEC(ioapic_intr111),
183 IDTVEC(ioapic_intr112),
184 IDTVEC(ioapic_intr113),
185 IDTVEC(ioapic_intr114),
186 IDTVEC(ioapic_intr115),
187 IDTVEC(ioapic_intr116),
188 IDTVEC(ioapic_intr117),
189 IDTVEC(ioapic_intr118),
190 IDTVEC(ioapic_intr119),
191 IDTVEC(ioapic_intr120),
192 IDTVEC(ioapic_intr121),
193 IDTVEC(ioapic_intr122),
194 IDTVEC(ioapic_intr123),
195 IDTVEC(ioapic_intr124),
196 IDTVEC(ioapic_intr125),
197 IDTVEC(ioapic_intr126),
198 IDTVEC(ioapic_intr127),
199 IDTVEC(ioapic_intr128),
200 IDTVEC(ioapic_intr129),
201 IDTVEC(ioapic_intr130),
202 IDTVEC(ioapic_intr131),
203 IDTVEC(ioapic_intr132),
204 IDTVEC(ioapic_intr133),
205 IDTVEC(ioapic_intr134),
206 IDTVEC(ioapic_intr135),
207 IDTVEC(ioapic_intr136),
208 IDTVEC(ioapic_intr137),
209 IDTVEC(ioapic_intr138),
210 IDTVEC(ioapic_intr139),
211 IDTVEC(ioapic_intr140),
212 IDTVEC(ioapic_intr141),
213 IDTVEC(ioapic_intr142),
214 IDTVEC(ioapic_intr143),
215 IDTVEC(ioapic_intr144),
216 IDTVEC(ioapic_intr145),
217 IDTVEC(ioapic_intr146),
218 IDTVEC(ioapic_intr147),
219 IDTVEC(ioapic_intr148),
220 IDTVEC(ioapic_intr149),
221 IDTVEC(ioapic_intr150),
222 IDTVEC(ioapic_intr151),
223 IDTVEC(ioapic_intr152),
224 IDTVEC(ioapic_intr153),
225 IDTVEC(ioapic_intr154),
226 IDTVEC(ioapic_intr155),
227 IDTVEC(ioapic_intr156),
228 IDTVEC(ioapic_intr157),
229 IDTVEC(ioapic_intr158),
230 IDTVEC(ioapic_intr159),
231 IDTVEC(ioapic_intr160),
232 IDTVEC(ioapic_intr161),
233 IDTVEC(ioapic_intr162),
234 IDTVEC(ioapic_intr163),
235 IDTVEC(ioapic_intr164),
236 IDTVEC(ioapic_intr165),
237 IDTVEC(ioapic_intr166),
238 IDTVEC(ioapic_intr167),
239 IDTVEC(ioapic_intr168),
240 IDTVEC(ioapic_intr169),
241 IDTVEC(ioapic_intr170),
242 IDTVEC(ioapic_intr171),
243 IDTVEC(ioapic_intr172),
244 IDTVEC(ioapic_intr173),
245 IDTVEC(ioapic_intr174),
246 IDTVEC(ioapic_intr175),
247 IDTVEC(ioapic_intr176),
248 IDTVEC(ioapic_intr177),
249 IDTVEC(ioapic_intr178),
250 IDTVEC(ioapic_intr179),
251 IDTVEC(ioapic_intr180),
252 IDTVEC(ioapic_intr181),
253 IDTVEC(ioapic_intr182),
254 IDTVEC(ioapic_intr183),
255 IDTVEC(ioapic_intr184),
256 IDTVEC(ioapic_intr185),
257 IDTVEC(ioapic_intr186),
258 IDTVEC(ioapic_intr187),
259 IDTVEC(ioapic_intr188),
260 IDTVEC(ioapic_intr189),
261 IDTVEC(ioapic_intr190),
262 IDTVEC(ioapic_intr191);
263
264static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
265 &IDTVEC(ioapic_intr0),
266 &IDTVEC(ioapic_intr1),
267 &IDTVEC(ioapic_intr2),
268 &IDTVEC(ioapic_intr3),
269 &IDTVEC(ioapic_intr4),
270 &IDTVEC(ioapic_intr5),
271 &IDTVEC(ioapic_intr6),
272 &IDTVEC(ioapic_intr7),
273 &IDTVEC(ioapic_intr8),
274 &IDTVEC(ioapic_intr9),
275 &IDTVEC(ioapic_intr10),
276 &IDTVEC(ioapic_intr11),
277 &IDTVEC(ioapic_intr12),
278 &IDTVEC(ioapic_intr13),
279 &IDTVEC(ioapic_intr14),
280 &IDTVEC(ioapic_intr15),
281 &IDTVEC(ioapic_intr16),
282 &IDTVEC(ioapic_intr17),
283 &IDTVEC(ioapic_intr18),
284 &IDTVEC(ioapic_intr19),
285 &IDTVEC(ioapic_intr20),
286 &IDTVEC(ioapic_intr21),
287 &IDTVEC(ioapic_intr22),
288 &IDTVEC(ioapic_intr23),
289 &IDTVEC(ioapic_intr24),
290 &IDTVEC(ioapic_intr25),
291 &IDTVEC(ioapic_intr26),
292 &IDTVEC(ioapic_intr27),
293 &IDTVEC(ioapic_intr28),
294 &IDTVEC(ioapic_intr29),
295 &IDTVEC(ioapic_intr30),
296 &IDTVEC(ioapic_intr31),
297 &IDTVEC(ioapic_intr32),
298 &IDTVEC(ioapic_intr33),
299 &IDTVEC(ioapic_intr34),
300 &IDTVEC(ioapic_intr35),
301 &IDTVEC(ioapic_intr36),
302 &IDTVEC(ioapic_intr37),
303 &IDTVEC(ioapic_intr38),
304 &IDTVEC(ioapic_intr39),
305 &IDTVEC(ioapic_intr40),
306 &IDTVEC(ioapic_intr41),
307 &IDTVEC(ioapic_intr42),
308 &IDTVEC(ioapic_intr43),
309 &IDTVEC(ioapic_intr44),
310 &IDTVEC(ioapic_intr45),
311 &IDTVEC(ioapic_intr46),
312 &IDTVEC(ioapic_intr47),
313 &IDTVEC(ioapic_intr48),
314 &IDTVEC(ioapic_intr49),
315 &IDTVEC(ioapic_intr50),
316 &IDTVEC(ioapic_intr51),
317 &IDTVEC(ioapic_intr52),
318 &IDTVEC(ioapic_intr53),
319 &IDTVEC(ioapic_intr54),
320 &IDTVEC(ioapic_intr55),
321 &IDTVEC(ioapic_intr56),
322 &IDTVEC(ioapic_intr57),
323 &IDTVEC(ioapic_intr58),
324 &IDTVEC(ioapic_intr59),
325 &IDTVEC(ioapic_intr60),
326 &IDTVEC(ioapic_intr61),
327 &IDTVEC(ioapic_intr62),
328 &IDTVEC(ioapic_intr63),
329 &IDTVEC(ioapic_intr64),
330 &IDTVEC(ioapic_intr65),
331 &IDTVEC(ioapic_intr66),
332 &IDTVEC(ioapic_intr67),
333 &IDTVEC(ioapic_intr68),
334 &IDTVEC(ioapic_intr69),
335 &IDTVEC(ioapic_intr70),
336 &IDTVEC(ioapic_intr71),
337 &IDTVEC(ioapic_intr72),
338 &IDTVEC(ioapic_intr73),
339 &IDTVEC(ioapic_intr74),
340 &IDTVEC(ioapic_intr75),
341 &IDTVEC(ioapic_intr76),
342 &IDTVEC(ioapic_intr77),
343 &IDTVEC(ioapic_intr78),
344 &IDTVEC(ioapic_intr79),
345 &IDTVEC(ioapic_intr80),
346 &IDTVEC(ioapic_intr81),
347 &IDTVEC(ioapic_intr82),
348 &IDTVEC(ioapic_intr83),
349 &IDTVEC(ioapic_intr84),
350 &IDTVEC(ioapic_intr85),
351 &IDTVEC(ioapic_intr86),
352 &IDTVEC(ioapic_intr87),
353 &IDTVEC(ioapic_intr88),
354 &IDTVEC(ioapic_intr89),
355 &IDTVEC(ioapic_intr90),
356 &IDTVEC(ioapic_intr91),
357 &IDTVEC(ioapic_intr92),
358 &IDTVEC(ioapic_intr93),
359 &IDTVEC(ioapic_intr94),
360 &IDTVEC(ioapic_intr95),
361 &IDTVEC(ioapic_intr96),
362 &IDTVEC(ioapic_intr97),
363 &IDTVEC(ioapic_intr98),
364 &IDTVEC(ioapic_intr99),
365 &IDTVEC(ioapic_intr100),
366 &IDTVEC(ioapic_intr101),
367 &IDTVEC(ioapic_intr102),
368 &IDTVEC(ioapic_intr103),
369 &IDTVEC(ioapic_intr104),
370 &IDTVEC(ioapic_intr105),
371 &IDTVEC(ioapic_intr106),
372 &IDTVEC(ioapic_intr107),
373 &IDTVEC(ioapic_intr108),
374 &IDTVEC(ioapic_intr109),
375 &IDTVEC(ioapic_intr110),
376 &IDTVEC(ioapic_intr111),
377 &IDTVEC(ioapic_intr112),
378 &IDTVEC(ioapic_intr113),
379 &IDTVEC(ioapic_intr114),
380 &IDTVEC(ioapic_intr115),
381 &IDTVEC(ioapic_intr116),
382 &IDTVEC(ioapic_intr117),
383 &IDTVEC(ioapic_intr118),
384 &IDTVEC(ioapic_intr119),
385 &IDTVEC(ioapic_intr120),
386 &IDTVEC(ioapic_intr121),
387 &IDTVEC(ioapic_intr122),
388 &IDTVEC(ioapic_intr123),
389 &IDTVEC(ioapic_intr124),
390 &IDTVEC(ioapic_intr125),
391 &IDTVEC(ioapic_intr126),
392 &IDTVEC(ioapic_intr127),
393 &IDTVEC(ioapic_intr128),
394 &IDTVEC(ioapic_intr129),
395 &IDTVEC(ioapic_intr130),
396 &IDTVEC(ioapic_intr131),
397 &IDTVEC(ioapic_intr132),
398 &IDTVEC(ioapic_intr133),
399 &IDTVEC(ioapic_intr134),
400 &IDTVEC(ioapic_intr135),
401 &IDTVEC(ioapic_intr136),
402 &IDTVEC(ioapic_intr137),
403 &IDTVEC(ioapic_intr138),
404 &IDTVEC(ioapic_intr139),
405 &IDTVEC(ioapic_intr140),
406 &IDTVEC(ioapic_intr141),
407 &IDTVEC(ioapic_intr142),
408 &IDTVEC(ioapic_intr143),
409 &IDTVEC(ioapic_intr144),
410 &IDTVEC(ioapic_intr145),
411 &IDTVEC(ioapic_intr146),
412 &IDTVEC(ioapic_intr147),
413 &IDTVEC(ioapic_intr148),
414 &IDTVEC(ioapic_intr149),
415 &IDTVEC(ioapic_intr150),
416 &IDTVEC(ioapic_intr151),
417 &IDTVEC(ioapic_intr152),
418 &IDTVEC(ioapic_intr153),
419 &IDTVEC(ioapic_intr154),
420 &IDTVEC(ioapic_intr155),
421 &IDTVEC(ioapic_intr156),
422 &IDTVEC(ioapic_intr157),
423 &IDTVEC(ioapic_intr158),
424 &IDTVEC(ioapic_intr159),
425 &IDTVEC(ioapic_intr160),
426 &IDTVEC(ioapic_intr161),
427 &IDTVEC(ioapic_intr162),
428 &IDTVEC(ioapic_intr163),
429 &IDTVEC(ioapic_intr164),
430 &IDTVEC(ioapic_intr165),
431 &IDTVEC(ioapic_intr166),
432 &IDTVEC(ioapic_intr167),
433 &IDTVEC(ioapic_intr168),
434 &IDTVEC(ioapic_intr169),
435 &IDTVEC(ioapic_intr170),
436 &IDTVEC(ioapic_intr171),
437 &IDTVEC(ioapic_intr172),
438 &IDTVEC(ioapic_intr173),
439 &IDTVEC(ioapic_intr174),
440 &IDTVEC(ioapic_intr175),
441 &IDTVEC(ioapic_intr176),
442 &IDTVEC(ioapic_intr177),
443 &IDTVEC(ioapic_intr178),
444 &IDTVEC(ioapic_intr179),
445 &IDTVEC(ioapic_intr180),
446 &IDTVEC(ioapic_intr181),
447 &IDTVEC(ioapic_intr182),
448 &IDTVEC(ioapic_intr183),
449 &IDTVEC(ioapic_intr184),
450 &IDTVEC(ioapic_intr185),
451 &IDTVEC(ioapic_intr186),
452 &IDTVEC(ioapic_intr187),
453 &IDTVEC(ioapic_intr188),
454 &IDTVEC(ioapic_intr189),
455 &IDTVEC(ioapic_intr190),
456 &IDTVEC(ioapic_intr191)
c571da4a 457};
c8fe38ae 458
474ba684
SZ		 459#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
460
a3dd9120
SZ		 461static struct ioapic_irqmap {
462 int im_type; /* IOAPIC_IMT_ */
463 enum intr_trigger im_trig;
f6915355 464 enum intr_polarity im_pola;
a3dd9120 465 int im_gsi;
d1ae7328 466 uint32_t im_flags; /* IOAPIC_IMF_ */
6f072945 467} ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
a3dd9120
SZ		 468
469#define IOAPIC_IMT_UNUSED 0
470#define IOAPIC_IMT_RESERVED 1
471#define IOAPIC_IMT_LINE 2
474ba684 472#define IOAPIC_IMT_SYSCALL 3
a3dd9120 473
981239a7
SZ		 474#define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \
475 (map)->im_type != IOAPIC_IMT_SYSCALL)
476
d1ae7328
SZ		 477#define IOAPIC_IMF_CONF 0x1
478
9e0e3f85
SZ		 479extern void IOAPIC_INTREN(int);
480extern void IOAPIC_INTRDIS(int);
481
85bcaa51
SZ		 482extern int imcr_present;
483
35b2edcb
SZ		 484static void ioapic_abi_intr_enable(int);
485static void ioapic_abi_intr_disable(int);
f416026e
SZ		 486static void ioapic_abi_intr_setup(int, int);
487static void ioapic_abi_intr_teardown(int);
aea76754
SZ		 488static void ioapic_abi_intr_config(int,
489 enum intr_trigger, enum intr_polarity);
a05c798c 490static int ioapic_abi_intr_cpuid(int);
35b2edcb 491
aea76754
SZ		 492static void ioapic_abi_finalize(void);
493static void ioapic_abi_cleanup(void);
494static void ioapic_abi_setdefault(void);
495static void ioapic_abi_stabilize(void);
496static void ioapic_abi_initmap(void);
981239a7 497static void ioapic_abi_rman_setup(struct rman *);
9e0e3f85 498
95874ffd
SZ		 499static int ioapic_abi_gsi_cpuid(int, int);
500
9e0e3f85
SZ		 501struct machintr_abi MachIntrABI_IOAPIC = {
502 MACHINTR_IOAPIC,
35b2edcb
SZ		 503 .intr_disable = ioapic_abi_intr_disable,
504 .intr_enable = ioapic_abi_intr_enable,
f416026e
SZ		 505 .intr_setup = ioapic_abi_intr_setup,
506 .intr_teardown = ioapic_abi_intr_teardown,
aea76754 507 .intr_config = ioapic_abi_intr_config,
a05c798c 508 .intr_cpuid = ioapic_abi_intr_cpuid,
35b2edcb 509
aea76754
SZ		 510 .finalize = ioapic_abi_finalize,
511 .cleanup = ioapic_abi_cleanup,
512 .setdefault = ioapic_abi_setdefault,
513 .stabilize = ioapic_abi_stabilize,
981239a7
SZ		 514 .initmap = ioapic_abi_initmap,
515 .rman_setup = ioapic_abi_rman_setup
c8fe38ae
MD		 516};
517
6b809ec7 518static int ioapic_abi_extint_irq = -1;
bf2e6ffb 519static int ioapic_abi_line_irq_max;
2b195d6a 520static int ioapic_abi_gsi_balance;
6b809ec7 521
5ac5ccd2 522struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
566d27d4
SZ		 523
524static void
35b2edcb 525ioapic_abi_intr_enable(int irq)
566d27d4 526{
aef690c8
SZ		 527 const struct ioapic_irqmap *map;
528
529 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
530 ("ioapic enable, invalid irq %d\n", irq));
531
532 map = &ioapic_irqmaps[mycpuid][irq];
533 KASSERT(IOAPIC_IMT_ISHWI(map),
534 ("ioapic enable, not hwi irq %d, type %d, cpu%d\n",
535 irq, map->im_type, mycpuid));
536 if (map->im_type != IOAPIC_IMT_LINE) {
537 kprintf("ioapic enable, irq %d cpu%d not LINE\n",
538 irq, mycpuid);
566d27d4
SZ		 539 return;
540 }
aef690c8 541
566d27d4
SZ		 542 IOAPIC_INTREN(irq);
543}
544
545static void
35b2edcb 546ioapic_abi_intr_disable(int irq)
566d27d4 547{
aef690c8
SZ		 548 const struct ioapic_irqmap *map;
549
550 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
551 ("ioapic disable, invalid irq %d\n", irq));
552
553 map = &ioapic_irqmaps[mycpuid][irq];
554 KASSERT(IOAPIC_IMT_ISHWI(map),
555 ("ioapic disable, not hwi irq %d, type %d, cpu%d\n",
556 irq, map->im_type, mycpuid));
557 if (map->im_type != IOAPIC_IMT_LINE) {
558 kprintf("ioapic disable, irq %d cpu%d not LINE\n",
559 irq, mycpuid);
566d27d4
SZ		 560 return;
561 }
aef690c8 562
566d27d4
SZ		 563 IOAPIC_INTRDIS(irq);
564}
565
c8fe38ae 566static void
aea76754 567ioapic_abi_finalize(void)
c8fe38ae 568{
e0918665 569 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 570 KKASSERT(ioapic_enable);
10db3cc6 571
339478ac
SZ		 572 /*
573 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 574 * from the BSP.
339478ac 575 */
9d758cc4 576 if (imcr_present) {
339478ac
SZ		 577 outb(0x22, 0x70); /* select IMCR */
578 outb(0x23, 0x01); /* disconnect 8259 */
579 }
c8fe38ae
MD		 580}
581
582/*
583 * This routine is called after physical interrupts are enabled but before
584 * the critical section is released. We need to clean out any interrupts
585 * that had already been posted to the cpu.
586 */
587static void
aea76754 588ioapic_abi_cleanup(void)
c8fe38ae 589{
9611ff20 590 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
c8fe38ae
MD		 591}
592
7bf5fa56
SZ		 593/* Must never be called */
594static void
aea76754 595ioapic_abi_stabilize(void)
7bf5fa56
SZ		 596{
597 panic("ioapic_stabilize is called\n");
598}
599
f416026e
SZ		 600static void
601ioapic_abi_intr_setup(int intr, int flags)
c8fe38ae 602{
f416026e 603 int vector, select;
339478ac 604 uint32_t value;
7bf5fa56 605 register_t ef;
c8fe38ae 606
f416026e
SZ		 607 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
608 intr != IOAPIC_HWI_SYSCALL);
609 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
610
611 ef = read_rflags();
612 cpu_disable_intr();
613
614 vector = IDT_OFFSET + intr;
f416026e
SZ		 615
616 /*
617 * Now reprogram the vector in the IO APIC. In order to avoid
618 * losing an EOI for a level interrupt, which is vector based,
619 * make sure that the IO APIC is programmed for edge-triggering
620 * first, then reprogrammed with the new vector. This should
621 * clear the IRR bit.
622 */
623 imen_lock();
624
625 select = ioapic_irqs[intr].io_idx;
626 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
627 value |= IOART_INTMSET;
628
629 ioapic_write(ioapic_irqs[intr].io_addr, select,
630 (value & ~APIC_TRIGMOD_MASK));
631 ioapic_write(ioapic_irqs[intr].io_addr, select,
632 (value & ~IOART_INTVEC) | vector);
633
634 imen_unlock();
635
35b2edcb 636 machintr_intr_enable(intr);
c8fe38ae 637
f416026e
SZ		 638 write_rflags(ef);
639}
640
641static void
642ioapic_abi_intr_teardown(int intr)
643{
644 int vector, select;
645 uint32_t value;
646 register_t ef;
647
648 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
649 intr != IOAPIC_HWI_SYSCALL);
650 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
5ac5ccd2 651
339478ac
SZ		 652 ef = read_rflags();
653 cpu_disable_intr();
f416026e
SZ		 654
655 /*
656 * Teardown an interrupt vector. The vector should already be
657 * installed in the cpu's IDT, but make sure.
658 */
35b2edcb 659 machintr_intr_disable(intr);
f416026e
SZ		 660
661 vector = IDT_OFFSET + intr;
f416026e
SZ		 662
663 /*
664 * In order to avoid losing an EOI for a level interrupt, which
665 * is vector based, make sure that the IO APIC is programmed for
666 * edge-triggering first, then reprogrammed with the new vector.
667 * This should clear the IRR bit.
668 */
669 imen_lock();
670
671 select = ioapic_irqs[intr].io_idx;
672 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
673
674 ioapic_write(ioapic_irqs[intr].io_addr, select,
675 (value & ~APIC_TRIGMOD_MASK));
676 ioapic_write(ioapic_irqs[intr].io_addr, select,
677 (value & ~IOART_INTVEC) | vector);
678
679 imen_unlock();
c8fe38ae 680
339478ac 681 write_rflags(ef);
339478ac 682}
c8fe38ae 683
10db3cc6 684static void
aea76754 685ioapic_abi_setdefault(void)
10db3cc6
SZ		 686{
687 int intr;
688
9e0e3f85 689 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 690 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 691 continue;
9e0e3f85 692 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
10db3cc6
SZ		 693 SEL_KPL, 0);
694 }
695}
696
a3dd9120 697static void
aea76754 698ioapic_abi_initmap(void)
a3dd9120 699{
6f072945 700 int cpu;
a3dd9120 701
2b195d6a
SZ		 702 kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
703
6f072945
SZ		 704 /*
705 * NOTE: ncpus is not ready yet
706 */
707 for (cpu = 0; cpu < MAXCPU; ++cpu) {
708 int i;
709
710 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
711 ioapic_irqmaps[cpu][i].im_gsi = -1;
712 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
713 IOAPIC_IMT_SYSCALL;
714 }
a3dd9120
SZ		 715}
716
929c940f
SZ		 717void
718ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
719 enum intr_polarity pola)
720{
5ac5ccd2 721 struct ioapic_irqinfo *info;
929c940f
SZ		 722 struct ioapic_irqmap *map;
723 void *ioaddr;
95874ffd 724 int pin, cpuid;
929c940f
SZ		 725
726 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
727 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ		 728
729 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
bf2e6ffb
SZ		 730 if (irq > ioapic_abi_line_irq_max)
731 ioapic_abi_line_irq_max = irq;
732
6f072945
SZ		 733 cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
734
735 map = &ioapic_irqmaps[cpuid][irq];
929c940f
SZ		 736
737 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
738 map->im_type = IOAPIC_IMT_LINE;
739
740 map->im_gsi = gsi;
741 map->im_trig = trig;
742 map->im_pola = pola;
743
744 if (bootverbose) {
4ecd5d4d
SZ		 745 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
746 irq, map->im_gsi,
747 intr_str_trigger(map->im_trig),
748 intr_str_polarity(map->im_pola));
929c940f
SZ		 749 }
750
d1ae7328
SZ		 751 pin = ioapic_gsi_pin(map->im_gsi);
752 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 753
5ac5ccd2 754 info = &ioapic_irqs[irq];
929c940f 755
7bceaa10
SZ		 756 imen_lock();
757
5ac5ccd2
SZ		 758 info->io_addr = ioaddr;
759 info->io_idx = IOAPIC_REDTBL + (2 * pin);
760 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 761 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 762 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
SZ		 763
764 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 765 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ		 766
767 imen_unlock();
d1ae7328
SZ		 768}
769
4a913811
SZ		 770void
771ioapic_abi_fixup_irqmap(void)
772{
6f072945
SZ		 773 int cpu;
774
775 for (cpu = 0; cpu < ncpus; ++cpu) {
776 int i;
4a913811 777
6f072945
SZ		 778 for (i = 0; i < ISA_IRQ_CNT; ++i) {
779 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
4a913811 780
6f072945
SZ		 781 if (map->im_type == IOAPIC_IMT_UNUSED) {
782 map->im_type = IOAPIC_IMT_RESERVED;
783 if (bootverbose) {
784 kprintf("IOAPIC: "
785 "cpu%d irq %d reserved\n", cpu, i);
786 }
787 }
4a913811
SZ		 788 }
789 }
6f072945 790
bf2e6ffb
SZ		 791 ioapic_abi_line_irq_max += 1;
792 if (bootverbose)
793 kprintf("IOAPIC: line irq max %d\n", ioapic_abi_line_irq_max);
4a913811
SZ		 794}
795
e90e7ac4
SZ		 796int
797ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
798{
6f072945 799 int cpu;
e90e7ac4
SZ		 800
801 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
802 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4 803
6f072945
SZ		 804 for (cpu = 0; cpu < ncpus; ++cpu) {
805 int irq;
e90e7ac4 806
6f072945
SZ		 807 for (irq = 0; irq < ioapic_abi_line_irq_max; ++irq) {
808 const struct ioapic_irqmap *map =
809 &ioapic_irqmaps[cpu][irq];
e90e7ac4 810
6f072945
SZ		 811 if (map->im_gsi == gsi) {
812 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
813
814 if (map->im_flags & IOAPIC_IMF_CONF) {
815 if (map->im_trig != trig ||
816 map->im_pola != pola)
817 return -1;
818 }
819 return irq;
e90e7ac4 820 }
e90e7ac4
SZ		 821 }
822 }
823 return -1;
824}
825
826int
827ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
828{
6f072945 829 int cpu;
e90e7ac4
SZ		 830
831 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
832 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4 833
6f072945 834 if (irq < 0 || irq >= ioapic_abi_line_irq_max)
e90e7ac4 835 return -1;
e90e7ac4 836
6f072945
SZ		 837 for (cpu = 0; cpu < ncpus; ++cpu) {
838 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
e90e7ac4 839
6f072945
SZ		 840 if (map->im_type == IOAPIC_IMT_LINE) {
841 if (map->im_flags & IOAPIC_IMF_CONF) {
842 if (map->im_trig != trig ||
843 map->im_pola != pola)
844 return -1;
845 }
846 return irq;
847 }
e90e7ac4 848 }
6f072945 849 return -1;
e90e7ac4
SZ		 850}
851
d1ae7328 852static void
aea76754 853ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
d1ae7328 854{
5ac5ccd2 855 struct ioapic_irqinfo *info;
6f072945 856 struct ioapic_irqmap *map = NULL;
d1ae7328 857 void *ioaddr;
95874ffd 858 int pin, cpuid;
d1ae7328 859
d1ae7328
SZ		 860 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
861 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328 862
6f072945
SZ		 863 KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
864 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
865 map = &ioapic_irqmaps[cpuid][irq];
866 if (map->im_type == IOAPIC_IMT_LINE)
867 break;
868 }
869 KKASSERT(cpuid < ncpus);
d1ae7328 870
7962296e 871#ifdef notyet
d1ae7328
SZ		 872 if (map->im_flags & IOAPIC_IMF_CONF) {
873 if (trig != map->im_trig) {
4ecd5d4d
SZ		 874 panic("ioapic_intr_config: trig %s -> %s\n",
875 intr_str_trigger(map->im_trig),
876 intr_str_trigger(trig));
d1ae7328
SZ		 877 }
878 if (pola != map->im_pola) {
879 panic("ioapic_intr_config: pola %s -> %s\n",
4ecd5d4d
SZ		 880 intr_str_polarity(map->im_pola),
881 intr_str_polarity(pola));
d1ae7328
SZ		 882 }
883 return;
884 }
7962296e 885#endif
d1ae7328
SZ		 886 map->im_flags |= IOAPIC_IMF_CONF;
887
888 if (trig == map->im_trig && pola == map->im_pola)
889 return;
890
891 if (bootverbose) {
4ecd5d4d
SZ		 892 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
893 irq, map->im_gsi,
894 intr_str_trigger(map->im_trig),
895 intr_str_polarity(map->im_pola),
896 intr_str_trigger(trig),
897 intr_str_polarity(pola));
d1ae7328 898 }
d1ae7328
SZ		 899 map->im_trig = trig;
900 map->im_pola = pola;
901
902 pin = ioapic_gsi_pin(map->im_gsi);
903 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
904
5ac5ccd2 905 info = &ioapic_irqs[irq];
d1ae7328 906
7bceaa10
SZ		 907 imen_lock();
908
5ac5ccd2 909 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 910 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 911 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 912
ecec8ddc 913 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 914 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ		 915
916 imen_unlock();
929c940f
SZ		 917}
918
6b809ec7
SZ		 919int
920ioapic_abi_extint_irqmap(int irq)
921{
5ac5ccd2 922 struct ioapic_irqinfo *info;
6b809ec7
SZ		 923 struct ioapic_irqmap *map;
924 void *ioaddr;
925 int pin, error, vec;
926
95874ffd
SZ		 927 /* XXX only irq0 is allowed */
928 KKASSERT(irq == 0);
929
6b809ec7
SZ		 930 vec = IDT_OFFSET + irq;
931
932 if (ioapic_abi_extint_irq == irq)
933 return 0;
934 else if (ioapic_abi_extint_irq >= 0)
935 return EEXIST;
936
937 error = icu_ioapic_extint(irq, vec);
938 if (error)
939 return error;
940
6f072945
SZ		 941 /* ExtINT is always targeted to cpu0 */
942 map = &ioapic_irqmaps[0][irq];
6b809ec7
SZ		 943
944 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
945 map->im_type == IOAPIC_IMT_LINE);
946 if (map->im_type == IOAPIC_IMT_LINE) {
947 if (map->im_flags & IOAPIC_IMF_CONF)
948 return EEXIST;
949 }
950 ioapic_abi_extint_irq = irq;
951
952 map->im_type = IOAPIC_IMT_LINE;
953 map->im_trig = INTR_TRIGGER_EDGE;
954 map->im_pola = INTR_POLARITY_HIGH;
955 map->im_flags = IOAPIC_IMF_CONF;
956
957 map->im_gsi = ioapic_extpin_gsi();
958 KKASSERT(map->im_gsi >= 0);
959
960 if (bootverbose) {
4ecd5d4d
SZ		 961 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
962 irq, map->im_gsi,
963 intr_str_trigger(map->im_trig),
964 intr_str_polarity(map->im_pola));
6b809ec7
SZ		 965 }
966
967 pin = ioapic_gsi_pin(map->im_gsi);
968 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
969
5ac5ccd2 970 info = &ioapic_irqs[irq];
6b809ec7
SZ		 971
972 imen_lock();
973
5ac5ccd2
SZ		 974 info->io_addr = ioaddr;
975 info->io_idx = IOAPIC_REDTBL + (2 * pin);
976 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ		 977
978 ioapic_extpin_setup(ioaddr, pin, vec);
979
980 imen_unlock();
981
982 return 0;
983}
a05c798c
SZ		 984
985static int
95874ffd 986ioapic_abi_intr_cpuid(int irq)
a05c798c 987{
6f072945
SZ		 988 const struct ioapic_irqmap *map = NULL;
989 int cpuid;
95874ffd 990
6f072945 991 KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
95874ffd 992
6f072945
SZ		 993 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
994 map = &ioapic_irqmaps[cpuid][irq];
995 if (map->im_type == IOAPIC_IMT_LINE)
996 return cpuid;
95874ffd
SZ		 997 }
998
6f072945
SZ		 999 /* XXX some drivers tries to peek at reserved IRQs */
1000 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1001 map = &ioapic_irqmaps[cpuid][irq];
1002 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1003 }
1004 return 0;
95874ffd
SZ		 1005}
1006
1007static int
1008ioapic_abi_gsi_cpuid(int irq, int gsi)
1009{
1010 char envpath[32];
1011 int cpuid = -1;
1012
1013 KKASSERT(gsi >= 0);
1014
1015 if (irq == 0 || gsi == 0) {
621d2ccf
SZ		 1016 if (bootverbose) {
1017 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1018 irq, gsi);
1019 }
95874ffd
SZ		 1020 return 0;
1021 }
1022
1023 if (irq == acpi_sci_irqno()) {
621d2ccf
SZ		 1024 if (bootverbose) {
1025 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1026 irq, gsi);
1027 }
95874ffd
SZ		 1028 return 0;
1029 }
1030
1031 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1032 kgetenv_int(envpath, &cpuid);
1033
1034 if (cpuid < 0) {
b8dfb6b1
SZ		 1035 if (!ioapic_abi_gsi_balance) {
1036 if (bootverbose) {
1037 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1038 "(fixed)\n", irq, gsi);
1039 }
1040 return 0;
1041 }
1042
95874ffd 1043 cpuid = gsi % ncpus;
621d2ccf
SZ		 1044 if (bootverbose) {
1045 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1046 irq, gsi, cpuid);
1047 }
95874ffd
SZ		 1048 } else if (cpuid >= ncpus) {
1049 cpuid = ncpus - 1;
621d2ccf
SZ		 1050 if (bootverbose) {
1051 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1052 irq, gsi, cpuid);
1053 }
95874ffd 1054 } else {
621d2ccf
SZ		 1055 if (bootverbose) {
1056 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1057 irq, gsi, cpuid);
1058 }
95874ffd
SZ		 1059 }
1060 return cpuid;
a05c798c 1061}
981239a7
SZ		 1062
1063static void
1064ioapic_abi_rman_setup(struct rman *rm)
1065{
1066 int start, end, i;
1067
1068 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1069 ("invalid rman cpuid %d", rm->rm_cpuid));
1070
1071 start = end = -1;
1072 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1073 const struct ioapic_irqmap *map =
1074 &ioapic_irqmaps[rm->rm_cpuid][i];
1075
1076 if (start < 0) {
1077 if (IOAPIC_IMT_ISHWI(map))
1078 start = end = i;
1079 } else {
1080 if (IOAPIC_IMT_ISHWI(map)) {
1081 end = i;
1082 } else {
1083 KKASSERT(end >= 0);
1084 if (bootverbose) {
1085 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1086 rm->rm_cpuid, start, end);
1087 }
1088 if (rman_manage_region(rm, start, end)) {
1089 panic("rman_manage_region"
1090 "(cpu%d %d - %d)", rm->rm_cpuid,
1091 start, end);
1092 }
1093 start = end = -1;
1094 }
1095 }
1096 }
1097 if (start >= 0) {
1098 KKASSERT(end >= 0);
1099 if (bootverbose) {
1100 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1101 rm->rm_cpuid, start, end);
1102 }
1103 if (rman_manage_region(rm, start, end)) {
1104 panic("rman_manage_region(cpu%d %d - %d)",
1105 rm->rm_cpuid, start, end);
1106 }
1107 }
1108}
DragonFly Project GIT Source repo