Change the kernel dev_t, representing a pointer to a specinfo structure,
[dragonfly.git] / sys / bus / firewire / fwohci.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
16 *
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
78748771 34 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.72 2004/01/22 14:41:17 simokawa Exp $
984263bc 35 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.1.2.19 2003/05/01 06:24:37 simokawa Exp $
b13267a5 36 * $DragonFly: src/sys/bus/firewire/fwohci.c,v 1.13 2006/09/10 01:26:32 dillon Exp $
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37 */
38
39#define ATRQ_CH 0
40#define ATRS_CH 1
41#define ARRQ_CH 2
42#define ARRS_CH 3
43#define ITX_CH 4
44#define IRX_CH 0x24
45
46#include <sys/param.h>
984263bc 47#include <sys/systm.h>
984263bc 48#include <sys/mbuf.h>
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49#include <sys/malloc.h>
50#include <sys/sockio.h>
51#include <sys/bus.h>
52#include <sys/kernel.h>
53#include <sys/conf.h>
fef8985e 54#include <sys/device.h>
984263bc 55#include <sys/endian.h>
4e01b467 56#include <sys/thread2.h>
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57
58#include <machine/bus.h>
984263bc 59
90dec0df 60#if defined(__DragonFly__) || __FreeBSD_version < 500000
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61#include <machine/clock.h> /* for DELAY() */
62#endif
984263bc 63
78748771 64#ifdef __DragonFly__
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65#include "firewire.h"
66#include "firewirereg.h"
67#include "fwdma.h"
68#include "fwohcireg.h"
69#include "fwohcivar.h"
70#include "firewire_phy.h"
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71#else
72#include <dev/firewire/firewire.h>
73#include <dev/firewire/firewirereg.h>
74#include <dev/firewire/fwdma.h>
75#include <dev/firewire/fwohcireg.h>
76#include <dev/firewire/fwohcivar.h>
77#include <dev/firewire/firewire_phy.h>
78#endif
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79
80#undef OHCI_DEBUG
81
82static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
83 "STOR","LOAD","NOP ","STOP",};
84
85static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
86 "UNDEF","REG","SYS","DEV"};
87static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
88char fwohcicode[32][0x20]={
89 "No stat","Undef","long","miss Ack err",
90 "underrun","overrun","desc err", "data read err",
91 "data write err","bus reset","timeout","tcode err",
92 "Undef","Undef","unknown event","flushed",
93 "Undef","ack complete","ack pend","Undef",
94 "ack busy_X","ack busy_A","ack busy_B","Undef",
95 "Undef","Undef","Undef","ack tardy",
96 "Undef","ack data_err","ack type_err",""};
97
78748771
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98#define MAX_SPEED 3
99extern char *linkspeed[];
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100u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
101
102static struct tcode_info tinfo[] = {
103/* hdr_len block flag*/
104/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
105/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
106/* 2 WRES */ {12, FWTI_RES},
107/* 3 XXX */ { 0, 0},
108/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
109/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
110/* 6 RRESQ */ {16, FWTI_RES},
111/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
112/* 8 CYCS */ { 0, 0},
113/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
114/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
115/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
116/* c XXX */ { 0, 0},
117/* d XXX */ { 0, 0},
118/* e PHY */ {12, FWTI_REQ},
119/* f XXX */ { 0, 0}
120};
121
122#define OHCI_WRITE_SIGMASK 0xffff0000
123#define OHCI_READ_SIGMASK 0xffff0000
124
125#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
126#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
127
330ca0ab
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128static void fwohci_ibr (struct firewire_comm *);
129static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
130static void fwohci_db_free (struct fwohci_dbch *);
131static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
132static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
133static void fwohci_start_atq (struct firewire_comm *);
134static void fwohci_start_ats (struct firewire_comm *);
135static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
136static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t);
137static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t);
138static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
139static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
140static int fwohci_irx_enable (struct firewire_comm *, int);
141static int fwohci_irx_disable (struct firewire_comm *, int);
984263bc 142#if BYTE_ORDER == BIG_ENDIAN
330ca0ab 143static void fwohci_irx_post (struct firewire_comm *, u_int32_t *);
984263bc 144#endif
330ca0ab
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145static int fwohci_itxbuf_enable (struct firewire_comm *, int);
146static int fwohci_itx_disable (struct firewire_comm *, int);
147static void fwohci_timeout (void *);
330ca0ab
RG
148static void fwohci_set_intr (struct firewire_comm *, int);
149
150static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
151static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
152static void dump_db (struct fwohci_softc *, u_int32_t);
78748771 153static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t);
330ca0ab
RG
154static void dump_dma (struct fwohci_softc *, u_int32_t);
155static u_int32_t fwohci_cyctimer (struct firewire_comm *);
156static void fwohci_rbuf_update (struct fwohci_softc *, int);
157static void fwohci_tbuf_update (struct fwohci_softc *, int);
158void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
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159#if FWOHCI_TASKQUEUE
160static void fwohci_complete(void *, int);
161#endif
162
163/*
164 * memory allocated for DMA programs
165 */
166#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
167
984263bc 168#define NDB FWMAXQUEUE
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169
170#define OHCI_VERSION 0x00
171#define OHCI_ATRETRY 0x08
172#define OHCI_CROMHDR 0x18
173#define OHCI_BUS_OPT 0x20
174#define OHCI_BUSIRMC (1 << 31)
175#define OHCI_BUSCMC (1 << 30)
176#define OHCI_BUSISC (1 << 29)
177#define OHCI_BUSBMC (1 << 28)
178#define OHCI_BUSPMC (1 << 27)
179#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
180 OHCI_BUSBMC | OHCI_BUSPMC
181
182#define OHCI_EUID_HI 0x24
183#define OHCI_EUID_LO 0x28
184
185#define OHCI_CROMPTR 0x34
186#define OHCI_HCCCTL 0x50
187#define OHCI_HCCCTLCLR 0x54
188#define OHCI_AREQHI 0x100
189#define OHCI_AREQHICLR 0x104
190#define OHCI_AREQLO 0x108
191#define OHCI_AREQLOCLR 0x10c
192#define OHCI_PREQHI 0x110
193#define OHCI_PREQHICLR 0x114
194#define OHCI_PREQLO 0x118
195#define OHCI_PREQLOCLR 0x11c
196#define OHCI_PREQUPPER 0x120
197
198#define OHCI_SID_BUF 0x64
199#define OHCI_SID_CNT 0x68
200#define OHCI_SID_ERR (1 << 31)
201#define OHCI_SID_CNT_MASK 0xffc
202
203#define OHCI_IT_STAT 0x90
204#define OHCI_IT_STATCLR 0x94
205#define OHCI_IT_MASK 0x98
206#define OHCI_IT_MASKCLR 0x9c
207
208#define OHCI_IR_STAT 0xa0
209#define OHCI_IR_STATCLR 0xa4
210#define OHCI_IR_MASK 0xa8
211#define OHCI_IR_MASKCLR 0xac
212
213#define OHCI_LNKCTL 0xe0
214#define OHCI_LNKCTLCLR 0xe4
215
216#define OHCI_PHYACCESS 0xec
217#define OHCI_CYCLETIMER 0xf0
218
219#define OHCI_DMACTL(off) (off)
220#define OHCI_DMACTLCLR(off) (off + 4)
221#define OHCI_DMACMD(off) (off + 0xc)
222#define OHCI_DMAMATCH(off) (off + 0x10)
223
224#define OHCI_ATQOFF 0x180
225#define OHCI_ATQCTL OHCI_ATQOFF
226#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
227#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
228#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
229
230#define OHCI_ATSOFF 0x1a0
231#define OHCI_ATSCTL OHCI_ATSOFF
232#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
233#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
234#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
235
236#define OHCI_ARQOFF 0x1c0
237#define OHCI_ARQCTL OHCI_ARQOFF
238#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
239#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
240#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
241
242#define OHCI_ARSOFF 0x1e0
243#define OHCI_ARSCTL OHCI_ARSOFF
244#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
245#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
246#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
247
248#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
249#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
250#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
251#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
252
253#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
254#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
255#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
256#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
257#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
258
259d_ioctl_t fwohci_ioctl;
260
261/*
262 * Communication with PHY device
263 */
264static u_int32_t
265fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
266{
267 u_int32_t fun;
268
269 addr &= 0xf;
270 data &= 0xff;
271
272 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
273 OWRITE(sc, OHCI_PHYACCESS, fun);
274 DELAY(100);
275
276 return(fwphy_rddata( sc, addr));
277}
278
279static u_int32_t
280fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
281{
282 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
283 int i;
284 u_int32_t bm;
285
286#define OHCI_CSR_DATA 0x0c
287#define OHCI_CSR_COMP 0x10
288#define OHCI_CSR_CONT 0x14
289#define OHCI_BUS_MANAGER_ID 0
290
291 OWRITE(sc, OHCI_CSR_DATA, node);
292 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
293 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
294 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
295 DELAY(10);
296 bm = OREAD(sc, OHCI_CSR_DATA);
297 if((bm & 0x3f) == 0x3f)
298 bm = node;
299 if (bootverbose)
300 device_printf(sc->fc.dev,
301 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
302
303 return(bm);
304}
305
306static u_int32_t
307fwphy_rddata(struct fwohci_softc *sc, u_int addr)
308{
309 u_int32_t fun, stat;
310 u_int i, retry = 0;
311
312 addr &= 0xf;
313#define MAX_RETRY 100
314again:
315 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
316 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
317 OWRITE(sc, OHCI_PHYACCESS, fun);
318 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
319 fun = OREAD(sc, OHCI_PHYACCESS);
320 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
321 break;
322 DELAY(100);
323 }
324 if(i >= MAX_RETRY) {
325 if (bootverbose)
326 device_printf(sc->fc.dev, "phy read failed(1).\n");
327 if (++retry < MAX_RETRY) {
328 DELAY(100);
329 goto again;
330 }
331 }
332 /* Make sure that SCLK is started */
333 stat = OREAD(sc, FWOHCI_INTSTAT);
334 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
335 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
336 if (bootverbose)
337 device_printf(sc->fc.dev, "phy read failed(2).\n");
338 if (++retry < MAX_RETRY) {
339 DELAY(100);
340 goto again;
341 }
342 }
343 if (bootverbose || retry >= MAX_RETRY)
344 device_printf(sc->fc.dev,
78748771 345 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
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346#undef MAX_RETRY
347 return((fun >> PHYDEV_RDDATA )& 0xff);
348}
349/* Device specific ioctl. */
350int
fef8985e 351fwohci_ioctl (struct dev_ioctl_args *ap)
984263bc 352{
b13267a5 353 cdev_t dev = ap->a_head.a_dev;
984263bc
MD
354 struct firewire_softc *sc;
355 struct fwohci_softc *fc;
356 int unit = DEV2UNIT(dev);
357 int err = 0;
fef8985e
MD
358 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) ap->a_data;
359 u_int32_t *dmach = (u_int32_t *) ap->a_data;
984263bc
MD
360
361 sc = devclass_get_softc(firewire_devclass, unit);
362 if(sc == NULL){
363 return(EINVAL);
364 }
365 fc = (struct fwohci_softc *)sc->fc;
366
fef8985e 367 if (!ap->a_data)
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MD
368 return(EINVAL);
369
fef8985e 370 switch (ap->a_cmd) {
984263bc
MD
371 case FWOHCI_WRREG:
372#define OHCI_MAX_REG 0x800
373 if(reg->addr <= OHCI_MAX_REG){
374 OWRITE(fc, reg->addr, reg->data);
375 reg->data = OREAD(fc, reg->addr);
376 }else{
377 err = EINVAL;
378 }
379 break;
380 case FWOHCI_RDREG:
381 if(reg->addr <= OHCI_MAX_REG){
382 reg->data = OREAD(fc, reg->addr);
383 }else{
384 err = EINVAL;
385 }
386 break;
387/* Read DMA descriptors for debug */
388 case DUMPDMA:
389 if(*dmach <= OHCI_MAX_DMA_CH ){
390 dump_dma(fc, *dmach);
391 dump_db(fc, *dmach);
392 }else{
393 err = EINVAL;
394 }
395 break;
78748771
JS
396/* Read/Write Phy registers */
397#define OHCI_MAX_PHY_REG 0xf
398 case FWOHCI_RDPHYREG:
399 if (reg->addr <= OHCI_MAX_PHY_REG)
400 reg->data = fwphy_rddata(fc, reg->addr);
401 else
402 err = EINVAL;
403 break;
404 case FWOHCI_WRPHYREG:
405 if (reg->addr <= OHCI_MAX_PHY_REG)
406 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
407 else
408 err = EINVAL;
409 break;
984263bc 410 default:
78748771 411 err = EINVAL;
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MD
412 break;
413 }
414 return err;
415}
416
417static int
418fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
419{
420 u_int32_t reg, reg2;
421 int e1394a = 1;
422/*
423 * probe PHY parameters
424 * 0. to prove PHY version, whether compliance of 1394a.
425 * 1. to probe maximum speed supported by the PHY and
426 * number of port supported by core-logic.
427 * It is not actually available port on your PC .
428 */
429 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
430 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
431
432 if((reg >> 5) != 7 ){
433 sc->fc.mode &= ~FWPHYASYST;
434 sc->fc.nport = reg & FW_PHY_NP;
435 sc->fc.speed = reg & FW_PHY_SPD >> 6;
436 if (sc->fc.speed > MAX_SPEED) {
437 device_printf(dev, "invalid speed %d (fixed to %d).\n",
438 sc->fc.speed, MAX_SPEED);
439 sc->fc.speed = MAX_SPEED;
440 }
441 device_printf(dev,
442 "Phy 1394 only %s, %d ports.\n",
443 linkspeed[sc->fc.speed], sc->fc.nport);
444 }else{
445 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
446 sc->fc.mode |= FWPHYASYST;
447 sc->fc.nport = reg & FW_PHY_NP;
448 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
449 if (sc->fc.speed > MAX_SPEED) {
450 device_printf(dev, "invalid speed %d (fixed to %d).\n",
451 sc->fc.speed, MAX_SPEED);
452 sc->fc.speed = MAX_SPEED;
453 }
454 device_printf(dev,
455 "Phy 1394a available %s, %d ports.\n",
456 linkspeed[sc->fc.speed], sc->fc.nport);
457
458 /* check programPhyEnable */
459 reg2 = fwphy_rddata(sc, 5);
460#if 0
461 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
462#else /* XXX force to enable 1394a */
463 if (e1394a) {
464#endif
465 if (bootverbose)
466 device_printf(dev,
467 "Enable 1394a Enhancements\n");
468 /* enable EAA EMC */
469 reg2 |= 0x03;
470 /* set aPhyEnhanceEnable */
471 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
472 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
473 } else {
474 /* for safe */
475 reg2 &= ~0x83;
476 }
477 reg2 = fwphy_wrdata(sc, 5, reg2);
478 }
479
480 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
481 if((reg >> 5) == 7 ){
482 reg = fwphy_rddata(sc, 4);
483 reg |= 1 << 6;
484 fwphy_wrdata(sc, 4, reg);
485 reg = fwphy_rddata(sc, 4);
486 }
487 return 0;
488}
489
490
491void
492fwohci_reset(struct fwohci_softc *sc, device_t dev)
493{
494 int i, max_rec, speed;
495 u_int32_t reg, reg2;
496 struct fwohcidb_tr *db_tr;
497
498 /* Disable interrupt */
499 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
500
501 /* Now stopping all DMA channel */
502 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
503 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
504 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
505 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
506
507 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
508 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
509 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
510 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
511 }
512
513 /* FLUSH FIFO and reset Transmitter/Reciever */
514 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
515 if (bootverbose)
516 device_printf(dev, "resetting OHCI...");
517 i = 0;
518 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
519 if (i++ > 100) break;
520 DELAY(1000);
521 }
522 if (bootverbose)
523 printf("done (loop=%d)\n", i);
524
525 /* Probe phy */
526 fwohci_probe_phy(sc, dev);
527
528 /* Probe link */
529 reg = OREAD(sc, OHCI_BUS_OPT);
530 reg2 = reg | OHCI_BUSFNC;
531 max_rec = (reg & 0x0000f000) >> 12;
532 speed = (reg & 0x00000007);
533 device_printf(dev, "Link %s, max_rec %d bytes.\n",
534 linkspeed[speed], MAXREC(max_rec));
535 /* XXX fix max_rec */
536 sc->fc.maxrec = sc->fc.speed + 8;
537 if (max_rec != sc->fc.maxrec) {
538 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
539 device_printf(dev, "max_rec %d -> %d\n",
540 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
541 }
542 if (bootverbose)
543 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
544 OWRITE(sc, OHCI_BUS_OPT, reg2);
545
546 /* Initialize registers */
547 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
548 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
549 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
550 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
551 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
552 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
984263bc
MD
553
554 /* Enable link */
555 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
556
557 /* Force to start async RX DMA */
558 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
559 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
560 fwohci_rx_enable(sc, &sc->arrq);
561 fwohci_rx_enable(sc, &sc->arrs);
562
563 /* Initialize async TX */
564 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
565 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
78748771 566
984263bc
MD
567 /* AT Retries */
568 OWRITE(sc, FWOHCI_RETRY,
569 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
570 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
78748771
JS
571
572 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
573 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
574 sc->atrq.bottom = sc->atrq.top;
575 sc->atrs.bottom = sc->atrs.top;
576
984263bc
MD
577 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
578 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
579 db_tr->xfer = NULL;
580 }
581 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
582 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
583 db_tr->xfer = NULL;
584 }
585
586
587 /* Enable interrupt */
588 OWRITE(sc, FWOHCI_INTMASK,
589 OHCI_INT_ERR | OHCI_INT_PHY_SID
590 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
591 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
592 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
593 fwohci_set_intr(&sc->fc, 1);
594
595}
596
597int
598fwohci_init(struct fwohci_softc *sc, device_t dev)
599{
78748771 600 int i, mver;
984263bc
MD
601 u_int32_t reg;
602 u_int8_t ui[8];
603
604#if FWOHCI_TASKQUEUE
605 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
606#endif
607
78748771 608/* OHCI version */
984263bc 609 reg = OREAD(sc, OHCI_VERSION);
78748771 610 mver = (reg >> 16) & 0xff;
984263bc 611 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
78748771
JS
612 mver, reg & 0xff, (reg>>24) & 1);
613 if (mver < 1 || mver > 9) {
614 device_printf(dev, "invalid OHCI version\n");
615 return (ENXIO);
616 }
984263bc
MD
617
618/* Available Isochrounous DMA channel probe */
619 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
620 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
621 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
622 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
623 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
624 for (i = 0; i < 0x20; i++)
625 if ((reg & (1 << i)) == 0)
626 break;
627 sc->fc.nisodma = i;
628 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
78748771
JS
629 if (i == 0)
630 return (ENXIO);
984263bc
MD
631
632 sc->fc.arq = &sc->arrq.xferq;
633 sc->fc.ars = &sc->arrs.xferq;
634 sc->fc.atq = &sc->atrq.xferq;
635 sc->fc.ats = &sc->atrs.xferq;
636
637 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
638 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
639 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
640 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
641
642 sc->arrq.xferq.start = NULL;
643 sc->arrs.xferq.start = NULL;
644 sc->atrq.xferq.start = fwohci_start_atq;
645 sc->atrs.xferq.start = fwohci_start_ats;
646
647 sc->arrq.xferq.buf = NULL;
648 sc->arrs.xferq.buf = NULL;
649 sc->atrq.xferq.buf = NULL;
650 sc->atrs.xferq.buf = NULL;
651
78748771
JS
652 sc->arrq.xferq.dmach = -1;
653 sc->arrs.xferq.dmach = -1;
654 sc->atrq.xferq.dmach = -1;
655 sc->atrs.xferq.dmach = -1;
656
984263bc
MD
657 sc->arrq.ndesc = 1;
658 sc->arrs.ndesc = 1;
659 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
660 sc->atrs.ndesc = 2;
661
662 sc->arrq.ndb = NDB;
663 sc->arrs.ndb = NDB / 2;
664 sc->atrq.ndb = NDB;
665 sc->atrs.ndb = NDB / 2;
666
667 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
668 sc->fc.it[i] = &sc->it[i].xferq;
669 sc->fc.ir[i] = &sc->ir[i].xferq;
78748771
JS
670 sc->it[i].xferq.dmach = i;
671 sc->ir[i].xferq.dmach = i;
984263bc
MD
672 sc->it[i].ndb = 0;
673 sc->ir[i].ndb = 0;
674 }
675
676 sc->fc.tcode = tinfo;
677 sc->fc.dev = dev;
678
679 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
680 &sc->crom_dma, BUS_DMA_WAITOK);
681 if(sc->fc.config_rom == NULL){
682 device_printf(dev, "config_rom alloc failed.");
683 return ENOMEM;
684 }
685
78748771
JS
686#if 0
687 bzero(&sc->fc.config_rom[0], CROMSIZE);
984263bc
MD
688 sc->fc.config_rom[1] = 0x31333934;
689 sc->fc.config_rom[2] = 0xf000a002;
690 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
691 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
692 sc->fc.config_rom[5] = 0;
693 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
694
695 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
696#endif
697
698
699/* SID recieve buffer must allign 2^11 */
700#define OHCI_SIDSIZE (1 << 11)
701 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
702 &sc->sid_dma, BUS_DMA_WAITOK);
703 if (sc->sid_buf == NULL) {
704 device_printf(dev, "sid_buf alloc failed.");
705 return ENOMEM;
706 }
707
708 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
709 &sc->dummy_dma, BUS_DMA_WAITOK);
710
711 if (sc->dummy_dma.v_addr == NULL) {
712 device_printf(dev, "dummy_dma alloc failed.");
713 return ENOMEM;
714 }
715
716 fwohci_db_init(sc, &sc->arrq);
717 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
718 return ENOMEM;
719
720 fwohci_db_init(sc, &sc->arrs);
721 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
722 return ENOMEM;
723
724 fwohci_db_init(sc, &sc->atrq);
725 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
726 return ENOMEM;
727
728 fwohci_db_init(sc, &sc->atrs);
729 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
730 return ENOMEM;
731
732 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
733 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
734 for( i = 0 ; i < 8 ; i ++)
735 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
736 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
737 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
738
739 sc->fc.ioctl = fwohci_ioctl;
740 sc->fc.cyctimer = fwohci_cyctimer;
741 sc->fc.set_bmr = fwohci_set_bus_manager;
742 sc->fc.ibr = fwohci_ibr;
743 sc->fc.irx_enable = fwohci_irx_enable;
744 sc->fc.irx_disable = fwohci_irx_disable;
745
746 sc->fc.itx_enable = fwohci_itxbuf_enable;
747 sc->fc.itx_disable = fwohci_itx_disable;
748#if BYTE_ORDER == BIG_ENDIAN
749 sc->fc.irx_post = fwohci_irx_post;
750#else
751 sc->fc.irx_post = NULL;
752#endif
753 sc->fc.itx_post = NULL;
754 sc->fc.timeout = fwohci_timeout;
755 sc->fc.poll = fwohci_poll;
756 sc->fc.set_intr = fwohci_set_intr;
757
758 sc->intmask = sc->irstat = sc->itstat = 0;
759
760 fw_init(&sc->fc);
761 fwohci_reset(sc, dev);
762
763 return 0;
764}
765
766void
767fwohci_timeout(void *arg)
768{
769 struct fwohci_softc *sc;
770
771 sc = (struct fwohci_softc *)arg;
772}
773
774u_int32_t
775fwohci_cyctimer(struct firewire_comm *fc)
776{
777 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
778 return(OREAD(sc, OHCI_CYCLETIMER));
779}
780
781int
782fwohci_detach(struct fwohci_softc *sc, device_t dev)
783{
784 int i;
785
786 if (sc->sid_buf != NULL)
787 fwdma_free(&sc->fc, &sc->sid_dma);
788 if (sc->fc.config_rom != NULL)
789 fwdma_free(&sc->fc, &sc->crom_dma);
790
791 fwohci_db_free(&sc->arrq);
792 fwohci_db_free(&sc->arrs);
793
794 fwohci_db_free(&sc->atrq);
795 fwohci_db_free(&sc->atrs);
796
797 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
798 fwohci_db_free(&sc->it[i]);
799 fwohci_db_free(&sc->ir[i]);
800 }
801
802 return 0;
803}
804
805#define LAST_DB(dbtr, db) do { \
806 struct fwohcidb_tr *_dbtr = (dbtr); \
807 int _cnt = _dbtr->dbcnt; \
808 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
809} while (0)
810
811static void
812fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
813{
814 struct fwohcidb_tr *db_tr;
78748771 815 struct fwohcidb *db;
984263bc
MD
816 bus_dma_segment_t *s;
817 int i;
818
819 db_tr = (struct fwohcidb_tr *)arg;
820 db = &db_tr->db[db_tr->dbcnt];
821 if (error) {
822 if (firewire_debug || error != EFBIG)
823 printf("fwohci_execute_db: error=%d\n", error);
824 return;
825 }
826 for (i = 0; i < nseg; i++) {
827 s = &segs[i];
828 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
829 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
830 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
831 db++;
832 db_tr->dbcnt++;
833 }
834}
835
836static void
837fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
838 bus_size_t size, int error)
839{
840 fwohci_execute_db(arg, segs, nseg, error);
841}
842
843static void
844fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
845{
4e01b467 846 int i;
78748771 847 int tcode, hdr_len, pl_off;
984263bc
MD
848 int fsegment = -1;
849 u_int32_t off;
850 struct fw_xfer *xfer;
851 struct fw_pkt *fp;
78748771 852 struct fwohci_txpkthdr *ohcifp;
984263bc 853 struct fwohcidb_tr *db_tr;
78748771
JS
854 struct fwohcidb *db;
855 u_int32_t *ld;
984263bc
MD
856 struct tcode_info *info;
857 static int maxdesc=0;
858
859 if(&sc->atrq == dbch){
860 off = OHCI_ATQOFF;
861 }else if(&sc->atrs == dbch){
862 off = OHCI_ATSOFF;
863 }else{
864 return;
865 }
866
867 if (dbch->flags & FWOHCI_DBCH_FULL)
868 return;
869
4e01b467 870 crit_enter();
984263bc
MD
871 db_tr = dbch->top;
872txloop:
873 xfer = STAILQ_FIRST(&dbch->xferq.q);
874 if(xfer == NULL){
875 goto kick;
876 }
877 if(dbch->xferq.queued == 0 ){
878 device_printf(sc->fc.dev, "TX queue empty\n");
879 }
880 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
881 db_tr->xfer = xfer;
882 xfer->state = FWXF_START;
883
78748771 884 fp = &xfer->send.hdr;
984263bc
MD
885 tcode = fp->mode.common.tcode;
886
78748771 887 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
984263bc
MD
888 info = &tinfo[tcode];
889 hdr_len = pl_off = info->hdr_len;
78748771
JS
890
891 ld = &ohcifp->mode.ld[0];
892 ld[0] = ld[1] = ld[2] = ld[3] = 0;
893 for( i = 0 ; i < pl_off ; i+= 4)
894 ld[i/4] = fp->mode.ld[i/4];
895
896 ohcifp->mode.common.spd = xfer->send.spd & 0x7;
984263bc
MD
897 if (tcode == FWTCODE_STREAM ){
898 hdr_len = 8;
899 ohcifp->mode.stream.len = fp->mode.stream.len;
900 } else if (tcode == FWTCODE_PHY) {
901 hdr_len = 12;
78748771
JS
902 ld[1] = fp->mode.ld[1];
903 ld[2] = fp->mode.ld[2];
984263bc
MD
904 ohcifp->mode.common.spd = 0;
905 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
906 } else {
907 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
908 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
909 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
910 }
911 db = &db_tr->db[0];
912 FWOHCI_DMA_WRITE(db->db.desc.cmd,
913 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
78748771 914 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
984263bc
MD
915 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
916/* Specify bound timer of asy. responce */
917 if(&sc->atrs == dbch){
918 FWOHCI_DMA_WRITE(db->db.desc.res,
919 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
920 }
921#if BYTE_ORDER == BIG_ENDIAN
922 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
923 hdr_len = 12;
924 for (i = 0; i < hdr_len/4; i ++)
78748771 925 FWOHCI_DMA_WRITE(ld[i], ld[i]);
984263bc
MD
926#endif
927
928again:
929 db_tr->dbcnt = 2;
930 db = &db_tr->db[db_tr->dbcnt];
78748771 931 if (xfer->send.pay_len > 0) {
984263bc
MD
932 int err;
933 /* handle payload */
934 if (xfer->mbuf == NULL) {
984263bc 935 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
78748771 936 &xfer->send.payload[0], xfer->send.pay_len,
984263bc
MD
937 fwohci_execute_db, db_tr,
938 /*flags*/0);
939 } else {
940 /* XXX we can handle only 6 (=8-2) mbuf chains */
941 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
942 xfer->mbuf,
943 fwohci_execute_db2, db_tr,
944 /* flags */0);
945 if (err == EFBIG) {
946 struct mbuf *m0;
947
948 if (firewire_debug)
949 device_printf(sc->fc.dev, "EFBIG.\n");
74f1caca 950 m0 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
951 if (m0 != NULL) {
952 m_copydata(xfer->mbuf, 0,
953 xfer->mbuf->m_pkthdr.len,
954 mtod(m0, caddr_t));
955 m0->m_len = m0->m_pkthdr.len =
956 xfer->mbuf->m_pkthdr.len;
957 m_freem(xfer->mbuf);
958 xfer->mbuf = m0;
959 goto again;
960 }
961 device_printf(sc->fc.dev, "m_getcl failed.\n");
962 }
963 }
964 if (err)
965 printf("dmamap_load: err=%d\n", err);
966 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
967 BUS_DMASYNC_PREWRITE);
968#if 0 /* OHCI_OUTPUT_MODE == 0 */
969 for (i = 2; i < db_tr->dbcnt; i++)
970 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
971 OHCI_OUTPUT_MORE);
972#endif
973 }
974 if (maxdesc < db_tr->dbcnt) {
975 maxdesc = db_tr->dbcnt;
976 if (bootverbose)
977 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
978 }
979 /* last db */
980 LAST_DB(db_tr, db);
981 FWOHCI_DMA_SET(db->db.desc.cmd,
982 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
983 FWOHCI_DMA_WRITE(db->db.desc.depend,
984 STAILQ_NEXT(db_tr, link)->bus_addr);
985
986 if(fsegment == -1 )
987 fsegment = db_tr->dbcnt;
988 if (dbch->pdb_tr != NULL) {
989 LAST_DB(dbch->pdb_tr, db);
990 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
991 }
992 dbch->pdb_tr = db_tr;
993 db_tr = STAILQ_NEXT(db_tr, link);
994 if(db_tr != dbch->bottom){
995 goto txloop;
996 } else {
997 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
998 dbch->flags |= FWOHCI_DBCH_FULL;
999 }
1000kick:
1001 /* kick asy q */
1002 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1003 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1004
1005 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1006 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1007 } else {
1008 if (bootverbose)
1009 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1010 OREAD(sc, OHCI_DMACTL(off)));
1011 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1012 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1013 dbch->xferq.flag |= FWXFERQ_RUNNING;
1014 }
1015
1016 dbch->top = db_tr;
4e01b467 1017 crit_exit();
984263bc
MD
1018 return;
1019}
1020
1021static void
1022fwohci_start_atq(struct firewire_comm *fc)
1023{
1024 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1025 fwohci_start( sc, &(sc->atrq));
1026 return;
1027}
1028
1029static void
1030fwohci_start_ats(struct firewire_comm *fc)
1031{
1032 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1033 fwohci_start( sc, &(sc->atrs));
1034 return;
1035}
1036
1037void
1038fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1039{
4e01b467 1040 int ch, err = 0;
984263bc 1041 struct fwohcidb_tr *tr;
78748771 1042 struct fwohcidb *db;
984263bc
MD
1043 struct fw_xfer *xfer;
1044 u_int32_t off;
1045 u_int stat, status;
1046 int packets;
1047 struct firewire_comm *fc = (struct firewire_comm *)sc;
1048
1049 if(&sc->atrq == dbch){
1050 off = OHCI_ATQOFF;
1051 ch = ATRQ_CH;
1052 }else if(&sc->atrs == dbch){
1053 off = OHCI_ATSOFF;
1054 ch = ATRS_CH;
1055 }else{
1056 return;
1057 }
4e01b467 1058 crit_enter();
984263bc
MD
1059 tr = dbch->bottom;
1060 packets = 0;
1061 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1062 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1063 while(dbch->xferq.queued > 0){
1064 LAST_DB(tr, db);
1065 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1066 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1067 if (fc->status != FWBUSRESET)
1068 /* maybe out of order?? */
1069 goto out;
1070 }
1071 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1072 BUS_DMASYNC_POSTWRITE);
1073 bus_dmamap_unload(dbch->dmat, tr->dma_map);
78748771
JS
1074#if 1
1075 if (firewire_debug)
1076 dump_db(sc, ch);
984263bc
MD
1077#endif
1078 if(status & OHCI_CNTL_DMA_DEAD) {
1079 /* Stop DMA */
1080 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1081 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1082 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1083 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1084 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1085 }
1086 stat = status & FWOHCIEV_MASK;
1087 switch(stat){
1088 case FWOHCIEV_ACKPEND:
1089 case FWOHCIEV_ACKCOMPL:
1090 err = 0;
1091 break;
1092 case FWOHCIEV_ACKBSA:
1093 case FWOHCIEV_ACKBSB:
1094 case FWOHCIEV_ACKBSX:
1095 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1096 err = EBUSY;
1097 break;
1098 case FWOHCIEV_FLUSHED:
1099 case FWOHCIEV_ACKTARD:
1100 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1101 err = EAGAIN;
1102 break;
1103 case FWOHCIEV_MISSACK:
1104 case FWOHCIEV_UNDRRUN:
1105 case FWOHCIEV_OVRRUN:
1106 case FWOHCIEV_DESCERR:
1107 case FWOHCIEV_DTRDERR:
1108 case FWOHCIEV_TIMEOUT:
1109 case FWOHCIEV_TCODERR:
1110 case FWOHCIEV_UNKNOWN:
1111 case FWOHCIEV_ACKDERR:
1112 case FWOHCIEV_ACKTERR:
1113 default:
1114 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1115 stat, fwohcicode[stat]);
1116 err = EINVAL;
1117 break;
1118 }
1119 if (tr->xfer != NULL) {
1120 xfer = tr->xfer;
1121 if (xfer->state == FWXF_RCVD) {
78748771 1122#if 0
984263bc
MD
1123 if (firewire_debug)
1124 printf("already rcvd\n");
78748771 1125#endif
984263bc
MD
1126 fw_xfer_done(xfer);
1127 } else {
1128 xfer->state = FWXF_SENT;
1129 if (err == EBUSY && fc->status != FWBUSRESET) {
1130 xfer->state = FWXF_BUSY;
1131 xfer->resp = err;
1132 if (xfer->retry_req != NULL)
1133 xfer->retry_req(xfer);
1134 else {
78748771 1135 xfer->recv.pay_len = 0;
984263bc
MD
1136 fw_xfer_done(xfer);
1137 }
1138 } else if (stat != FWOHCIEV_ACKPEND) {
1139 if (stat != FWOHCIEV_ACKCOMPL)
1140 xfer->state = FWXF_SENTERR;
1141 xfer->resp = err;
78748771 1142 xfer->recv.pay_len = 0;
984263bc
MD
1143 fw_xfer_done(xfer);
1144 }
1145 }
1146 /*
1147 * The watchdog timer takes care of split
1148 * transcation timeout for ACKPEND case.
1149 */
1150 } else {
1151 printf("this shouldn't happen\n");
1152 }
1153 dbch->xferq.queued --;
1154 tr->xfer = NULL;
1155
1156 packets ++;
1157 tr = STAILQ_NEXT(tr, link);
1158 dbch->bottom = tr;
1159 if (dbch->bottom == dbch->top) {
1160 /* we reaches the end of context program */
1161 if (firewire_debug && dbch->xferq.queued > 0)
1162 printf("queued > 0\n");
1163 break;
1164 }
1165 }
1166out:
1167 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1168 printf("make free slot\n");
1169 dbch->flags &= ~FWOHCI_DBCH_FULL;
1170 fwohci_start(sc, dbch);
1171 }
4e01b467 1172 crit_exit();
984263bc
MD
1173}
1174
1175static void
1176fwohci_db_free(struct fwohci_dbch *dbch)
1177{
1178 struct fwohcidb_tr *db_tr;
1179 int idb;
1180
1181 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1182 return;
1183
1184 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1185 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1186 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1187 db_tr->buf != NULL) {
1188 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1189 db_tr->buf, dbch->xferq.psize);
1190 db_tr->buf = NULL;
1191 } else if (db_tr->dma_map != NULL)
1192 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1193 }
1194 dbch->ndb = 0;
1195 db_tr = STAILQ_FIRST(&dbch->db_trq);
1196 fwdma_free_multiseg(dbch->am);
efda3bd0 1197 kfree(db_tr, M_FW);
984263bc
MD
1198 STAILQ_INIT(&dbch->db_trq);
1199 dbch->flags &= ~FWOHCI_DBCH_INIT;
1200}
1201
1202static void
1203fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1204{
1205 int idb;
1206 struct fwohcidb_tr *db_tr;
1207
1208 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1209 goto out;
1210
1211 /* create dma_tag for buffers */
1212#define MAX_REQCOUNT 0xffff
1213 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1214 /*alignment*/ 1, /*boundary*/ 0,
1215 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1216 /*highaddr*/ BUS_SPACE_MAXADDR,
1217 /*filter*/NULL, /*filterarg*/NULL,
1218 /*maxsize*/ dbch->xferq.psize,
1219 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1220 /*maxsegsz*/ MAX_REQCOUNT,
78748771 1221 /*flags*/ 0,
90dec0df 1222#if defined(__FreeBSD__) && __FreeBSD_version >= 501102
78748771
JS
1223 /*lockfunc*/busdma_lock_mutex,
1224 /*lockarg*/&Giant,
1225#endif
1226 &dbch->dmat))
984263bc
MD
1227 return;
1228
1229 /* allocate DB entries and attach one to each DMA channels */
1230 /* DB entry must start at 16 bytes bounary. */
1231 STAILQ_INIT(&dbch->db_trq);
1232 db_tr = (struct fwohcidb_tr *)
77652cad 1233 kmalloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
984263bc
MD
1234 M_FW, M_WAITOK | M_ZERO);
1235 if(db_tr == NULL){
1236 printf("fwohci_db_init: malloc(1) failed\n");
1237 return;
1238 }
1239
1240#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1241 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1242 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1243 if (dbch->am == NULL) {
1244 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
efda3bd0 1245 kfree(db_tr, M_FW);
984263bc
MD
1246 return;
1247 }
1248 /* Attach DB to DMA ch. */
1249 for(idb = 0 ; idb < dbch->ndb ; idb++){
1250 db_tr->dbcnt = 0;
1251 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1252 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1253 /* create dmamap for buffers */
1254 /* XXX do we need 4bytes alignment tag? */
1255 /* XXX don't alloc dma_map for AR */
1256 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1257 printf("bus_dmamap_create failed\n");
1258 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1259 fwohci_db_free(dbch);
1260 return;
1261 }
1262 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1263 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1264 if (idb % dbch->xferq.bnpacket == 0)
1265 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1266 ].start = (caddr_t)db_tr;
1267 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1268 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1269 ].end = (caddr_t)db_tr;
1270 }
1271 db_tr++;
1272 }
1273 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1274 = STAILQ_FIRST(&dbch->db_trq);
1275out:
1276 dbch->xferq.queued = 0;
1277 dbch->pdb_tr = NULL;
1278 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1279 dbch->bottom = dbch->top;
1280 dbch->flags = FWOHCI_DBCH_INIT;
1281}
1282
1283static int
1284fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1285{
1286 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1287 int sleepch;
1288
1289 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1290 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1291 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1292 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1293 /* XXX we cannot free buffers until the DMA really stops */
1294 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1295 fwohci_db_free(&sc->it[dmach]);
1296 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1297 return 0;
1298}
1299
1300static int
1301fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1302{
1303 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1304 int sleepch;
1305
1306 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1307 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1308 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1309 /* XXX we cannot free buffers until the DMA really stops */
1310 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1311 fwohci_db_free(&sc->ir[dmach]);
1312 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1313 return 0;
1314}
1315
1316#if BYTE_ORDER == BIG_ENDIAN
1317static void
1318fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1319{
1320 qld[0] = FWOHCI_DMA_READ(qld[0]);
1321 return;
1322}
1323#endif
1324
1325static int
1326fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1327{
1328 int err = 0;
1329 int idb, z, i, dmach = 0, ldesc;
78748771 1330 u_int32_t off = 0;
984263bc 1331 struct fwohcidb_tr *db_tr;
78748771 1332 struct fwohcidb *db;
984263bc
MD
1333
1334 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1335 err = EINVAL;
1336 return err;
1337 }
1338 z = dbch->ndesc;
1339 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1340 if( &sc->it[dmach] == dbch){
1341 off = OHCI_ITOFF(dmach);
1342 break;
1343 }
1344 }
78748771 1345 if(off == 0){
984263bc
MD
1346 err = EINVAL;
1347 return err;
1348 }
1349 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1350 return err;
1351 dbch->xferq.flag |= FWXFERQ_RUNNING;
1352 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1353 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1354 }
1355 db_tr = dbch->top;
1356 for (idb = 0; idb < dbch->ndb; idb ++) {
1357 fwohci_add_tx_buf(dbch, db_tr, idb);
1358 if(STAILQ_NEXT(db_tr, link) == NULL){
1359 break;
1360 }
1361 db = db_tr->db;
1362 ldesc = db_tr->dbcnt - 1;
1363 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1364 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1365 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1366 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1367 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1368 FWOHCI_DMA_SET(
1369 db[ldesc].db.desc.cmd,
1370 OHCI_INTERRUPT_ALWAYS);
1371 /* OHCI 1.1 and above */
1372 FWOHCI_DMA_SET(
1373 db[0].db.desc.cmd,
1374 OHCI_INTERRUPT_ALWAYS);
1375 }
1376 }
1377 db_tr = STAILQ_NEXT(db_tr, link);
1378 }
1379 FWOHCI_DMA_CLEAR(
1380 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1381 return err;
1382}
1383
1384static int
1385fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1386{
1387 int err = 0;
1388 int idb, z, i, dmach = 0, ldesc;
78748771 1389 u_int32_t off = 0;
984263bc 1390 struct fwohcidb_tr *db_tr;
78748771 1391 struct fwohcidb *db;
984263bc
MD
1392
1393 z = dbch->ndesc;
1394 if(&sc->arrq == dbch){
1395 off = OHCI_ARQOFF;
1396 }else if(&sc->arrs == dbch){
1397 off = OHCI_ARSOFF;
1398 }else{
1399 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1400 if( &sc->ir[dmach] == dbch){
1401 off = OHCI_IROFF(dmach);
1402 break;
1403 }
1404 }
1405 }
78748771 1406 if(off == 0){
984263bc
MD
1407 err = EINVAL;
1408 return err;
1409 }
1410 if(dbch->xferq.flag & FWXFERQ_STREAM){
1411 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1412 return err;
1413 }else{
1414 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1415 err = EBUSY;
1416 return err;
1417 }
1418 }
1419 dbch->xferq.flag |= FWXFERQ_RUNNING;
1420 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1421 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1422 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1423 }
1424 db_tr = dbch->top;
1425 for (idb = 0; idb < dbch->ndb; idb ++) {
1426 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1427 if (STAILQ_NEXT(db_tr, link) == NULL)
1428 break;
1429 db = db_tr->db;
1430 ldesc = db_tr->dbcnt - 1;
1431 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1432 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1433 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1434 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1435 FWOHCI_DMA_SET(
1436 db[ldesc].db.desc.cmd,
1437 OHCI_INTERRUPT_ALWAYS);
1438 FWOHCI_DMA_CLEAR(
1439 db[ldesc].db.desc.depend,
1440 0xf);
1441 }
1442 }
1443 db_tr = STAILQ_NEXT(db_tr, link);
1444 }
1445 FWOHCI_DMA_CLEAR(
1446 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1447 dbch->buf_offset = 0;
1448 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1449 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1450 if(dbch->xferq.flag & FWXFERQ_STREAM){
1451 return err;
1452 }else{
1453 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1454 }
1455 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1456 return err;
1457}
1458
1459static int
1460fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1461{
1462 int sec, cycle, cycle_match;
1463
1464 cycle = cycle_now & 0x1fff;
1465 sec = cycle_now >> 13;
1466#define CYCLE_MOD 0x10
1467#if 1
1468#define CYCLE_DELAY 8 /* min delay to start DMA */
1469#else
1470#define CYCLE_DELAY 7000 /* min delay to start DMA */
1471#endif
1472 cycle = cycle + CYCLE_DELAY;
1473 if (cycle >= 8000) {
1474 sec ++;
1475 cycle -= 8000;
1476 }
1477 cycle = roundup2(cycle, CYCLE_MOD);
1478 if (cycle >= 8000) {
1479 sec ++;
1480 if (cycle == 8000)
1481 cycle = 0;
1482 else
1483 cycle = CYCLE_MOD;
1484 }
1485 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1486
1487 return(cycle_match);
1488}
1489
1490static int
1491fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1492{
1493 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1494 int err = 0;
1495 unsigned short tag, ich;
1496 struct fwohci_dbch *dbch;
4e01b467 1497 int cycle_match, cycle_now, ldesc;
984263bc
MD
1498 u_int32_t stat;
1499 struct fw_bulkxfer *first, *chunk, *prev;
1500 struct fw_xferq *it;
1501
1502 dbch = &sc->it[dmach];
1503 it = &dbch->xferq;
1504
1505 tag = (it->flag >> 6) & 3;
1506 ich = it->flag & 0x3f;
1507 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1508 dbch->ndb = it->bnpacket * it->bnchunk;
1509 dbch->ndesc = 3;
1510 fwohci_db_init(sc, dbch);
1511 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1512 return ENOMEM;
1513 err = fwohci_tx_enable(sc, dbch);
1514 }
1515 if(err)
1516 return err;
1517
1518 ldesc = dbch->ndesc - 1;
4e01b467 1519 crit_enter();
984263bc
MD
1520 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1521 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
78748771 1522 struct fwohcidb *db;
984263bc
MD
1523
1524 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1525 BUS_DMASYNC_PREWRITE);
1526 fwohci_txbufdb(sc, dmach, chunk);
1527 if (prev != NULL) {
1528 db = ((struct fwohcidb_tr *)(prev->end))->db;
1529#if 0 /* XXX necessary? */
1530 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1531 OHCI_BRANCH_ALWAYS);
1532#endif
1533#if 0 /* if bulkxfer->npacket changes */
1534 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1535 ((struct fwohcidb_tr *)
1536 (chunk->start))->bus_addr | dbch->ndesc;
1537#else
1538 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1539 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1540#endif
1541 }
1542 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1543 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1544 prev = chunk;
1545 }
1546 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1547 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
4e01b467 1548 crit_exit();
984263bc
MD
1549 stat = OREAD(sc, OHCI_ITCTL(dmach));
1550 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1551 printf("stat 0x%x\n", stat);
1552
1553 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1554 return 0;
1555
1556#if 0
1557 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1558#endif
1559 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1560 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1561 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1562 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1563
1564 first = STAILQ_FIRST(&it->stdma);
1565 OWRITE(sc, OHCI_ITCMD(dmach),
1566 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1567 if (firewire_debug) {
1568 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1569#if 1
1570 dump_dma(sc, ITX_CH + dmach);
1571#endif
1572 }
1573 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1574#if 1
1575 /* Don't start until all chunks are buffered */
1576 if (STAILQ_FIRST(&it->stfree) != NULL)
1577 goto out;
1578#endif
1579#if 1
1580 /* Clear cycle match counter bits */
1581 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1582
1583 /* 2bit second + 13bit cycle */
1584 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1585 cycle_match = fwohci_next_cycle(fc, cycle_now);
1586
1587 OWRITE(sc, OHCI_ITCTL(dmach),
1588 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1589 | OHCI_CNTL_DMA_RUN);
1590#else
1591 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1592#endif
1593 if (firewire_debug) {
1594 printf("cycle_match: 0x%04x->0x%04x\n",
1595 cycle_now, cycle_match);
1596 dump_dma(sc, ITX_CH + dmach);
1597 dump_db(sc, ITX_CH + dmach);
1598 }
1599 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1600 device_printf(sc->fc.dev,
1601 "IT DMA underrun (0x%08x)\n", stat);
1602 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1603 }
1604out:
1605 return err;
1606}
1607
1608static int
1609fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1610{
1611 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
4e01b467 1612 int err = 0, ldesc;
984263bc
MD
1613 unsigned short tag, ich;
1614 u_int32_t stat;
1615 struct fwohci_dbch *dbch;
1616 struct fwohcidb_tr *db_tr;
1617 struct fw_bulkxfer *first, *prev, *chunk;
1618 struct fw_xferq *ir;
1619
1620 dbch = &sc->ir[dmach];
1621 ir = &dbch->xferq;
1622
1623 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1624 tag = (ir->flag >> 6) & 3;
1625 ich = ir->flag & 0x3f;
1626 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1627
1628 ir->queued = 0;
1629 dbch->ndb = ir->bnpacket * ir->bnchunk;
1630 dbch->ndesc = 2;
1631 fwohci_db_init(sc, dbch);
1632 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1633 return ENOMEM;
1634 err = fwohci_rx_enable(sc, dbch);
1635 }
1636 if(err)
1637 return err;
1638
1639 first = STAILQ_FIRST(&ir->stfree);
1640 if (first == NULL) {
1641 device_printf(fc->dev, "IR DMA no free chunk\n");
1642 return 0;
1643 }
1644
1645 ldesc = dbch->ndesc - 1;
4e01b467 1646 crit_enter();
984263bc
MD
1647 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1648 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
78748771 1649 struct fwohcidb *db;
984263bc
MD
1650
1651#if 1 /* XXX for if_fwe */
1652 if (chunk->mbuf != NULL) {
1653 db_tr = (struct fwohcidb_tr *)(chunk->start);
1654 db_tr->dbcnt = 1;
1655 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1656 chunk->mbuf, fwohci_execute_db2, db_tr,
1657 /* flags */0);
1658 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1659 OHCI_UPDATE | OHCI_INPUT_LAST |
1660 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1661 }
1662#endif
1663 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1664 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1665 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1666 if (prev != NULL) {
1667 db = ((struct fwohcidb_tr *)(prev->end))->db;
1668 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1669 }
1670 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1671 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1672 prev = chunk;
1673 }
1674 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1675 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
4e01b467 1676 crit_exit();
984263bc
MD
1677 stat = OREAD(sc, OHCI_IRCTL(dmach));
1678 if (stat & OHCI_CNTL_DMA_ACTIVE)
1679 return 0;
1680 if (stat & OHCI_CNTL_DMA_RUN) {
1681 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1682 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1683 }
1684
1685 if (firewire_debug)
1686 printf("start IR DMA 0x%x\n", stat);
1687 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1688 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1689 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1690 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1691 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1692 OWRITE(sc, OHCI_IRCMD(dmach),
1693 ((struct fwohcidb_tr *)(first->start))->bus_addr
1694 | dbch->ndesc);
1695 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1696 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1697#if 0
1698 dump_db(sc, IRX_CH + dmach);
1699#endif
1700 return err;
1701}
1702
1703int
1704fwohci_stop(struct fwohci_softc *sc, device_t dev)
1705{
1706 u_int i;
1707
1708/* Now stopping all DMA channel */
1709 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1710 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1711 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1712 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1713
1714 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1715 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1716 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1717 }
1718
1719/* FLUSH FIFO and reset Transmitter/Reciever */
1720 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1721
1722/* Stop interrupt */
1723 OWRITE(sc, FWOHCI_INTMASKCLR,
1724 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1725 | OHCI_INT_PHY_INT
1726 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1727 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1728 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1729 | OHCI_INT_PHY_BUS_R);
78748771
JS
1730
1731 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1732 fw_drain_txq(&sc->fc);
1733
984263bc
MD
1734/* XXX Link down? Bus reset? */
1735 return 0;
1736}
1737
1738int
1739fwohci_resume(struct fwohci_softc *sc, device_t dev)
1740{
1741 int i;
78748771
JS
1742 struct fw_xferq *ir;
1743 struct fw_bulkxfer *chunk;
984263bc
MD
1744
1745 fwohci_reset(sc, dev);
1746 /* XXX resume isochronus receive automatically. (how about TX?) */
1747 for(i = 0; i < sc->fc.nisodma; i ++) {
78748771
JS
1748 ir = &sc->ir[i].xferq;
1749 if((ir->flag & FWXFERQ_RUNNING) != 0) {
984263bc
MD
1750 device_printf(sc->fc.dev,
1751 "resume iso receive ch: %d\n", i);
78748771
JS
1752 ir->flag &= ~FWXFERQ_RUNNING;
1753 /* requeue stdma to stfree */
1754 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1755 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1756 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1757 }
984263bc
MD
1758 sc->fc.irx_enable(&sc->fc, i);
1759 }
1760 }
1761
1762 bus_generic_resume(dev);
1763 sc->fc.ibr(&sc->fc);
1764 return 0;
1765}
1766
1767#define ACK_ALL
1768static void
1769fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1770{
1771 u_int32_t irstat, itstat;
1772 u_int i;
1773 struct firewire_comm *fc = (struct firewire_comm *)sc;
1774
1775#ifdef OHCI_DEBUG
1776 if(stat & OREAD(sc, FWOHCI_INTMASK))
1777 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1778 stat & OHCI_INT_EN ? "DMA_EN ":"",
1779 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1780 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1781 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1782 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1783 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1784 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1785 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1786 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1787 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1788 stat & OHCI_INT_PHY_SID ? "SID ":"",
1789 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1790 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1791 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1792 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1793 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1794 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1795 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1796 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1797 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1798 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1799 stat, OREAD(sc, FWOHCI_INTMASK)
1800 );
1801#endif
1802/* Bus reset */
1803 if(stat & OHCI_INT_PHY_BUS_R ){
1804 if (fc->status == FWBUSRESET)
1805 goto busresetout;
1806 /* Disable bus reset interrupt until sid recv. */
1807 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1808
1809 device_printf(fc->dev, "BUS reset\n");
1810 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1811 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1812
1813 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1814 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1815 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1816 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1817
1818#ifndef ACK_ALL
1819 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1820#endif
1821 fw_busreset(fc);
78748771
JS
1822 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1823 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
984263bc
MD
1824 }
1825busresetout:
1826 if((stat & OHCI_INT_DMA_IR )){
1827#ifndef ACK_ALL
1828 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1829#endif
90dec0df 1830#if defined(__DragonFly__) || __FreeBSD_version < 500000
984263bc
MD
1831 irstat = sc->irstat;
1832 sc->irstat = 0;
90dec0df
JS
1833#else
1834 irstat = atomic_readandclear_int(&sc->irstat);
984263bc
MD
1835#endif
1836 for(i = 0; i < fc->nisodma ; i++){
1837 struct fwohci_dbch *dbch;
1838
1839 if((irstat & (1 << i)) != 0){
1840 dbch = &sc->ir[i];
1841 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1842 device_printf(sc->fc.dev,
1843 "dma(%d) not active\n", i);
1844 continue;
1845 }
1846 fwohci_rbuf_update(sc, i);
1847 }
1848 }
1849 }
1850 if((stat & OHCI_INT_DMA_IT )){
1851#ifndef ACK_ALL
1852 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1853#endif
90dec0df 1854#if defined(__DragonFly__) || __FreeBSD_version < 500000
984263bc
MD
1855 itstat = sc->itstat;
1856 sc->itstat = 0;
90dec0df
JS
1857#else
1858 itstat = atomic_readandclear_int(&sc->itstat);
984263bc
MD
1859#endif
1860 for(i = 0; i < fc->nisodma ; i++){
1861 if((itstat & (1 << i)) != 0){
1862 fwohci_tbuf_update(sc, i);
1863 }
1864 }
1865 }
1866 if((stat & OHCI_INT_DMA_PRRS )){
1867#ifndef ACK_ALL
1868 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1869#endif
1870#if 0
1871 dump_dma(sc, ARRS_CH);
1872 dump_db(sc, ARRS_CH);
1873#endif
1874 fwohci_arcv(sc, &sc->arrs, count);
1875 }
1876 if((stat & OHCI_INT_DMA_PRRQ )){
1877#ifndef ACK_ALL
1878 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1879#endif
1880#if 0
1881 dump_dma(sc, ARRQ_CH);
1882 dump_db(sc, ARRQ_CH);
1883#endif
1884 fwohci_arcv(sc, &sc->arrq, count);
1885 }
1886 if(stat & OHCI_INT_PHY_SID){
1887 u_int32_t *buf, node_id;
1888 int plen;
1889
1890#ifndef ACK_ALL
1891 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1892#endif
1893 /* Enable bus reset interrupt */
1894 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1895 /* Allow async. request to us */
1896 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1897 /* XXX insecure ?? */
1898 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1899 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1900 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1901 /* Set ATRetries register */
1902 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1903/*
1904** Checking whether the node is root or not. If root, turn on
1905** cycle master.
1906*/
1907 node_id = OREAD(sc, FWOHCI_NODEID);
1908 plen = OREAD(sc, OHCI_SID_CNT);
1909
1910 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1911 node_id, (plen >> 16) & 0xff);
1912 if (!(node_id & OHCI_NODE_VALID)) {
1913 printf("Bus reset failure\n");
1914 goto sidout;
1915 }
1916 if (node_id & OHCI_NODE_ROOT) {
1917 printf("CYCLEMASTER mode\n");
1918 OWRITE(sc, OHCI_LNKCTL,
1919 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1920 } else {
1921 printf("non CYCLEMASTER mode\n");
1922 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1923 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1924 }
1925 fc->nodeid = node_id & 0x3f;
1926
1927 if (plen & OHCI_SID_ERR) {
1928 device_printf(fc->dev, "SID Error\n");
1929 goto sidout;
1930 }
1931 plen &= OHCI_SID_CNT_MASK;
1932 if (plen < 4 || plen > OHCI_SIDSIZE) {
1933 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1934 goto sidout;
1935 }
1936 plen -= 4; /* chop control info */
efda3bd0 1937 buf = (u_int32_t *)kmalloc(OHCI_SIDSIZE, M_FW, M_INTWAIT);
984263bc
MD
1938 if (buf == NULL) {
1939 device_printf(fc->dev, "malloc failed\n");
1940 goto sidout;
1941 }
1942 for (i = 0; i < plen / 4; i ++)
1943 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1944#if 1
1945 /* pending all pre-bus_reset packets */
1946 fwohci_txd(sc, &sc->atrq);
1947 fwohci_txd(sc, &sc->atrs);
1948 fwohci_arcv(sc, &sc->arrs, -1);
1949 fwohci_arcv(sc, &sc->arrq, -1);
1950 fw_drain_txq(fc);
1951#endif
1952 fw_sidrcv(fc, buf, plen);
efda3bd0 1953 kfree(buf, M_FW);
984263bc
MD
1954 }
1955sidout:
1956 if((stat & OHCI_INT_DMA_ATRQ )){
1957#ifndef ACK_ALL
1958 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1959#endif
1960 fwohci_txd(sc, &(sc->atrq));
1961 }
1962 if((stat & OHCI_INT_DMA_ATRS )){
1963#ifndef ACK_ALL
1964 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1965#endif
1966 fwohci_txd(sc, &(sc->atrs));
1967 }
1968 if((stat & OHCI_INT_PW_ERR )){
1969#ifndef ACK_ALL
1970 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1971#endif
1972 device_printf(fc->dev, "posted write error\n");
1973 }
1974 if((stat & OHCI_INT_ERR )){
1975#ifndef ACK_ALL
1976 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1977#endif
1978 device_printf(fc->dev, "unrecoverable error\n");
1979 }
1980 if((stat & OHCI_INT_PHY_INT)) {
1981#ifndef ACK_ALL
1982 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1983#endif
1984 device_printf(fc->dev, "phy int\n");
1985 }
1986
1987 return;
1988}
1989
1990#if FWOHCI_TASKQUEUE
1991static void
1992fwohci_complete(void *arg, int pending)
1993{
1994 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1995 u_int32_t stat;
1996
1997again:
1998 stat = atomic_readandclear_int(&sc->intstat);
1999 if (stat)
2000 fwohci_intr_body(sc, stat, -1);
2001 else
2002 return;
2003 goto again;
2004}
2005#endif
2006
2007static u_int32_t
2008fwochi_check_stat(struct fwohci_softc *sc)
2009{
2010 u_int32_t stat, irstat, itstat;
2011
2012 stat = OREAD(sc, FWOHCI_INTSTAT);
2013 if (stat == 0xffffffff) {
2014 device_printf(sc->fc.dev,
2015 "device physically ejected?\n");
2016 return(stat);
2017 }
2018#ifdef ACK_ALL
2019 if (stat)
2020 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2021#endif
2022 if (stat & OHCI_INT_DMA_IR) {
2023 irstat = OREAD(sc, OHCI_IR_STAT);
2024 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2025 atomic_set_int(&sc->irstat, irstat);
2026 }
2027 if (stat & OHCI_INT_DMA_IT) {
2028 itstat = OREAD(sc, OHCI_IT_STAT);
2029 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2030 atomic_set_int(&sc->itstat, itstat);
2031 }
2032 return(stat);
2033}
2034
2035void
2036fwohci_intr(void *arg)
2037{
2038 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2039 u_int32_t stat;
2040#if !FWOHCI_TASKQUEUE
2041 u_int32_t bus_reset = 0;
2042#endif
2043
2044 if (!(sc->intmask & OHCI_INT_EN)) {
2045 /* polling mode */
2046 return;
2047 }
2048
2049#if !FWOHCI_TASKQUEUE
2050again:
2051#endif
2052 stat = fwochi_check_stat(sc);
2053 if (stat == 0 || stat == 0xffffffff)
2054 return;
2055#if FWOHCI_TASKQUEUE
2056 atomic_set_int(&sc->intstat, stat);
2057 /* XXX mask bus reset intr. during bus reset phase */
2058 if (stat)
2059 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2060#else
2061 /* We cannot clear bus reset event during bus reset phase */
2062 if ((stat & ~bus_reset) == 0)
2063 return;
2064 bus_reset = stat & OHCI_INT_PHY_BUS_R;
2065 fwohci_intr_body(sc, stat, -1);
2066 goto again;
2067#endif
2068}
2069
78748771 2070void
984263bc
MD
2071fwohci_poll(struct firewire_comm *fc, int quick, int count)
2072{
984263bc
MD
2073 u_int32_t stat;
2074 struct fwohci_softc *sc;
2075
2076
2077 sc = (struct fwohci_softc *)fc;
2078 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2079 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2080 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2081#if 0
2082 if (!quick) {
2083#else
2084 if (1) {
2085#endif
2086 stat = fwochi_check_stat(sc);
2087 if (stat == 0 || stat == 0xffffffff)
2088 return;
2089 }
4e01b467 2090 crit_enter();
984263bc 2091 fwohci_intr_body(sc, stat, count);
4e01b467 2092 crit_exit();
984263bc
MD
2093}
2094
2095static void
2096fwohci_set_intr(struct firewire_comm *fc, int enable)
2097{
2098 struct fwohci_softc *sc;
2099
2100 sc = (struct fwohci_softc *)fc;
2101 if (bootverbose)
2102 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2103 if (enable) {
2104 sc->intmask |= OHCI_INT_EN;
2105 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2106 } else {
2107 sc->intmask &= ~OHCI_INT_EN;
2108 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2109 }
2110}
2111
2112static void
2113fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2114{
2115 struct firewire_comm *fc = &sc->fc;
78748771 2116 struct fwohcidb *db;
984263bc
MD
2117 struct fw_bulkxfer *chunk;
2118 struct fw_xferq *it;
2119 u_int32_t stat, count;
4e01b467 2120 int w=0, ldesc;
984263bc
MD
2121
2122 it = fc->it[dmach];
2123 ldesc = sc->it[dmach].ndesc - 1;
4e01b467 2124 crit_enter(); /* unnecessary? */
984263bc 2125 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
78748771
JS
2126 if (firewire_debug)
2127 dump_db(sc, ITX_CH + dmach);
984263bc
MD
2128 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2129 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2130 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2131 >> OHCI_STATUS_SHIFT;
2132 db = ((struct fwohcidb_tr *)(chunk->start))->db;
78748771 2133 /* timestamp */
984263bc
MD
2134 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2135 & OHCI_COUNT_MASK;
2136 if (stat == 0)
2137 break;
2138 STAILQ_REMOVE_HEAD(&it->stdma, link);
2139 switch (stat & FWOHCIEV_MASK){
2140 case FWOHCIEV_ACKCOMPL:
2141#if 0
2142 device_printf(fc->dev, "0x%08x\n", count);
2143#endif
2144 break;
2145 default:
2146 device_printf(fc->dev,
2147 "Isochronous transmit err %02x(%s)\n",
2148 stat, fwohcicode[stat & 0x1f]);
2149 }
2150 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2151 w++;
2152 }
4e01b467 2153 crit_exit();
984263bc
MD
2154 if (w)
2155 wakeup(it);
2156}
2157
2158static void
2159fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2160{
2161 struct firewire_comm *fc = &sc->fc;
78748771 2162 struct fwohcidb_tr *db_tr;
984263bc
MD
2163 struct fw_bulkxfer *chunk;
2164 struct fw_xferq *ir;
2165 u_int32_t stat;
4e01b467 2166 int w=0, ldesc;
984263bc
MD
2167
2168 ir = fc->ir[dmach];
2169 ldesc = sc->ir[dmach].ndesc - 1;
2170#if 0
2171 dump_db(sc, dmach);
2172#endif
4e01b467 2173 crit_enter();
984263bc
MD
2174 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2175 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2176 db_tr = (struct fwohcidb_tr *)chunk->end;
2177 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2178 >> OHCI_STATUS_SHIFT;
2179 if (stat == 0)
2180 break;
2181
2182 if (chunk->mbuf != NULL) {
2183 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2184 BUS_DMASYNC_POSTREAD);
2185 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2186 } else if (ir->buf != NULL) {
2187 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2188 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2189 } else {
2190 /* XXX */
2191 printf("fwohci_rbuf_update: this shouldn't happend\n");
2192 }
2193
2194 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2195 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2196 switch (stat & FWOHCIEV_MASK) {
2197 case FWOHCIEV_ACKCOMPL:
2198 chunk->resp = 0;
2199 break;
2200 default:
2201 chunk->resp = EINVAL;
2202 device_printf(fc->dev,
2203 "Isochronous receive err %02x(%s)\n",
2204 stat, fwohcicode[stat & 0x1f]);
2205 }
2206 w++;
2207 }
4e01b467 2208 crit_exit();
984263bc
MD
2209 if (w) {
2210 if (ir->flag & FWXFERQ_HANDLER)
2211 ir->hand(ir);
2212 else
2213 wakeup(ir);
2214 }
2215}
2216
2217void
2218dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2219{
2220 u_int32_t off, cntl, stat, cmd, match;
2221
2222 if(ch == 0){
2223 off = OHCI_ATQOFF;
2224 }else if(ch == 1){
2225 off = OHCI_ATSOFF;
2226 }else if(ch == 2){
2227 off = OHCI_ARQOFF;
2228 }else if(ch == 3){
2229 off = OHCI_ARSOFF;
2230 }else if(ch < IRX_CH){
2231 off = OHCI_ITCTL(ch - ITX_CH);
2232 }else{
2233 off = OHCI_IRCTL(ch - IRX_CH);
2234 }
2235 cntl = stat = OREAD(sc, off);
2236 cmd = OREAD(sc, off + 0xc);
2237 match = OREAD(sc, off + 0x10);
2238
2239 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2240 ch,
2241 cntl,
2242 cmd,
2243 match);
2244 stat &= 0xffff ;
2245 if (stat) {
2246 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2247 ch,
2248 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2249 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2250 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2251 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2252 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2253 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2254 fwohcicode[stat & 0x1f],
2255 stat & 0x1f
2256 );
2257 }else{
2258 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2259 }
2260}
2261
2262void
2263dump_db(struct fwohci_softc *sc, u_int32_t ch)
2264{
2265 struct fwohci_dbch *dbch;
2266 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
78748771 2267 struct fwohcidb *curr = NULL, *prev, *next = NULL;
984263bc
MD
2268 int idb, jdb;
2269 u_int32_t cmd, off;
2270 if(ch == 0){
2271 off = OHCI_ATQOFF;
2272 dbch = &sc->atrq;
2273 }else if(ch == 1){
2274 off = OHCI_ATSOFF;
2275 dbch = &sc->atrs;
2276 }else if(ch == 2){
2277 off = OHCI_ARQOFF;
2278 dbch = &sc->arrq;
2279 }else if(ch == 3){
2280 off = OHCI_ARSOFF;
2281 dbch = &sc->arrs;
2282 }else if(ch < IRX_CH){
2283 off = OHCI_ITCTL(ch - ITX_CH);
2284 dbch = &sc->it[ch - ITX_CH];
2285 }else {
2286 off = OHCI_IRCTL(ch - IRX_CH);
2287 dbch = &sc->ir[ch - IRX_CH];
2288 }
2289 cmd = OREAD(sc, off + 0xc);
2290
2291 if( dbch->ndb == 0 ){
2292 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2293 return;
2294 }
2295 pp = dbch->top;
2296 prev = pp->db;
2297 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2298 if(pp == NULL){
2299 curr = NULL;
2300 goto outdb;
2301 }
2302 cp = STAILQ_NEXT(pp, link);
2303 if(cp == NULL){
2304 curr = NULL;
2305 goto outdb;
2306 }
2307 np = STAILQ_NEXT(cp, link);
2308 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2309 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2310 curr = cp->db;
2311 if(np != NULL){
2312 next = np->db;
2313 }else{
2314 next = NULL;
2315 }
2316 goto outdb;
2317 }
2318 }
2319 pp = STAILQ_NEXT(pp, link);
2320 prev = pp->db;
2321 }
2322outdb:
2323 if( curr != NULL){
2324#if 0
2325 printf("Prev DB %d\n", ch);
2326 print_db(pp, prev, ch, dbch->ndesc);
2327#endif
2328 printf("Current DB %d\n", ch);
2329 print_db(cp, curr, ch, dbch->ndesc);
2330#if 0
2331 printf("Next DB %d\n", ch);
2332 print_db(np, next, ch, dbch->ndesc);
2333#endif
2334 }else{
2335 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2336 }
2337 return;
2338}
2339
2340void
78748771 2341print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
984263bc
MD
2342 u_int32_t ch, u_int32_t max)
2343{
2344 fwohcireg_t stat;
2345 int i, key;
2346 u_int32_t cmd, res;
2347
2348 if(db == NULL){
2349 printf("No Descriptor is found\n");
2350 return;
2351 }
2352
2353 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2354 ch,
2355 "Current",
2356 "OP ",
2357 "KEY",
2358 "INT",
2359 "BR ",
2360 "len",
2361 "Addr",
2362 "Depend",
2363 "Stat",
2364 "Cnt");
2365 for( i = 0 ; i <= max ; i ++){
2366 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2367 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2368 key = cmd & OHCI_KEY_MASK;
2369 stat = res >> OHCI_STATUS_SHIFT;
90dec0df 2370#if defined(__DragonFly__) || __FreeBSD_version < 500000
984263bc
MD
2371 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2372 db_tr->bus_addr,
90dec0df
JS
2373#else
2374 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2375 (uintmax_t)db_tr->bus_addr,
984263bc
MD
2376#endif
2377 dbcode[(cmd >> 28) & 0xf],
2378 dbkey[(cmd >> 24) & 0x7],
2379 dbcond[(cmd >> 20) & 0x3],
2380 dbcond[(cmd >> 18) & 0x3],
2381 cmd & OHCI_COUNT_MASK,
2382 FWOHCI_DMA_READ(db[i].db.desc.addr),
2383 FWOHCI_DMA_READ(db[i].db.desc.depend),
2384 stat,
2385 res & OHCI_COUNT_MASK);
2386 if(stat & 0xff00){
2387 printf(" %s%s%s%s%s%s %s(%x)\n",
2388 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2389 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2390 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2391 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2392 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2393 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2394 fwohcicode[stat & 0x1f],
2395 stat & 0x1f
2396 );
2397 }else{
2398 printf(" Nostat\n");
2399 }
2400 if(key == OHCI_KEY_ST2 ){
2401 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2402 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2403 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2404 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2405 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2406 }
2407 if(key == OHCI_KEY_DEVICE){
2408 return;
2409 }
2410 if((cmd & OHCI_BRANCH_MASK)
2411 == OHCI_BRANCH_ALWAYS){
2412 return;
2413 }
2414 if((cmd & OHCI_CMD_MASK)
2415 == OHCI_OUTPUT_LAST){
2416 return;
2417 }
2418 if((cmd & OHCI_CMD_MASK)
2419 == OHCI_INPUT_LAST){
2420 return;
2421 }
2422 if(key == OHCI_KEY_ST2 ){
2423 i++;
2424 }
2425 }
2426 return;
2427}
2428
2429void
2430fwohci_ibr(struct firewire_comm *fc)
2431{
2432 struct fwohci_softc *sc;
2433 u_int32_t fun;
2434
2435 device_printf(fc->dev, "Initiate bus reset\n");
2436 sc = (struct fwohci_softc *)fc;
2437
2438 /*
2439 * Set root hold-off bit so that non cyclemaster capable node
2440 * shouldn't became the root node.
2441 */
2442#if 1
2443 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2444 fun |= FW_PHY_IBR | FW_PHY_RHB;
2445 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2446#else /* Short bus reset */
2447 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2448 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2449 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2450#endif
2451}
2452
2453void
2454fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2455{
2456 struct fwohcidb_tr *db_tr, *fdb_tr;
2457 struct fwohci_dbch *dbch;
78748771 2458 struct fwohcidb *db;
984263bc 2459 struct fw_pkt *fp;
78748771 2460 struct fwohci_txpkthdr *ohcifp;
984263bc
MD
2461 unsigned short chtag;
2462 int idb;
2463
2464 dbch = &sc->it[dmach];
2465 chtag = sc->it[dmach].xferq.flag & 0xff;
2466
2467 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2468 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2469/*
2470device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2471*/
2472 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2473 db = db_tr->db;
2474 fp = (struct fw_pkt *)db_tr->buf;
78748771 2475 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
984263bc 2476 ohcifp->mode.ld[0] = fp->mode.ld[0];
78748771 2477 ohcifp->mode.common.spd = 0 & 0x7;
984263bc
MD
2478 ohcifp->mode.stream.len = fp->mode.stream.len;
2479 ohcifp->mode.stream.chtag = chtag;
2480 ohcifp->mode.stream.tcode = 0xa;
984263bc
MD
2481#if BYTE_ORDER == BIG_ENDIAN
2482 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2483 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2484#endif
2485
2486 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2487 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2488 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2489#if 0 /* if bulkxfer->npackets changes */
2490 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2491 | OHCI_UPDATE
2492 | OHCI_BRANCH_ALWAYS;
2493 db[0].db.desc.depend =
2494 = db[dbch->ndesc - 1].db.desc.depend
2495 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2496#else
2497 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2498 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2499#endif
2500 bulkxfer->end = (caddr_t)db_tr;
2501 db_tr = STAILQ_NEXT(db_tr, link);
2502 }
2503 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2504 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2505 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2506#if 0 /* if bulkxfer->npackets changes */
2507 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2508 /* OHCI 1.1 and above */
2509 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2510#endif
2511/*
2512 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2513 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2514device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2515*/
2516 return;
2517}
2518
2519static int
2520fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2521 int poffset)
2522{
78748771 2523 struct fwohcidb *db = db_tr->db;
984263bc
MD
2524 struct fw_xferq *it;
2525 int err = 0;
2526
2527 it = &dbch->xferq;
2528 if(it->buf == 0){
2529 err = EINVAL;
2530 return err;
2531 }
2532 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2533 db_tr->dbcnt = 3;
2534
2535 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2536 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
78748771
JS
2537 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2538 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
984263bc
MD
2539 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2540 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2541
2542 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2543 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2544#if 1
2545 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2546 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2547#endif
2548 return 0;
2549}
2550
2551int
2552fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2553 int poffset, struct fwdma_alloc *dummy_dma)
2554{
78748771 2555 struct fwohcidb *db = db_tr->db;
984263bc
MD
2556 struct fw_xferq *ir;
2557 int i, ldesc;
2558 bus_addr_t dbuf[2];
2559 int dsiz[2];
2560
2561 ir = &dbch->xferq;
2562 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2563 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2564 ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2565 if (db_tr->buf == NULL)
2566 return(ENOMEM);
2567 db_tr->dbcnt = 1;
2568 dsiz[0] = ir->psize;
2569 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2570 BUS_DMASYNC_PREREAD);
2571 } else {
2572 db_tr->dbcnt = 0;
2573 if (dummy_dma != NULL) {
2574 dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2575 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2576 }
2577 dsiz[db_tr->dbcnt] = ir->psize;
2578 if (ir->buf != NULL) {
2579 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2580 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2581 }
2582 db_tr->dbcnt++;
2583 }
2584 for(i = 0 ; i < db_tr->dbcnt ; i++){
2585 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2586 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2587 if (ir->flag & FWXFERQ_STREAM) {
2588 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2589 }
2590 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2591 }
2592 ldesc = db_tr->dbcnt - 1;
2593 if (ir->flag & FWXFERQ_STREAM) {
2594 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2595 }
2596 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2597 return 0;
2598}
2599
2600
2601static int
2602fwohci_arcv_swap(struct fw_pkt *fp, int len)
2603{
2604 struct fw_pkt *fp0;
2605 u_int32_t ld0;
78748771 2606 int slen, hlen;
984263bc
MD
2607#if BYTE_ORDER == BIG_ENDIAN
2608 int i;
2609#endif
2610
2611 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2612#if 0
2613 printf("ld0: x%08x\n", ld0);
2614#endif
2615 fp0 = (struct fw_pkt *)&ld0;
78748771 2616 /* determine length to swap */
984263bc
MD
2617 switch (fp0->mode.common.tcode) {
2618 case FWTCODE_RREQQ:
2619 case FWTCODE_WRES:
2620 case FWTCODE_WREQQ:
2621 case FWTCODE_RRESQ:
2622 case FWOHCITCODE_PHY:
2623 slen = 12;
2624 break;
2625 case FWTCODE_RREQB:
2626 case FWTCODE_WREQB:
2627 case FWTCODE_LREQ:
2628 case FWTCODE_RRESB:
2629 case FWTCODE_LRES:
2630 slen = 16;
2631 break;
2632 default:
2633 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2634 return(0);
2635 }
78748771
JS
2636 hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2637 if (hlen > len) {
984263bc
MD
2638 if (firewire_debug)
2639 printf("splitted header\n");
78748771 2640 return(-hlen);
984263bc
MD
2641 }
2642#if BYTE_ORDER == BIG_ENDIAN
2643 for(i = 0; i < slen/4; i ++)
2644 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2645#endif
78748771 2646 return(hlen);
984263bc
MD
2647}
2648
984263bc
MD
2649static int
2650fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2651{
78748771 2652 struct tcode_info *info;
984263bc
MD
2653 int r;
2654
78748771
JS
2655 info = &tinfo[fp->mode.common.tcode];
2656 r = info->hdr_len + sizeof(u_int32_t);
2657 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2658 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t));
2659
2660 if (r == sizeof(u_int32_t))
2661 /* XXX */
984263bc
MD
2662 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2663 fp->mode.common.tcode);
78748771 2664
984263bc
MD
2665 if (r > dbch->xferq.psize) {
2666 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2667 /* panic ? */
2668 }
78748771 2669
984263bc
MD
2670 return r;
2671}
2672
2673static void
2674fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
2675{
78748771 2676 struct fwohcidb *db = &db_tr->db[0];
984263bc
MD
2677
2678 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2679 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2680 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2681 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2682 dbch->bottom = db_tr;
2683}
2684
2685static void
2686fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2687{
2688 struct fwohcidb_tr *db_tr;
2689 struct iovec vec[2];
2690 struct fw_pkt pktbuf;
2691 int nvec;
2692 struct fw_pkt *fp;
2693 u_int8_t *ld;
2694 u_int32_t stat, off, status;
2695 u_int spd;
2696 int len, plen, hlen, pcnt, offset;
984263bc
MD
2697 caddr_t buf;
2698 int resCount;
2699
2700 if(&sc->arrq == dbch){
2701 off = OHCI_ARQOFF;
2702 }else if(&sc->arrs == dbch){
2703 off = OHCI_ARSOFF;
2704 }else{
2705 return;
2706 }
2707
4e01b467 2708 crit_enter();
984263bc
MD
2709 db_tr = dbch->top;
2710 pcnt = 0;
2711 /* XXX we cannot handle a packet which lies in more than two buf */
2712 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2713 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2714 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2715 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2716#if 0
2717 printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2718#endif
2719 while (status & OHCI_CNTL_DMA_ACTIVE) {
2720 len = dbch->xferq.psize - resCount;
2721 ld = (u_int8_t *)db_tr->buf;
2722 if (dbch->pdb_tr == NULL) {
2723 len -= dbch->buf_offset;
2724 ld += dbch->buf_offset;
2725 }
2726 if (len > 0)
2727 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2728 BUS_DMASYNC_POSTREAD);
2729 while (len > 0 ) {
2730 if (count >= 0 && count-- == 0)
2731 goto out;
2732 if(dbch->pdb_tr != NULL){
2733 /* we have a fragment in previous buffer */
2734 int rlen;
2735
2736 offset = dbch->buf_offset;
2737 if (offset < 0)
2738 offset = - offset;
2739 buf = dbch->pdb_tr->buf + offset;
2740 rlen = dbch->xferq.psize - offset;
2741 if (firewire_debug)
2742 printf("rlen=%d, offset=%d\n",
2743 rlen, dbch->buf_offset);
2744 if (dbch->buf_offset < 0) {
2745 /* splitted in header, pull up */
2746 char *p;
2747
2748 p = (char *)&pktbuf;
2749 bcopy(buf, p, rlen);
2750 p += rlen;
2751 /* this must be too long but harmless */
2752 rlen = sizeof(pktbuf) - rlen;
2753 if (rlen < 0)
2754 printf("why rlen < 0\n");
2755 bcopy(db_tr->buf, p, rlen);
2756 ld += rlen;
2757 len -= rlen;
2758 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2759 if (hlen < 0) {
2760 printf("hlen < 0 shouldn't happen");
2761 }
2762 offset = sizeof(pktbuf);
2763 vec[0].iov_base = (char *)&pktbuf;
2764 vec[0].iov_len = offset;
2765 } else {
2766 /* splitted in payload */
2767 offset = rlen;
2768 vec[0].iov_base = buf;
2769 vec[0].iov_len = rlen;
2770 }
2771 fp=(struct fw_pkt *)vec[0].iov_base;
2772 nvec = 1;
2773 } else {
2774 /* no fragment in previous buffer */
2775 fp=(struct fw_pkt *)ld;
2776 hlen = fwohci_arcv_swap(fp, len);
2777 if (hlen == 0)
2778 /* XXX need reset */
2779 goto out;
2780 if (hlen < 0) {
2781 dbch->pdb_tr = db_tr;
2782 dbch->buf_offset = - dbch->buf_offset;
2783 /* sanity check */
2784 if (resCount != 0)
78748771
JS
2785 printf("resCount = %d !?\n",
2786 resCount);
2787 /* XXX clear pdb_tr */
984263bc
MD
2788 goto out;
2789 }
2790 offset = 0;
2791 nvec = 0;
2792 }
2793 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2794 if (plen < 0) {
2795 /* minimum header size + trailer
2796 = sizeof(fw_pkt) so this shouldn't happens */
78748771
JS
2797 printf("plen(%d) is negative! offset=%d\n",
2798 plen, offset);
2799 /* XXX clear pdb_tr */
984263bc
MD
2800 goto out;
2801 }
2802 if (plen > 0) {
2803 len -= plen;
2804 if (len < 0) {
2805 dbch->pdb_tr = db_tr;
2806 if (firewire_debug)
2807 printf("splitted payload\n");
2808 /* sanity check */
2809 if (resCount != 0)
78748771
JS
2810 printf("resCount = %d !?\n",
2811 resCount);
2812 /* XXX clear pdb_tr */
984263bc
MD
2813 goto out;
2814 }
2815 vec[nvec].iov_base = ld;
2816 vec[nvec].iov_len = plen;
2817 nvec ++;
2818 ld += plen;
2819 }
2820 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2821 if (nvec == 0)
2822 printf("nvec == 0\n");
2823
2824/* DMA result-code will be written at the tail of packet */
2825#if BYTE_ORDER == BIG_ENDIAN
2826 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2827#else
2828 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2829#endif
2830#if 0
78748771
JS
2831 printf("plen: %d, stat %x\n",
2832 plen ,stat);
984263bc
MD
2833#endif
2834 spd = (stat >> 5) & 0x3;
2835 stat &= 0x1f;
2836 switch(stat){
2837 case FWOHCIEV_ACKPEND:
2838#if 0
2839 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2840#endif
2841 /* fall through */
2842 case FWOHCIEV_ACKCOMPL:
78748771
JS
2843 {
2844 struct fw_rcv_buf rb;
2845
984263bc
MD
2846 if ((vec[nvec-1].iov_len -=
2847 sizeof(struct fwohci_trailer)) == 0)
2848 nvec--;
78748771
JS
2849 rb.fc = &sc->fc;
2850 rb.vec = vec;
2851 rb.nvec = nvec;
2852 rb.spd = spd;
2853 fw_rcv(&rb);
2854 break;
2855 }
984263bc
MD
2856 case FWOHCIEV_BUSRST:
2857 if (sc->fc.status != FWBUSRESET)
2858 printf("got BUSRST packet!?\n");
2859 break;
2860 default:
2861 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2862#if 0 /* XXX */
2863 goto out;
2864#endif
2865 break;
2866 }
2867 pcnt ++;
2868 if (dbch->pdb_tr != NULL) {
2869 fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
2870 dbch->pdb_tr = NULL;
2871 }
2872
2873 }
2874out:
2875 if (resCount == 0) {
2876 /* done on this buffer */
2877 if (dbch->pdb_tr == NULL) {
2878 fwohci_arcv_free_buf(dbch, db_tr);
2879 dbch->buf_offset = 0;
2880 } else
2881 if (dbch->pdb_tr != db_tr)
2882 printf("pdb_tr != db_tr\n");
2883 db_tr = STAILQ_NEXT(db_tr, link);
2884 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2885 >> OHCI_STATUS_SHIFT;
2886 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2887 & OHCI_COUNT_MASK;
2888 /* XXX check buffer overrun */
2889 dbch->top = db_tr;
2890 } else {
2891 dbch->buf_offset = dbch->xferq.psize - resCount;
2892 break;
2893 }
2894 /* XXX make sure DMA is not dead */
2895 }
2896#if 0
2897 if (pcnt < 1)
2898 printf("fwohci_arcv: no packets\n");
2899#endif
4e01b467 2900 crit_exit();
984263bc 2901}