Change the kernel dev_t, representing a pointer to a specinfo structure,
[dragonfly.git] / sys / dev / misc / tw / tw.c
CommitLineData
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1/*-
2 * Copyright (c) 1992, 1993, 1995 Eugene W. Stark
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Eugene W. Stark.
16 * 4. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY EUGENE W. STARK (THE AUTHOR) ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: src/sys/i386/isa/tw.c,v 1.38 2000/01/29 16:00:32 peter Exp $
b13267a5 32 * $DragonFly: src/sys/dev/misc/tw/tw.c,v 1.18 2006/09/10 01:26:35 dillon Exp $
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33 *
34 */
35
1f2de5d4 36#include "use_tw.h"
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37
38/*
39 * Driver configuration parameters
40 */
41
42/*
43 * Time for 1/2 of a power line cycle, in microseconds.
44 * Change this to 10000 for 50Hz power. Phil Sampson
45 * (vk2jnt@gw.vk2jnt.ampr.org OR sampson@gidday.enet.dec.com)
46 * reports that this works (at least in Australia) using a
47 * TW7223 module (a local version of the TW523).
48 */
49#define HALFCYCLE 8333 /* 1/2 cycle = 8333us at 60Hz */
50
51/*
52 * Undefine the following if you don't have the high-resolution "microtime"
53 * routines (leave defined for FreeBSD, which has them).
54 */
55#define HIRESTIME
56
57/*
58 * End of driver configuration parameters
59 */
60
61/*
62 * FreeBSD Device Driver for X-10 POWERHOUSE (tm)
63 * Two-Way Power Line Interface, Model #TW523
64 *
65 * written by Eugene W. Stark (stark@cs.sunysb.edu)
66 * December 2, 1992
67 *
68 * NOTES:
69 *
70 * The TW523 is a carrier-current modem for home control/automation purposes.
71 * It is made by:
72 *
73 * X-10 Inc.
74 * 185A LeGrand Ave.
75 * Northvale, NJ 07647
76 * USA
77 * (201) 784-9700 or 1-800-526-0027
78 *
79 * X-10 Home Controls Inc.
80 * 1200 Aerowood Drive, Unit 20
81 * Mississauga, Ontario
82 * (416) 624-4446 or 1-800-387-3346
83 *
84 * The TW523 is designed for communications using the X-10 protocol,
85 * which is compatible with a number of home control systems, including
86 * Radio Shack "Plug 'n Power(tm)" and Stanley "Lightmaker(tm)."
87 * I bought my TW523 from:
88 *
89 * Home Control Concepts
90 * 9353-C Activity Road
91 * San Diego, CA 92126
92 * (619) 693-8887
93 *
94 * They supplied me with the TW523 (which has an RJ-11 four-wire modular
95 * telephone connector), a modular cable, an RJ-11 to DB-25 connector with
96 * internal wiring, documentation from X-10 on the TW523 (very good),
97 * an instruction manual by Home Control Concepts (not very informative),
98 * and a floppy disk containing binary object code of some demonstration/test
99 * programs and of a C function library suitable for controlling the TW523
100 * by an IBM PC under MS-DOS (not useful to me other than to verify that
101 * the unit worked). I suggest saving money and buying the bare TW523
102 * rather than the TW523 development kit (what I bought), because if you
103 * are running FreeBSD you don't really care about the DOS binaries.
104 *
105 * The interface to the TW-523 consists of four wires on the RJ-11 connector,
106 * which are jumpered to somewhat more wires on the DB-25 connector, which
107 * in turn is intended to plug into the PC parallel printer port. I dismantled
108 * the DB-25 connector to find out what they had done:
109 *
110 * Signal RJ-11 pin DB-25 pin(s) Parallel Port
111 * Transmit TX 4 (Y) 2, 4, 6, 8 Data out
112 * Receive RX 3 (G) 10, 14 -ACK, -AutoFeed
113 * Common 2 (R) 25 Common
114 * Zero crossing 1 (B) 17 or 12 -Select or +PaperEnd
115 *
116 * NOTE: In the original cable I have (which I am still using, May, 1997)
117 * the Zero crossing signal goes to pin 17 (-Select) on the parallel port.
118 * In retrospect, this doesn't make a whole lot of sense, given that the
119 * -Select signal propagates the other direction. Indeed, some people have
120 * reported problems with this, and have had success using pin 12 (+PaperEnd)
121 * instead. This driver searches for the zero crossing signal on either
122 * pin 17 or pin 12, so it should work with either cable configuration.
123 * My suggestion would be to start by making the cable so that the zero
124 * crossing signal goes to pin 12 on the parallel port.
125 *
126 * The zero crossing signal is used to synchronize transmission to the
127 * zero crossings of the AC line, as detailed in the X-10 documentation.
128 * It would be nice if one could generate interrupts with this signal,
129 * however one needs interrupts on both the rising and falling edges,
130 * and the -ACK signal to the parallel port interrupts only on the falling
131 * edge, so it can't be done without additional hardware.
132 *
133 * In this driver, the transmit function is performed in a non-interrupt-driven
134 * fashion, by polling the zero crossing signal to determine when a transition
135 * has occurred. This wastes CPU time during transmission, but it seems like
136 * the best that can be done without additional hardware. One problem with
137 * the scheme is that preemption of the CPU during transmission can cause loss
138 * of sync. The driver tries to catch this, by noticing that a long delay
139 * loop has somehow become foreshortened, and the transmission is aborted with
140 * an error return. It is up to the user level software to handle this
141 * situation (most likely by retrying the transmission).
142 */
143
144#include <sys/param.h>
145#include <sys/systm.h>
146#include <sys/conf.h>
fef8985e 147#include <sys/device.h>
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148#include <sys/kernel.h>
149#include <sys/uio.h>
150#include <sys/syslog.h>
9183fa5b 151#include <sys/selinfo.h>
984263bc 152#include <sys/poll.h>
8ba87358 153#include <sys/thread2.h>
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154
155#ifdef HIRESTIME
156#include <sys/time.h>
157#endif /* HIRESTIME */
158
1f2de5d4 159#include <bus/isa/i386/isa_device.h>
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160
161/*
162 * Transmission is done by calling write() to send three byte packets of data.
163 * The first byte contains a four bit house code (0=A to 15=P).
164 * The second byte contains five bit unit/key code (0=unit 1 to 15=unit 16,
165 * 16=All Units Off to 31 = Status Request). The third byte specifies
166 * the number of times the packet is to be transmitted without any
167 * gaps between successive transmissions. Normally this is 2, as per
168 * the X-10 documentation, but sometimes (e.g. for bright and dim codes)
169 * it can be another value. Each call to write can specify an arbitrary
170 * number of data bytes. An incomplete packet is buffered until a subsequent
171 * call to write() provides data to complete it. At most one packet will
172 * actually be processed in any call to write(). Successive calls to write()
173 * leave a three-cycle gap between transmissions, per the X-10 documentation.
174 *
175 * Reception is done using read().
176 * The driver produces a series of three-character packets.
177 * In each packet, the first character consists of flags,
178 * the second character is a four bit house code (0-15),
179 * and the third character is a five bit key/function code (0-31).
180 * The flags are the following:
181 */
182
183#define TW_RCV_LOCAL 1 /* The packet arrived during a local transmission */
184#define TW_RCV_ERROR 2 /* An invalid/corrupted packet was received */
185
186/*
187 * IBM PC parallel port definitions relevant to TW523
188 */
189
190#define tw_data 0 /* Data to tw523 (R/W) */
191
192#define tw_status 1 /* Status of tw523 (R) */
193#define TWS_RDATA 0x40 /* tw523 receive data */
194#define TWS_OUT 0x20 /* pin 12, out of paper */
195
196#define tw_control 2 /* Control tw523 (R/W) */
197#define TWC_SYNC 0x08 /* tw523 sync (pin 17) */
198#define TWC_ENA 0x10 /* tw523 interrupt enable */
199
200/*
201 * Miscellaneous defines
202 */
203
204#define TWUNIT(dev) (minor(dev)) /* Extract unit number from device */
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205
206static int twprobe(struct isa_device *idp);
207static int twattach(struct isa_device *idp);
208
209struct isa_driver twdriver = {
210 twprobe, twattach, "tw"
211};
212
213static d_open_t twopen;
214static d_close_t twclose;
215static d_read_t twread;
216static d_write_t twwrite;
217static d_poll_t twpoll;
218
219#define CDEV_MAJOR 19
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220static struct dev_ops tw_ops = {
221 { "tw", CDEV_MAJOR, 0 },
222 .d_open = twopen,
223 .d_close = twclose,
224 .d_read = twread,
225 .d_write = twwrite,
226 .d_poll = twpoll,
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227};
228
229/*
230 * Software control structure for TW523
231 */
232
233#define TWS_XMITTING 1 /* Transmission in progress */
234#define TWS_RCVING 2 /* Reception in progress */
235#define TWS_WANT 4 /* A process wants received data */
236#define TWS_OPEN 8 /* Is it currently open? */
237
238#define TW_SIZE 3*60 /* Enough for about 10 sec. of input */
239#define TW_MIN_DELAY 1500 /* Ignore interrupts of lesser latency */
240
241static struct tw_sc {
242 u_int sc_port; /* I/O Port */
243 u_int sc_state; /* Current software control state */
244 struct selinfo sc_selp; /* Information for select() */
245 u_char sc_xphase; /* Current state of sync (for transmitter) */
246 u_char sc_rphase; /* Current state of sync (for receiver) */
247 u_char sc_flags; /* Flags for current reception */
248 short sc_rcount; /* Number of bits received so far */
249 int sc_bits; /* Bits received so far */
250 u_char sc_pkt[3]; /* Packet not yet transmitted */
251 short sc_pktsize; /* How many bytes in the packet? */
252 u_char sc_buf[TW_SIZE]; /* We buffer our own input */
253 int sc_nextin; /* Next free slot in circular buffer */
254 int sc_nextout; /* First used slot in circular buffer */
255 /* Callout for canceling our abortrcv timeout */
726b8254 256 struct callout abortrcv_ch;
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257#ifdef HIRESTIME
258 int sc_xtimes[22]; /* Times for bits in current xmit packet */
259 int sc_rtimes[22]; /* Times for bits in current rcv packet */
260 int sc_no_rcv; /* number of interrupts received */
261#define SC_RCV_TIME_LEN 128
262 int sc_rcv_time[SC_RCV_TIME_LEN]; /* usec time stamp on interrupt */
263#endif /* HIRESTIME */
264} tw_sc[NTW];
265
266static int tw_zcport; /* offset of port for zero crossing signal */
267static int tw_zcmask; /* mask for the zero crossing signal */
268
269static void twdelay25(void);
270static void twdelayn(int n);
271static void twsetuptimes(int *a);
272static int wait_for_zero(struct tw_sc *sc);
273static int twputpkt(struct tw_sc *sc, u_char *p);
1b51b0fa 274static void twintr(void *);
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275static int twgetbytes(struct tw_sc *sc, u_char *p, int cnt);
276static timeout_t twabortrcv;
277static int twsend(struct tw_sc *sc, int h, int k, int cnt);
278static int next_zero(struct tw_sc *sc);
279static int twchecktime(int target, int tol);
280static void twdebugtimes(struct tw_sc *sc);
281
282/*
283 * Counter value for delay loop.
284 * It is adjusted by twprobe so that the delay loop takes about 25us.
285 */
286
287#define TWDELAYCOUNT 161 /* Works on my 486DX/33 */
288static int twdelaycount;
289
290/*
291 * Twdelay25 is used for very short delays of about 25us.
292 * It is implemented with a calibrated delay loop, and should be
293 * fairly accurate ... unless we are preempted by an interrupt.
294 *
295 * We use this to wait for zero crossings because the X-10 specs say we
296 * are supposed to assert carrier within 25us when one happens.
297 * I don't really believe we can do this, but the X-10 devices seem to be
298 * fairly forgiving.
299 */
300
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301static void
302twdelay25(void)
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303{
304 int cnt;
305 for(cnt = twdelaycount; cnt; cnt--); /* Should take about 25us */
306}
307
308/*
309 * Twdelayn is used to time the length of the 1ms carrier pulse.
310 * This is not very critical, but if we have high-resolution time-of-day
311 * we check it every apparent 200us to make sure we don't get too far off
312 * if we happen to be interrupted during the delay.
313 */
314
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315static void
316twdelayn(int n)
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317{
318#ifdef HIRESTIME
319 int t, d;
320 struct timeval tv;
321 microtime(&tv);
322 t = tv.tv_usec;
323 t += n;
324#endif /* HIRESTIME */
325 while(n > 0) {
326 twdelay25();
327 n -= 25;
328#ifdef HIRESTIME
329 if((n & 0x7) == 0) {
330 microtime(&tv);
331 d = tv.tv_usec - t;
332 if(d >= 0 && d < 1000000) return;
333 }
334#endif /* HIRESTIME */
335 }
336}
337
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338static int
339twprobe(struct isa_device *idp)
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340{
341 struct tw_sc sc;
342 int d;
343 int tries;
984263bc 344
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345 sc.sc_port = idp->id_iobase;
346 /* Search for the zero crossing signal at ports, bit combinations. */
347 tw_zcport = tw_control;
348 tw_zcmask = TWC_SYNC;
349 sc.sc_xphase = inb(idp->id_iobase + tw_zcport) & tw_zcmask;
350 if(wait_for_zero(&sc) < 0) {
351 tw_zcport = tw_status;
352 tw_zcmask = TWS_OUT;
353 sc.sc_xphase = inb(idp->id_iobase + tw_zcport) & tw_zcmask;
354 }
355 if(wait_for_zero(&sc) < 0)
356 return(0);
357 /*
358 * Iteratively check the timing of a few sync transitions, and adjust
359 * the loop delay counter, if necessary, to bring the timing reported
360 * by wait_for_zero() close to HALFCYCLE. Give up if anything
361 * ridiculous happens.
362 */
363 if(twdelaycount == 0) { /* Only adjust timing for first unit */
364 twdelaycount = TWDELAYCOUNT;
365 for(tries = 0; tries < 10; tries++) {
366 sc.sc_xphase = inb(idp->id_iobase + tw_zcport) & tw_zcmask;
367 if(wait_for_zero(&sc) >= 0) {
368 d = wait_for_zero(&sc);
369 if(d <= HALFCYCLE/100 || d >= HALFCYCLE*100) {
370 twdelaycount = 0;
371 return(0);
372 }
373 twdelaycount = (twdelaycount * d)/HALFCYCLE;
374 }
375 }
376 }
377 /*
378 * Now do a final check, just to make sure
379 */
380 sc.sc_xphase = inb(idp->id_iobase + tw_zcport) & tw_zcmask;
381 if(wait_for_zero(&sc) >= 0) {
382 d = wait_for_zero(&sc);
383 if(d <= (HALFCYCLE * 110)/100 && d >= (HALFCYCLE * 90)/100) return(8);
384 }
385 return(0);
386}
387
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388static int
389twattach(struct isa_device *idp)
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390{
391 struct tw_sc *sc;
392 int unit;
393
1b51b0fa 394 idp->id_intr = (inthand2_t *)twintr;
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395 sc = &tw_sc[unit = idp->id_unit];
396 sc->sc_port = idp->id_iobase;
397 sc->sc_state = 0;
398 sc->sc_rcount = 0;
726b8254 399 callout_init(&sc->abortrcv_ch);
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400 dev_ops_add(&tw_ops, -1, unit);
401 make_dev(&tw_ops, unit, 0, 0, 0600, "tw%d", unit);
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402 return (1);
403}
404
c436375a 405int
fef8985e 406twopen(struct dev_open_args *ap)
984263bc 407{
b13267a5 408 cdev_t dev = ap->a_head.a_dev;
984263bc 409 struct tw_sc *sc = &tw_sc[TWUNIT(dev)];
984263bc 410
8ba87358 411 crit_enter();
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412 if(sc->sc_state == 0) {
413 sc->sc_state = TWS_OPEN;
414 sc->sc_nextin = sc->sc_nextout = 0;
415 sc->sc_pktsize = 0;
416 outb(sc->sc_port+tw_control, TWC_ENA);
417 }
8ba87358 418 crit_exit();
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419 return(0);
420}
421
c436375a 422int
fef8985e 423twclose(struct dev_close_args *ap)
984263bc 424{
b13267a5 425 cdev_t dev = ap->a_head.a_dev;
984263bc 426 struct tw_sc *sc = &tw_sc[TWUNIT(dev)];
984263bc 427
8ba87358 428 crit_enter();
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429 sc->sc_state = 0;
430 outb(sc->sc_port+tw_control, 0);
8ba87358 431 crit_exit();
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432 return(0);
433}
434
c436375a 435int
fef8985e 436twread(struct dev_read_args *ap)
984263bc 437{
b13267a5 438 cdev_t dev = ap->a_head.a_dev;
fef8985e 439 struct uio *uio = ap->a_uio;
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440 u_char buf[3];
441 struct tw_sc *sc = &tw_sc[TWUNIT(dev)];
8ba87358 442 int error, cnt;
984263bc 443
8ba87358 444 crit_enter();
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445 cnt = MIN(uio->uio_resid, 3);
446 if((error = twgetbytes(sc, buf, cnt)) == 0) {
447 error = uiomove(buf, cnt, uio);
448 }
8ba87358 449 crit_exit();
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450 return(error);
451}
452
c436375a 453int
fef8985e 454twwrite(struct dev_write_args *ap)
984263bc 455{
b13267a5 456 cdev_t dev = ap->a_head.a_dev;
fef8985e 457 struct uio *uio = ap->a_uio;
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458 struct tw_sc *sc;
459 int house, key, reps;
8ba87358 460 int error;
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461 int cnt;
462
463 sc = &tw_sc[TWUNIT(dev)];
464 /*
465 * Note: Although I had intended to allow concurrent transmitters,
466 * there is a potential problem here if two processes both write
467 * into the sc_pkt buffer at the same time. The following code
468 * is an additional critical section that needs to be synchronized.
469 */
8ba87358 470 crit_enter();
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471 cnt = MIN(3 - sc->sc_pktsize, uio->uio_resid);
472 error = uiomove(&(sc->sc_pkt[sc->sc_pktsize]), cnt, uio);
473 if(error) {
8ba87358 474 crit_exit();
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475 return(error);
476 }
477 sc->sc_pktsize += cnt;
478 if(sc->sc_pktsize < 3) { /* Only transmit 3-byte packets */
8ba87358 479 crit_exit();
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480 return(0);
481 }
482 sc->sc_pktsize = 0;
483 /*
484 * Collect house code, key code, and rep count, and check for sanity.
485 */
486 house = sc->sc_pkt[0];
487 key = sc->sc_pkt[1];
488 reps = sc->sc_pkt[2];
489 if(house >= 16 || key >= 32) {
8ba87358 490 crit_exit();
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491 return(ENODEV);
492 }
493 /*
494 * Synchronize with the receiver operating in the bottom half, and
495 * also with concurrent transmitters.
496 * We don't want to interfere with a packet currently being received,
497 * and we would like the receiver to recognize when a packet has
498 * originated locally.
499 */
500 while(sc->sc_state & (TWS_RCVING | TWS_XMITTING)) {
377d4740 501 error = tsleep((caddr_t)sc, PCATCH, "twwrite", 0);
984263bc 502 if(error) {
8ba87358 503 crit_exit();
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504 return(error);
505 }
506 }
507 sc->sc_state |= TWS_XMITTING;
508 /*
509 * Everything looks OK, let's do the transmission.
510 */
8ba87358 511 crit_exit(); /* Enable interrupts because this takes a LONG time */
984263bc 512 error = twsend(sc, house, key, reps);
8ba87358 513 crit_enter();
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514 sc->sc_state &= ~TWS_XMITTING;
515 wakeup((caddr_t)sc);
8ba87358 516 crit_exit();
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517 if(error) return(EIO);
518 else return(0);
519}
520
521/*
522 * Determine if there is data available for reading
523 */
524
c436375a 525int
fef8985e 526twpoll(struct dev_poll_args *ap)
984263bc 527{
b13267a5 528 cdev_t dev = ap->a_head.a_dev;
984263bc 529 struct tw_sc *sc;
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530 int revents = 0;
531
532 sc = &tw_sc[TWUNIT(dev)];
8ba87358 533 crit_enter();
984263bc 534 /* XXX is this correct? the original code didn't test select rw mode!! */
fef8985e 535 if (ap->a_events & (POLLIN | POLLRDNORM)) {
984263bc 536 if(sc->sc_nextin != sc->sc_nextout)
fef8985e 537 revents |= ap->a_events & (POLLIN | POLLRDNORM);
984263bc 538 else
fef8985e 539 selrecord(curthread, &sc->sc_selp);
984263bc 540 }
8ba87358 541 crit_exit();
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542 ap->a_events = revents;
543 return(0);
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544}
545
546/*
547 * X-10 Protocol
548 */
549
550#define X10_START_LENGTH 4
551static char X10_START[] = { 1, 1, 1, 0 };
552
553/*
554 * Each bit of the 4-bit house code and 5-bit key code
555 * is transmitted twice, once in true form, and then in
556 * complemented form. This is already taken into account
557 * in the following tables.
558 */
559
560#define X10_HOUSE_LENGTH 8
561static char X10_HOUSE[16][8] = {
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562 { 0, 1, 1, 0, 1, 0, 0, 1 }, /* A = 0110 */
563 { 1, 0, 1, 0, 1, 0, 0, 1 }, /* B = 1110 */
564 { 0, 1, 0, 1, 1, 0, 0, 1 }, /* C = 0010 */
565 { 1, 0, 0, 1, 1, 0, 0, 1 }, /* D = 1010 */
566 { 0, 1, 0, 1, 0, 1, 1, 0 }, /* E = 0001 */
567 { 1, 0, 0, 1, 0, 1, 1, 0 }, /* F = 1001 */
568 { 0, 1, 1, 0, 0, 1, 1, 0 }, /* G = 0101 */
569 { 1, 0, 1, 0, 0, 1, 1, 0 }, /* H = 1101 */
570 { 0, 1, 1, 0, 1, 0, 1, 0 }, /* I = 0111 */
571 { 1, 0, 1, 0, 1, 0, 1, 0 }, /* J = 1111 */
572 { 0, 1, 0, 1, 1, 0, 1, 0 }, /* K = 0011 */
573 { 1, 0, 0, 1, 1, 0, 1, 0 }, /* L = 1011 */
574 { 0, 1, 0, 1, 0, 1, 0, 1 }, /* M = 0000 */
575 { 1, 0, 0, 1, 0, 1, 0, 1 }, /* N = 1000 */
576 { 0, 1, 1, 0, 0, 1, 0, 1 }, /* O = 0100 */
577 { 1, 0, 1, 0, 0, 1, 0, 1 } /* P = 1100 */
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578};
579
580#define X10_KEY_LENGTH 10
581static char X10_KEY[32][10] = {
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582 { 0, 1, 1, 0, 1, 0, 0, 1, 0, 1 }, /* 01100 => 1 */
583 { 1, 0, 1, 0, 1, 0, 0, 1, 0, 1 }, /* 11100 => 2 */
584 { 0, 1, 0, 1, 1, 0, 0, 1, 0, 1 }, /* 00100 => 3 */
585 { 1, 0, 0, 1, 1, 0, 0, 1, 0, 1 }, /* 10100 => 4 */
586 { 0, 1, 0, 1, 0, 1, 1, 0, 0, 1 }, /* 00010 => 5 */
587 { 1, 0, 0, 1, 0, 1, 1, 0, 0, 1 }, /* 10010 => 6 */
588 { 0, 1, 1, 0, 0, 1, 1, 0, 0, 1 }, /* 01010 => 7 */
589 { 1, 0, 1, 0, 0, 1, 1, 0, 0, 1 }, /* 11010 => 8 */
590 { 0, 1, 1, 0, 1, 0, 1, 0, 0, 1 }, /* 01110 => 9 */
591 { 1, 0, 1, 0, 1, 0, 1, 0, 0, 1 }, /* 11110 => 10 */
592 { 0, 1, 0, 1, 1, 0, 1, 0, 0, 1 }, /* 00110 => 11 */
593 { 1, 0, 0, 1, 1, 0, 1, 0, 0, 1 }, /* 10110 => 12 */
594 { 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 }, /* 00000 => 13 */
595 { 1, 0, 0, 1, 0, 1, 0, 1, 0, 1 }, /* 10000 => 14 */
596 { 0, 1, 1, 0, 0, 1, 0, 1, 0, 1 }, /* 01000 => 15 */
597 { 1, 0, 1, 0, 0, 1, 0, 1, 0, 1 }, /* 11000 => 16 */
598 { 0, 1, 0, 1, 0, 1, 0, 1, 1, 0 }, /* 00001 => All Units Off */
599 { 0, 1, 0, 1, 0, 1, 1, 0, 1, 0 }, /* 00011 => All Units On */
600 { 0, 1, 0, 1, 1, 0, 0, 1, 1, 0 }, /* 00101 => On */
601 { 0, 1, 0, 1, 1, 0, 1, 0, 1, 0 }, /* 00111 => Off */
602 { 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 }, /* 01001 => Dim */
603 { 0, 1, 1, 0, 0, 1, 1, 0, 1, 0 }, /* 01011 => Bright */
604 { 0, 1, 1, 0, 1, 0, 0, 1, 1, 0 }, /* 01101 => All LIGHTS Off */
605 { 0, 1, 1, 0, 1, 0, 1, 0, 1, 0 }, /* 01111 => Extended Code */
606 { 1, 0, 0, 1, 0, 1, 0, 1, 1, 0 }, /* 10001 => Hail Request */
607 { 1, 0, 0, 1, 0, 1, 1, 0, 1, 0 }, /* 10011 => Hail Acknowledge */
608 { 1, 0, 0, 1, 1, 0, 0, 1, 1, 0 }, /* 10101 => Preset Dim 0 */
609 { 1, 0, 0, 1, 1, 0, 1, 0, 1, 0 }, /* 10111 => Preset Dim 1 */
610 { 1, 0, 1, 0, 0, 1, 0, 1, 0, 1 }, /* 11000 => Extended Data (analog) */
611 { 1, 0, 1, 0, 0, 1, 1, 0, 1, 0 }, /* 11011 => Status = on */
612 { 1, 0, 1, 0, 1, 0, 0, 1, 1, 0 }, /* 11101 => Status = off */
613 { 1, 0, 1, 0, 1, 0, 1, 0, 1, 0 } /* 11111 => Status request */
984263bc
MD
614};
615
616/*
617 * Tables for mapping received X-10 code back to house/key number.
618 */
619
620static short X10_HOUSE_INV[16] = {
621 12, 4, 2, 10, 14, 6, 0, 8,
622 13, 5, 3, 11, 15, 7, 1, 9
623};
624
625static short X10_KEY_INV[32] = {
626 12, 16, 4, 17, 2, 18, 10, 19,
627 14, 20, 6, 21, 0, 22, 8, 23,
628 13, 24, 5, 25, 3, 26, 11, 27,
629 15, 28, 7, 29, 1, 30, 9, 31
630};
631
632static char *X10_KEY_LABEL[32] = {
633 "1",
634 "2",
635 "3",
636 "4",
637 "5",
638 "6",
639 "7",
640 "8",
641 "9",
642 "10",
643 "11",
644 "12",
645 "13",
646 "14",
647 "15",
648 "16",
649 "All Units Off",
650 "All Units On",
651 "On",
652 "Off",
653 "Dim",
654 "Bright",
655 "All LIGHTS Off",
656 "Extended Code",
657 "Hail Request",
658 "Hail Acknowledge",
659 "Preset Dim 0",
660 "Preset Dim 1",
661 "Extended Data (analog)",
662 "Status = on",
663 "Status = off",
664 "Status request"
665};
666/*
667 * Transmit a packet containing house code h and key code k
668 */
669
670#define TWRETRY 10 /* Try 10 times to sync with AC line */
671
c436375a
SW
672static int
673twsend(struct tw_sc *sc, int h, int k, int cnt)
984263bc
MD
674{
675 int i;
676 int port = sc->sc_port;
677
678 /*
679 * Make sure we get a reliable sync with a power line zero crossing
680 */
681 for(i = 0; i < TWRETRY; i++) {
682 if(wait_for_zero(sc) > 100) goto insync;
683 }
684 log(LOG_ERR, "TWXMIT: failed to sync.\n");
685 return(-1);
686
687 insync:
688 /*
689 * Be sure to leave 3 cycles space between transmissions
690 */
691 for(i = 6; i > 0; i--)
692 if(next_zero(sc) < 0) return(-1);
693 /*
694 * The packet is transmitted cnt times, with no gaps.
695 */
696 while(cnt--) {
697 /*
698 * Transmit the start code
699 */
700 for(i = 0; i < X10_START_LENGTH; i++) {
701 outb(port+tw_data, X10_START[i] ? 0xff : 0x00); /* Waste no time! */
702#ifdef HIRESTIME
703 if(i == 0) twsetuptimes(sc->sc_xtimes);
704 if(twchecktime(sc->sc_xtimes[i], HALFCYCLE/20) == 0) {
705 outb(port+tw_data, 0);
706 return(-1);
707 }
708#endif /* HIRESTIME */
709 twdelayn(1000); /* 1ms pulse width */
710 outb(port+tw_data, 0);
711 if(next_zero(sc) < 0) return(-1);
712 }
713 /*
714 * Transmit the house code
715 */
716 for(i = 0; i < X10_HOUSE_LENGTH; i++) {
717 outb(port+tw_data, X10_HOUSE[h][i] ? 0xff : 0x00); /* Waste no time! */
718#ifdef HIRESTIME
719 if(twchecktime(sc->sc_xtimes[i+X10_START_LENGTH], HALFCYCLE/20) == 0) {
720 outb(port+tw_data, 0);
721 return(-1);
722 }
723#endif /* HIRESTIME */
724 twdelayn(1000); /* 1ms pulse width */
725 outb(port+tw_data, 0);
726 if(next_zero(sc) < 0) return(-1);
727 }
728 /*
729 * Transmit the unit/key code
730 */
731 for(i = 0; i < X10_KEY_LENGTH; i++) {
732 outb(port+tw_data, X10_KEY[k][i] ? 0xff : 0x00);
733#ifdef HIRESTIME
734 if(twchecktime(sc->sc_xtimes[i+X10_START_LENGTH+X10_HOUSE_LENGTH],
735 HALFCYCLE/20) == 0) {
736 outb(port+tw_data, 0);
737 return(-1);
738 }
739#endif /* HIRESTIME */
740 twdelayn(1000); /* 1ms pulse width */
741 outb(port+tw_data, 0);
742 if(next_zero(sc) < 0) return(-1);
743 }
744 }
745 return(0);
746}
747
748/*
749 * Waste CPU cycles to get in sync with a power line zero crossing.
750 * The value returned is roughly how many microseconds we wasted before
751 * seeing the transition. To avoid wasting time forever, we give up after
752 * waiting patiently for 1/4 sec (15 power line cycles at 60 Hz),
753 * which is more than the 11 cycles it takes to transmit a full
754 * X-10 packet.
755 */
756
c436375a
SW
757static int
758wait_for_zero(struct tw_sc *sc)
984263bc
MD
759{
760 int i, old, new, max;
761 int port = sc->sc_port + tw_zcport;
762
763 old = sc->sc_xphase;
764 max = 10000; /* 10000 * 25us = 0.25 sec */
765 i = 0;
766 while(max--) {
767 new = inb(port) & tw_zcmask;
768 if(new != old) {
769 sc->sc_xphase = new;
770 return(i*25);
771 }
772 i++;
773 twdelay25();
774 }
775 return(-1);
776}
777
778/*
779 * Wait for the next zero crossing transition, and if we don't have
780 * high-resolution time-of-day, check to see that the zero crossing
781 * appears to be arriving on schedule.
782 * We expect to be waiting almost a full half-cycle (8.333ms-1ms = 7.333ms).
783 * If we don't seem to wait very long, something is wrong (like we got
784 * preempted!) and we should abort the transmission because
785 * there's no telling how long it's really been since the
786 * last bit was transmitted.
787 */
788
c436375a
SW
789static int
790next_zero(struct tw_sc *sc)
984263bc
MD
791{
792 int d;
793#ifdef HIRESTIME
794 if((d = wait_for_zero(sc)) < 0) {
795#else
796 if((d = wait_for_zero(sc)) < 6000 || d > 8500) {
797 /* No less than 6.0ms, no more than 8.5ms */
798#endif /* HIRESTIME */
799 log(LOG_ERR, "TWXMIT framing error: %d\n", d);
800 return(-1);
801 }
802 return(0);
803}
804
805/*
806 * Put a three-byte packet into the circular buffer
8ba87358 807 * Should be called from a critical section.
984263bc
MD
808 */
809
c436375a
SW
810static int
811twputpkt(struct tw_sc *sc, u_char *p)
984263bc
MD
812{
813 int i, next;
814
815 for(i = 0; i < 3; i++) {
816 next = sc->sc_nextin+1;
817 if(next >= TW_SIZE) next = 0;
818 if(next == sc->sc_nextout) { /* Buffer full */
819/*
820 log(LOG_ERR, "TWRCV: Buffer overrun\n");
821 */
822 return(1);
823 }
824 sc->sc_buf[sc->sc_nextin] = *p++;
825 sc->sc_nextin = next;
826 }
827 if(sc->sc_state & TWS_WANT) {
828 sc->sc_state &= ~TWS_WANT;
829 wakeup((caddr_t)(&sc->sc_buf));
830 }
831 selwakeup(&sc->sc_selp);
832 return(0);
833}
834
835/*
836 * Get bytes from the circular buffer
8ba87358 837 * Should be called from a critical section.
984263bc
MD
838 */
839
c436375a
SW
840static int
841twgetbytes(struct tw_sc *sc, u_char *p, int cnt)
984263bc
MD
842{
843 int error;
844
845 while(cnt--) {
846 while(sc->sc_nextin == sc->sc_nextout) { /* Buffer empty */
847 sc->sc_state |= TWS_WANT;
377d4740 848 error = tsleep((caddr_t)(&sc->sc_buf), PCATCH, "twread", 0);
984263bc
MD
849 if(error) {
850 return(error);
851 }
852 }
853 *p++ = sc->sc_buf[sc->sc_nextout++];
854 if(sc->sc_nextout >= TW_SIZE) sc->sc_nextout = 0;
855 }
856 return(0);
857}
858
859/*
860 * Abort reception that has failed to complete in the required time.
861 */
862
863static void
c436375a 864twabortrcv(void *arg)
984263bc
MD
865{
866 struct tw_sc *sc = arg;
984263bc
MD
867 u_char pkt[3];
868
8ba87358 869 crit_enter();
984263bc
MD
870 sc->sc_state &= ~TWS_RCVING;
871 /* simply ignore single isolated interrupts. */
872 if (sc->sc_no_rcv > 1) {
873 sc->sc_flags |= TW_RCV_ERROR;
874 pkt[0] = sc->sc_flags;
875 pkt[1] = pkt[2] = 0;
876 twputpkt(sc, pkt);
877 log(LOG_ERR, "TWRCV: aborting (%x, %d)\n", sc->sc_bits, sc->sc_rcount);
878 twdebugtimes(sc);
879 }
880 wakeup((caddr_t)sc);
8ba87358 881 crit_exit();
984263bc
MD
882}
883
884static int
885tw_is_within(int value, int expected, int tolerance)
886{
887 int diff;
888 diff = value - expected;
889 if (diff < 0)
890 diff *= -1;
891 if (diff < tolerance)
892 return 1;
893 return 0;
894}
895
896/*
897 * This routine handles interrupts that occur when there is a falling
898 * transition on the RX input. There isn't going to be a transition
899 * on every bit (some are zero), but if we are smart and keep track of
900 * how long it's been since the last interrupt (via the zero crossing
901 * detect line and/or high-resolution time-of-day routine), we can
902 * reconstruct the transmission without having to poll.
903 */
904
c436375a
SW
905static void
906twintr(void *arg)
984263bc 907{
477d3c1c 908 int unit = (int)arg;
984263bc
MD
909 struct tw_sc *sc = &tw_sc[unit];
910 int port;
911 int newphase;
912 u_char pkt[3];
913 int delay = 0;
914 struct timeval tv;
915
916 port = sc->sc_port;
917 /*
918 * Ignore any interrupts that occur if the device is not open.
919 */
920 if(sc->sc_state == 0) return;
921 newphase = inb(port + tw_zcport) & tw_zcmask;
922 microtime(&tv);
923
924 /*
925 * NEW PACKET:
926 * If we aren't currently receiving a packet, set up a new packet
927 * and put in the first "1" bit that has just arrived.
928 * Arrange for the reception to be aborted if too much time goes by.
929 */
930 if((sc->sc_state & TWS_RCVING) == 0) {
931#ifdef HIRESTIME
932 twsetuptimes(sc->sc_rtimes);
933#endif /* HIRESTIME */
934 sc->sc_state |= TWS_RCVING;
935 sc->sc_rcount = 1;
936 if(sc->sc_state & TWS_XMITTING) sc->sc_flags = TW_RCV_LOCAL;
937 else sc->sc_flags = 0;
938 sc->sc_bits = 0;
939 sc->sc_rphase = newphase;
940 /* 3 cycles of silence = 3/60 = 1/20 = 50 msec */
726b8254 941 callout_reset(&sc->abortrcv_ch, hz / 20, twabortrcv, sc);
984263bc
MD
942 sc->sc_rcv_time[0] = tv.tv_usec;
943 sc->sc_no_rcv = 1;
944 return;
945 }
726b8254 946 callout_reset(&sc->abortrcv_ch, hz / 20, twabortrcv, sc);
984263bc
MD
947 newphase = inb(port + tw_zcport) & tw_zcmask;
948
949 /* enforce a minimum delay since the last interrupt */
950 delay = tv.tv_usec - sc->sc_rcv_time[sc->sc_no_rcv - 1];
951 if (delay < 0)
952 delay += 1000000;
953 if (delay < TW_MIN_DELAY)
954 return;
955
956 sc->sc_rcv_time[sc->sc_no_rcv] = tv.tv_usec;
957 if (sc->sc_rcv_time[sc->sc_no_rcv] < sc->sc_rcv_time[0])
958 sc->sc_rcv_time[sc->sc_no_rcv] += 1000000;
959 sc->sc_no_rcv++;
960
961 /*
962 * START CODE:
963 * The second and third bits are a special case.
964 */
965 if (sc->sc_rcount < 3) {
966 if (
967#ifdef HIRESTIME
968 tw_is_within(delay, HALFCYCLE, HALFCYCLE / 6)
969#else
970 newphase != sc->sc_rphase
971#endif
972 ) {
973 sc->sc_rcount++;
974 } else {
975 /*
976 * Invalid start code -- abort reception.
977 */
978 sc->sc_state &= ~TWS_RCVING;
979 sc->sc_flags |= TW_RCV_ERROR;
726b8254 980 callout_stop(&sc->abortrcv_ch);
984263bc
MD
981 log(LOG_ERR, "TWRCV: Invalid start code\n");
982 twdebugtimes(sc);
983 sc->sc_no_rcv = 0;
984 return;
985 }
986 if(sc->sc_rcount == 3) {
987 /*
988 * We've gotten three "1" bits in a row. The start code
989 * is really 1110, but this might be followed by a zero
990 * bit from the house code, so if we wait any longer we
991 * might be confused about the first house code bit.
992 * So, we guess that the start code is correct and insert
993 * the trailing zero without actually having seen it.
994 * We don't change sc_rphase in this case, because two
995 * bit arrivals in a row preserve parity.
996 */
997 sc->sc_rcount++;
998 return;
999 }
1000 /*
1001 * Update sc_rphase to the current phase before returning.
1002 */
1003 sc->sc_rphase = newphase;
1004 return;
1005 }
1006 /*
1007 * GENERAL CASE:
1008 * Now figure out what the current bit is that just arrived.
1009 * The X-10 protocol transmits each data bit twice: once in
1010 * true form and once in complemented form on the next half
1011 * cycle. So, there will be at least one interrupt per bit.
1012 * By comparing the phase we see at the time of the interrupt
1013 * with the saved sc_rphase, we can tell on which half cycle
1014 * the interrupt occrred. This assumes, of course, that the
1015 * packet is well-formed. We do the best we can at trying to
1016 * catch errors by aborting if too much time has gone by, and
1017 * by tossing out a packet if too many bits arrive, but the
1018 * whole scheme is probably not as robust as if we had a nice
1019 * interrupt on every half cycle of the power line.
1020 * If we have high-resolution time-of-day routines, then we
1021 * can do a bit more sanity checking.
1022 */
1023
1024 /*
1025 * A complete packet is 22 half cycles.
1026 */
1027 if(sc->sc_rcount <= 20) {
1028#ifdef HIRESTIME
1029 int bit = 0, last_bit;
1030 if (sc->sc_rcount == 4)
1031 last_bit = 1; /* Start (1110) ends in 10, a 'one' code. */
1032 else
1033 last_bit = sc->sc_bits & 0x1;
1034 if ( ( (last_bit == 1)
1035 && (tw_is_within(delay, HALFCYCLE * 2, HALFCYCLE / 6)))
1036 || ( (last_bit == 0)
1037 && (tw_is_within(delay, HALFCYCLE * 1, HALFCYCLE / 6))))
1038 bit = 1;
1039 else if ( ( (last_bit == 1)
1040 && (tw_is_within(delay, HALFCYCLE * 3, HALFCYCLE / 6)))
1041 || ( (last_bit == 0)
1042 && (tw_is_within(delay, HALFCYCLE * 2, HALFCYCLE / 6))))
1043 bit = 0;
1044 else {
1045 sc->sc_flags |= TW_RCV_ERROR;
1046 log(LOG_ERR, "TWRCV: %d cycle after %d bit, delay %d%%\n",
1047 sc->sc_rcount, last_bit, 100 * delay / HALFCYCLE);
1048 }
1049 sc->sc_bits = (sc->sc_bits << 1) | bit;
1050#else
1051 sc->sc_bits = (sc->sc_bits << 1)
1052 | ((newphase == sc->sc_rphase) ? 0x0 : 0x1);
1053#endif /* HIRESTIME */
1054 sc->sc_rcount += 2;
1055 }
1056 if(sc->sc_rcount >= 22 || sc->sc_flags & TW_RCV_ERROR) {
1057 if(sc->sc_rcount != 22) {
1058 sc->sc_flags |= TW_RCV_ERROR;
1059 pkt[0] = sc->sc_flags;
1060 pkt[1] = pkt[2] = 0;
1061 } else {
1062 pkt[0] = sc->sc_flags;
1063 pkt[1] = X10_HOUSE_INV[(sc->sc_bits & 0x1e0) >> 5];
1064 pkt[2] = X10_KEY_INV[sc->sc_bits & 0x1f];
1065 }
1066 sc->sc_state &= ~TWS_RCVING;
1067 twputpkt(sc, pkt);
726b8254 1068 callout_stop(&sc->abortrcv_ch);
984263bc
MD
1069 if(sc->sc_flags & TW_RCV_ERROR) {
1070 log(LOG_ERR, "TWRCV: invalid packet: (%d, %x) %c %s\n",
1071 sc->sc_rcount, sc->sc_bits, 'A' + pkt[1], X10_KEY_LABEL[pkt[2]]);
1072 twdebugtimes(sc);
1073 } else {
1074/* log(LOG_ERR, "TWRCV: valid packet: (%d, %x) %c %s\n",
1075 sc->sc_rcount, sc->sc_bits, 'A' + pkt[1], X10_KEY_LABEL[pkt[2]]); */
1076 }
1077 sc->sc_rcount = 0;
1078 wakeup((caddr_t)sc);
1079 }
1080}
1081
c436375a
SW
1082static void
1083twdebugtimes(struct tw_sc *sc)
984263bc
MD
1084{
1085 int i;
1086 for (i = 0; (i < sc->sc_no_rcv) && (i < SC_RCV_TIME_LEN); i++)
1087 log(LOG_ERR, "TWRCV: interrupt %2d: %d\t%d%%\n", i, sc->sc_rcv_time[i],
1088 (sc->sc_rcv_time[i] - sc->sc_rcv_time[(i?i-1:0)])*100/HALFCYCLE);
1089}
1090
1091#ifdef HIRESTIME
1092/*
1093 * Initialize an array of 22 times, starting from the current
1094 * microtime and continuing for the next 21 half cycles.
1095 * We use the times as a reference to make sure transmission
1096 * or reception is on schedule.
1097 */
1098
c436375a
SW
1099static void
1100twsetuptimes(int *a)
984263bc
MD
1101{
1102 struct timeval tv;
1103 int i, t;
1104
1105 microtime(&tv);
1106 t = tv.tv_usec;
1107 for(i = 0; i < 22; i++) {
1108 *a++ = t;
1109 t += HALFCYCLE;
1110 if(t >= 1000000) t -= 1000000;
1111 }
1112}
1113
1114/*
1115 * Check the current time against a slot in a previously set up
1116 * timing array, and make sure that it looks like we are still
1117 * on schedule.
1118 */
1119
c436375a
SW
1120static int
1121twchecktime(int target, int tol)
984263bc
MD
1122{
1123 struct timeval tv;
1124 int t, d;
1125
1126 microtime(&tv);
1127 t = tv.tv_usec;
1128 d = (target - t) >= 0 ? (target - t) : (t - target);
1129 if(d > 500000) d = 1000000-d;
1130 if(d <= tol && d >= -tol) {
1131 return(1);
1132 } else {
1133 return(0);
1134 }
1135}
1136#endif /* HIRESTIME */